[fedora-electronic-lab] Is there a verilog synthesis tool available under FEL umbrella

Chitlesh GOORAH chitlesh at fedoraproject.org
Thu Dec 24 07:35:48 UTC 2009

On Thu, Dec 24, 2009 at 8:30 AM, Rangeen Basu <sherry151 at gmail.com> wrote:
> Hi
> @subject
> Anything similar to alliance( VHDL) for Verilog?


Actually not a real one.

You can use "vasy" to translate verilog structural design to a vhdl
one. Else you can use iverilog to translate the verilog structural
design to a vhdl one.

Once you have the vhdl equivalent, you can resume the normal flow.

However the verilog to vhdl translations are not perfect, but I would
say try both conversions and benchmark the outcomes. I believe
iverilog's translator is a better one. I'm curious about the outcomes.
Let us know your progress.


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