Sun Mar 19 15:13:42 UTC 2006

Author: sailer

Update of /cvs/extras/rpms/ghdl/devel
In directory cvs-int.fedora.redhat.com:/tmp/cvs-serv9079

Modified Files:
	.cvsignore ghdl.spec sources 
Added Files:
	gcc41-ada-pr18302.patch gcc41-ada-tweaks.patch 
	gcc41-cfaval.patch gcc41-gnuc-rh-release.patch 
	gcc41-ia64-libunwind.patch gcc41-ice-hack.patch 
	gcc41-java-nomulti.patch gcc41-java-slow_pthread_self.patch 
	gcc41-mni.patch gcc41-ppc32-retaddr.patch 
	gcc41-ppc64-m32-m64-multilib-only.patch gcc41-rh184446.patch 
	gcc41-x86_64-sse3.patch 
Log Message:
use core gcc sources as baseline sources
does not work yet on x86_64, waiting for upstream to fix


gcc41-ada-pr18302.patch:

--- NEW FILE gcc41-ada-pr18302.patch ---
gcc/ada/
2004-11-28  James A. Morrison  <ja2morri at csclub.uwaterloo.ca>

	PR ada/18302
	* Make-lang.in (check-gnat): Set EXPECT environment variable.

testsuite/
2005-05-18  Jakub Jelinek  <jakub at redhat.com>

	* ada/acats/run_all.sh: Filter out spawn line from target_bit.

2004-11-28  James A. Morrison  <ja2morri at csclub.uwaterloo.ca>

	PR ada/18302
	* ada/acats/run_all.sh (target_run): Run test through run_test.expect.
	* ada/acats/run_test.expect: Expect script for ACATS tests.

--- gcc/testsuite/ada/acats/run_all.sh	(.../gcc-4_0-branch)	(revision 107266)
+++ gcc/testsuite/ada/acats/run_all.sh	(.../redhat/gcc-4_0-branch)	(revision 107414)
@@ -13,7 +13,8 @@
 gnatflags="-gnatws"
 
 target_run () {
-$*
+  LD_LIBRARY_PATH=$ADA_INCLUDE_PATH${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH} \
+    $EXPECT -f $testdir/run_test.exp $1 > $2
 }
 
 # End of customization section.
@@ -92,8 +93,8 @@
 
 # Find out the size in bit of an address on the target
 target_gnatmake $testdir/support/impbit.adb >> $dir/acats.log 2>&1
-target_run $dir/support/impbit > $dir/support/impbit.out 2>&1
-target_bit=`cat $dir/support/impbit.out`
+target_run $dir/support/impbit $dir/support/impbit.out 2>/dev/null
+target_bit=`egrep -v -e ^spawn $dir/support/impbit.out`
 echo target_bit="$target_bit" >> $dir/acats.log
 
 # Find out a suitable asm statement
@@ -259,7 +260,7 @@
       if [ ! -x $dir/tests/$chapter/$i/$binmain ]; then
          sync
       fi
-      target_run $dir/tests/$chapter/$i/$binmain > $dir/tests/$chapter/$i/${i}.log 2>&1
+      target_run $dir/tests/$chapter/$i/$binmain $dir/tests/$chapter/$i/${i}.log 2>&1
       cd $dir/tests/$chapter/$i
       cat ${i}.log >> $dir/acats.log
       egrep -e '(==== |\+\+\+\+ |\!\!\!\! )' ${i}.log > /dev/null 2>&1
--- gcc/testsuite/ada/acats/run_test.exp	(.../gcc-4_0-branch)	(revision 0)
+++ gcc/testsuite/ada/acats/run_test.exp	(.../redhat/gcc-4_0-branch)	(revision 107414)
@@ -0,0 +1,13 @@
+#!/usr/bin/expect -f
+
+if {[info exists env(DEJAGNU_TIMEOUT)]} {
+  set timeout $env(DEJAGNU_TIMEOUT)
+} else {
+  set timeout 300
+}
+
+spawn $argv
+expect timeout {
+	send_user "Program timed out.\n"
+	exit 1
+}
--- gcc/ada/Make-lang.in	(.../gcc-4_0-branch)	(revision 107266)
+++ gcc/ada/Make-lang.in	(.../redhat/gcc-4_0-branch)	(revision 107414)
@@ -809,6 +809,7 @@
 check-gnat:
 	test -d $(ACATSDIR) || mkdir -p $(ACATSDIR)
 	testdir=`cd ${srcdir}/${ACATSDIR}; ${PWD_COMMAND}`; \
+	EXPECT=${EXPECT} ; export EXPECT ; \
 	export testdir; cd $(ACATSDIR); $(SHELL) $${testdir}/run_acats $(CHAPTERS)
 
 .PHONY: check-gnat

gcc41-ada-tweaks.patch:

--- NEW FILE gcc41-ada-tweaks.patch ---
2004-10-04  Jakub Jelinek  <jakub at redhat.com>

	* gnat_ugn.texi: Add : and . to direntry.
	* gnat-style.texi: Change dircategory to GNU Ada tools.

2005-02-08  Jakub Jelinek  <jakub at redhat.com>

	* Makefile.in (gnatlib-shared-default): Disallow dlopening of
	libgnat.so.

--- gcc/ada/gnat-style.texi	(.../gcc-4_0-branch)	(revision 107266)
+++ gcc/ada/gnat-style.texi	(.../redhat/gcc-4_0-branch)	(revision 107414)
@@ -28,7 +28,7 @@
 @setchapternewpage odd
 
 
- at dircategory Programming
+ at dircategory GNU Ada tools
 @direntry
 * gnat-style: (gnat-style).      GNAT Coding Style
 @end direntry
--- gcc/ada/Makefile.in	(.../gcc-4_0-branch)	(revision 107266)
+++ gcc/ada/Makefile.in	(.../redhat/gcc-4_0-branch)	(revision 107414)
@@ -1316,7 +1316,7 @@
   LIBRARY_VERSION := $(LIB_VERSION)
 endif
 
-ifeq ($(strip $(filter-out powerpc% linux%,$(arch) $(osys))),)
+ifeq ($(strip $(filter-out powerpc% ppc% linux%,$(arch) $(osys))),)
   LIBGNAT_TARGET_PAIRS = \
   a-intnam.ads<a-intnam-linux.ads \
   s-inmaop.adb<s-inmaop-posix.adb \
@@ -1862,7 +1862,7 @@
 	     THREAD_KIND="$(THREAD_KIND)" \
              gnatlib
 	$(RM) rts/libgna*$(soext)
-	cd rts; ../../xgcc -B../../ -shared $(TARGET_LIBGCC2_CFLAGS) \
+	cd rts; ../../xgcc -B../../ -shared -Wl,-z,nodlopen $(TARGET_LIBGCC2_CFLAGS) \
 		-o libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
 		$(GNATRTL_NONTASKING_OBJS) $(LIBGNAT_OBJS) \
 		$(SO_OPTS)libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
--- gcc/ada/gnat_ugn.texi	(.../gcc-4_0-branch)	(revision 107266)
+++ gcc/ada/gnat_ugn.texi	(.../redhat/gcc-4_0-branch)	(revision 107414)
@@ -101,7 +101,7 @@
 @settitle @value{EDITION} User's Guide @value{PLATFORM}
 @dircategory GNU Ada tools
 @direntry
-* @value{EDITION} User's Guide (@value{FILE}) @value{PLATFORM}
+* @value{EDITION} User's Guide: (@value{FILE}). User's Guide for GNU Ada Tools.
 @end direntry
 
 @include gcc-common.texi
--- gcc/ada/link.c	(.../gcc-4_0-branch)	(revision 107266)
+++ gcc/ada/link.c	(.../redhat/gcc-4_0-branch)	(revision 107414)
@@ -164,9 +164,9 @@
 
 #elif defined (linux)
 const char *__gnat_object_file_option = "";
-const char *__gnat_run_path_option = "-Wl,-rpath,";
-char __gnat_shared_libgnat_default = STATIC;
-int __gnat_link_max = 8192;
+const char *__gnat_run_path_option = "";
+char __gnat_shared_libgnat_default = SHARED;
+int __gnat_link_max = 131072;
 unsigned char __gnat_objlist_file_supported = 1;
 unsigned char __gnat_using_gnu_linker = 1;
 const char *__gnat_object_library_extension = ".a";

gcc41-cfaval.patch:

--- NEW FILE gcc41-cfaval.patch ---
2006-03-03  Jakub Jelinek  <jakub at redhat.com>

	* unwind-dw2.h (_Unwind_FrameState): Add REG_SAVED_VAL_OFFSET
	and REG_SAVED_VAL_EXP constants.
	* unwind-dw2.c (struct _Unwind_Context): Add by_value array.
	(_Unwind_GetGR, _Unwind_SetGR, _Unwind_GetGRPtr, _Unwind_SetGRPtr):
	Handle regs stored by value.
	(_Unwind_SetGRValue, _Unwind_GRByValue): New functions.
	(execute_cfa_program): Handle DW_CFA_val_offset,
	DW_CFA_val_offset_sf and DW_CFA_val_expression.
	(uw_update_context_1): Handle REG_SAVED_REG with regs stored by
	value specially.  Handle REG_SAVED_VAL_OFFSET and REG_SAVED_VAL_EXP.
	(uw_install_context_1): Handle target regs stored by value.

	* gcc.target/i386/cleanup-1.c: New test.
	* gcc.target/i386/cleanup-2.c: New test.

--- gcc/unwind-dw2.h.jj	2006-03-01 14:43:03.000000000 +0100
+++ gcc/unwind-dw2.h	2006-03-01 15:02:51.000000000 +0100
@@ -53,7 +53,9 @@ typedef struct
 	REG_UNSAVED,
 	REG_SAVED_OFFSET,
 	REG_SAVED_REG,
-	REG_SAVED_EXP
+	REG_SAVED_EXP,
+	REG_SAVED_VAL_OFFSET,
+	REG_SAVED_VAL_EXP
       } how;
     } reg[DWARF_FRAME_REGISTERS+1];
 
--- gcc/unwind-dw2.c.jj	2006-03-01 14:43:03.000000000 +0100
+++ gcc/unwind-dw2.c	2006-03-02 18:59:34.000000000 +0100
@@ -72,6 +72,7 @@ struct _Unwind_Context
   struct dwarf_eh_bases bases;
   _Unwind_Word args_size;
   char signal_frame;
+  char by_value[DWARF_FRAME_REGISTERS+1];
 };
 
 /* Byte size of every register managed by these routines.  */
@@ -118,7 +119,7 @@ read_8u (const void *p) { const union un
 static inline unsigned long
 read_8s (const void *p) { const union unaligned *up = p; return up->s8; }
 
-/* Get the value of register REG as saved in CONTEXT.  */
+/* Get the value of register INDEX as saved in CONTEXT.  */
 
 inline _Unwind_Word
 _Unwind_GetGR (struct _Unwind_Context *context, int index)
@@ -136,6 +137,9 @@ _Unwind_GetGR (struct _Unwind_Context *c
   size = dwarf_reg_size_table[index];
   ptr = context->reg[index];
 
+  if (context->by_value[index])
+    return (_Unwind_Word) (_Unwind_Internal_Ptr) ptr;
+
   /* This will segfault if the register hasn't been saved.  */
   if (size == sizeof(_Unwind_Ptr))
     return * (_Unwind_Ptr *) ptr;
@@ -160,7 +164,7 @@ _Unwind_GetCFA (struct _Unwind_Context *
   return (_Unwind_Ptr) context->cfa;
 }
 
-/* Overwrite the saved value for register REG in CONTEXT with VAL.  */
+/* Overwrite the saved value for register INDEX in CONTEXT with VAL.  */
 
 inline void
 _Unwind_SetGR (struct _Unwind_Context *context, int index, _Unwind_Word val)
@@ -171,6 +175,13 @@ _Unwind_SetGR (struct _Unwind_Context *c
   index = DWARF_REG_TO_UNWIND_COLUMN (index);
   gcc_assert (index < (int) sizeof(dwarf_reg_size_table));
   size = dwarf_reg_size_table[index];
+
+  if (context->by_value[index])
+    {
+      context->reg[index] = (void *) (_Unwind_Internal_Ptr) val;
+      return;
+    }
+
   ptr = context->reg[index];
 
   if (size == sizeof(_Unwind_Ptr))
@@ -188,6 +199,8 @@ static inline void *
 _Unwind_GetGRPtr (struct _Unwind_Context *context, int index)
 {
   index = DWARF_REG_TO_UNWIND_COLUMN (index);
+  if (context->by_value[index])
+    return &context->reg[index];
   return context->reg[index];
 }
 
@@ -197,9 +210,34 @@ static inline void
 _Unwind_SetGRPtr (struct _Unwind_Context *context, int index, void *p)
 {
   index = DWARF_REG_TO_UNWIND_COLUMN (index);
+  context->by_value[index] = 0;
   context->reg[index] = p;
 }
 
+/* Overwrite the saved value for register INDEX in CONTEXT with VAL.  */
+
+static inline void
+_Unwind_SetGRValue (struct _Unwind_Context *context, int index,
+		    _Unwind_Word val)
+{
+  index = DWARF_REG_TO_UNWIND_COLUMN (index);
+  gcc_assert (index < (int) sizeof(dwarf_reg_size_table));
+  gcc_assert (dwarf_reg_size_table[index] == sizeof (_Unwind_Ptr));
+
+  context->by_value[index] = 1;
+  context->reg[index] = (void *) (_Unwind_Internal_Ptr) val;
+}
+
+/* Return non-zero if register INDEX is stored by value rather than
+   by reference.  */
+
+static inline int
+_Unwind_GRByValue (struct _Unwind_Context *context, int index)
+{
+  index = DWARF_REG_TO_UNWIND_COLUMN (index);
+  return context->by_value[index];
+}
+
 /* Retrieve the return address for CONTEXT.  */
 
 inline _Unwind_Ptr
@@ -922,7 +960,7 @@ execute_cfa_program (const unsigned char
 	  insn_ptr += utmp;
 	  break;
 
-	  /* From the dwarf3 draft.  */
+	  /* Dwarf3.  */
 	case DW_CFA_offset_extended_sf:
 	  insn_ptr = read_uleb128 (insn_ptr, &reg);
 	  insn_ptr = read_sleb128 (insn_ptr, &stmp);
@@ -945,6 +983,33 @@ execute_cfa_program (const unsigned char
 	  /* cfa_how deliberately not set.  */
 	  break;
 
+	case DW_CFA_val_offset:
+	  insn_ptr = read_uleb128 (insn_ptr, &reg);
+	  insn_ptr = read_uleb128 (insn_ptr, &utmp);
+	  offset = (_Unwind_Sword) utmp * fs->data_align;
+	  fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how
+	    = REG_SAVED_VAL_OFFSET;
+	  fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = offset;
+	  break;
+
+	case DW_CFA_val_offset_sf:
+	  insn_ptr = read_uleb128 (insn_ptr, &reg);
+	  insn_ptr = read_sleb128 (insn_ptr, &stmp);
+	  offset = stmp * fs->data_align;
+	  fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how
+	    = REG_SAVED_VAL_OFFSET;
+	  fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = offset;
+	  break;
+
+	case DW_CFA_val_expression:
+	  insn_ptr = read_uleb128 (insn_ptr, &reg);
+	  fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how
+	    = REG_SAVED_VAL_EXP;
+	  fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.exp = insn_ptr;
+	  insn_ptr = read_uleb128 (insn_ptr, &utmp);
+	  insn_ptr += utmp;
+	  break;
+
 	case DW_CFA_GNU_window_save:
 	  /* ??? Hardcoded for SPARC register window configuration.  */
 	  for (reg = 16; reg < 32; ++reg)
@@ -1113,7 +1178,7 @@ typedef union { _Unwind_Ptr ptr; _Unwind
 
 static inline void
 _Unwind_SetSpColumn (struct _Unwind_Context *context, void *cfa,
-                     _Unwind_SpTmp *tmp_sp)
+		     _Unwind_SpTmp *tmp_sp)
 {
   int size = dwarf_reg_size_table[__builtin_dwarf_sp_column ()];
   
@@ -1194,9 +1259,14 @@ uw_update_context_1 (struct _Unwind_Cont
 	break;
 
       case REG_SAVED_REG:
-	_Unwind_SetGRPtr
-	  (context, i,
-	   _Unwind_GetGRPtr (&orig_context, fs->regs.reg[i].loc.reg));
+	if (_Unwind_GRByValue (&orig_context, fs->regs.reg[i].loc.reg))
+	  _Unwind_SetGRValue (context, i,
+			      _Unwind_GetGR (&orig_context,
+					     fs->regs.reg[i].loc.reg));
+	else
+	  _Unwind_SetGRPtr (context, i,
+			    _Unwind_GetGRPtr (&orig_context,
+					      fs->regs.reg[i].loc.reg));
 	break;
 
       case REG_SAVED_EXP:
@@ -1211,6 +1281,25 @@ uw_update_context_1 (struct _Unwind_Cont
 	  _Unwind_SetGRPtr (context, i, (void *) val);
 	}
 	break;
+
+      case REG_SAVED_VAL_OFFSET:
+	_Unwind_SetGRValue (context, i,
+			    (_Unwind_Internal_Ptr)
+			    (cfa + fs->regs.reg[i].loc.offset));
+	break;
+
+      case REG_SAVED_VAL_EXP:
+	{
+	  const unsigned char *exp = fs->regs.reg[i].loc.exp;
+	  _Unwind_Word len;
+	  _Unwind_Ptr val;
+
+	  exp = read_uleb128 (exp, &len);
+	  val = execute_stack_op (exp, exp + len, &orig_context,
+				  (_Unwind_Ptr) cfa);
+	  _Unwind_SetGRValue (context, i, val);
+	}
+	break;
       }
 
   context->signal_frame = fs->signal_frame;
@@ -1327,14 +1416,31 @@ uw_install_context_1 (struct _Unwind_Con
   /* If the target frame does not have a saved stack pointer,
      then set up the target's CFA.  */
   if (!_Unwind_GetGRPtr (target, __builtin_dwarf_sp_column ()))
-	_Unwind_SetSpColumn (target, target->cfa, &sp_slot);
+    _Unwind_SetSpColumn (target, target->cfa, &sp_slot);
 
   for (i = 0; i < DWARF_FRAME_REGISTERS; ++i)
     {
       void *c = current->reg[i];
       void *t = target->reg[i];
 
-      if (t && c && t != c)
+      gcc_assert (current->by_value[i] == 0);
+      if (target->by_value[i] && c)
+	{
+	  _Unwind_Word w;
+	  _Unwind_Ptr p;
+	  if (dwarf_reg_size_table[i] == sizeof (_Unwind_Word))
+	    {
+	      w = (_Unwind_Internal_Ptr) t;
+	      memcpy (c, &w, sizeof (_Unwind_Word));
+	    }
+	  else
+	    {
+	      gcc_assert (dwarf_reg_size_table[i] == sizeof (_Unwind_Ptr));
+	      p = (_Unwind_Internal_Ptr) t;
+	      memcpy (c, &p, sizeof (_Unwind_Ptr));
+	    }
+	}
+      else if (t && c && t != c)
 	memcpy (c, t, dwarf_reg_size_table[i]);
     }
 
--- gcc/testsuite/gcc.target/i386/cleanup-1.c.jj	2006-03-03 11:25:14.000000000 +0100
+++ gcc/testsuite/gcc.target/i386/cleanup-1.c	2006-03-03 11:25:48.000000000 +0100
@@ -0,0 +1,240 @@
+/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */
+/* { dg-options "-fexceptions -fnon-call-exceptions -fasynchronous-unwind-tables -O2" } */
+/* Test complex CFA value expressions.  */
+
+#include <unwind.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <unistd.h>
+
+static _Unwind_Reason_Code
+force_unwind_stop (int version, _Unwind_Action actions,
+		   _Unwind_Exception_Class exc_class,
+		   struct _Unwind_Exception *exc_obj,
+		   struct _Unwind_Context *context,
+		   void *stop_parameter)
+{
+  if (actions & _UA_END_OF_STACK)
+    abort ();
+  return _URC_NO_REASON;
+}
+
+static void
+force_unwind ()
+{
+  struct _Unwind_Exception *exc = malloc (sizeof (*exc));
+  memset (&exc->exception_class, 0, sizeof (exc->exception_class));
+  exc->exception_cleanup = 0;
+
+  _Unwind_ForcedUnwind (exc, force_unwind_stop, 0);
+  abort ();
+}
+
+int count;
+
+static void
+counter (void *p __attribute__((unused)))
+{
+  ++count;
+}
+
+static void
+handler (void *p __attribute__((unused)))
+{
+  if (count != 2)
+    abort ();
+  _exit (0);
+}
+
+static int __attribute__((noinline))
+fn5 (void)
+{
+  char dummy __attribute__((cleanup (counter)));
+  force_unwind ();
+  return 0;
+}
+
+void
+bar (void)
+{
+  char dummy __attribute__((cleanup (counter)));
+  fn5 ();
+}
+
+void __attribute__((noinline))
+foo (int x)
+{
+  char buf[256];
+#ifdef __i386__
+  __asm (
+	"testl	%0, %0\n\t"
+	"jnz	1f\n\t"
+	".subsection 1\n\t"
+	".type	_L_mutex_lock_%=, @function\n"
+"_L_mutex_lock_%=:\n"
+"1:\t"	"leal	%1, %%ecx\n"
+"2:\t"	"call	bar\n"
+"3:\t"	"jmp	18f\n"
+"4:\t"	".size _L_mutex_lock_%=, .-_L_mutex_lock_%=\n\t"
+	".previous\n\t"
+	".section	.eh_frame,\"a\", at progbits\n"
+"5:\t"	".long	7f-6f	# Length of Common Information Entry\n"
+"6:\t"	".long	0x0	# CIE Identifier Tag\n\t"
+	".byte	0x1	# CIE Version\n\t"
+	".ascii \"zR\\0\"	# CIE Augmentation\n\t"
+	".uleb128 0x1	# CIE Code Alignment Factor\n\t"
+	".sleb128 -4	# CIE Data Alignment Factor\n\t"
+	".byte	0x8	# CIE RA Column\n\t"
+	".uleb128 0x1	# Augmentation size\n\t"
+	".byte	0x1b	# FDE Encoding (pcrel sdata4)\n\t"
+	".byte	0xc	# DW_CFA_def_cfa\n\t"
+	".uleb128 0x4\n\t"
+	".uleb128 0x0\n\t"
+	".align 4\n"
+"7:\t"	".long	17f-8f	# FDE Length\n"
+"8:\t"	".long	8b-5b	# FDE CIE offset\n\t"
+	".long	1b-.	# FDE initial location\n\t"
+	".long	4b-1b	# FDE address range\n\t"
+	".uleb128 0x0	# Augmentation size\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x8\n\t"
+	".uleb128 10f-9f\n"
+"9:\t"	".byte	0x78	# DW_OP_breg8\n\t"
+	".sleb128 3b-1b\n"
+"10:\t"	".byte	0x40 + (2b-1b) # DW_CFA_advance_loc\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x8\n\t"
+	".uleb128 12f-11f\n"
+"11:\t"	".byte	0x78	# DW_OP_breg8\n\t"
+	".sleb128 3b-2b\n"
+"12:\t"	".byte	0x40 + (3b-2b-1) # DW_CFA_advance_loc\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x8\n\t"
+	".uleb128 16f-13f\n"
+"13:\t"	".byte	0x78	# DW_OP_breg8\n\t"
+	".sleb128 15f-14f\n\t"
+	".byte	0x0d	# DW_OP_const4s\n"
+"14:\t"	".4byte	3b-.\n\t"
+	".byte	0x1c	# DW_OP_minus\n\t"
+	".byte	0x0d	# DW_OP_const4s\n"
+"15:\t"	".4byte	18f-.\n\t"
+	".byte	0x22	# DW_OP_plus\n"
+"16:\t"	".align 4\n"
+"17:\t"	".previous\n"
+"18:"
+	: : "r" (x), "m" (x), "r" (buf)
+	: "memory", "eax", "edx", "ecx");
+#elif defined __x86_64__
+  __asm (
+	"testl	%0, %0\n\t"
+	"jnz	1f\n\t"
+	".subsection 1\n\t"
+	".type	_L_mutex_lock_%=, @function\n"
+"_L_mutex_lock_%=:\n"
+"1:\t"	"leaq	%1, %%rdi\n"
+"2:\t"	"subq	$128, %%rsp\n"
+"3:\t"	"call	bar\n"
+"4:\t"	"addq	$128, %%rsp\n"
+"5:\t"	"jmp	24f\n"
+"6:\t"	".size _L_mutex_lock_%=, .-_L_mutex_lock_%=\n\t"
+	".previous\n\t"
+	".section	.eh_frame,\"a\", at progbits\n"
+"7:\t"	".long	9f-8f	# Length of Common Information Entry\n"
+"8:\t"	".long	0x0	# CIE Identifier Tag\n\t"
+	".byte	0x1	# CIE Version\n\t"
+	".ascii \"zR\\0\"	# CIE Augmentation\n\t"
+	".uleb128 0x1	# CIE Code Alignment Factor\n\t"
+	".sleb128 -8	# CIE Data Alignment Factor\n\t"
+	".byte	0x10	# CIE RA Column\n\t"
+	".uleb128 0x1	# Augmentation size\n\t"
+	".byte	0x1b	# FDE Encoding (pcrel sdata4)\n\t"
+	".byte	0x12	# DW_CFA_def_cfa_sf\n\t"
+	".uleb128 0x7\n\t"
+	".sleb128 16\n\t"
+	".align 8\n"
+"9:\t"	".long	23f-10f	# FDE Length\n"
+"10:\t"	".long	10b-7b	# FDE CIE offset\n\t"
+	".long	1b-.	# FDE initial location\n\t"
+	".long	6b-1b	# FDE address range\n\t"
+	".uleb128 0x0	# Augmentation size\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 12f-11f\n"
+"11:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 4b-1b\n"
+"12:\t"	".byte	0x40 + (2b-1b) # DW_CFA_advance_loc\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 14f-13f\n"
+"13:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 4b-2b\n"
+"14:\t"	".byte	0x40 + (3b-2b) # DW_CFA_advance_loc\n\t"
+	".byte	0x0e	# DW_CFA_def_cfa_offset\n\t"
+	".uleb128 0\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 16f-15f\n"
+"15:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 4b-3b\n"
+"16:\t"	".byte	0x40 + (4b-3b-1) # DW_CFA_advance_loc\n\t"
+	".byte	0x0e	# DW_CFA_def_cfa_offset\n\t"
+	".uleb128 128\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 20f-17f\n"
+"17:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 19f-18f\n\t"
+	".byte	0x0d	# DW_OP_const4s\n"
+"18:\t"	".4byte	4b-.\n\t"
+	".byte	0x1c	# DW_OP_minus\n\t"
+	".byte	0x0d	# DW_OP_const4s\n"
+"19:\t"	".4byte	24f-.\n\t"
+	".byte	0x22	# DW_OP_plus\n"
+"20:\t"	".byte	0x40 + (5b-4b+1) # DW_CFA_advance_loc\n\t"
+	".byte	0x13	# DW_CFA_def_cfa_offset_sf\n\t"
+	".sleb128 16\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 22f-21f\n"
+"21:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 4b-5b\n"
+"22:\t"	".align 8\n"
+"23:\t"	".previous\n"
+"24:"
+	: : "r" (x), "m" (x), "r" (buf)
+	: "memory", "rax", "rdx", "rcx", "rsi", "rdi",
+	  "r8", "r9", "r10", "r11");
+#else
+# error Unsupported test architecture
+#endif
+}
+
+static int __attribute__((noinline))
+fn2 (void)
+{
+  foo (3);
+  return 0;
+}
+
+static int __attribute__((noinline))
+fn1 (void)
+{
+  fn2 ();
+  return 0;
+}
+
+static void *
+fn0 (void)
+{
+  char dummy __attribute__((cleanup (handler)));
+  fn1 ();
+  return 0;
+}
+
+int
+main (void)
+{
+  fn0 ();
+  return 0;
+}
--- gcc/testsuite/gcc.target/i386/cleanup-2.c.jj	2006-03-03 11:25:26.000000000 +0100
+++ gcc/testsuite/gcc.target/i386/cleanup-2.c	2006-03-03 11:27:06.000000000 +0100
@@ -0,0 +1,205 @@
+/* { dg-do run { target { { i?86-*-linux* x86_64-*-linux* } && lp64 } } } */
+/* { dg-options "-fexceptions -fnon-call-exceptions -fasynchronous-unwind-tables -O2" } */
+/* Test complex CFA value expressions.  */
+
+#include <unwind.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <unistd.h>
+
+static _Unwind_Reason_Code
+force_unwind_stop (int version, _Unwind_Action actions,
+		   _Unwind_Exception_Class exc_class,
+		   struct _Unwind_Exception *exc_obj,
+		   struct _Unwind_Context *context,
+		   void *stop_parameter)
+{
+  if (actions & _UA_END_OF_STACK)
+    abort ();
+  return _URC_NO_REASON;
+}
+
+static void
+force_unwind ()
+{
+  struct _Unwind_Exception *exc = malloc (sizeof (*exc));
+  memset (&exc->exception_class, 0, sizeof (exc->exception_class));
+  exc->exception_cleanup = 0;
+
+  _Unwind_ForcedUnwind (exc, force_unwind_stop, 0);
+  abort ();
+}
+
+int count;
+
+static void
+counter (void *p __attribute__((unused)))
+{
+  ++count;
+}
+
+static void
+handler (void *p __attribute__((unused)))
+{
+  if (count != 2)
+    abort ();
+  _exit (0);
+}
+
+static int __attribute__((noinline))
+fn5 (void)
+{
+  char dummy __attribute__((cleanup (counter)));
+  force_unwind ();
+  return 0;
+}
+
+void
+bar (void)
+{
+  char dummy __attribute__((cleanup (counter)));
+  fn5 ();
+}
+
+void __attribute__((noinline))
+foo (int x)
+{
+  char buf[256];
+#ifdef __x86_64__
+  __asm (
+	"testl	%0, %0\n\t"
+	"jnz	1f\n\t"
+	".subsection 1\n\t"
+	".type	_L_mutex_lock_%=, @function\n"
+"_L_mutex_lock_%=:\n"
+"1:\t"	"leaq	%1, %%rdi\n"
+"2:\t"	"subq	$128, %%rsp\n"
+"3:\t"	"call	bar\n"
+"4:\t"	"addq	$128, %%rsp\n"
+"5:\t"	"jmp	21f\n"
+"6:\t"	".size _L_mutex_lock_%=, .-_L_mutex_lock_%=\n\t"
+	".previous\n\t"
+	".section	.eh_frame,\"a\", at progbits\n"
+"7:\t"	".long	9f-8f	# Length of Common Information Entry\n"
+"8:\t"	".long	0x0	# CIE Identifier Tag\n\t"
+	".byte	0x1	# CIE Version\n\t"
+	".ascii \"zR\\0\"	# CIE Augmentation\n\t"
+	".uleb128 0x1	# CIE Code Alignment Factor\n\t"
+	".sleb128 -8	# CIE Data Alignment Factor\n\t"
+	".byte	0x10	# CIE RA Column\n\t"
+	".uleb128 0x1	# Augmentation size\n\t"
+	".byte	0x1b	# FDE Encoding (pcrel sdata4)\n\t"
+	".byte	0xc	# DW_CFA_def_cfa\n\t"
+	".uleb128 0x7\n\t"
+	".uleb128 0x0\n\t"
+	".align 8\n"
+"9:\t"	".long	20f-10f	# FDE Length\n"
+"10:\t"	".long	10b-7b	# FDE CIE offset\n\t"
+	".long	1b-.	# FDE initial location\n\t"
+	".long	6b-1b	# FDE address range\n\t"
+	".uleb128 0x0	# Augmentation size\n\t"
+	/* This CFA expression computes the address right
+	   past the jnz instruction above, from %rip somewhere
+	   within the _L_mutex_lock_%= subsection.  */
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 19f-11f\n"
+"11:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 0\n"
+"12:\t"	".byte	0x12	# DW_OP_dup\n\t"
+	".byte	0x94	# DW_OP_deref_size\n\t"
+	".byte	1\n\t"
+	".byte	0x12	# DW_OP_dup\n\t"
+	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	0x48\n\t"
+	".byte	0x2e	# DW_OP_ne\n\t"
+	".byte	0x28	# DW_OP_bra\n\t"
+	".2byte	16f-13f\n"
+"13:\t"	".byte	0x13	# DW_OP_drop\n\t"
+	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 1\n\t"
+	".byte	0x12	# DW_OP_dup\n\t"
+	".byte	0x94	# DW_OP_deref_size\n\t"
+	".byte	1\n\t"
+	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	0x81\n\t"
+	".byte	0x2e	# DW_OP_ne\n\t"
+	".byte	0x28	# DW_OP_bra\n\t"
+	".2byte	15f-14f\n"
+"14:\t"	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 3b-2b-1\n\t"
+	".byte	0x2f	# DW_OP_skip\n\t"
+	".2byte	12b-15f\n"
+"15:\t"	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 2b-1b-1\n\t"
+	".byte	0x2f	# DW_OP_skip\n\t"
+	".2byte	12b-16f\n"
+"16:\t"	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	0xe8\n\t"
+	".byte	0x2e	# DW_OP_ne\n\t"
+	".byte	0x28	# DW_OP_bra\n\t"
+	".2byte	18f-17f\n"
+"17:\t"	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 4b-3b\n\t"
+	".byte	0x2f	# DW_OP_skip\n\t"
+	".2byte	12b-18f\n"
+"18:\t"	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 1\n\t"
+	".byte	0x12	# DW_OP_dup\n\t"
+	".byte	0x94	# DW_OP_deref_size\n\t"
+	".byte	4\n\t"
+	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	72 - (6b-5b) * 8 # (6b-5b) == 5 ? 32 : 56\n\t"
+	".byte	0x24	# DW_OP_shl\n\t"
+	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	72 - (6b-5b) * 8 # (6b-5b) == 5 ? 32 : 56\n\t"
+	".byte	0x26	# DW_OP_shra\n\t"
+	".byte	0x22	# DW_OP_plus\n\t"
+	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 6b-5b-1\n"
+"19:\t"	".byte	0x40 + (3b-1b) # DW_CFA_advance_loc\n\t"
+	".byte	0xe	# DW_CFA_def_cfa_offset\n\t"
+	".uleb128 128\n\t"
+	".byte	0x40 + (5b-3b) # DW_CFA_advance_loc\n\t"
+	".byte	0xe	# DW_CFA_def_cfa_offset\n\t"
+	".uleb128 0\n\t"
+	".align 8\n"
+"20:\t"	".previous\n"
+"21:"
+	: : "r" (x), "m" (x), "r" (buf)
+	: "memory", "rax", "rdx", "rcx", "rsi", "rdi",
+	  "r8", "r9", "r10", "r11");
+#else
+# error Unsupported test architecture
+#endif
+}
+
+static int __attribute__((noinline))
+fn2 (void)
+{
+  foo (3);
+  return 0;
+}
+
+static int __attribute__((noinline))
+fn1 (void)
+{
+  fn2 ();
+  return 0;
+}
+
+static void *
+fn0 (void)
+{
+  char dummy __attribute__((cleanup (handler)));
+  fn1 ();
+  return 0;
+}
+
+int
+main (void)
+{
+  fn0 ();
+  return 0;
+}

gcc41-gnuc-rh-release.patch:

--- NEW FILE gcc41-gnuc-rh-release.patch ---
2004-10-19  Jakub Jelinek  <jakub at redhat.com>

	* c-cppbuiltin.c (define__GNUC__): Also define __GNUC_RH_RELEASE__.

--- gcc/c-cppbuiltin.c.jj	2004-10-07 21:27:38.000000000 +0200
+++ gcc/c-cppbuiltin.c	2004-10-19 11:41:50.000000000 +0200
@@ -257,13 +257,13 @@ define__GNUC__ (void)
 {
   /* The format of the version string, enforced below, is
      ([^0-9]*-)?[0-9]+[.][0-9]+([.][0-9]+)?([- ].*)?  */
-  const char *q, *v = version_string;
+  const char *q, *v = version_string, *vstart, *vend;
 
   while (*v && !ISDIGIT (*v))
     v++;
   gcc_assert (*v && (v <= version_string || v[-1] == '-'));
 
-  q = v;
+  vstart = q = v;
   while (ISDIGIT (*v))
     v++;
   builtin_define_with_value_n ("__GNUC__", q, v - q);
@@ -289,6 +289,27 @@ define__GNUC__ (void)
     builtin_define_with_value_n ("__GNUC_PATCHLEVEL__", "0", 1);
 
   gcc_assert (!*v || *v == ' ' || *v == '-');
+
+  vend = v;
+  v = strchr (v, '(');
+  if (v != NULL && strncmp (v + 1, "Red Hat ", 8) == 0)
+    {
+      v += 9;
+      if (strncmp (v, "Linux ", 6) == 0)
+	v += 6;
+
+      gcc_assert (strncmp (v, vstart, vend - vstart) == 0);
+      gcc_assert (v[vend - vstart] == '-');
+
+      v += vend - vstart + 1;
+      q = v;
+      gcc_assert (ISDIGIT (*v));
+      while (ISDIGIT (*v))
+	v++;
+      builtin_define_with_value_n ("__GNUC_RH_RELEASE__", q, v - q);
+
+      gcc_assert (!*v || *v == ')' || *v == '.');
+    }
 }
 
 /* Define macros used by <stdint.h>.  Currently only defines limits

gcc41-ia64-libunwind.patch:

--- NEW FILE gcc41-ia64-libunwind.patch ---
2004-11-27  Jakub Jelinek  <jakub at redhat.com>

	* config.gcc (ia64*-*-linux*): If native and libelf is installed,
	use ia64/t-glibc-no-libunwind instead of the other t-*unwind*
	fragments.
	* config/ia64/t-glibc-no-libunwind: New file.
	* config/ia64/change-symver.c: New file.
	* config/ia64/unwind-ia64.c: If USE_SYMVER_GLOBAL and SHARED,
	define _Unwind_* to __symverglobal_Unwind_*.
	(alias): Undefine.
	(symverglobal): Define.  Use it on _Unwind_*.
	* config/ia64/mkmap-symver-multi.awk: New file.
	* config/ia64/libgcc-ia64-no-libunwind.ver: New file.

--- gcc/config.gcc.jj	2004-10-04 08:55:44.000000000 -0400
+++ gcc/config.gcc	2004-11-13 05:23:50.000000000 -0500
@@ -1185,9 +1185,16 @@ ia64*-*-freebsd*)
 	;;
 ia64*-*-linux*)
 	tm_file="${tm_file} dbxelf.h elfos.h svr4.h linux.h ia64/sysv4.h ia64/linux.h"
-	tmake_file="${tmake_file} ia64/t-ia64 t-libunwind ia64/t-glibc"
-	if test x$with_system_libunwind != xyes ; then
-		tmake_file="${tmake_file} t-libunwind-elf ia64/t-glibc-libunwind"
+	tmake_file="${tmake_file} ia64/t-ia64"
+	if test x${target} = x${host} && test x${target} = x${build} \
+	   && grep gelf_getverdef /usr/include/gelf.h > /dev/null 2>&1 \
+	   && test -f /usr/lib/libelf.so; then
+		tmake_file="${tmake_file} ia64/t-glibc-no-libunwind"
+	else
+		tmake_file="${tmake_file} t-libunwind ia64/t-glibc"
+		if test x$with_system_libunwind != xyes ; then
+			tmake_file="${tmake_file} t-libunwind-elf ia64/t-glibc-libunwind"
+		fi
 	fi
 	target_cpu_default="MASK_GNU_AS|MASK_GNU_LD"
 	extra_parts="crtbegin.o crtend.o crtbeginS.o crtendS.o crtfastmath.o"
--- gcc/config/ia64/t-glibc-no-libunwind.jj	2004-02-18 10:27:36.000000000 -0500
+++ gcc/config/ia64/t-glibc-no-libunwind	2004-11-15 09:56:33.000000000 -0500
@@ -0,0 +1,30 @@
+# Don't use system libunwind library on IA-64 GLIBC based system,
+# but make _Unwind_* symbols unversioned, so that created programs
+# are usable even when libgcc_s uses libunwind.
+LIB2ADDEH += $(srcdir)/config/ia64/fde-glibc.c
+SHLIB_MAPFILES += $(srcdir)/config/ia64/libgcc-ia64-no-libunwind.ver
+SHLIB_MKMAP = $(srcdir)/config/ia64/mkmap-symver-multi.awk
+
+SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \
+	-Wl,--soname=$(SHLIB_SONAME) \
+	-Wl,--version-script=$(SHLIB_MAP) \
+	-o $(SHLIB_DIR)/$(SHLIB_SONAME).tmp @multilib_flags@ $(SHLIB_OBJS) -lc && \
+	rm -f $(SHLIB_DIR)/$(SHLIB_SOLINK) && \
+	if [ -f $(SHLIB_DIR)/$(SHLIB_SONAME) ]; then \
+	  mv -f $(SHLIB_DIR)/$(SHLIB_SONAME) \
+		$(SHLIB_DIR)/$(SHLIB_SONAME).backup; \
+	else true; fi && \
+	gcc -O2 -o $(SHLIB_DIR)/$(SHLIB_SONAME).tweak \
+	  $(srcdir)/config/ia64/change-symver.c -lelf && \
+	$(SHLIB_DIR)/$(SHLIB_SONAME).tweak $(SHLIB_DIR)/$(SHLIB_SONAME).tmp \
+	GCC_3.4.2 _GLOBAL_ \
+	_Unwind_GetGR _Unwind_RaiseException _Unwind_GetRegionStart _Unwind_SetIP \
+	_Unwind_GetIP _Unwind_GetLanguageSpecificData _Unwind_Resume \
+	_Unwind_DeleteException _Unwind_SetGR _Unwind_ForcedUnwind \
+	_Unwind_Backtrace _Unwind_FindEnclosingFunction _Unwind_GetCFA \
+	_Unwind_Resume_or_Rethrow _Unwind_GetBSP && \
+	rm -f $(SHLIB_DIR)/$(SHLIB_SONAME).tweak && \
+	mv $(SHLIB_DIR)/$(SHLIB_SONAME).tmp $(SHLIB_DIR)/$(SHLIB_SONAME) && \
+	$(LN_S) $(SHLIB_SONAME) $(SHLIB_DIR)/$(SHLIB_SOLINK)
+
+TARGET_LIBGCC2_CFLAGS += -DUSE_SYMVER_GLOBAL
--- gcc/config/ia64/change-symver.c.jj	2004-02-18 10:27:36.000000000 -0500
+++ gcc/config/ia64/change-symver.c	2004-11-13 05:23:50.000000000 -0500
@@ -0,0 +1,211 @@
+#define _GNU_SOURCE 1
+#define _FILE_OFFSET_BITS 64
+#include <endian.h>
+#include <errno.h>
+#include <error.h>
+#include <fcntl.h>
+#include <fnmatch.h>
+#include <gelf.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+int
+compute_veridx (const char *name, Elf *elf, Elf_Data *verd, GElf_Shdr *verd_shdr)
+{
+  if (strcmp (name, "_GLOBAL_") == 0)
+    return 1;
+
+  int cnt;
+  size_t offset = 0;
+  for (cnt = verd_shdr->sh_info; --cnt >= 0; )
+    {
+      GElf_Verdef defmem;
+      GElf_Verdef *def;
+      GElf_Verdaux auxmem;
+      GElf_Verdaux *aux;
+      unsigned int auxoffset;
+
+      /* Get the data at the next offset.  */
+      def = gelf_getverdef (verd, offset, &defmem);
+      if (def == NULL)
+	break;
+
+      auxoffset = offset + def->vd_aux;
+      aux = gelf_getverdaux (verd, auxoffset, &auxmem);
+      if (aux == NULL)
+	break;
+
+      if (strcmp (name, elf_strptr (elf, verd_shdr->sh_link,
+		  aux->vda_name)) == 0)
+	return def->vd_ndx;
+
+      /* Find the next offset.  */
+      offset += def->vd_next;
+    }
+
+  return -1;
+}
+
+int
+main (int argc, char **argv)
+{
+  if (argc < 4)
+    error (1, 0, "Usage: change_symver library from_symver to_symver symbol...\nExample: change_symver libfoo.so FOO_1.0 *global* bar baz");
+
+  const char *fname = argv[1];
+
+  /* Open the file.  */
+  int fd;
+  fd = open (fname, O_RDWR);
+  if (fd == -1)
+    error (1, errno, fname);
+
+  elf_version (EV_CURRENT);
+
+  /* Now get the ELF descriptor.  */
+  Elf *elf = elf_begin (fd, ELF_C_READ_MMAP, NULL);
+  if (elf == NULL || elf_kind (elf) != ELF_K_ELF)
+    error (1, 0, "Couldn't open %s: %s", fname, elf_errmsg (-1));
+
+  size_t shstrndx;
+  /* Get the section header string table index.  */
+  if (elf_getshstrndx (elf, &shstrndx) < 0)
+    error (1, 0, "cannot get shstrndx from %s", fname);
+
+  GElf_Ehdr ehdr_mem;
+  GElf_Ehdr *ehdr;
+
+  /* We need the ELF header in a few places.  */
+  ehdr = gelf_getehdr (elf, &ehdr_mem);
+  if (ehdr == NULL)
+    error (1, 0, "couldn't get ELF headers %s: %s", fname, elf_errmsg (-1));
+
+  Elf_Scn *scn = NULL;
+  GElf_Shdr shdr_mem, verd_shdr, ver_shdr, dynsym_shdr;
+  Elf_Data *ver = NULL, *verd = NULL, *dynsym = NULL;
+
+  while ((scn = elf_nextscn (elf, scn)) != NULL)
+    {
+      GElf_Shdr *shdr = gelf_getshdr (scn, &shdr_mem);
+
+      if (shdr == NULL)
+	error (1, 0, "couldn't get shdr from %s", fname);
+
+      if ((shdr->sh_flags & SHF_ALLOC) != 0)
+	{
+	  const char *name = elf_strptr (elf, shstrndx, shdr->sh_name);
+	  Elf_Data **p;
+
+	  if (strcmp (name, ".gnu.version") == 0)
+	    {
+	      p = &ver;
+	      ver_shdr = *shdr;
+	    }
+	  else if (strcmp (name, ".gnu.version_d") == 0)
+	    {
+	      p = &verd;
+	      verd_shdr = *shdr;
+	    }
+	  else if (strcmp (name, ".dynsym") == 0)
+	    {
+	      p = &dynsym;
+	      dynsym_shdr = *shdr;
+	    }
+	  else
+	    continue;
+
+	  if (*p != NULL)
+	    error (1, 0, "Two %s sections in %s", name, fname);
+	  *p = elf_getdata (scn, NULL);
+	  if (*p == NULL || elf_getdata (scn, *p) != NULL)
+	    error (1, 0, "No data or non-contiguous data in %s section in %s",
+		   name, fname);
+	}
+    }
+
+  if (ver == NULL || verd == NULL || dynsym == NULL)
+    error (1, 0, "Couldn't find one of the needed sections in %s", fname);
+
+  int from_idx = compute_veridx (argv[2], elf, verd, &verd_shdr);
+  if (from_idx == -1)
+    error (1, 0, "Could not find symbol version %s in %s", argv[2], fname);
+
+  int to_idx = compute_veridx (argv[3], elf, verd, &verd_shdr);
+  if (to_idx == -1)
+    error (1, 0, "Could not find symbol version %s in %s", argv[3], fname);
+
+  if (dynsym_shdr.sh_entsize != gelf_fsize (elf, ELF_T_SYM, 1, ehdr->e_version)
+      || dynsym_shdr.sh_size % dynsym_shdr.sh_entsize
+      || ver_shdr.sh_entsize != 2
+      || (ver_shdr.sh_size & 1)
+      || dynsym_shdr.sh_size / dynsym_shdr.sh_entsize != ver_shdr.sh_size / 2)
+    error (1, 0, "Unexpected sh_size or sh_entsize in %s", fname);
+
+  size_t nentries = ver_shdr.sh_size / 2;
+  size_t cnt;
+  GElf_Versym array[nentries];
+  for (cnt = 0; cnt < nentries; ++cnt)
+    {
+      GElf_Versym vsymmem;
+      GElf_Versym *vsym;
+
+      vsym = gelf_getversym (ver, cnt, &vsymmem);
+      if (vsym == NULL)
+	error (1, 0, "gelt_getversym failed in %s: %s", fname, elf_errmsg (-1));
+
+      array[cnt] = *vsym;
+      if (*vsym != from_idx)
+	continue;
+
+      GElf_Sym sym_mem;
+      GElf_Sym *sym;
+      sym = gelf_getsym (dynsym, cnt, &sym_mem);
+      if (sym == NULL)
+	error (1, 0, "gelt_getsym failed in %s: %s", fname, elf_errmsg (-1));
+
+      const char *name = elf_strptr (elf, dynsym_shdr.sh_link, sym->st_name);
+
+      int argn;
+      for (argn = 4; argn < argc; ++argn)
+	if (fnmatch (argv[argn], name, 0) == 0)
+	  {
+	    array[cnt] = to_idx;
+	    break;
+	  }
+    }
+
+  if (sizeof (array[0]) != 2)
+    abort ();
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+  if (ehdr->e_ident[EI_DATA] == ELFDATA2LSB)
+    ;
+  else if (ehdr->e_ident[EI_DATA] == ELFDATA2MSB)
+#elif __BYTE_ORDER == __BIG_ENDIAN
+  if (ehdr->e_ident[EI_DATA] == ELFDATA2MSB)
+    ;
+  else if (ehdr->e_ident[EI_DATA] == ELFDATA2LSB)
+#else
+# error Unsupported endianity
+#endif
+    {
+      for (cnt = 0; cnt < nentries; ++cnt)
+	array[cnt] = ((array[cnt] & 0xff) << 8) | ((array[cnt] & 0xff00) >> 8);
+    }
+  else
+    error (1, 0, "Unknown EI_DATA %d in %s", ehdr->e_ident[EI_DATA], fname);
+
+  if (elf_end (elf) != 0)
+    error (1, 0, "couldn't close %s: %s", fname, elf_errmsg (-1));
+
+  if (lseek (fd, ver_shdr.sh_offset, SEEK_SET) != (off_t) ver_shdr.sh_offset)
+    error (1, 0, "failed to seek to %zd in %s", (size_t) ver_shdr.sh_offset,
+	   fname);
+
+  if (write (fd, array, 2 * nentries) != (ssize_t) (2 * nentries))
+    error (1, 0, "failed to write .gnu.version section into %s", fname);
+
+  close (fd);
+  return 0;
+}
--- gcc/config/ia64/unwind-ia64.c.jj	2004-10-04 08:55:57.000000000 -0400
+++ gcc/config/ia64/unwind-ia64.c	2004-11-15 09:07:45.000000000 -0500
@@ -51,6 +51,51 @@
 #define UNW_FLAG_UHANDLER(x)	((x) & 0x0000000200000000L)
 #define UNW_LENGTH(x)		((x) & 0x00000000ffffffffL)
 
+#if defined (USE_SYMVER_GLOBAL) && defined (SHARED)
+extern _Unwind_Reason_Code __symverglobal_Unwind_Backtrace
+  (_Unwind_Trace_Fn, void *);
+extern void __symverglobal_Unwind_DeleteException
+  (struct _Unwind_Exception *);
+extern void * __symverglobal_Unwind_FindEnclosingFunction (void *);
+extern _Unwind_Reason_Code __symverglobal_Unwind_ForcedUnwind
+  (struct _Unwind_Exception *, _Unwind_Stop_Fn, void *);
+extern _Unwind_Word __symverglobal_Unwind_GetCFA
+  (struct _Unwind_Context *);
+extern _Unwind_Word __symverglobal_Unwind_GetBSP
+  (struct _Unwind_Context *);
+extern _Unwind_Word __symverglobal_Unwind_GetGR
+  (struct _Unwind_Context *, int );
+extern _Unwind_Ptr __symverglobal_Unwind_GetIP (struct _Unwind_Context *);
+extern void *__symverglobal_Unwind_GetLanguageSpecificData
+  (struct _Unwind_Context *);
+extern _Unwind_Ptr __symverglobal_Unwind_GetRegionStart
+  (struct _Unwind_Context *);
+extern _Unwind_Reason_Code __symverglobal_Unwind_RaiseException
+  (struct _Unwind_Exception *);
+extern void __symverglobal_Unwind_Resume (struct _Unwind_Exception *);
+extern _Unwind_Reason_Code __symverglobal_Unwind_Resume_or_Rethrow
+   (struct _Unwind_Exception *);
+extern void __symverglobal_Unwind_SetGR
+  (struct _Unwind_Context *, int, _Unwind_Word);
+extern void __symverglobal_Unwind_SetIP
+  (struct _Unwind_Context *, _Unwind_Ptr);
+#define _Unwind_Backtrace __symverglobal_Unwind_Backtrace
+#define _Unwind_DeleteException __symverglobal_Unwind_DeleteException
+#define _Unwind_FindEnclosingFunction __symverglobal_Unwind_FindEnclosingFunction
+#define _Unwind_ForcedUnwind __symverglobal_Unwind_ForcedUnwind
+#define _Unwind_GetBSP __symverglobal_Unwind_GetBSP
+#define _Unwind_GetCFA __symverglobal_Unwind_GetCFA
+#define _Unwind_GetGR __symverglobal_Unwind_GetGR
+#define _Unwind_GetIP __symverglobal_Unwind_GetIP
+#define _Unwind_GetLanguageSpecificData __symverglobal_Unwind_GetLanguageSpecificData
+#define _Unwind_GetRegionStart __symverglobal_Unwind_GetRegionStart
+#define _Unwind_RaiseException __symverglobal_Unwind_RaiseException
+#define _Unwind_Resume __symverglobal_Unwind_Resume
+#define _Unwind_Resume_or_Rethrow __symverglobal_Unwind_Resume_or_Rethrow
+#define _Unwind_SetGR __symverglobal_Unwind_SetGR
+#define _Unwind_SetIP __symverglobal_Unwind_SetIP
+#endif
+
 enum unw_application_register
 {
   UNW_AR_BSP,
@@ -2402,4 +2447,44 @@ alias (_Unwind_SetGR);
 alias (_Unwind_SetIP);
 #endif
 
+#if defined (USE_SYMVER_GLOBAL) && defined (SHARED)
+#undef alias
+#define symverglobal(name, version) \
+__typeof (__symverglobal##name) __symverlocal##name		\
+  __attribute__ ((alias ("__symverglobal" #name)));		\
+__asm__ (".symver __symverglobal" #name"," #name "@@GCC_3.4.2");\
+__asm__ (".symver __symverlocal" #name"," #name "@" #version)
+
+#undef _Unwind_Backtrace
+#undef _Unwind_DeleteException
+#undef _Unwind_FindEnclosingFunction
+#undef _Unwind_ForcedUnwind
+#undef _Unwind_GetBSP
+#undef _Unwind_GetCFA
+#undef _Unwind_GetGR
+#undef _Unwind_GetIP
+#undef _Unwind_GetLanguageSpecificData
+#undef _Unwind_GetRegionStart
+#undef _Unwind_RaiseException
+#undef _Unwind_Resume
+#undef _Unwind_Resume_or_Rethrow
+#undef _Unwind_SetGR
+#undef _Unwind_SetIP
+symverglobal (_Unwind_Backtrace, GCC_3.3);
+symverglobal (_Unwind_DeleteException, GCC_3.0);
+symverglobal (_Unwind_FindEnclosingFunction, GCC_3.3);
+symverglobal (_Unwind_ForcedUnwind, GCC_3.0);
+symverglobal (_Unwind_GetBSP, GCC_3.3.2);
+symverglobal (_Unwind_GetCFA, GCC_3.3);
+symverglobal (_Unwind_GetGR, GCC_3.0);
+symverglobal (_Unwind_GetIP, GCC_3.0);
+symverglobal (_Unwind_GetLanguageSpecificData, GCC_3.0);
+symverglobal (_Unwind_GetRegionStart, GCC_3.0);
+symverglobal (_Unwind_RaiseException, GCC_3.0);
+symverglobal (_Unwind_Resume, GCC_3.0);
+symverglobal (_Unwind_Resume_or_Rethrow, GCC_3.3);
+symverglobal (_Unwind_SetGR, GCC_3.0);
+symverglobal (_Unwind_SetIP, GCC_3.0);
+#endif
+
 #endif
--- gcc/config/ia64/mkmap-symver-multi.awk.jj	2004-02-18 10:27:36.000000000 -0500
+++ gcc/config/ia64/mkmap-symver-multi.awk	2004-11-15 09:46:50.000000000 -0500
@@ -0,0 +1,133 @@
+# Generate an ELF symbol version map a-la Solaris and GNU ld.
+#	Contributed by Richard Henderson <rth at cygnus.com>
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2, or (at your option) any later
+# version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING.  If not, write to the Free
+# Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+# 02110-1301, USA.
+
+BEGIN {
+  state = "nm";
+  sawsymbol = 0;
+}
+
+# Remove comment and blank lines.
+/^ *#/ || /^ *$/ {
+  next;
+}
+
+# We begin with nm input.  Collect the set of symbols that are present
+# so that we can not emit them into the final version script -- Solaris
+# complains at us if we do.
+
+state == "nm" && /^%%/ {
+  state = "ver";
+  next;
+}
+
+state == "nm" && ($1 == "U" || $2 == "U") {
+  next;
+}
+
+state == "nm" && NF == 3 {
+  if ($3 ~ /^[^@]*@GCC_[0-9.]*$/) {
+    def[$3] = 1
+    tl=$3
+    sub(/^.*@/,"",tl)
+    ver[$3] = tl
+  } else {
+    sub(/@@?GCC_[0-9.]*$/,"",$3)
+    def[$3] = 1;
+  }
+  sawsymbol = 1;
+  next;
+}
+
+state == "nm" {
+  next;
+}
+
+# Now we process a simplified variant of the Solaris symbol version
+# script.  We have one symbol per line, no semicolons, simple markers
+# for beginning and ending each section, and %inherit markers for
+# describing version inheritence.  A symbol may appear in more than
+# one symbol version, and the last seen takes effect.
+
+NF == 3 && $1 == "%inherit" {
+  inherit[$2] = $3;
+  next;
+}
+
+NF == 2 && $2 == "{" {
+  libs[$1] = 1;
+  thislib = $1;
+  next;
+}
+
+$1 == "}" {
+  thislib = "";
+  next;
+}
+
+{
+  ver[$1] = thislib;
+  next;
+}
+
+END {
+  if (!sawsymbol)
+    {
+      print "No symbols seen -- broken or mis-installed nm?" | "cat 1>&2";
+      exit 1;
+    }
+  for (l in libs)
+    output(l);
+}
+
+function output(lib) {
+  if (done[lib])
+    return;
+  done[lib] = 1;
+  if (inherit[lib])
+    output(inherit[lib]);
+
+  empty=1
+  for (sym in ver)
+    if ((ver[sym] == lib) && (sym in def))
+      {
+	if (empty)
+	  {
+	    printf("%s {\n", lib);
+	    printf("  global:\n");
+	    empty = 0;
+	  }
+	symp = sym;
+	sub(/@GCC_[0-9.]*$/,"",symp);
+	printf("\t%s;\n", symp);
+	if (dotsyms)
+	  printf("\t.%s;\n", symp);
+      }
+
+  if (empty)
+    {
+      for (l in libs)
+	if (inherit[l] == lib)
+	  inherit[l] = inherit[lib];
+    }
+  else if (inherit[lib])
+    printf("} %s;\n", inherit[lib]);
+  else
+    printf ("\n  local:\n\t*;\n};\n");
+}
--- gcc/config/ia64/libgcc-ia64-no-libunwind.ver.jj	2004-02-18 10:27:36.000000000 -0500
+++ gcc/config/ia64/libgcc-ia64-no-libunwind.ver	2004-11-15 09:19:56.000000000 -0500
@@ -0,0 +1,17 @@
+GCC_3.4.2 {
+  _Unwind_GetGR
+  _Unwind_RaiseException
+  _Unwind_GetRegionStart
+  _Unwind_SetIP
+  _Unwind_GetIP
+  _Unwind_GetLanguageSpecificData
+  _Unwind_Resume
+  _Unwind_DeleteException
+  _Unwind_SetGR
+  _Unwind_ForcedUnwind
+  _Unwind_Backtrace
+  _Unwind_FindEnclosingFunction
+  _Unwind_GetCFA
+  _Unwind_Resume_or_Rethrow
+  _Unwind_GetBSP
+}

gcc41-ice-hack.patch:

--- NEW FILE gcc41-ice-hack.patch ---
2004-01-23  Jakub Jelinek  <jakub at redhat.com>

	* system.h (ICE_EXIT_CODE): Define.
	* gcc.c (execute): Don't free first string early, but at the end
	of the function.  Call retry_ice if compiler exited with
	ICE_EXIT_CODE.
	(retry_ice): New function.
	* diagnostic.c (diagnostic_count_diagnostic,
	diagnostic_action_after_output, error_recursion): Exit with
	ICE_EXIT_CODE instead of FATAL_EXIT_CODE.

--- gcc/system.h.jj	2004-01-19 17:29:30.000000000 +0100
+++ gcc/system.h	2004-01-21 11:53:41.000000000 +0100
@@ -153,6 +153,10 @@ extern int errno;
 # endif
 #endif
 
+#ifndef ICE_EXIT_CODE
+# define ICE_EXIT_CODE 27
+#endif
+
 #ifdef HAVE_UNISTD_H
 # include <unistd.h>
 #endif
--- gcc/gcc.c.jj	2004-01-21 11:45:20.000000000 +0100
+++ gcc/gcc.c	2004-01-21 11:56:46.000000000 +0100
@@ -346,6 +346,9 @@ static void init_gcc_specs (struct obsta
 #if defined(HAVE_TARGET_OBJECT_SUFFIX) || defined(HAVE_TARGET_EXECUTABLE_SUFFIX)
 static const char *convert_filename (const char *, int, int);
 #endif
+#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS))
+static void retry_ice (const char *prog, const char **argv);
+#endif
 
 static const char *if_exists_spec_function (int, const char **);
 static const char *if_exists_else_spec_function (int, const char **);
@@ -2841,7 +2844,7 @@ execute (void)
 	    }
 	}
 
-      if (string != commands[i].prog)
+      if (i && string != commands[i].prog)
 	free ((void *) string);
     }
 
@@ -2897,6 +2900,16 @@ See %s for instructions.",
 	else if (WIFEXITED (status)
 		 && WEXITSTATUS (status) >= MIN_FATAL_STATUS)
 	  {
+#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS))
+	    /* For ICEs in cc1, cc1obj, cc1plus see if it is
+	       reproducible or not.  */
+	    char *p;
+	    if (WEXITSTATUS (status) == ICE_EXIT_CODE
+		&& i == 0
+		&& (p = strrchr (commands[0].argv[0], DIR_SEPARATOR))
+		&& ! strncmp (p + 1, "cc1", 3))
+	      retry_ice (commands[0].prog, commands[0].argv);
+#endif
 	    if (WEXITSTATUS (status) > greatest_status)
 	      greatest_status = WEXITSTATUS (status);
 	    ret_code = -1;
@@ -2917,6 +2930,9 @@ See %s for instructions.",
 	  }
       }
 
+    if (commands[0].argv[0] != commands[0].prog)
+      free ((PTR) commands[0].argv[0]);
+
     return ret_code;
   }
 }
@@ -5898,6 +5914,224 @@ give_switch (int switchnum, int omit_fir
   switches[switchnum].validated = 1;
 }
 
+#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS))
+#define RETRY_ICE_ATTEMPTS 2
+
+static void
+retry_ice (const char *prog, const char **argv)
+{
+  int nargs, out_arg = -1, quiet = 0, attempt;
+  int pid, retries, sleep_interval;
+  const char **new_argv;
+  char *temp_filenames[RETRY_ICE_ATTEMPTS * 2 + 2];
+
+  if (input_filename == NULL || ! strcmp (input_filename, "-"))
+    return;
+
+  for (nargs = 0; argv[nargs] != NULL; ++nargs)
+    /* Only retry compiler ICEs, not preprocessor ones.  */
+    if (! strcmp (argv[nargs], "-E"))
+      return;
+    else if (argv[nargs][0] == '-' && argv[nargs][1] == 'o')
+      {
+	if (out_arg == -1)
+	  out_arg = nargs;
+	else
+	  return;
+      }
+    /* If the compiler is going to output any time information,
+       it might varry between invocations.  */
+    else if (! strcmp (argv[nargs], "-quiet"))
+      quiet = 1;
+    else if (! strcmp (argv[nargs], "-ftime-report"))
+      return;
+
+  if (out_arg == -1 || !quiet)
+    return;
+
+  memset (temp_filenames, '\0', sizeof (temp_filenames));
+  new_argv = alloca ((nargs + 3) * sizeof (const char *));
+  memcpy (new_argv, argv, (nargs + 1) * sizeof (const char *));
+  new_argv[nargs++] = "-frandom-seed=0";
+  new_argv[nargs] = NULL;
+  if (new_argv[out_arg][2] == '\0')
+    new_argv[out_arg + 1] = "-";
+  else
+    new_argv[out_arg] = "-o-";
+
+  for (attempt = 0; attempt < RETRY_ICE_ATTEMPTS + 1; ++attempt)
+    {
+      int fd = -1;
+      int status;
+
+      temp_filenames[attempt * 2] = make_temp_file (".out");
+      temp_filenames[attempt * 2 + 1] = make_temp_file (".err");
+
+      if (attempt == RETRY_ICE_ATTEMPTS)
+        {
+	  int i;
+	  int fd1, fd2;
+	  struct stat st1, st2;
+	  size_t n, len;
+	  char *buf;
+
+	  buf = xmalloc (8192);
+
+	  for (i = 0; i < 2; ++i)
+	    {
+	      fd1 = open (temp_filenames[i], O_RDONLY);
+	      fd2 = open (temp_filenames[2 + i], O_RDONLY);
+
+	      if (fd1 < 0 || fd2 < 0)
+		{
+		  i = -1;
+		  close (fd1);
+		  close (fd2);
+		  break;
+		}
+
+	      if (fstat (fd1, &st1) < 0 || fstat (fd2, &st2) < 0)
+		{
+		  i = -1;
+		  close (fd1);
+		  close (fd2);
+		  break;
+		}
+
+	      if (st1.st_size != st2.st_size)
+		{
+		  close (fd1);
+		  close (fd2);
+		  break;
+		}
+
+	      len = 0;
+	      for (n = st1.st_size; n; n -= len)
+		{
+		  len = n;
+		  if (len > 4096)
+		    len = 4096;
+
+		  if (read (fd1, buf, len) != (int) len
+		      || read (fd2, buf + 4096, len) != (int) len)
+		    {
+		      i = -1;
+		      break;
+		    }
+
+		  if (memcmp (buf, buf + 4096, len) != 0)
+		    break;
+		}
+
+	      close (fd1);
+	      close (fd2);
+
+	      if (n)
+		break;
+	    }
+
+	  free (buf);
+	  if (i == -1)
+	    break;
+
+	  if (i != 2)
+	    {
+	      notice ("The bug is not reproducible, so it is likely a hardware or OS problem.\n");
+	      break;
+	    }
+
+          fd = open (temp_filenames[attempt * 2], O_RDWR);
+	  if (fd < 0)
+	    break;
+	  write (fd, "//", 2);
+	  for (i = 0; i < nargs; i++)
+	    {
+	      write (fd, " ", 1);
+	      write (fd, new_argv[i], strlen (new_argv[i]));
+	    }
+	  write (fd, "\n", 1);
+	  new_argv[nargs] = "-E";
+	  new_argv[nargs + 1] = NULL;
+        }
+
+      /* Fork a subprocess; wait and retry if it fails.  */
+      sleep_interval = 1;
+      pid = -1;
+      for (retries = 0; retries < 4; retries++)
+	{
+	  pid = fork ();
+	  if (pid >= 0)
+	    break;
+	  sleep (sleep_interval);
+	  sleep_interval *= 2;
+	}
+
+      if (pid < 0)
+	break;
+      else if (pid == 0)
+	{
+	  if (attempt != RETRY_ICE_ATTEMPTS)
+	    fd = open (temp_filenames[attempt * 2], O_RDWR);
+	  if (fd < 0)
+	    exit (-1);
+	  if (fd != 1)
+	    {
+	      close (1);
+	      dup (fd);
+	      close (fd);
+	    }
+
+	  fd = open (temp_filenames[attempt * 2 + 1], O_RDWR);
+	  if (fd < 0)
+	    exit (-1);
+	  if (fd != 2)
+	    {
+	      close (2);
+	      dup (fd);
+	      close (fd);
+	    }
+
+	  if (prog == new_argv[0])
+	    execvp (prog, (char *const *) new_argv);
+	  else
+	    execv (new_argv[0], (char *const *) new_argv);
+	  exit (-1);
+	}
+
+      if (waitpid (pid, &status, 0) < 0)
+	break;
+
+      if (attempt < RETRY_ICE_ATTEMPTS
+	  && (! WIFEXITED (status) || WEXITSTATUS (status) != ICE_EXIT_CODE))
+	{
+	  notice ("The bug is not reproducible, so it is likely a hardware or OS problem.\n");
+	  break;
+	}
+      else if (attempt == RETRY_ICE_ATTEMPTS)
+	{
+	  close (fd);
+	  if (WIFEXITED (status)
+	      && WEXITSTATUS (status) == SUCCESS_EXIT_CODE)
+	    {
+	      notice ("Preprocessed source stored into %s file, please attach this to your bugreport.\n",
+		      temp_filenames[attempt * 2]);
+	      /* Make sure it is not deleted.  */
+	      free (temp_filenames[attempt * 2]);
+	      temp_filenames[attempt * 2] = NULL;
+	      break;
+	    }
+	}
+    }
+
+  for (attempt = 0; attempt < RETRY_ICE_ATTEMPTS * 2 + 2; attempt++)
+    if (temp_filenames[attempt])
+      {
+	unlink (temp_filenames[attempt]);
+	free (temp_filenames[attempt]);
+      }
+}
+#endif
+
 /* Search for a file named NAME trying various prefixes including the
    user's -B prefix and some standard ones.
    Return the absolute file name found.  If nothing is found, return NAME.  */
--- gcc/diagnostic.c.jj	2003-10-01 12:09:21.000000000 +0200
+++ gcc/diagnostic.c	2004-01-21 11:54:47.000000000 +0100
@@ -237,14 +237,14 @@ diagnostic_action_after_output (diagnost
       fnotice (stderr, "Please submit a full bug report,\n"
 	       "with preprocessed source if appropriate.\n"
 	       "See %s for instructions.\n", bug_report_url);
-      exit (FATAL_EXIT_CODE);
+      exit (ICE_EXIT_CODE);
 
     case DK_FATAL:
       if (context->abort_on_error)
 	real_abort ();
 
       fnotice (stderr, "compilation terminated.\n");
-      exit (FATAL_EXIT_CODE);
+      exit (ICE_EXIT_CODE);
 
     default:
       gcc_unreachable ();

gcc41-java-nomulti.patch:

--- NEW FILE gcc41-java-nomulti.patch ---
--- libjava/configure.ac.jj	2004-08-16 21:13:29.000000000 +0200
+++ libjava/configure.ac	2004-08-21 11:44:59.020755542 +0200
@@ -367,6 +367,10 @@ use_gtk_awt=""
 TOOLKIT=
 AC_SUBST(TOOLKIT)
 
+if test -n "${with_multisubdir}"; then
+  peerlibs=no
+fi
+
 for peer in $peerlibs ; do
   case $peer in
     xlib)
--- libjava/configure.jj	2004-08-16 21:22:14.000000000 +0200
+++ libjava/configure	2004-08-21 11:45:16.260738060 +0200
@@ -4118,6 +4118,9 @@ use_gtk_awt=""
 # The default toolkit to use is the first one specified.
 TOOLKIT=
 
+if test -n "${with_multisubdir}"; then
+  peerlibs=no
+fi
 
 for peer in $peerlibs ; do
   case $peer in

gcc41-java-slow_pthread_self.patch:

--- NEW FILE gcc41-java-slow_pthread_self.patch ---
2005-05-20  Jakub Jelinek  <jakub at redhat.com>

	* configure.host (slow_pthread_self): Set to empty unconditionally
	on Linux targets.

--- libjava/configure.host	(.../gcc-4_0-branch)	(revision 107266)
+++ libjava/configure.host	(.../redhat/gcc-4_0-branch)	(revision 107414)
@@ -174,6 +174,7 @@
   sh-linux* | sh[34]*-linux*)
   	can_unwind_signal=yes
 	libgcj_ld_symbolic='-Wl,-Bsymbolic'
+	slow_pthread_self=
 	if test x$slow_pthread_self = xyes \
 	   && test x$cross_compiling != xyes; then
 	  cat > conftest.c <<EOF

gcc41-mni.patch:

--- NEW FILE gcc41-mni.patch ---
2006-02-24  H.J. Lu  <hongjiu.lu at intel.com>

	* config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers.
	(x86_64-*-*): Likewise.

	* config/i386/i386.c (pta_flags): Add PTA_MNI.
	(override_options): Check MNI.
	(ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD,
	IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD,
	IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW,
	IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB,
	IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND,
	IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW,
	IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128,
	IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128,
	IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128,
	IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128,
	IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128,
	IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128,
	IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128,
	IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and
	IX86_BUILTIN_PABSD128.
	(bdesc_2arg): Add MNI.
	(bdesc_1arg): Likewise.
	(ix86_init_mmx_sse_builtins): Support MNI.
	(ix86_expand_builtin): Likewise.
	* config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise.

	* config/i386/i386.md (UNSPEC_LDQQU): Renamed to ...
	(UNSPEC_LDDQU): This.
	(UNSPEC_PSHUFB): New.
	(UNSPEC_PSIGN): Likewise.
	(UNSPEC_PALIGNR): Likewise.
	Include mmx.md before sse.md.

	* config/i386/i386.opt: Add -mmni.

	* config/i386/sse.md (sse3_lddqu): Updated.
	(mni_phaddwv8hi3): New pattern for MNI.
	(mni_phaddwv4hi3): Likewise.
	(mni_phadddv4si3): Likewise.
	(mni_phadddv2si3): Likewise.
	(mni_phaddswv8hi3): Likewise.
	(mni_phaddswv4hi3): Likewise.
	(mni_phsubwv8hi3): Likewise.
	(mni_phsubwv4hi3): Likewise.
	(mni_phsubdv4si3): Likewise.
	(mni_phsubdv2si3): Likewise.
	(mni_phsubswv8hi3): Likewise.
	(mni_phsubswv4hi3): Likewise.
	(mni_pmaddubswv8hi3): Likewise.
	(mni_pmaddubswv4hi3): Likewise.
	(mni_pmulhrswv8hi3): Likewise.
	(mni_pmulhrswv4hi3): Likewise.
	(mni_pshufbv16qi3): Likewise.
	(mni_pshufbv8qi3): Likewise.
	(mni_psign<mode>3): Likewise.
	(mni_psign<mode>3): Likewise.
	(mni_palignrti): Likewise.
	(mni_palignrdi): Likewise.
	(mni_pabs<mode>2): Likewise.
	(mni_pabs<mode>2): Likewise.

	* config/i386/tmmintrin.h: New file.

	* doc/extend.texi: Document MNI built-in functions.

	* doc/invoke.texi: Document -mmni/-mno-mni switches.

--- gcc/config.gcc.mni	2006-02-14 13:18:08.000000000 -0800
+++ gcc/config.gcc	2006-02-24 13:39:19.000000000 -0800
@@ -263,11 +263,13 @@ xscale-*-*)
 	;;
 i[34567]86-*-*)
 	cpu_type=i386
-	extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h pmmintrin.h"
+	extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h
+		       pmmintrin.h tmmintrin.h"
 	;;
 x86_64-*-*)
 	cpu_type=i386
-	extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h pmmintrin.h"
+	extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h
+		       pmmintrin.h tmmintrin.h"
 	need_64bit_hwint=yes
 	;;
 ia64-*-*)
--- gcc/config/i386/i386.c.mni	2006-02-24 13:39:19.000000000 -0800
+++ gcc/config/i386/i386.c	2006-02-24 13:39:19.000000000 -0800
@@ -1446,11 +1446,12 @@ override_options (void)
 	  PTA_SSE = 1,
 	  PTA_SSE2 = 2,
 	  PTA_SSE3 = 4,
-	  PTA_MMX = 8,
-	  PTA_PREFETCH_SSE = 16,
-	  PTA_3DNOW = 32,
-	  PTA_3DNOW_A = 64,
-	  PTA_64BIT = 128
+	  PTA_MNI = 8,
+	  PTA_MMX = 16,
+	  PTA_PREFETCH_SSE = 32,
+	  PTA_3DNOW = 64,
+	  PTA_3DNOW_A = 128,
+	  PTA_64BIT = 256
 	} flags;
     }
   const processor_alias_table[] =
@@ -1645,6 +1646,9 @@ override_options (void)
 	if (processor_alias_table[i].flags & PTA_SSE3
 	    && !(target_flags_explicit & MASK_SSE3))
 	  target_flags |= MASK_SSE3;
+	if (processor_alias_table[i].flags & PTA_MNI
+	    && !(target_flags_explicit & MASK_MNI))
+	  target_flags |= MASK_MNI;
 	if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
 	  x86_prefetch_sse = true;
 	if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
@@ -1836,6 +1840,10 @@ override_options (void)
   if (!TARGET_80387)
     target_flags |= MASK_NO_FANCY_MATH_387;
 
+  /* Turn on SSE3 builtins for -mmni.  */
+  if (TARGET_MNI)
+    target_flags |= MASK_SSE3;
+
   /* Turn on SSE2 builtins for -msse3.  */
   if (TARGET_SSE3)
     target_flags |= MASK_SSE2;
@@ -14147,6 +14155,41 @@ enum ix86_builtins
   IX86_BUILTIN_MONITOR,
   IX86_BUILTIN_MWAIT,
 
+  /* Merom New Instructions.  */
+  IX86_BUILTIN_PHADDW,
+  IX86_BUILTIN_PHADDD,
+  IX86_BUILTIN_PHADDSW,
+  IX86_BUILTIN_PHSUBW,
+  IX86_BUILTIN_PHSUBD,
+  IX86_BUILTIN_PHSUBSW,
+  IX86_BUILTIN_PMADDUBSW,
+  IX86_BUILTIN_PMULHRSW,
+  IX86_BUILTIN_PSHUFB,
+  IX86_BUILTIN_PSIGNB,
+  IX86_BUILTIN_PSIGNW,
+  IX86_BUILTIN_PSIGND,
+  IX86_BUILTIN_PALIGNR,
+  IX86_BUILTIN_PABSB,
+  IX86_BUILTIN_PABSW,
+  IX86_BUILTIN_PABSD,
+
+  IX86_BUILTIN_PHADDW128,
+  IX86_BUILTIN_PHADDD128,
+  IX86_BUILTIN_PHADDSW128,
+  IX86_BUILTIN_PHSUBW128,
+  IX86_BUILTIN_PHSUBD128,
+  IX86_BUILTIN_PHSUBSW128,
+  IX86_BUILTIN_PMADDUBSW128,
+  IX86_BUILTIN_PMULHRSW128,
+  IX86_BUILTIN_PSHUFB128,
+  IX86_BUILTIN_PSIGNB128,
+  IX86_BUILTIN_PSIGNW128,
+  IX86_BUILTIN_PSIGND128,
+  IX86_BUILTIN_PALIGNR128,
+  IX86_BUILTIN_PABSB128,
+  IX86_BUILTIN_PABSW128,
+  IX86_BUILTIN_PABSD128,
+
   IX86_BUILTIN_VEC_INIT_V2SI,
   IX86_BUILTIN_VEC_INIT_V4HI,
   IX86_BUILTIN_VEC_INIT_V8QI,
@@ -14487,7 +14530,33 @@ static const struct builtin_description 
   { MASK_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
   { MASK_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
   { MASK_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
-  { MASK_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
+  { MASK_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 },
+
+  /* MNI MMX */
+  { MASK_MNI, CODE_FOR_mni_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_pmaddubswv8hi3, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_pmaddubswv4hi3, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, 0, 0 }
 };
 
 static const struct builtin_description bdesc_1arg[] =
@@ -14532,8 +14601,16 @@ static const struct builtin_description 
   { MASK_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 },
 
   /* SSE3 */
-  { MASK_SSE3, CODE_FOR_sse3_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
-  { MASK_SSE3, CODE_FOR_sse3_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
+  { MASK_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, 0, 0 },
+  { MASK_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, 0, 0 },
+
+  /* MNI */
+  { MASK_MNI, CODE_FOR_mni_pabsv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_pabsv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_pabsv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_pabsv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_pabsv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, 0, 0 },
+  { MASK_MNI, CODE_FOR_mni_pabsv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, 0, 0 }
 };
 
 static void
@@ -14678,6 +14755,16 @@ ix86_init_mmx_sse_builtins (void)
   /* Normal vector unops.  */
   tree v4sf_ftype_v4sf
     = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
+  tree v16qi_ftype_v16qi
+    = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
+  tree v8hi_ftype_v8hi
+    = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
+  tree v4si_ftype_v4si
+    = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
+  tree v8qi_ftype_v8qi
+    = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
+  tree v4hi_ftype_v4hi
+    = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
 
   /* Normal vector binops.  */
   tree v4sf_ftype_v4sf_v4sf
@@ -14697,6 +14784,12 @@ ix86_init_mmx_sse_builtins (void)
 				long_long_unsigned_type_node,
 				long_long_unsigned_type_node, NULL_TREE);
 
+  tree di_ftype_di_di_int
+    = build_function_type_list (long_long_unsigned_type_node,
+				long_long_unsigned_type_node,
+				long_long_unsigned_type_node,
+				integer_type_node, NULL_TREE);
+
   tree v2si_ftype_v2sf
     = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
   tree v2sf_ftype_v2si
@@ -14801,6 +14894,9 @@ ix86_init_mmx_sse_builtins (void)
   tree v2di_ftype_v2di_int
     = build_function_type_list (V2DI_type_node,
 				V2DI_type_node, integer_type_node, NULL_TREE);
+  tree v2di_ftype_v2di_v2di_int
+    = build_function_type_list (V2DI_type_node, V2DI_type_node,
+				V2DI_type_node, integer_type_node, NULL_TREE);
   tree v4si_ftype_v4si_int
     = build_function_type_list (V4SI_type_node,
 				V4SI_type_node, integer_type_node, NULL_TREE);
@@ -14926,6 +15022,50 @@ ix86_init_mmx_sse_builtins (void)
       def_builtin (d->mask, d->name, type, d->code);
     }
 
+  /* Add all builtins that are more or less simple operations on 1 operand.  */
+  for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
+    {
+      enum machine_mode mode;
+      tree type;
+
+      if (d->name == 0)
+	continue;
+      mode = insn_data[d->icode].operand[1].mode;
+
+      switch (mode)
+	{
+	case V16QImode:
+	  type = v16qi_ftype_v16qi;
+	  break;
+	case V8HImode:
+	  type = v8hi_ftype_v8hi;
+	  break;
+	case V4SImode:
+	  type = v4si_ftype_v4si;
+	  break;
+	case V2DFmode:
+	  type = v2df_ftype_v2df;
+	  break;
+	case V4SFmode:
+	  type = v4sf_ftype_v4sf;
+	  break;
+	case V8QImode:
+	  type = v8qi_ftype_v8qi;
+	  break;
+	case V4HImode:
+	  type = v4hi_ftype_v4hi;
+	  break;
+	case V2SImode:
+	  type = v2si_ftype_v2si;
+	  break;
+
+	default:
+	  abort ();
+	}
+
+      def_builtin (d->mask, d->name, type, d->code);
+    }
+
   /* Add the remaining MMX insns with somewhat more complicated types.  */
   def_builtin (MASK_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
   def_builtin (MASK_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW);
@@ -15128,15 +15268,15 @@ ix86_init_mmx_sse_builtins (void)
 		   void_ftype_unsigned_unsigned,
 		   IX86_BUILTIN_MWAIT);
     }
-  def_builtin (MASK_SSE3, "__builtin_ia32_movshdup",
-	       v4sf_ftype_v4sf,
-	       IX86_BUILTIN_MOVSHDUP);
-  def_builtin (MASK_SSE3, "__builtin_ia32_movsldup",
-	       v4sf_ftype_v4sf,
-	       IX86_BUILTIN_MOVSLDUP);
   def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
 	       v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
 
+  /* Merom New Instructions.  */
+  def_builtin (MASK_MNI, "__builtin_ia32_palignr128",
+	       v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128);
+  def_builtin (MASK_MNI, "__builtin_ia32_palignr", di_ftype_di_di_int,
+	       IX86_BUILTIN_PALIGNR);
+
   /* Access to the vec_init patterns.  */
   ftype = build_function_type_list (V2SI_type_node, integer_type_node,
 				    integer_type_node, NULL_TREE);
@@ -15627,7 +15767,7 @@ ix86_expand_builtin (tree exp, rtx targe
   tree arglist = TREE_OPERAND (exp, 1);
   tree arg0, arg1, arg2;
   rtx op0, op1, op2, pat;
-  enum machine_mode tmode, mode0, mode1, mode2;
+  enum machine_mode tmode, mode0, mode1, mode2, mode3;
   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
 
   switch (fcode)
@@ -16004,6 +16144,52 @@ ix86_expand_builtin (tree exp, rtx targe
       return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, arglist,
 				       target, 1);
 
+    case IX86_BUILTIN_PALIGNR:
+    case IX86_BUILTIN_PALIGNR128:
+      if (fcode == IX86_BUILTIN_PALIGNR)
+	{
+	  icode = CODE_FOR_mni_palignrdi;
+	  mode = DImode;
+	}
+      else
+	{
+	  icode = CODE_FOR_mni_palignrti;
+	  mode = V2DImode;
+	}
+      arg0 = TREE_VALUE (arglist);
+      arg1 = TREE_VALUE (TREE_CHAIN (arglist));
+      arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
+      op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
+      op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
+      op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
+      tmode = insn_data[icode].operand[0].mode;
+      mode1 = insn_data[icode].operand[1].mode;
+      mode2 = insn_data[icode].operand[2].mode;
+      mode3 = insn_data[icode].operand[3].mode;
+
+      if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
+	{
+	  op0 = copy_to_reg (op0);
+	  op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
+	}
+      if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
+	{
+	  op1 = copy_to_reg (op1);
+	  op1 = simplify_gen_subreg (mode2, op1, GET_MODE (op1), 0);
+	}
+      if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
+	{
+	  error ("shift must be an immediate");
+	  return const0_rtx;
+	}
+      target = gen_reg_rtx (mode);
+      pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, mode, 0),
+			     op0, op1, op2);
+      if (! pat)
+	return 0;
+      emit_insn (pat);
+      return target;
+
     case IX86_BUILTIN_VEC_INIT_V2SI:
     case IX86_BUILTIN_VEC_INIT_V4HI:
     case IX86_BUILTIN_VEC_INIT_V8QI:
--- gcc/config/i386/i386.h.mni	2006-02-04 06:59:11.000000000 -0800
+++ gcc/config/i386/i386.h	2006-02-24 13:39:19.000000000 -0800
@@ -385,6 +385,8 @@ extern int x86_prefetch_sse;
 	builtin_define ("__SSE2__");				\
       if (TARGET_SSE3)						\
 	builtin_define ("__SSE3__");				\
+      if (TARGET_MNI)						\
+	builtin_define ("__MNI__");				\
       if (TARGET_SSE_MATH && TARGET_SSE)			\
 	builtin_define ("__SSE_MATH__");			\
       if (TARGET_SSE_MATH && TARGET_SSE2)			\
--- gcc/config/i386/i386.md.mni	2006-02-24 13:39:19.000000000 -0800
+++ gcc/config/i386/i386.md	2006-02-24 13:39:19.000000000 -0800
@@ -102,7 +102,7 @@
    (UNSPEC_MFENCE		44)
    (UNSPEC_LFENCE		45)
    (UNSPEC_PSADBW		46)
-   (UNSPEC_LDQQU		47)
+   (UNSPEC_LDDQU		47)
 
    ; Generic math support
    (UNSPEC_COPYSIGN		50)
@@ -146,6 +146,11 @@
    (UNSPEC_SP_TEST		101)
    (UNSPEC_SP_TLS_SET		102)
    (UNSPEC_SP_TLS_TEST		103)
+
+   ; MNI
+   (UNSPEC_PSHUFB		120)
+   (UNSPEC_PSIGN		121)
+   (UNSPEC_PALIGNR		122)
   ])
 
 (define_constants
@@ -20262,6 +20267,6 @@
   "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR %%fs:%P2}"
   [(set_attr "type" "multi")])
 
-(include "sse.md")
 (include "mmx.md")
+(include "sse.md")
 (include "sync.md")
--- gcc/config/i386/i386.opt.mni	2006-02-24 13:39:19.000000000 -0800
+++ gcc/config/i386/i386.opt	2006-02-24 13:39:19.000000000 -0800
@@ -197,6 +197,10 @@ msse3
 Target Report Mask(SSE3)
 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
 
+mmni
+Target Report Mask(MNI)
+Support MMX, SSE, SSE2, SSE3 and MNI built-in functions and code generation
+
 msseregparm
 Target RejectNegative Mask(SSEREGPARM)
 Use SSE register passing conventions for SF and DF mode
--- gcc/config/i386/sse.md.mni	2006-02-24 13:39:19.000000000 -0800
+++ gcc/config/i386/sse.md	2006-02-24 13:39:19.000000000 -0800
@@ -278,7 +278,7 @@
 (define_insn "sse3_lddqu"
   [(set (match_operand:V16QI 0 "register_operand" "=x")
 	(unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
-		      UNSPEC_LDQQU))]
+		      UNSPEC_LDDQU))]
   "TARGET_SSE3"
   "lddqu\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
@@ -3923,3 +3923,578 @@
 ;;  "monitor\t%0, %1, %2"
   "monitor"
   [(set_attr "length" "3")])
+
+;; MNI
+(define_insn "mni_phaddwv8hi3"
+  [(set (match_operand:V8HI 0 "register_operand" "=x")
+	(vec_concat:V8HI
+	  (vec_concat:V4HI
+	    (vec_concat:V2HI
+	      (plus:HI
+		(vec_select:HI
+		  (match_operand:V8HI 1 "register_operand" "0")
+		  (parallel [(const_int 0)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+	      (plus:HI
+		(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
+	    (vec_concat:V2HI
+	      (plus:HI
+		(vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
+	      (plus:HI
+		(vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
+	  (vec_concat:V4HI
+	    (vec_concat:V2HI
+	      (plus:HI
+		(vec_select:HI
+		  (match_operand:V8HI 2 "nonimmediate_operand" "xm")
+		  (parallel [(const_int 0)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
+	      (plus:HI
+		(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
+	    (vec_concat:V2HI
+	      (plus:HI
+		(vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
+	      (plus:HI
+		(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
+  "TARGET_MNI"
+  "phaddw\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "TI")])
+
+(define_insn "mni_phaddwv4hi3"
+  [(set (match_operand:V4HI 0 "register_operand" "=y")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (plus:HI
+	      (vec_select:HI
+		(match_operand:V4HI 1 "register_operand" "0")
+		(parallel [(const_int 0)]))
+	      (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+	    (plus:HI
+	      (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+	      (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
+	  (vec_concat:V2HI
+	    (plus:HI
+	      (vec_select:HI
+		(match_operand:V4HI 2 "nonimmediate_operand" "ym")
+		(parallel [(const_int 0)]))
+	      (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
+	    (plus:HI
+	      (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
+	      (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
+  "TARGET_MNI"
+  "phaddw\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "DI")])
+
+(define_insn "mni_phadddv4si3"
+  [(set (match_operand:V4SI 0 "register_operand" "=x")
+	(vec_concat:V4SI
+	  (vec_concat:V2SI
+	    (plus:SI
+	      (vec_select:SI
+		(match_operand:V4SI 1 "register_operand" "0")
+		(parallel [(const_int 0)]))
+	      (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
+	    (plus:SI
+	      (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
+	      (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
+	  (vec_concat:V2SI
+	    (plus:SI
+	      (vec_select:SI
+		(match_operand:V4SI 2 "nonimmediate_operand" "xm")
+		(parallel [(const_int 0)]))
+	      (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
+	    (plus:SI
+	      (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
+	      (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
+  "TARGET_MNI"
+  "phaddd\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "TI")])
+
+(define_insn "mni_phadddv2si3"
+  [(set (match_operand:V2SI 0 "register_operand" "=y")
+	(vec_concat:V2SI
+	  (plus:SI
+	    (vec_select:SI
+	      (match_operand:V2SI 1 "register_operand" "0")
+	      (parallel [(const_int 0)]))
+	    (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
+	  (plus:SI
+	    (vec_select:SI
+	      (match_operand:V2SI 2 "nonimmediate_operand" "ym")
+	      (parallel [(const_int 0)]))
+	    (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
+  "TARGET_MNI"
+  "phaddd\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "DI")])
+
+(define_insn "mni_phaddswv8hi3"
+  [(set (match_operand:V8HI 0 "register_operand" "=x")
+	(vec_concat:V8HI
+	  (vec_concat:V4HI
+	    (vec_concat:V2HI
+	      (ss_plus:HI
+		(vec_select:HI
+		  (match_operand:V8HI 1 "register_operand" "0")
+		  (parallel [(const_int 0)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+	      (ss_plus:HI
+		(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
+	    (vec_concat:V2HI
+	      (ss_plus:HI
+		(vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
+	      (ss_plus:HI
+		(vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
+	  (vec_concat:V4HI
+	    (vec_concat:V2HI
+	      (ss_plus:HI
+		(vec_select:HI
+		  (match_operand:V8HI 2 "nonimmediate_operand" "xm")
+		  (parallel [(const_int 0)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
+	      (ss_plus:HI
+		(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
+	    (vec_concat:V2HI
+	      (ss_plus:HI
+		(vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
+	      (ss_plus:HI
+		(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
+  "TARGET_MNI"
+  "phaddsw\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "TI")])
+
+(define_insn "mni_phaddswv4hi3"
+  [(set (match_operand:V4HI 0 "register_operand" "=y")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (ss_plus:HI
+	      (vec_select:HI
+		(match_operand:V4HI 1 "register_operand" "0")
+		(parallel [(const_int 0)]))
+	      (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+	    (ss_plus:HI
+	      (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+	      (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
+	  (vec_concat:V2HI
+	    (ss_plus:HI
+	      (vec_select:HI
+		(match_operand:V4HI 2 "nonimmediate_operand" "ym")
+		(parallel [(const_int 0)]))
+	      (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
+	    (ss_plus:HI
+	      (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
+	      (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
+  "TARGET_MNI"
+  "phaddsw\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "DI")])
+
+(define_insn "mni_phsubwv8hi3"
+  [(set (match_operand:V8HI 0 "register_operand" "=x")
+	(vec_concat:V8HI
+	  (vec_concat:V4HI
+	    (vec_concat:V2HI
+	      (minus:HI
+		(vec_select:HI
+		  (match_operand:V8HI 1 "register_operand" "0")
+		  (parallel [(const_int 0)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+	      (minus:HI
+		(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
+	    (vec_concat:V2HI
+	      (minus:HI
+		(vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
+	      (minus:HI
+		(vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
+	  (vec_concat:V4HI
+	    (vec_concat:V2HI
+	      (minus:HI
+		(vec_select:HI
+		  (match_operand:V8HI 2 "nonimmediate_operand" "xm")
+		  (parallel [(const_int 0)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
+	      (minus:HI
+		(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
+	    (vec_concat:V2HI
+	      (minus:HI
+		(vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
+	      (minus:HI
+		(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
+  "TARGET_MNI"
+  "phsubw\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "TI")])
+
+(define_insn "mni_phsubwv4hi3"
+  [(set (match_operand:V4HI 0 "register_operand" "=y")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (minus:HI
+	      (vec_select:HI
+		(match_operand:V4HI 1 "register_operand" "0")
+		(parallel [(const_int 0)]))
+	      (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+	    (minus:HI
+	      (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+	      (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
+	  (vec_concat:V2HI
+	    (minus:HI
+	      (vec_select:HI
+		(match_operand:V4HI 2 "nonimmediate_operand" "ym")
+		(parallel [(const_int 0)]))
+	      (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
+	    (minus:HI
+	      (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
+	      (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
+  "TARGET_MNI"
+  "phsubw\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "DI")])
+
+(define_insn "mni_phsubdv4si3"
+  [(set (match_operand:V4SI 0 "register_operand" "=x")
+	(vec_concat:V4SI
+	  (vec_concat:V2SI
+	    (minus:SI
+	      (vec_select:SI
+		(match_operand:V4SI 1 "register_operand" "0")
+		(parallel [(const_int 0)]))
+	      (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
+	    (minus:SI
+	      (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
+	      (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
+	  (vec_concat:V2SI
+	    (minus:SI
+	      (vec_select:SI
+		(match_operand:V4SI 2 "nonimmediate_operand" "xm")
+		(parallel [(const_int 0)]))
+	      (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
+	    (minus:SI
+	      (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
+	      (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
+  "TARGET_MNI"
+  "phsubd\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "TI")])
+
+(define_insn "mni_phsubdv2si3"
+  [(set (match_operand:V2SI 0 "register_operand" "=y")
+	(vec_concat:V2SI
+	  (minus:SI
+	    (vec_select:SI
+	      (match_operand:V2SI 1 "register_operand" "0")
+	      (parallel [(const_int 0)]))
+	    (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
+	  (minus:SI
+	    (vec_select:SI
+	      (match_operand:V2SI 2 "nonimmediate_operand" "ym")
+	      (parallel [(const_int 0)]))
+	    (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
+  "TARGET_MNI"
+  "phsubd\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "DI")])
+
+(define_insn "mni_phsubswv8hi3"
+  [(set (match_operand:V8HI 0 "register_operand" "=x")
+	(vec_concat:V8HI
+	  (vec_concat:V4HI
+	    (vec_concat:V2HI
+	      (ss_minus:HI
+		(vec_select:HI
+		  (match_operand:V8HI 1 "register_operand" "0")
+		  (parallel [(const_int 0)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+	      (ss_minus:HI
+		(vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
+	    (vec_concat:V2HI
+	      (ss_minus:HI
+		(vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
+	      (ss_minus:HI
+		(vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
+		(vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
+	  (vec_concat:V4HI
+	    (vec_concat:V2HI
+	      (ss_minus:HI
+		(vec_select:HI
+		  (match_operand:V8HI 2 "nonimmediate_operand" "xm")
+		  (parallel [(const_int 0)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
+	      (ss_minus:HI
+		(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
+	    (vec_concat:V2HI
+	      (ss_minus:HI
+		(vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
+	      (ss_minus:HI
+		(vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
+		(vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
+  "TARGET_MNI"
+  "phsubsw\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "TI")])
+
+(define_insn "mni_phsubswv4hi3"
+  [(set (match_operand:V4HI 0 "register_operand" "=y")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (ss_minus:HI
+	      (vec_select:HI
+		(match_operand:V4HI 1 "register_operand" "0")
+		(parallel [(const_int 0)]))
+	      (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+	    (ss_minus:HI
+	      (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+	      (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
+	  (vec_concat:V2HI
+	    (ss_minus:HI
+	      (vec_select:HI
+		(match_operand:V4HI 2 "nonimmediate_operand" "ym")
+		(parallel [(const_int 0)]))
+	      (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
+	    (ss_minus:HI
+	      (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
+	      (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
+  "TARGET_MNI"
+  "phsubsw\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "DI")])
+
+(define_insn "mni_pmaddubswv8hi3"
+  [(set (match_operand:V8HI 0 "register_operand" "=x")
+	(ss_plus:V8HI
+	  (mult:V8HI
+	    (zero_extend:V8HI
+	      (vec_select:V4QI
+		(match_operand:V16QI 1 "nonimmediate_operand" "%0")
+		(parallel [(const_int 0)
+			   (const_int 2)
+			   (const_int 4)
+			   (const_int 6)
+			   (const_int 8)
+			   (const_int 10)
+			   (const_int 12)
+			   (const_int 14)])))
+	    (sign_extend:V8HI
+	      (vec_select:V8QI
+		(match_operand:V16QI 2 "nonimmediate_operand" "xm")
+		(parallel [(const_int 0)
+			   (const_int 2)
+			   (const_int 4)
+			   (const_int 6)
+			   (const_int 8)
+			   (const_int 10)
+			   (const_int 12)
+			   (const_int 14)]))))
+	  (mult:V8HI
+	    (zero_extend:V8HI
+	      (vec_select:V16QI (match_dup 1)
+		(parallel [(const_int 1)
+			   (const_int 3)
+			   (const_int 5)
+			   (const_int 7)
+			   (const_int 9)
+			   (const_int 11)
+			   (const_int 13)
+			   (const_int 15)])))
+	    (sign_extend:V8HI
+	      (vec_select:V16QI (match_dup 2)
+		(parallel [(const_int 1)
+			   (const_int 3)
+			   (const_int 5)
+			   (const_int 7)
+			   (const_int 9)
+			   (const_int 11)
+			   (const_int 13)
+			   (const_int 15)]))))))]
+  "TARGET_MNI"
+  "pmaddubsw\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "TI")])
+
+(define_insn "mni_pmaddubswv4hi3"
+  [(set (match_operand:V4HI 0 "register_operand" "=y")
+	(ss_plus:V4HI
+	  (mult:V4HI
+	    (zero_extend:V4HI
+	      (vec_select:V4QI
+		(match_operand:V8QI 1 "nonimmediate_operand" "%0")
+		(parallel [(const_int 0)
+			   (const_int 2)
+			   (const_int 4)
+			   (const_int 6)])))
+	    (sign_extend:V4HI
+	      (vec_select:V4QI
+		(match_operand:V8QI 2 "nonimmediate_operand" "ym")
+		(parallel [(const_int 0)
+			   (const_int 2)
+			   (const_int 4)
+			   (const_int 6)]))))
+	  (mult:V4HI
+	    (zero_extend:V4HI
+	      (vec_select:V8QI (match_dup 1)
+		(parallel [(const_int 1)
+			   (const_int 3)
+			   (const_int 5)
+			   (const_int 7)])))
+	    (sign_extend:V4HI
+	      (vec_select:V8QI (match_dup 2)
+		(parallel [(const_int 1)
+			   (const_int 3)
+			   (const_int 5)
+			   (const_int 7)]))))))]
+  "TARGET_MNI"
+  "pmaddubsw\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "mode" "DI")])
+
+(define_insn "mni_pmulhrswv8hi3"
+  [(set (match_operand:V8HI 0 "register_operand" "=x")
+	(truncate:V8HI
+	  (lshiftrt:V8SI
+	    (plus:V8SI
+	      (lshiftrt:V8SI
+		(mult:V8SI
+		  (sign_extend:V8SI
+		    (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
+		  (sign_extend:V8SI
+		    (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
+		(const_int 14))
+	      (const_vector:V8HI [(const_int 1) (const_int 1)
+				  (const_int 1) (const_int 1)
+				  (const_int 1) (const_int 1)
+				  (const_int 1) (const_int 1)]))
+	    (const_int 1))))]
+  "TARGET_MNI && ix86_binary_operator_ok (MULT, V8HImode, operands)"
+  "pmulhrsw\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseimul")
+   (set_attr "mode" "TI")])
+
+(define_insn "mni_pmulhrswv4hi3"
+  [(set (match_operand:V4HI 0 "register_operand" "=y")
+	(truncate:V4HI
+	  (lshiftrt:V4SI
+	    (plus:V4SI
+	      (lshiftrt:V4SI
+		(mult:V4SI
+		  (sign_extend:V4SI
+		    (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
+		  (sign_extend:V4SI
+		    (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
+		(const_int 14))
+	      (const_vector:V4HI [(const_int 1) (const_int 1)
+				  (const_int 1) (const_int 1)]))
+	    (const_int 1))))]
+  "TARGET_MNI && ix86_binary_operator_ok (MULT, V4HImode, operands)"
+  "pmulhrsw\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseimul")
+   (set_attr "mode" "DI")])
+
+(define_insn "mni_pshufbv16qi3"
+  [(set (match_operand:V16QI 0 "register_operand" "=x")
+	(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
+		       (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
+		       UNSPEC_PSHUFB))]
+  "TARGET_MNI"
+  "pshufb\t{%2, %0|%0, %2}";
+  [(set_attr "type" "sselog1")
+   (set_attr "mode" "TI")])
+
+(define_insn "mni_pshufbv8qi3"
+  [(set (match_operand:V8QI 0 "register_operand" "=y")
+	(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0")
+		      (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
+		      UNSPEC_PSHUFB))]
+  "TARGET_MNI"
+  "pshufb\t{%2, %0|%0, %2}";
+  [(set_attr "type" "sselog1")
+   (set_attr "mode" "DI")])
+
+(define_insn "mni_psign<mode>3"
+  [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
+	(unspec:SSEMODE124 [(match_operand:SSEMODE124 1 "register_operand" "0")
+			    (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")]
+			    UNSPEC_PSIGN))]
+  "TARGET_MNI"
+  "psign<ssevecsize>\t{%2, %0|%0, %2}";
+  [(set_attr "type" "sselog1")
+   (set_attr "mode" "TI")])
+
+(define_insn "mni_psign<mode>3"
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
+	(unspec:MMXMODEI [(match_operand:MMXMODEI 1 "register_operand" "0")
+			  (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")]
+			  UNSPEC_PSIGN))]
+  "TARGET_MNI"
+  "psign<mmxvecsize>\t{%2, %0|%0, %2}";
+  [(set_attr "type" "sselog1")
+   (set_attr "mode" "DI")])
+
+(define_insn "mni_palignrti"
+  [(set (match_operand:TI 0 "register_operand" "=x")
+	(unspec:TI [(match_operand:TI 1 "register_operand" "0")
+		    (match_operand:TI 2 "nonimmediate_operand" "xm")
+		    (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
+		    UNSPEC_PALIGNR))]
+  "TARGET_MNI"
+{
+  operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
+  return "palignr\t{%3, %2, %0|%0, %2, %3}";
+}
+  [(set_attr "type" "sseishft")
+   (set_attr "mode" "TI")])
+
+(define_insn "mni_palignrdi"
+  [(set (match_operand:DI 0 "register_operand" "=y")
+	(unspec:DI [(match_operand:DI 1 "register_operand" "0")
+		    (match_operand:DI 2 "nonimmediate_operand" "ym")
+		    (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
+		    UNSPEC_PALIGNR))]
+  "TARGET_MNI"
+{
+  operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
+  return "palignr\t{%3, %2, %0|%0, %2, %3}";
+}
+  [(set_attr "type" "sseishft")
+   (set_attr "mode" "DI")])
+
+(define_insn "mni_pabs<mode>2"
+  [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
+	(abs:SSEMODE124 (match_operand:SSEMODE124 1 "nonimmediate_operand" "xm")))]
+  "TARGET_MNI"
+  "pabs<ssevecsize>\t{%1, %0|%0, %1}";
+  [(set_attr "type" "sselog1")
+   (set_attr "mode" "TI")])
+
+(define_insn "mni_pabs<mode>2"
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
+	(abs:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]
+  "TARGET_MNI"
+  "pabs<mmxvecsize>\t{%1, %0|%0, %1}";
+  [(set_attr "type" "sselog1")
+   (set_attr "mode" "DI")])
--- gcc/config/i386/tmmintrin.h.mni	2006-02-24 13:39:19.000000000 -0800
+++ gcc/config/i386/tmmintrin.h	2006-02-24 13:39:19.000000000 -0800
@@ -0,0 +1,224 @@
+/* Copyright (C) 2006 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+/* As a special exception, if you include this header file into source
+   files compiled by GCC, this header file does not by itself cause
+   the resulting executable to be covered by the GNU General Public
+   License.  This exception does not however invalidate any other
+   reasons why the executable file might be covered by the GNU General
+   Public License.  */
+
+/* Implemented from the specification included in the Intel C++ Compiler
+   User Guide and Reference, version 9.1.  */
+
+#ifndef _TMMINTRIN_H_INCLUDED
+#define _TMMINTRIN_H_INCLUDED
+
+#ifdef __MNI__
+#include <pmmintrin.h>
+
+static __inline __m128i
+_mm_hadd_epi16 (__m128i __X, __m128i __Y)
+{
+  return (__m128i) __builtin_ia32_phaddw128 ((__v8hi)__X, (__v8hi)__Y);
+}
+
+static __inline __m128i
+_mm_hadd_epi32 (__m128i __X, __m128i __Y)
+{
+  return (__m128i) __builtin_ia32_phaddd128 ((__v4si)__X, (__v4si)__Y);
+}
+
+static __inline __m128i
+_mm_hadds_epi16 (__m128i __X, __m128i __Y)
+{
+  return (__m128i) __builtin_ia32_phaddsw128 ((__v8hi)__X, (__v8hi)__Y);
+}
+
+static __inline __m64
+_mm_hadd_pi16 (__m64 __X, __m64 __Y)
+{
+  return (__m64) __builtin_ia32_phaddw ((__v4hi)__X, (__v4hi)__Y);
+}
+
+static __inline __m64
+_mm_hadd_pi32 (__m64 __X, __m64 __Y)
+{
+  return (__m64) __builtin_ia32_phaddd ((__v2si)__X, (__v2si)__Y);
+}
+
+static __inline __m64
+_mm_hadds_pi16 (__m64 __X, __m64 __Y)
+{
+  return (__m64) __builtin_ia32_phaddsw ((__v4hi)__X, (__v4hi)__Y);
+}
+
+static __inline __m128i
+_mm_hsub_epi16 (__m128i __X, __m128i __Y)
+{
+  return (__m128i) __builtin_ia32_phsubw128 ((__v8hi)__X, (__v8hi)__Y);
+}
+
+static __inline __m128i
+_mm_hsub_epi32 (__m128i __X, __m128i __Y)
+{
+  return (__m128i) __builtin_ia32_phsubd128 ((__v4si)__X, (__v4si)__Y);
+}
+
+static __inline __m128i
+_mm_hsubs_epi16 (__m128i __X, __m128i __Y)
+{
+  return (__m128i) __builtin_ia32_phsubsw128 ((__v8hi)__X, (__v8hi)__Y);
+}
+
+static __inline __m64
+_mm_hsub_pi16 (__m64 __X, __m64 __Y)
+{
+  return (__m64) __builtin_ia32_phsubw ((__v4hi)__X, (__v4hi)__Y);
+}
+
+static __inline __m64
+_mm_hsub_pi32 (__m64 __X, __m64 __Y)
+{
+  return (__m64) __builtin_ia32_phsubd ((__v2si)__X, (__v2si)__Y);
+}
+
+static __inline __m64
+_mm_hsubs_pi16 (__m64 __X, __m64 __Y)
+{
+  return (__m64) __builtin_ia32_phsubsw ((__v4hi)__X, (__v4hi)__Y);
+}
+
+static __inline __m128i
+_mm_maddubs_epi16 (__m128i __X, __m128i __Y)
+{
+  return (__m128i) __builtin_ia32_pmaddubsw128 ((__v16qi)__X, (__v16qi)__Y);
+}
+
+static __inline __m64
+_mm_maddubs_pi16 (__m64 __X, __m64 __Y)
+{
+  return (__m64) __builtin_ia32_pmaddubsw ((__v8qi)__X, (__v8qi)__Y);
+}
+
+static __inline __m128i
+_mm_mulhrs_epi16 (__m128i __X, __m128i __Y)
+{
+  return (__m128i) __builtin_ia32_pmulhrsw128 ((__v8hi)__X, (__v8hi)__Y);
+}
+
+static __inline __m64
+_mm_mulhrs_pi16 (__m64 __X, __m64 __Y)
+{
+  return (__m64) __builtin_ia32_pmulhrsw ((__v4hi)__X, (__v4hi)__Y);
+}
+
+static __inline __m128i
+_mm_shuffle_epi8 (__m128i __X, __m128i __Y)
+{
+  return (__m128i) __builtin_ia32_pshufb128 ((__v16qi)__X, (__v16qi)__Y);
+}
+
+static __inline __m64
+_mm_shuffle_pi8 (__m64 __X, __m64 __Y)
+{
+  return (__m64) __builtin_ia32_pshufb ((__v8qi)__X, (__v8qi)__Y);
+}
+
+static __inline __m128i
+_mm_sign_epi8 (__m128i __X, __m128i __Y)
+{
+  return (__m128i) __builtin_ia32_psignb128 ((__v16qi)__X, (__v16qi)__Y);
+}
+
+static __inline __m128i
+_mm_sign_epi16 (__m128i __X, __m128i __Y)
+{
+  return (__m128i) __builtin_ia32_psignw128 ((__v8hi)__X, (__v8hi)__Y);
+}
+
+static __inline __m128i
+_mm_sign_epi32 (__m128i __X, __m128i __Y)
+{
+  return (__m128i) __builtin_ia32_psignd128 ((__v4si)__X, (__v4si)__Y);
+}
+
+static __inline __m64
+_mm_sign_pi8 (__m64 __X, __m64 __Y)
+{
+  return (__m64) __builtin_ia32_psignb ((__v8qi)__X, (__v8qi)__Y);
+}
+
+static __inline __m64
+_mm_sign_pi16 (__m64 __X, __m64 __Y)
+{
+  return (__m64) __builtin_ia32_psignw ((__v4hi)__X, (__v4hi)__Y);
+}
+
+static __inline __m64
+_mm_sign_pi32 (__m64 __X, __m64 __Y)
+{
+  return (__m64) __builtin_ia32_psignd ((__v2si)__X, (__v2si)__Y);
+}
+
+#define _mm_alignr_epi8(__X, __Y, __N) \
+  ((__m128i)__builtin_ia32_palignr128 ((__v2di) __X, (__v2di) __Y, (__N) * 8))
+
+#define _mm_alignr_pi8(__X, __Y, __N) \
+  ((__m64)__builtin_ia32_palignr ((long long) (__X), (long long) (__Y), (__N) * 8))
+
+static __inline __m128i
+_mm_abs_epi8 (__m128i __X)
+{
+  return (__m128i) __builtin_ia32_pabsb128 ((__v16qi)__X);
+}
+
+static __inline __m128i
+_mm_abs_epi16 (__m128i __X)
+{
+  return (__m128i) __builtin_ia32_pabsw128 ((__v8hi)__X);
+}
+
+static __inline __m128i
+_mm_abs_epi32 (__m128i __X)
+{
+  return (__m128i) __builtin_ia32_pabsd128 ((__v4si)__X);
+}
+
+static __inline __m64
+_mm_abs_pi8 (__m64 __X)
+{
+  return (__m64) __builtin_ia32_pabsb ((__v8qi)__X);
+}
+
+static __inline __m64
+_mm_abs_pi16 (__m64 __X)
+{
+  return (__m64) __builtin_ia32_pabsw ((__v4hi)__X);
+}
+
+static __inline __m64
+_mm_abs_pi32 (__m64 __X)
+{
+  return (__m64) __builtin_ia32_pabsd ((__v2si)__X);
+}
+
+#endif /* __MNI__ */
+
+#endif /* _TMMINTRIN_H_INCLUDED */
--- gcc/doc/extend.texi.mni	2006-02-21 22:42:04.000000000 -0800
+++ gcc/doc/extend.texi	2006-02-24 13:39:19.000000000 -0800
@@ -6701,6 +6701,52 @@ The following built-in functions are ava
 Generates the @code{movddup} machine instruction as a load from memory.
 @end table
 
+The following built-in functions are available when @option{-mmni} is used.
+All of them generate the machine instruction that is part of the name
+with MMX registers.
+
+ at smallexample
+v2si __builtin_ia32_phaddd (v2si, v2si)
+v4hi __builtin_ia32_phaddw (v4hi, v4hi)
+v4hi __builtin_ia32_phaddsw (v4hi, v4hi)
+v2si __builtin_ia32_phsubd (v2si, v2si)
+v4hi __builtin_ia32_phsubw (v4hi, v4hi)
+v4hi __builtin_ia32_phsubsw (v4hi, v4hi)
+v8qi __builtin_ia32_pmaddubsw (v8qi, v8qi)
+v4hi __builtin_ia32_pmulhrsw (v4hi, v4hi)
+v8qi __builtin_ia32_pshufb (v8qi, v8qi)
+v8qi __builtin_ia32_psignb (v8qi, v8qi)
+v2si __builtin_ia32_psignd (v2si, v2si)
+v4hi __builtin_ia32_psignw (v4hi, v4hi)
+long long __builtin_ia32_palignr (long long, long long, int)
+v8qi __builtin_ia32_pabsb (v8qi)
+v2si __builtin_ia32_pabsd (v2si)
+v4hi __builtin_ia32_pabsw (v4hi)
+ at end smallexample
+
+The following built-in functions are available when @option{-mmni} is used.
+All of them generate the machine instruction that is part of the name
+with SSE registers.
+
+ at smallexample
+v4si __builtin_ia32_phaddd128 (v4si, v4si)
+v8hi __builtin_ia32_phaddw128 (v8hi, v8hi)
+v8hi __builtin_ia32_phaddsw128 (v8hi, v8hi)
+v4si __builtin_ia32_phsubd128 (v4si, v4si)
+v8hi __builtin_ia32_phsubw128 (v8hi, v8hi)
+v8hi __builtin_ia32_phsubsw128 (v8hi, v8hi)
+v16qi __builtin_ia32_pmaddubsw128 (v16qi, v16qi)
+v8hi __builtin_ia32_pmulhrsw128 (v8hi, v8hi)
+v16qi __builtin_ia32_pshufb128 (v16qi, v16qi)
+v16qi __builtin_ia32_psignb128 (v16qi, v16qi)
+v4si __builtin_ia32_psignd128 (v4si, v4si)
+v8hi __builtin_ia32_psignw128 (v8hi, v8hi)
+v2di __builtin_ia32_palignr (v2di, v2di, int)
+v16qi __builtin_ia32_pabsb128 (v16qi)
+v4si __builtin_ia32_pabsd128 (v4si)
+v8hi __builtin_ia32_pabsw128 (v8hi)
+ at end smallexample
+
 The following built-in functions are available when @option{-m3dnow} is used.
 All of them generate the machine instruction that is part of the name.
 
--- gcc/doc/invoke.texi.mni	2006-02-14 13:17:58.000000000 -0800
+++ gcc/doc/invoke.texi	2006-02-24 13:42:50.000000000 -0800
@@ -522,7 +522,7 @@ Objective-C and Objective-C++ Dialects}.
 -mno-fp-ret-in-387  -msoft-float  -msvr3-shlib @gol
 -mno-wide-multiply  -mrtd  -malign-double @gol
 -mpreferred-stack-boundary=@var{num} @gol
--mmmx  -msse  -msse2 -msse3 -m3dnow @gol
+-mmmx  -msse  -msse2 -msse3 -mmni -m3dnow @gol
 -mthreads  -mno-align-stringops  -minline-all-stringops @gol
 -mpush-args  -maccumulate-outgoing-args  -m128bit-long-double @gol
 -m96bit-long-double  -mregparm=@var{num}  -msseregparm @gol
@@ -9343,6 +9343,8 @@ preferred alignment to @option{-mpreferr
 @itemx -mno-sse2
 @item -msse3
 @itemx -mno-sse3
+ at item -mmni
+ at itemx -mno-mni
 @item -m3dnow
 @itemx -mno-3dnow
 @opindex mmmx

gcc41-ppc32-retaddr.patch:

--- NEW FILE gcc41-ppc32-retaddr.patch ---
2005-11-28  Jakub Jelinek  <jakub at redhat.com>

	* config/rs6000/rs6000.c (rs6000_return_addr): If COUNT == 0,
	read word RETURN_ADDRESS_OFFSET bytes above arg_pointer_rtx
	instead of doing an extran indirection from frame_pointer_rtx.

	* gcc.dg/20051128-1.c: New test.

--- gcc/config/rs6000/rs6000.c.jj	2005-11-26 14:38:01.000000000 +0100
+++ gcc/config/rs6000/rs6000.c	2005-11-28 20:32:18.000000000 +0100
@@ -13166,17 +13166,22 @@ rs6000_return_addr (int count, rtx frame
      don't try to be too clever here.  */
   if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
     {
+      rtx x;
       cfun->machine->ra_needs_full_frame = 1;
 
-      return
-	gen_rtx_MEM
-	  (Pmode,
-	   memory_address
-	   (Pmode,
-	    plus_constant (copy_to_reg
-			   (gen_rtx_MEM (Pmode,
-					 memory_address (Pmode, frame))),
-			   RETURN_ADDRESS_OFFSET)));
+      if (count == 0)
+	{
+	  gcc_assert (frame == frame_pointer_rtx);
+	  x = arg_pointer_rtx;
+	}
+      else
+	{
+	  x = memory_address (Pmode, frame);
+	  x = copy_to_reg (gen_rtx_MEM (Pmode, x));
+	}
+
+      x = plus_constant (x, RETURN_ADDRESS_OFFSET);
+      return gen_rtx_MEM (Pmode, memory_address (Pmode, x));
     }
 
   cfun->machine->ra_need_lr = 1;
--- gcc/testsuite/gcc.dg/20051128-1.c.jj	2005-10-10 11:21:41.096999000 +0200
+++ gcc/testsuite/gcc.dg/20051128-1.c	2005-11-28 12:30:57.000000000 +0100
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fpic" } */
+
+extern void exit (int);
+extern void abort (void);
+
+int b;
+
+struct A
+{
+  void *pad[147];
+  void *ra, *h;
+  long o;
+};
+
+void
+__attribute__((noinline))
+foo (struct A *a, void *x)
+{
+  __builtin_memset (a, 0, sizeof (a));
+  if (!b)
+    exit (0);
+}
+
+void
+__attribute__((noinline))
+bar (void)
+{
+  struct A a;
+
+  __builtin_unwind_init ();
+  foo (&a, __builtin_return_address (0));
+}
+
+int
+main (void)
+{
+  bar ();
+  abort ();
+  return 0;
+}

gcc41-ppc64-m32-m64-multilib-only.patch:

--- NEW FILE gcc41-ppc64-m32-m64-multilib-only.patch ---
--- gcc/config/rs6000/t-linux64	2003-06-03 05:11:45.000000000 -0400
+++ gcc/config/rs6000/t-linux64	2003-06-11 17:07:16.000000000 -0400
@@ -4,13 +4,13 @@ LIB2FUNCS_EXTRA = tramp.S $(srcdir)/conf
 # Modify the shared lib version file
 SHLIB_MKMAP_OPTS = -v dotsyms=1
 
-MULTILIB_OPTIONS        = m64/m32 msoft-float
-MULTILIB_DIRNAMES       = 64 32 nof
+MULTILIB_OPTIONS        = m64/m32
+MULTILIB_DIRNAMES       = 64 32
 MULTILIB_EXTRA_OPTS     = fPIC mstrict-align
-MULTILIB_EXCEPTIONS     = m64/msoft-float
-MULTILIB_EXCLUSIONS     = m64/!m32/msoft-float
-MULTILIB_OSDIRNAMES	= ../lib64 ../lib nof
-MULTILIB_MATCHES        = $(MULTILIB_MATCHES_FLOAT)
+MULTILIB_EXCEPTIONS     =
+MULTILIB_EXCLUSIONS     =
+MULTILIB_OSDIRNAMES	= ../lib64 ../lib
+MULTILIB_MATCHES        =
 
 TARGET_LIBGCC2_CFLAGS = -mno-minimal-toc -fPIC
 

gcc41-rh184446.patch:

--- NEW FILE gcc41-rh184446.patch ---
for gcc/ChangeLog
from  Richard Henderson  <rth at redhat.com>, Alexandre Oliva  <aoliva at redhat.com>

	* config/rs6000/rs6000.c (rs6000_legitimize_tls_address): Use
	secure-plt-compatible load sequence to compute the GOT address
	for -fPIC -msecure-plt.

Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c.orig	2006-03-09 20:02:13.000000000 -0300
+++ gcc/config/rs6000/rs6000.c	2006-03-09 22:00:43.000000000 -0300
@@ -3081,7 +3081,7 @@ rs6000_legitimize_tls_address (rtx addr,
 	    {
 	      rtx gsym = rs6000_got_sym ();
 	      got = gen_reg_rtx (Pmode);
-	      if (flag_pic == 0)
+	      if (flag_pic == 0 || (flag_pic && TARGET_SECURE_PLT))
 		rs6000_emit_move (got, gsym, Pmode);
 	      else
 		{

gcc41-x86_64-sse3.patch:

--- NEW FILE gcc41-x86_64-sse3.patch ---
2005-11-17  H.J. Lu  <hongjiu.lu at intel.com>

	PR target/24879
	* config/i386/i386.c (ix86_init_mmx_sse_builtins): Add
	void_ftype_di_di and void_ftype_pcvoid_di_di. Use void_ftype_di_di
	on __builtin_ia32_mwait and void_ftype_pcvoid_di_di on
	__builtin_ia32_monitor for 64bit.
	(ix86_expand_builtin): Support 64bit monitor and mwait.

	* config/i386/pmmintrin.h (_mm_monitor): Remove macro. Use
	inline function.
	(_mm_mwait): Likewise.

	* config/i386/sse.md (sse3_mwait): Make it 32bit only.
	(sse3_mwait64): New. 64bit mwait.
	(sse3_monitor): Make it 32bit only.
	(sse3_monitor64): New. 64bit monitor.

gcc/testsuite/

2005-11-17  H.J. Lu  <hongjiu.lu at intel.com>

	PR target/24879
	* gcc.target/i386/monitor.c: New file.

--- gcc/config/i386/i386.c.sse3	2005-11-15 17:33:02.000000000 -0800
+++ gcc/config/i386/i386.c	2005-11-17 09:44:47.000000000 -0800
@@ -14347,10 +14347,20 @@ ix86_init_mmx_sse_builtins (void)
   tree void_ftype_unsigned_unsigned
     = build_function_type_list (void_type_node, unsigned_type_node,
 				unsigned_type_node, NULL_TREE);
+  tree void_ftype_di_di
+    = build_function_type_list (void_type_node,
+				long_long_unsigned_type_node,
+				long_long_unsigned_type_node,
+				NULL_TREE);
   tree void_ftype_pcvoid_unsigned_unsigned
     = build_function_type_list (void_type_node, const_ptr_type_node,
 				unsigned_type_node, unsigned_type_node,
 				NULL_TREE);
+  tree void_ftype_pcvoid_di_di
+    = build_function_type_list (void_type_node, const_ptr_type_node,
+				long_long_unsigned_type_node,
+				long_long_unsigned_type_node,
+				NULL_TREE);
   tree unsigned_ftype_void
     = build_function_type (unsigned_type_node, void_list_node);
   tree v2si_ftype_v4sf
@@ -14811,12 +14821,24 @@ ix86_init_mmx_sse_builtins (void)
   def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
 
   /* Prescott New Instructions.  */
-  def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
-	       void_ftype_pcvoid_unsigned_unsigned,
-	       IX86_BUILTIN_MONITOR);
-  def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
-	       void_ftype_unsigned_unsigned,
-	       IX86_BUILTIN_MWAIT);
+  if (TARGET_64BIT)
+    {
+      def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
+		   void_ftype_pcvoid_di_di,
+		   IX86_BUILTIN_MONITOR);
+      def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
+		   void_ftype_di_di,
+		   IX86_BUILTIN_MWAIT);
+    }
+  else
+    {
+      def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
+		   void_ftype_pcvoid_unsigned_unsigned,
+		   IX86_BUILTIN_MONITOR);
+      def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
+		   void_ftype_unsigned_unsigned,
+		   IX86_BUILTIN_MWAIT);
+    }
   def_builtin (MASK_SSE3, "__builtin_ia32_movshdup",
 	       v4sf_ftype_v4sf,
 	       IX86_BUILTIN_MOVSHDUP);
@@ -15660,13 +15682,17 @@ ix86_expand_builtin (tree exp, rtx targe
       op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
       op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
       op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
+      mode = TARGET_64BIT ? DImode : SImode;
       if (!REG_P (op0))
-	op0 = copy_to_mode_reg (SImode, op0);
+	op0 = copy_to_mode_reg (mode, op0);
       if (!REG_P (op1))
-	op1 = copy_to_mode_reg (SImode, op1);
+	op1 = copy_to_mode_reg (mode, op1);
       if (!REG_P (op2))
-	op2 = copy_to_mode_reg (SImode, op2);
-      emit_insn (gen_sse3_monitor (op0, op1, op2));
+	op2 = copy_to_mode_reg (mode, op2);
+      if (TARGET_64BIT)
+	emit_insn (gen_sse3_monitor64 (op0, op1, op2));
+      else
+	emit_insn (gen_sse3_monitor (op0, op1, op2));
       return 0;
 
     case IX86_BUILTIN_MWAIT:
@@ -15674,11 +15700,15 @@ ix86_expand_builtin (tree exp, rtx targe
       arg1 = TREE_VALUE (TREE_CHAIN (arglist));
       op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
       op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
+      mode = TARGET_64BIT ? DImode : SImode;
       if (!REG_P (op0))
-	op0 = copy_to_mode_reg (SImode, op0);
+	op0 = copy_to_mode_reg (mode, op0);
       if (!REG_P (op1))
-	op1 = copy_to_mode_reg (SImode, op1);
-      emit_insn (gen_sse3_mwait (op0, op1));
+	op1 = copy_to_mode_reg (mode, op1);
+      if (TARGET_64BIT)
+	emit_insn (gen_sse3_mwait64 (op0, op1));
+      else
+	emit_insn (gen_sse3_mwait (op0, op1));
       return 0;
 
     case IX86_BUILTIN_LDDQU:
--- gcc/config/i386/pmmintrin.h.sse3	2005-11-04 14:13:48.000000000 -0800
+++ gcc/config/i386/pmmintrin.h	2005-11-15 22:44:02.000000000 -0800
@@ -110,7 +110,6 @@ _mm_lddqu_si128 (__m128i const *__P)
   return (__m128i) __builtin_ia32_lddqu ((char const *)__P);
 }
 
-#if 0
 static __inline void __attribute__((__always_inline__))
 _mm_monitor (void const * __P, unsigned int __E, unsigned int __H)
 {
@@ -122,10 +121,6 @@ _mm_mwait (unsigned int __E, unsigned in
 {
   __builtin_ia32_mwait (__E, __H);
 }
-#else
-#define _mm_monitor(P, E, H)	__builtin_ia32_monitor ((P), (E), (H))
-#define _mm_mwait(E, H)		__builtin_ia32_mwait ((E), (H))
-#endif
 
 #endif /* __SSE3__ */
 
--- gcc/config/i386/sse.md.sse3	2005-11-04 14:13:48.000000000 -0800
+++ gcc/config/i386/sse.md	2005-11-17 09:25:31.000000000 -0800
@@ -3890,15 +3890,36 @@
   [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
 		     (match_operand:SI 1 "register_operand" "c")]
 		    UNSPECV_MWAIT)]
-  "TARGET_SSE3"
+  "TARGET_SSE3 && !TARGET_64BIT"
   "mwait\t%0, %1"
   [(set_attr "length" "3")])
 
+(define_insn "sse3_mwait64"
+  [(unspec_volatile [(match_operand:DI 0 "register_operand" "a")
+		     (match_operand:DI 1 "register_operand" "c")]
+		    UNSPECV_MWAIT)]
+  "TARGET_SSE3 && TARGET_64BIT"
+;; Older assembler doesn't support "mwait %rax,%rcx".
+;;  "mwait\t%0, %1"
+  "mwait"
+  [(set_attr "length" "3")])
+
 (define_insn "sse3_monitor"
   [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
 		     (match_operand:SI 1 "register_operand" "c")
 		     (match_operand:SI 2 "register_operand" "d")]
 		    UNSPECV_MONITOR)]
-  "TARGET_SSE3"
+  "TARGET_SSE3 && !TARGET_64BIT"
   "monitor\t%0, %1, %2"
   [(set_attr "length" "3")])
+
+(define_insn "sse3_monitor64"
+  [(unspec_volatile [(match_operand:DI 0 "register_operand" "a")
+		     (match_operand:DI 1 "register_operand" "c")
+		     (match_operand:DI 2 "register_operand" "d")]
+		    UNSPECV_MONITOR)]
+  "TARGET_SSE3 && TARGET_64BIT"
+;; Older assembler doesn't support "monitor %rax,%rcx,%rdx".
+;;  "monitor\t%0, %1, %2"
+  "monitor"
+  [(set_attr "length" "3")])
--- gcc/testsuite/gcc.target/i386/monitor.c.sse3	2005-11-15 22:59:54.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/monitor.c	2005-11-15 23:25:23.000000000 -0800
@@ -0,0 +1,27 @@
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O2 -msse3" } */
+
+/* Verify that they work in both 32bit and 64bit.  */
+
+#include <pmmintrin.h>
+
+void
+foo (char *p, int x, int y, int z)
+{
+   _mm_monitor (p, y, x);
+   _mm_mwait (z, y);
+}
+
+void
+bar (char *p, long x, long y, long z)
+{
+   _mm_monitor (p, y, x);
+   _mm_mwait (z, y);
+}
+
+void
+foo1 (char *p)
+{
+   _mm_monitor (p, 0, 0);
+   _mm_mwait (0, 0);
+}


Index: .cvsignore
===================================================================
RCS file: /cvs/extras/rpms/ghdl/devel/.cvsignore,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -r1.5 -r1.6
--- .cvsignore	18 Mar 2006 01:09:58 -0000	1.5
+++ .cvsignore	19 Mar 2006 15:13:36 -0000	1.6
@@ -4,4 +4,5 @@
 ghdl-imagef64fix.patch
 ghdl-0.20.tar.bz2
 ghdl-0.21.tar.bz2
+gcc-4.1.0-20060304.tar.bz2
 gcc-core-4.1.0.tar.bz2


Index: ghdl.spec
===================================================================
RCS file: /cvs/extras/rpms/ghdl/devel/ghdl.spec,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -r1.12 -r1.13
--- ghdl.spec	17 Mar 2006 23:31:35 -0000	1.12
+++ ghdl.spec	19 Mar 2006 15:13:36 -0000	1.13
@@ -1,10 +1,11 @@
 %define gccver 4.1.0
 %define ghdlver 0.21
+%define DATE 20060304
 
 Summary: A VHDL simulator, using the GCC technology
 Name: ghdl
 Version: 0.22
-Release: 0.49svn.0%{?dist}
+Release: 0.49svn.1%{?dist}
 License: GPL
 Group: Development/Languages
 URL: http://ghdl.free.fr/
@@ -12,16 +13,76 @@
 # check out the SVN repo
 # cd translate/gcc/
 # ./dist.sh sources
-Source0: http://ghdl.free.fr/ghdl-%{ghdlver}.tar.bz2
-Source1: ftp://gcc.gnu.org/pub/gcc/releases/gcc-%{gccver}/gcc-core-%{gccver}.tar.bz2
-Patch0: ghdl-svn49.patch
+Source0: gcc-%{gccver}-%{DATE}.tar.bz2
+Source100: http://ghdl.free.fr/ghdl-%{ghdlver}.tar.bz2
+Patch1: gcc41-ice-hack.patch
+Patch2: gcc41-ppc64-m32-m64-multilib-only.patch
+Patch3: gcc41-ia64-libunwind.patch
+Patch4: gcc41-gnuc-rh-release.patch
+Patch5: gcc41-java-nomulti.patch
+Patch6: gcc41-ada-pr18302.patch
+Patch7: gcc41-ada-tweaks.patch
+Patch8: gcc41-java-slow_pthread_self.patch
+Patch9: gcc41-ppc32-retaddr.patch
+Patch10: gcc41-x86_64-sse3.patch
+Patch11: gcc41-mni.patch
+Patch12: gcc41-cfaval.patch
+Patch13: gcc41-rh184446.patch
+Patch100: ghdl-svn49.patch
 BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n)
-BuildRequires: gcc-gnat >= 4.0.0-0.40, texinfo
 Requires(post): /sbin/install-info
 Requires(preun): /sbin/install-info
 Requires: gcc
 # gcc-gnat missing on ppc: Bug 174720
 ExcludeArch: ppc
+# (Build)Requires from fc gcc41 package
+%define multilib_64_archs sparc64 ppc64 s390x x86_64
+%ifarch s390x
+%define multilib_32_arch s390
+%endif
+%ifarch sparc64
+%define multilib_32_arch sparc
+%endif
+%ifarch ppc64
+%define multilib_32_arch ppc
+%endif
+%ifarch x86_64
+%define multilib_32_arch i386
+%endif
+# Need binutils with -pie support >= 2.14.90.0.4-4
+# Need binutils which can omit dot symbols and overlap .opd on ppc64 >= 2.15.91.0.2-4
+# Need binutils which handle -msecure-plt on ppc >= 2.16.91.0.2-2
+# Need binutils which support .weakref >= 2.16.91.0.3-1
+BuildRequires: binutils >= 2.16.91.0.3-1
+BuildRequires: zlib-devel, gettext, bison, flex, texinfo
+# Make sure pthread.h doesn't contain __thread tokens
+# Make sure glibc supports stack protector
+BuildRequires: glibc-devel >= 2.3.90-2
+%ifarch ppc ppc64 s390 s390x sparc sparcv9 alpha
+# Make sure glibc supports TFmode long double
+BuildRequires: glibc >= 2.3.90-35
+%endif
+%ifarch %{multilib_64_archs} sparc ppc
+# Ensure glibc{,-devel} is installed for both multilib arches
+BuildRequires: /lib/libc.so.6 /usr/lib/libc.so /lib64/libc.so.6 /usr/lib64/libc.so
+%endif
+# Ada requires Ada to build
+BuildRequires: gcc-gnat >= 3.1, libgnat >= 3.1
+# Need .eh_frame ld optimizations
+# Need proper visibility support
+# Need -pie support
+# Need --as-needed/--no-as-needed support
+# On ppc64, need omit dot symbols support and --non-overlapping-opd
+# Need binutils that owns /usr/bin/c++filt
+# Need binutils that support .weakref
+Requires: binutils >= 2.16.91.0.3-1
+# Make sure gdb will understand DW_FORM_strp
+Conflicts: gdb < 5.1-2
+Requires: glibc-devel >= 2.2.90-12
+%ifarch ppc ppc64 s390 s390x sparc sparcv9 alpha
+# Make sure glibc supports TFmode long double
+Requires: glibc >= 2.3.90-35
+%endif
 
 # Make sure we don't use clashing namespaces
 %define _vendor fedora_ghdl
@@ -50,13 +111,29 @@
 Ada95.
 
 %prep
-%setup -q -n gcc-%{gccver} -T -b 1 -a 0
+%setup -q -n gcc-%{gccver}-%{DATE} -T -b 0 -a 100
+%patch1 -p0 -b .ice-hack~
+%patch2 -p0 -b .ppc64-m32-m64-multilib-only~
+%patch3 -p0 -b .ia64-libunwind~
+#patch4 -p0 -b .gnuc-rh-release~
+%patch5 -p0 -b .java-nomulti~
+%patch6 -p0 -b .ada-pr18302~
+%patch7 -p0 -b .ada-tweaks~
+%patch8 -p0 -b .java-slow_pthread_self~
+%patch9 -p0 -b .ppc32-retaddr~
+%patch10 -p0 -b .x86_64-sse3~
+%patch11 -p0 -b .mni~
+%patch12 -p0 -b .cfaval~
+%patch13 -p0 -b .rh184446~
+sed -i -e 's/4\.1\.1/4.1.0/' gcc/BASE-VER gcc/version.c
+sed -i -e 's/" (Red Hat[^)]*)"/" (Red Hat %{version}-%{gccver})"/' gcc/version.c
 pushd ghdl-%{ghdlver}
-%patch0 -p1
+%patch100 -p1
 %{__mv} vhdl ../gcc/
 popd
 
 %build
+%{__rm} -fr obj-%{gcc_target_platform}
 %{__mkdir} obj-%{gcc_target_platform}
 pushd obj-%{gcc_target_platform}
 
@@ -104,6 +181,13 @@
 	--infodir=%{_infodir} \
 	--enable-languages=vhdl \
 	%{!?_without_mock:--disable-multilib} \
+	--enable-shared \
+	--enable-threads=posix \
+	--enable-checking=release \
+	--with-system-zlib \
+	--enable-__cxa_atexit \
+	--disable-libunwind-exceptions \
+	--disable-libgcj \
 %ifarch sparc
 	--host=%{gcc_target_platform} \
 	--build=%{gcc_target_platform} \
@@ -221,6 +305,9 @@
 %{_libexecdir}/gcc/
 
 %changelog
+* Sun Mar 19 2006 Thomas Sailer <t.sailer at alumni.ethz.ch> - 0.22-0.49svn.1
+- use core gcc as base compiler sources
+
 * Thu Mar 16 2006 Thomas Sailer <t.sailer at alumni.ethz.ch> - 0.22-0.49svn.0
 - update to svn49, using gcc 4.1.0
 


Index: sources
===================================================================
RCS file: /cvs/extras/rpms/ghdl/devel/sources,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -r1.5 -r1.6
--- sources	18 Mar 2006 01:09:58 -0000	1.5
+++ sources	19 Mar 2006 15:13:36 -0000	1.6
@@ -1,2 +1,2 @@
 a0ebb9b4ea9d33e67e6ae9768d10eb3a  ghdl-0.21.tar.bz2
-15efa164579c7cf4a48859ee87d2a1fa  gcc-core-4.1.0.tar.bz2
+cc39dd702c70d0a784c7ecdedbb503b7  gcc-4.1.0-20060304.tar.bz2


