rpms/xorg-x11-drv-ati/F-8 radeon-6.7.196-atombios-support.patch, NONE, 1.1 radeon-git-upstream-fixes.patch, 1.2, 1.3 xorg-x11-drv-ati.spec, 1.68, 1.69
Dave Airlie (airlied)
fedora-extras-commits at redhat.com
Thu Dec 6 05:47:16 UTC 2007
Author: airlied
Update of /cvs/pkgs/rpms/xorg-x11-drv-ati/F-8
In directory cvs-int.fedora.redhat.com:/tmp/cvs-serv17225
Modified Files:
radeon-git-upstream-fixes.patch xorg-x11-drv-ati.spec
Added Files:
radeon-6.7.196-atombios-support.patch
Log Message:
* Thu Dec 06 2007 Dave Airlie <airlied at redhat.com> 6.7.196-3
- radeon-6.7.196-atombios-support.patch - Add atombios support
- update git fix to upstream latest tree
- need to rely on autotools now due to atombios
radeon-6.7.196-atombios-support.patch:
--- NEW FILE radeon-6.7.196-atombios-support.patch ---
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c
new file mode 100644
index 0000000..1e48f81
--- /dev/null
+++ b/src/AtomBios/CD_Operations.c
@@ -0,0 +1,954 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+
+Module Name:
+
+ CD_Operations.c
+
+Abstract:
+
+ Functions Implementing Command Operations and other common functions
+
+Revision History:
+
+ NEG:27.09.2002 Initiated.
+--*/
+#define __SW_4
+
+#include "Decoder.h"
+#include "atombios.h"
+
+
+
+VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData);
+UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable);
+
+
+WRITE_IO_FUNCTION WritePCIFunctions[8] = {
+ WritePCIReg32,
+ WritePCIReg16, WritePCIReg16, WritePCIReg16,
+ WritePCIReg8,WritePCIReg8,WritePCIReg8,WritePCIReg8
+};
+WRITE_IO_FUNCTION WriteIOFunctions[8] = {
+ WriteSysIOReg32,
+ WriteSysIOReg16,WriteSysIOReg16,WriteSysIOReg16,
+ WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8
+};
+READ_IO_FUNCTION ReadPCIFunctions[8] = {
+ (READ_IO_FUNCTION)ReadPCIReg32,
+ (READ_IO_FUNCTION)ReadPCIReg16,
+ (READ_IO_FUNCTION)ReadPCIReg16,
+ (READ_IO_FUNCTION)ReadPCIReg16,
+ (READ_IO_FUNCTION)ReadPCIReg8,
+ (READ_IO_FUNCTION)ReadPCIReg8,
+ (READ_IO_FUNCTION)ReadPCIReg8,
+ (READ_IO_FUNCTION)ReadPCIReg8
+};
+READ_IO_FUNCTION ReadIOFunctions[8] = {
+ (READ_IO_FUNCTION)ReadSysIOReg32,
+ (READ_IO_FUNCTION)ReadSysIOReg16,
+ (READ_IO_FUNCTION)ReadSysIOReg16,
+ (READ_IO_FUNCTION)ReadSysIOReg16,
+ (READ_IO_FUNCTION)ReadSysIOReg8,
+ (READ_IO_FUNCTION)ReadSysIOReg8,
+ (READ_IO_FUNCTION)ReadSysIOReg8,
+ (READ_IO_FUNCTION)ReadSysIOReg8
+};
+READ_IO_FUNCTION GetParametersDirectArray[8]={
+ GetParametersDirect32,
+ GetParametersDirect16,GetParametersDirect16,GetParametersDirect16,
+ GetParametersDirect8,GetParametersDirect8,GetParametersDirect8,
+ GetParametersDirect8
+};
+
+COMMANDS_DECODER PutDataFunctions[6] = {
+ PutDataRegister,
+ PutDataPS,
+ PutDataWS,
+ PutDataFB,
+ PutDataPLL,
+ PutDataMC
+};
+CD_GET_PARAMETERS GetDestination[6] = {
+ GetParametersRegister,
+ GetParametersPS,
+ GetParametersWS,
+ GetParametersFB,
+ GetParametersPLL,
+ GetParametersMC
+};
+
+COMMANDS_DECODER SkipDestination[6] = {
+ SkipParameters16,
+ SkipParameters8,
+ SkipParameters8,
+ SkipParameters8,
+ SkipParameters8,
+ SkipParameters8
+};
+
+CD_GET_PARAMETERS GetSource[8] = {
+ GetParametersRegister,
+ GetParametersPS,
+ GetParametersWS,
+ GetParametersFB,
+ GetParametersIndirect,
+ GetParametersDirect,
+ GetParametersPLL,
+ GetParametersMC
+};
+
+UINT32 AlignmentMask[8] = {0xFFFFFFFF,0xFFFF,0xFFFF,0xFFFF,0xFF,0xFF,0xFF,0xFF};
+UINT8 SourceAlignmentShift[8] = {0,0,8,16,0,8,16,24};
+UINT8 DestinationAlignmentShift[4] = {0,8,16,24};
+
+#define INDIRECTIO_ID 1
+#define INDIRECTIO_END_OF_ID 9
+
+VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID IndirectIOCommand_MOVE(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT32 temp);
+VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+
+INDIRECT_IO_PARSER_COMMANDS IndirectIOParserCommands[10]={
+ {IndirectIOCommand,1},
+ {IndirectIOCommand,2},
+ {ReadIndReg32,3},
+ {WriteIndReg32,3},
+ {IndirectIOCommand_CLEAR,3},
+ {IndirectIOCommand_SET,3},
+ {IndirectIOCommand_MOVE_INDEX,4},
+ {IndirectIOCommand_MOVE_ATTR,4},
+ {IndirectIOCommand_MOVE_DATA,4},
+ {IndirectIOCommand,3}
+};
+
+
+VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+}
+
+
+VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]);
+ pParserTempData->IndirectData |=(((pParserTempData->Index >> pParserTempData->IndirectIOTablePointer[2]) &
+ (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]);
+}
+
+VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
+ pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]);
+ pParserTempData->IndirectData |=(((pParserTempData->AttributesData >> pParserTempData->IndirectIOTablePointer[2])
+ & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]);
+}
[...16536 lines suppressed...]
+#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
+# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
+#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
+# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
+# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
+# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
+# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
+#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
+# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
+# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
+#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
+# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
+
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
+# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
+
+#define AVIVO_LVTMA_CNTL 0x7a80
+# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
+# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
+# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
+# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
+# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
+# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
+# define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
+#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84
+#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
+# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
+
+
+
+#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
+# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
+# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
+# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
+# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
+
+#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
+# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
+# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
+#define AVIVO_LVTMA_CLOCK_ENABLE 0x7b00
+
+#define AVIVO_LVTMA_TRANSMITTER_ENABLE 0x7b04
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
+# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
+
+#define AVIVO_LVTMA_TRANSMITTER_CONTROL 0x7b10
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
+# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
+
+#define AVIVO_LVTMA_PWRSEQ_CNTL 0x7af0
+# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
+# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
+# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
+# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4)
+# define AVIVO_LVTMA_SYNCEN (1 << 8)
+# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9)
+# define AVIVO_LVTMA_SYNCEN_POL (1 << 10)
+# define AVIVO_LVTMA_DIGON (1 << 16)
+# define AVIVO_LVTMA_DIGON_OVRD (1 << 17)
+# define AVIVO_LVTMA_DIGON_POL (1 << 18)
+# define AVIVO_LVTMA_BLON (1 << 24)
+# define AVIVO_LVTMA_BLON_OVRD (1 << 25)
+# define AVIVO_LVTMA_BLON_POL (1 << 26)
+
+#define AVIVO_LVTMA_PWRSEQ_STATE 0x7af4
+# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
+# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
+# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
+# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
+# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
+# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
+
+#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8
+# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0)
+# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00
+# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8
+
+#define AVIVO_GPIO_0 0x7e30
+#define AVIVO_GPIO_1 0x7e40
+#define AVIVO_GPIO_2 0x7e50
+#define AVIVO_GPIO_3 0x7e60
+
+#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
+
+#define AVIVO_I2C_STATUS 0x7d30
+# define AVIVO_I2C_STATUS_DONE (1 << 0)
+# define AVIVO_I2C_STATUS_NACK (1 << 1)
+# define AVIVO_I2C_STATUS_HALT (1 << 2)
+# define AVIVO_I2C_STATUS_GO (1 << 3)
+# define AVIVO_I2C_STATUS_MASK 0x7
+/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
+ * DONE? */
+# define AVIVO_I2C_STATUS_CMD_RESET 0x7
+# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3)
+#define AVIVO_I2C_STOP 0x7d34
+#define AVIVO_I2C_START_CNTL 0x7d38
+# define AVIVO_I2C_START (1 << 8)
+# define AVIVO_I2C_CONNECTOR0 (0 << 16)
+# define AVIVO_I2C_CONNECTOR1 (1 << 16)
+#define R520_I2C_START (1<<0)
+#define R520_I2C_STOP (1<<1)
+#define R520_I2C_RX (1<<2)
+#define R520_I2C_EN (1<<8)
+#define R520_I2C_DDC1 (0<<16)
+#define R520_I2C_DDC2 (1<<16)
+#define R520_I2C_DDC3 (2<<16)
+#define R520_I2C_DDC_MASK (3<<16)
+#define AVIVO_I2C_CONTROL2 0x7d3c
+# define AVIVO_I2C_7D3C_SIZE_SHIFT 8
+# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8)
+#define AVIVO_I2C_CONTROL3 0x7d40
+/* Reading is done 4 bytes at a time: read the bottom 8 bits from
+ * 7d44, four times in a row.
+ * Writing is a little more complex. First write DATA with
+ * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
+ * magic number, zz is, I think, the slave address, and yy is the byte
+ * you want to write. */
+#define AVIVO_I2C_DATA 0x7d44
+#define R520_I2C_ADDR_COUNT_MASK (0x7)
+#define R520_I2C_DATA_COUNT_SHIFT (8)
+#define R520_I2C_DATA_COUNT_MASK (0xF00)
+#define AVIVO_I2C_CNTL 0x7d50
+# define AVIVO_I2C_EN (1 << 0)
+# define AVIVO_I2C_RESET (1 << 8)
+
+#define R600_MC_VM_FB_LOCATION 0x2180
+#define R600_MC_VM_AGP_TOP 0x2184
+#define R600_MC_VM_AGP_BOT 0x2188
+#define R600_MC_VM_AGP_BASE 0x218c
+#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
+#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
+#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
+
+#define R600_BUS_CNTL 0x5420
+#define R600_CONFIG_CNTL 0x5424
+#define R600_CONFIG_MEMSIZE 0x5428
+#define R600_CONFIG_F0_BASE 0x542C
+#define R600_CONFIG_APER_SIZE 0x5430
#endif
radeon-git-upstream-fixes.patch:
View full diff with command:
/usr/bin/cvs -f diff -kk -u -N -r 1.2 -r 1.3 radeon-git-upstream-fixes.patch
Index: radeon-git-upstream-fixes.patch
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/F-8/radeon-git-upstream-fixes.patch,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -r1.2 -r1.3
--- radeon-git-upstream-fixes.patch 19 Nov 2007 00:13:28 -0000 1.2
+++ radeon-git-upstream-fixes.patch 6 Dec 2007 05:47:11 -0000 1.3
@@ -11,10 +11,1559 @@
AC_CHECK_FILE([${sdkdir}/dri.h],
[have_dri_h="yes"], [have_dri_h="no"])
AC_CHECK_FILE([${sdkdir}/sarea.h],
+diff --git a/man/radeon.man b/man/radeon.man
+index 5d31eb1..3c4df23 100644
+--- a/man/radeon.man
++++ b/man/radeon.man
+@@ -383,14 +383,14 @@ case. This is only useful for LVDS panels (laptop internal panels).
+ The default is
+ .B on.
+ .TP
+-.BI "Option \*TVDACLoadDetect\*q \*q" boolean \*q
++.BI "Option \*qTVDACLoadDetect\*q \*q" boolean \*q
+ Enable load detection on the TV DAC. The TV DAC is used to drive both
+ TV-OUT and analog monitors. Load detection is often unreliable in the
+ TV DAC so it is disabled by default.
+ The default is
+ .B off.
+ .TP
+-.BI "Option \*DefaultTMDSPLL\*q \*q" boolean \*q
++.BI "Option \*qDefaultTMDSPLL\*q \*q" boolean \*q
+ Use the default driver provided TMDS PLL values rather than the ones
+ provided by the bios. This option has no effect on Mac cards. Enable
+ this option if you are having problems with a DVI monitor using the
+@@ -414,20 +414,59 @@ The default is
+ .TP
+ .BI "Option \*qMacModel\*q \*q" string \*q
+ .br
+-Used to specify Mac models for connector tables and quirks. Only valid
+- on PowerPC.
++Used to specify Mac models for connector tables and quirks. If you have
++a powerbook or mini with DVI that does not work properly, try the alternate
++ options as Apple does not seem to provide a good way of knowing whether
++ they use internal or external TMDS for DVI. Only valid on PowerPC.
+ .br
+ ibook \-\- ibooks
+ .br
+-powerbook-duallink \-\- Powerbooks with external DVI
++powerbook-external \-\- Powerbooks with external DVI
+ .br
+-powerbook \-\- Powerbooks with integrated DVI
++powerbook-internal \-\- Powerbooks with integrated DVI
+ .br
+-mini \-\- Mac Mini
++powerbook-vga \-\- Powerbooks with VGA rather than DVI
++.br
++powerbook-duallink \-\- powerbook-external alias
++.br
++powerbook \-\- powerbook-internal alias
++.br
++mini-external \-\- Mac Mini with external DVI
++.br
++mini-internal \-\- Mac Mini with integrated DVI
++.br
++mini \-\- mini-external alias
++.br
++imac-g5-isight \-\- iMac G5 iSight
++.br
++The default value is
++.B undefined.
++.TP
++.BI "Option \*qTVStandard\*q \*q" string \*q
++.br
++Used to specify the default TV standard if you want to use something other than
++the bios default. Valid options are:
++.br
++ntsc
++.br
++pal
++.br
++pal-m
++.br
++pal-60
++.br
++ntsc-j
++.br
++scart-pal
+ .br
+ The default value is
+ .B undefined.
+ .TP
++.BI "Option \*qForceTVOut\*q \*q" boolean \*q
++Enable this option to force TV Out to always be detected as attached.
++The default is
++.B off
++.TP
+
+ .SH SEE ALSO
+ __xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
+diff --git a/src/Makefile.am b/src/Makefile.am
+index ff1e225..5152577 100644
+--- a/src/Makefile.am
++++ b/src/Makefile.am
+@@ -171,7 +171,6 @@ EXTRA_DIST = \
+ r128_reg.h \
+ r128_sarea.h \
+ r128_version.h \
+- radeon_chipset.h \
+ radeon_common.h \
+ radeon_commonfuncs.c \
+ radeon_dri.h \
+@@ -191,4 +190,10 @@ EXTRA_DIST = \
+ theatre.h \
+ theatre_reg.h \
+ atipciids.h \
+- atipcirename.h
++ atipcirename.h \
++ ati_pciids_gen.h \
++ radeon_chipinfo_gen.h \
++ radeon_chipset_gen.h \
++ radeon_pci_chipset_gen.h \
++ pcidb/ati_pciids.csv \
++ pcidb/parse_pci_ids.pl
+diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
+new file mode 100644
+index 0000000..ad54f64
+--- /dev/null
++++ b/src/ati_pciids_gen.h
+@@ -0,0 +1,219 @@
++#define PCI_CHIP_RV380_3150 0x3150
++#define PCI_CHIP_RV380_3152 0x3152
++#define PCI_CHIP_RV380_3154 0x3154
++#define PCI_CHIP_RV380_3E50 0x3E50
++#define PCI_CHIP_RV380_3E54 0x3E54
++#define PCI_CHIP_RS100_4136 0x4136
++#define PCI_CHIP_RS200_4137 0x4137
++#define PCI_CHIP_R300_AD 0x4144
++#define PCI_CHIP_R300_AE 0x4145
++#define PCI_CHIP_R300_AF 0x4146
++#define PCI_CHIP_R300_AG 0x4147
++#define PCI_CHIP_R350_AH 0x4148
++#define PCI_CHIP_R350_AI 0x4149
++#define PCI_CHIP_R350_AJ 0x414A
++#define PCI_CHIP_R350_AK 0x414B
++#define PCI_CHIP_RV350_AP 0x4150
++#define PCI_CHIP_RV350_AQ 0x4151
++#define PCI_CHIP_RV360_AR 0x4152
++#define PCI_CHIP_RV350_AS 0x4153
++#define PCI_CHIP_RV350_AT 0x4154
++#define PCI_CHIP_RV350_4155 0x4155
++#define PCI_CHIP_RV350_AV 0x4156
++#define PCI_CHIP_MACH32 0x4158
++#define PCI_CHIP_RS250_4237 0x4237
++#define PCI_CHIP_R200_BB 0x4242
++#define PCI_CHIP_R200_BC 0x4243
++#define PCI_CHIP_RS100_4336 0x4336
++#define PCI_CHIP_RS200_4337 0x4337
++#define PCI_CHIP_MACH64CT 0x4354
++#define PCI_CHIP_MACH64CX 0x4358
++#define PCI_CHIP_RS250_4437 0x4437
++#define PCI_CHIP_MACH64ET 0x4554
++#define PCI_CHIP_MACH64GB 0x4742
++#define PCI_CHIP_MACH64GD 0x4744
++#define PCI_CHIP_MACH64GI 0x4749
++#define PCI_CHIP_MACH64GL 0x474C
++#define PCI_CHIP_MACH64GM 0x474D
++#define PCI_CHIP_MACH64GN 0x474E
++#define PCI_CHIP_MACH64GO 0x474F
++#define PCI_CHIP_MACH64GP 0x4750
++#define PCI_CHIP_MACH64GQ 0x4751
++#define PCI_CHIP_MACH64GR 0x4752
++#define PCI_CHIP_MACH64GS 0x4753
++#define PCI_CHIP_MACH64GT 0x4754
++#define PCI_CHIP_MACH64GU 0x4755
++#define PCI_CHIP_MACH64GV 0x4756
++#define PCI_CHIP_MACH64GW 0x4757
++#define PCI_CHIP_MACH64GX 0x4758
++#define PCI_CHIP_MACH64GY 0x4759
++#define PCI_CHIP_MACH64GZ 0x475A
++#define PCI_CHIP_RV250_If 0x4966
++#define PCI_CHIP_RV250_Ig 0x4967
++#define PCI_CHIP_R420_JH 0x4A48
++#define PCI_CHIP_R420_JI 0x4A49
++#define PCI_CHIP_R420_JJ 0x4A4A
++#define PCI_CHIP_R420_JK 0x4A4B
++#define PCI_CHIP_R420_JL 0x4A4C
++#define PCI_CHIP_R420_JM 0x4A4D
++#define PCI_CHIP_R420_JN 0x4A4E
++#define PCI_CHIP_R420_4A4F 0x4A4F
++#define PCI_CHIP_R420_JP 0x4A50
++#define PCI_CHIP_R481_4B49 0x4B49
++#define PCI_CHIP_R481_4B4A 0x4B4A
++#define PCI_CHIP_R481_4B4B 0x4B4B
++#define PCI_CHIP_R481_4B4C 0x4B4C
++#define PCI_CHIP_MACH64LB 0x4C42
++#define PCI_CHIP_MACH64LD 0x4C44
++#define PCI_CHIP_RAGE128LE 0x4C45
++#define PCI_CHIP_RAGE128LF 0x4C46
++#define PCI_CHIP_MACH64LG 0x4C47
++#define PCI_CHIP_MACH64LI 0x4C49
++#define PCI_CHIP_MACH64LM 0x4C4D
[...2390 lines suppressed...]
+- { PCI_CHIP_R423_UI, PCI_CHIP_R423_UI, RES_SHARED_VGA },
+- { PCI_CHIP_R423_UJ, PCI_CHIP_R423_UJ, RES_SHARED_VGA },
+- { PCI_CHIP_R423_UK, PCI_CHIP_R423_UK, RES_SHARED_VGA },
+- { PCI_CHIP_R423_UQ, PCI_CHIP_R423_UQ, RES_SHARED_VGA },
+- { PCI_CHIP_R423_UR, PCI_CHIP_R423_UR, RES_SHARED_VGA },
+- { PCI_CHIP_R423_UT, PCI_CHIP_R423_UT, RES_SHARED_VGA },
+- { PCI_CHIP_R423_5D57, PCI_CHIP_R423_5D57, RES_SHARED_VGA },
+- { PCI_CHIP_R423_5550, PCI_CHIP_R423_5550, RES_SHARED_VGA },
+- { PCI_CHIP_R430_5D49, PCI_CHIP_R430_5D49, RES_SHARED_VGA },
+- { PCI_CHIP_R430_5D4A, PCI_CHIP_R430_5D4A, RES_SHARED_VGA },
+- { PCI_CHIP_R430_5D48, PCI_CHIP_R430_5D48, RES_SHARED_VGA },
+- { PCI_CHIP_R430_554F, PCI_CHIP_R430_554F, RES_SHARED_VGA },
+- { PCI_CHIP_R430_554D, PCI_CHIP_R430_554D, RES_SHARED_VGA },
+- { PCI_CHIP_R430_554E, PCI_CHIP_R430_554E, RES_SHARED_VGA },
+- { PCI_CHIP_R430_554C, PCI_CHIP_R430_554C, RES_SHARED_VGA },
+- { PCI_CHIP_R480_5D4C, PCI_CHIP_R480_5D4C, RES_SHARED_VGA },
+- { PCI_CHIP_R480_5D50, PCI_CHIP_R480_5D50, RES_SHARED_VGA },
+- { PCI_CHIP_R480_5D4E, PCI_CHIP_R480_5D4E, RES_SHARED_VGA },
+- { PCI_CHIP_R480_5D4F, PCI_CHIP_R480_5D4F, RES_SHARED_VGA },
+- { PCI_CHIP_R480_5D52, PCI_CHIP_R480_5D52, RES_SHARED_VGA },
+- { PCI_CHIP_R480_5D4D, PCI_CHIP_R480_5D4D, RES_SHARED_VGA },
+- { PCI_CHIP_R481_4B4B, PCI_CHIP_R481_4B4B, RES_SHARED_VGA },
+- { PCI_CHIP_R481_4B4A, PCI_CHIP_R481_4B4A, RES_SHARED_VGA },
+- { PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA },
+- { PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA },
+-
+- { -1, -1, RES_UNDEFINED }
+-};
++#include "radeon_pci_chipset_gen.h"
+
+ int gRADEONEntityIndex = -1;
+
+diff --git a/src/radeon_render.c b/src/radeon_render.c
+index 5074fe1..490dec1 100644
+--- a/src/radeon_render.c
++++ b/src/radeon_render.c
+@@ -392,7 +392,7 @@ static Bool FUNC_NAME(R100SetupTexture)(
+ #endif
+ ACCEL_PREAMBLE();
+
+- if ((width > 2048) || (height > 2048))
++ if ((width > 2047) || (height > 2047))
+ return FALSE;
+
+ txformat = RadeonGetTextureFormat(format);
+@@ -424,7 +424,7 @@ static Bool FUNC_NAME(R100SetupTexture)(
+ txformat |= ATILog2(width) << RADEON_TXFORMAT_WIDTH_SHIFT;
+ txformat |= ATILog2(height) << RADEON_TXFORMAT_HEIGHT_SHIFT;
+ } else {
+- tex_size = ((height - 1) << 16) | (width - 1);
++ tex_size = (height << 16) | width;
+ txformat |= RADEON_TXFORMAT_NON_POWER2;
+ }
+
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index 3a26a0a..2a8873c 100644
--- a/src/radeon_tv.c
@@ -121,3 +2678,142 @@
save->tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
else
save->tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
+diff --git a/src/radeon_video.c b/src/radeon_video.c
+index 26857a5..3f0209e 100644
+--- a/src/radeon_video.c
++++ b/src/radeon_video.c
+@@ -414,11 +414,11 @@ static XF86AttributeRec Attributes[NUM_DEC_ATTRIBUTES+1] =
+
+ #define FOURCC_RGB24 0x00000000
+
+-#define XVIMAGE_RGB24(byte_order) \
++#define XVIMAGE_RGB24 \
+ { \
+ FOURCC_RGB24, \
+ XvRGB, \
+- byte_order, \
++ LSBFirst, \
+ { 'R', 'G', 'B', 0, \
+ 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \
+ 24, \
+@@ -473,15 +473,14 @@ static XF86ImageRec Images[NUM_IMAGES] =
+ {
+ #if X_BYTE_ORDER == X_BIG_ENDIAN
+ XVIMAGE_RGBA32(MSBFirst),
+- XVIMAGE_RGB24(MSBFirst),
+ XVIMAGE_RGBT16(MSBFirst),
+ XVIMAGE_RGB16(MSBFirst),
+ #else
+ XVIMAGE_RGBA32(LSBFirst),
+- XVIMAGE_RGB24(LSBFirst),
+ XVIMAGE_RGBT16(LSBFirst),
+ XVIMAGE_RGB16(LSBFirst),
+ #endif
++ XVIMAGE_RGB24,
+ XVIMAGE_YUY2,
+ XVIMAGE_UYVY,
+ XVIMAGE_YV12,
+@@ -2199,7 +2198,7 @@ RADEONCopyRGB24Data(
+ unsigned int w
+ ){
+ CARD32 *dptr;
+- CARD8 *sptr = 0;
++ CARD8 *sptr;
+ int i,j;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ #ifdef XF86DRI
+@@ -2210,11 +2209,9 @@ RADEONCopyRGB24Data(
+ int x, y;
+ unsigned int hpass;
+
+- /* XXX Fix endian flip on R300 */
+-
+ RADEONHostDataParams( pScrn, dst, dstPitch, 4, &dstPitchOff, &x, &y );
+
+- while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitch,
++ while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitchOff,
+ &bufPitch, x, &y, &h,
+ &hpass )) )
+ {
+@@ -2224,11 +2221,11 @@ RADEONCopyRGB24Data(
+
+ for ( i = 0 ; i < w; i++, sptr += 3 )
+ {
+- *dptr++ = (sptr[0] << 24) | (sptr[1] << 16) | sptr[2];
++ dptr[i] = (sptr[2] << 16) | (sptr[1] << 8) | sptr[0];
+ }
+
+- src += hpass * srcPitch;
+- dptr += hpass * bufPitch;
++ src += srcPitch;
++ dptr += bufPitch / 4;
+ }
+ }
+
+@@ -2246,14 +2243,12 @@ RADEONCopyRGB24Data(
+ & ~RADEON_NONSURF_AP0_SWP_16BPP);
+ #endif
+
+- for(j=0;j<h;j++){
+- dptr=(CARD32 *)(dst+j*dstPitch);
+- sptr=src+j*srcPitch;
++ for (j = 0; j < h; j++) {
++ dptr = (CARD32 *)(dst + j * dstPitch);
++ sptr = src + j * srcPitch;
+
+- for(i=w;i>0;i--){
+- dptr[0]=((sptr[0])<<24)|((sptr[1])<<16)|(sptr[2]);
+- dptr++;
+- sptr+=3;
++ for (i = 0; i < w; i++, sptr += 3) {
++ dptr[i] = (sptr[2] << 16) | (sptr[1] << 8) | sptr[0];
+ }
+ }
+
+@@ -2927,17 +2922,17 @@ RADEONPutImage(
+
+ switch(id) {
+ case FOURCC_RGB24:
+- dstPitch=(width*4+0x0f)&(~0x0f);
+- srcPitch=width*3;
++ dstPitch = width * 4;
++ srcPitch = width * 3;
+ break;
+ case FOURCC_RGBA32:
+- dstPitch=(width*4+0x0f)&(~0x0f);
+- srcPitch=width*4;
++ dstPitch = width * 4;
++ srcPitch = width * 4;
+ break;
+ case FOURCC_RGB16:
+ case FOURCC_RGBT16:
+- dstPitch=(width*2+0x0f)&(~0x0f);
+- srcPitch=(width*2+3)&(~0x03);
++ dstPitch = width * 2;
++ srcPitch = (width * 2 + 3) & ~3;
+ break;
+ case FOURCC_YV12:
+ case FOURCC_I420:
+@@ -2950,11 +2945,20 @@ RADEONPutImage(
+ case FOURCC_UYVY:
+ case FOURCC_YUY2:
+ default:
+- dstPitch = ((width << 1) + 63) & ~63;
+- srcPitch = (width << 1);
++ dstPitch = width * 2;
++ srcPitch = width * 2;
+ break;
+ }
+
++#ifdef XF86DRI
++ if (info->directRenderingEnabled && info->DMAForXv) {
++ /* The upload blit only supports multiples of 64 bytes */
++ dstPitch = (dstPitch + 63) & ~63;
++ } else
++#endif
++ /* The overlay only supports multiples of 16 bytes */
++ dstPitch = (dstPitch + 15) & ~15;
++
+ new_size = dstPitch * height;
+ if (id == FOURCC_YV12 || id == FOURCC_I420) {
+ new_size += (dstPitch >> 1) * ((height + 1) & ~1);
Index: xorg-x11-drv-ati.spec
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/F-8/xorg-x11-drv-ati.spec,v
retrieving revision 1.68
retrieving revision 1.69
diff -u -r1.68 -r1.69
--- xorg-x11-drv-ati.spec 29 Nov 2007 09:19:22 -0000 1.68
+++ xorg-x11-drv-ati.spec 6 Dec 2007 05:47:11 -0000 1.69
@@ -20,6 +20,7 @@
Patch2: radeon-6.6.3-renderaccel-buglet.patch
Patch3: radeon-git-upstream-fixes.patch
Patch4: radeon-fix-randr-gamma.patch
+Patch5: radeon-6.7.196-atombios-support.patch
# Rage 128 patches (100-199)
# mach64 patches (200-299)
@@ -31,6 +32,8 @@
BuildRequires: xorg-x11-server-sdk >= 1.3.0.0-6
BuildRequires: mesa-libGL-devel >= 6.4-4
BuildRequires: libdrm-devel >= 2.0-1
+BuildRequires: automake autoconf libtool pkgconfig
+BuildRequires: xorg-x11-util-macros >= 1.1.5
Requires: hwdata
Requires: xorg-x11-server-Xorg >= 1.3.0.0-6
@@ -44,8 +47,10 @@
%patch2 -p1 -b .renderaccel
%patch3 -p1 -b .fixes
%patch4 -p1 -b .randr-gamma
+%patch5 -p1 -b .atombios
%build
+aclocal ; automake -a ; autoconf
%configure --disable-static
make %{?_smp_mflags}
@@ -84,6 +89,11 @@
%{_mandir}/man4/radeon.4*
%changelog
+* Thu Dec 06 2007 Dave Airlie <airlied at redhat.com> 6.7.196-3
+- radeon-6.7.196-atombios-support.patch - Add atombios support
+- update git fix to upstream latest tree
+- need to rely on autotools now due to atombios
+
* Thu Nov 29 2007 Dave Airlie <airlied at redhat.com> 6.7.196-2
- radeon-fix-randr-gamma.patch - fix access to rrcrtc if not initialised
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