rpms/xorg-x11-drv-ati/devel radeon-6.7.196-atombios-support.patch, NONE, 1.1 radeon-git-upstream-fixes.patch, 1.2, 1.3 radeon.xinf, 1.3, 1.4 xorg-x11-drv-ati.spec, 1.71, 1.72 ati-6.7.196-alloca.patch, 1.1, NONE radeon-6.6.3-renderaccel-buglet.patch, 1.1, NONE radeon-6.7.196-alloca.patch, 1.1, NONE
Dave Airlie (airlied)
fedora-extras-commits at redhat.com
Wed Dec 19 05:12:24 UTC 2007
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Author: airlied
Update of /cvs/pkgs/rpms/xorg-x11-drv-ati/devel
In directory cvs-int.fedora.redhat.com:/tmp/cvs-serv412
Modified Files:
radeon.xinf xorg-x11-drv-ati.spec
Added Files:
radeon-6.7.196-atombios-support.patch
radeon-git-upstream-fixes.patch
Removed Files:
ati-6.7.196-alloca.patch radeon-6.6.3-renderaccel-buglet.patch
radeon-6.7.196-alloca.patch
Log Message:
* Wed Dec 19 2007 Dave Airlie <airlied at redhat.com> 6.7.196-3
- radeon-git-upstream-fixes.patch - update for latest git master
- radeon-6.7.196-atombios-support.patch - update for r500/r600
radeon-6.7.196-atombios-support.patch:
--- NEW FILE radeon-6.7.196-atombios-support.patch ---
commit 78fb6c77f88d2ce5d2e1ec925958b97c51955ec6
Merge: f5e8c18... ce4fa1c...
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Dec 19 14:45:11 2007 +1000
Merge branch 'master' into atombios-support
Conflicts:
src/radeon_display.c
diff --git a/configure.ac b/configure.ac
index 1570e54..d395899 100644
--- a/configure.ac
+++ b/configure.ac
@@ -62,6 +62,11 @@ AC_ARG_ENABLE(exa,
[EXA="$enableval"],
[EXA=yes])
+AC_ARG_WITH(xserver-source,AC_HELP_STRING([--with-xserver-source=XSERVER_SOURCE],
+ [Path to X server source tree]),
+ [ XSERVER_SOURCE="$withval" ],
+ [ XSERVER_SOURCE="" ])
+
# Checks for extensions
XORG_DRIVER_CHECK_EXT(XINERAMA, xineramaproto)
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
@@ -71,7 +76,7 @@ XORG_DRIVER_CHECK_EXT(XF86MISC, xf86miscproto)
XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto)
# Checks for pkg-config packages
-PKG_CHECK_MODULES(XORG, [xorg-server >= 1.3 xproto fontsproto $REQUIRED_MODULES])
+PKG_CHECK_MODULES(XORG, [xorg-server xproto fontsproto $REQUIRED_MODULES])
sdkdir=$(pkg-config --variable=sdkdir xorg-server)
# Checks for libraries.
@@ -112,6 +117,10 @@ if test "$DRI" = yes; then
fi
fi
+CFLAGS="$XORG_CFLAGS"
+AC_CHECK_HEADER(xf86Modes.h,[XMODES=yes],[XMODES=no],[#include "xorg-server.h"])
+CFLAGS="$save_CFLAGS"
+
# Note that this is sort of inverted from drivers/ati/Imakefile in
# the monolith. We test for foo, not for !foo (i.e. ATMISC_CPIO, not
# ATIMISC_AVOID_CPIO), but the defines are negative. So beware. Oh yeah,
@@ -208,6 +217,48 @@ AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
[XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
[#include "xorg-server.h"])
+AM_CONDITIONAL(XMODES, test "x$XMODES" = xno)
+
+if test "x$XSERVER_SOURCE" = x; then
+ if test -d ../../xserver; then
+ XSERVER_SOURCE="`cd ../../xserver && pwd`"
+ fi
+fi
+
+if test -d "$XSERVER_SOURCE"; then
+ case "$XSERVER_SOURCE" in
+ /*)
+ ;;
+ *)
+ XSERVER_SOURCE="`cd $XSERVER_SOURCE && pwd`"
+ esac
+ if test -f src/modes/xf86Modes.h; then
+ :
+ else
+ ln -sf $XSERVER_SOURCE/hw/xfree86/modes src/modes
+ fi
+
+ if test -f src/parser/xf86Parser.h; then
+ :
+ else
+ ln -sf $XSERVER_SOURCE/hw/xfree86/parser src/parser
+ fi
+fi
+if test "x$XMODES" = xyes; then
+ AC_MSG_NOTICE([X server has new mode code])
+ AC_DEFINE(XMODES, 1,[X server has built-in mode code])
+ XMODES_CFLAGS=
+else
+ if test -f src/modes/xf86Modes.h -a -f src/parser/xf86Parser.h; then
+ AC_MSG_NOTICE([X server is missing new mode code, using local copy])
+ else
+ AC_MSG_ERROR([Must have X server >= 1.3 source tree for mode setting code. Please specify --with-xserver-source])
+ fi
+ XMODES_CFLAGS='-DXF86_MODES_RENAME -I$(top_srcdir)/src -I$(top_srcdir)/src/modes -I$(top_srcdir)/src/parser'
+fi
+
+AC_SUBST([XMODES_CFLAGS])
+
CPPFLAGS="$SAVE_CPPFLAGS"
AM_CONDITIONAL(USE_EXA, test "x$USE_EXA" = xyes)
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c
new file mode 100644
index 0000000..1e48f81
--- /dev/null
+++ b/src/AtomBios/CD_Operations.c
@@ -0,0 +1,954 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+
+Module Name:
+
+ CD_Operations.c
+
+Abstract:
+
+ Functions Implementing Command Operations and other common functions
+
+Revision History:
+
+ NEG:27.09.2002 Initiated.
+--*/
+#define __SW_4
+
+#include "Decoder.h"
+#include "atombios.h"
+
+
+
+VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
+
+UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData);
+UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable);
+
+
+WRITE_IO_FUNCTION WritePCIFunctions[8] = {
+ WritePCIReg32,
+ WritePCIReg16, WritePCIReg16, WritePCIReg16,
+ WritePCIReg8,WritePCIReg8,WritePCIReg8,WritePCIReg8
+};
+WRITE_IO_FUNCTION WriteIOFunctions[8] = {
+ WriteSysIOReg32,
+ WriteSysIOReg16,WriteSysIOReg16,WriteSysIOReg16,
+ WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8
+};
+READ_IO_FUNCTION ReadPCIFunctions[8] = {
+ (READ_IO_FUNCTION)ReadPCIReg32,
+ (READ_IO_FUNCTION)ReadPCIReg16,
+ (READ_IO_FUNCTION)ReadPCIReg16,
+ (READ_IO_FUNCTION)ReadPCIReg16,
+ (READ_IO_FUNCTION)ReadPCIReg8,
+ (READ_IO_FUNCTION)ReadPCIReg8,
+ (READ_IO_FUNCTION)ReadPCIReg8,
+ (READ_IO_FUNCTION)ReadPCIReg8
+};
+READ_IO_FUNCTION ReadIOFunctions[8] = {
+ (READ_IO_FUNCTION)ReadSysIOReg32,
+ (READ_IO_FUNCTION)ReadSysIOReg16,
+ (READ_IO_FUNCTION)ReadSysIOReg16,
+ (READ_IO_FUNCTION)ReadSysIOReg16,
+ (READ_IO_FUNCTION)ReadSysIOReg8,
[...18567 lines suppressed...]
+#define AVIVO_GPIO_1 0x7e40
+#define AVIVO_GPIO_2 0x7e50
+#define AVIVO_GPIO_3 0x7e60
+
+#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
+
+#define AVIVO_I2C_STATUS 0x7d30
+# define AVIVO_I2C_STATUS_DONE (1 << 0)
+# define AVIVO_I2C_STATUS_NACK (1 << 1)
+# define AVIVO_I2C_STATUS_HALT (1 << 2)
+# define AVIVO_I2C_STATUS_GO (1 << 3)
+# define AVIVO_I2C_STATUS_MASK 0x7
+/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
+ * DONE? */
+# define AVIVO_I2C_STATUS_CMD_RESET 0x7
+# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3)
+#define AVIVO_I2C_STOP 0x7d34
+#define AVIVO_I2C_START_CNTL 0x7d38
+# define AVIVO_I2C_START (1 << 8)
+# define AVIVO_I2C_CONNECTOR0 (0 << 16)
+# define AVIVO_I2C_CONNECTOR1 (1 << 16)
+#define R520_I2C_START (1<<0)
+#define R520_I2C_STOP (1<<1)
+#define R520_I2C_RX (1<<2)
+#define R520_I2C_EN (1<<8)
+#define R520_I2C_DDC1 (0<<16)
+#define R520_I2C_DDC2 (1<<16)
+#define R520_I2C_DDC3 (2<<16)
+#define R520_I2C_DDC_MASK (3<<16)
+#define AVIVO_I2C_CONTROL2 0x7d3c
+# define AVIVO_I2C_7D3C_SIZE_SHIFT 8
+# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8)
+#define AVIVO_I2C_CONTROL3 0x7d40
+/* Reading is done 4 bytes at a time: read the bottom 8 bits from
+ * 7d44, four times in a row.
+ * Writing is a little more complex. First write DATA with
+ * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
+ * magic number, zz is, I think, the slave address, and yy is the byte
+ * you want to write. */
+#define AVIVO_I2C_DATA 0x7d44
+#define R520_I2C_ADDR_COUNT_MASK (0x7)
+#define R520_I2C_DATA_COUNT_SHIFT (8)
+#define R520_I2C_DATA_COUNT_MASK (0xF00)
+#define AVIVO_I2C_CNTL 0x7d50
+# define AVIVO_I2C_EN (1 << 0)
+# define AVIVO_I2C_RESET (1 << 8)
+
+#define R600_MC_VM_FB_LOCATION 0x2180
+#define R600_MC_VM_AGP_TOP 0x2184
+#define R600_MC_VM_AGP_BOT 0x2188
+#define R600_MC_VM_AGP_BASE 0x218c
+#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
+#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
+#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
+
+#define R600_BUS_CNTL 0x5420
+#define R600_CONFIG_CNTL 0x5424
+#define R600_CONFIG_MEMSIZE 0x5428
+#define R600_CONFIG_F0_BASE 0x542C
+#define R600_CONFIG_APER_SIZE 0x5430
#endif
diff --git a/src/radeon_render.c b/src/radeon_render.c
index 490dec1..a80d136 100644
--- a/src/radeon_render.c
+++ b/src/radeon_render.c
@@ -317,7 +317,7 @@ static Bool RADEONSetupRenderByteswap(ScrnInfoPtr pScrn, int tex_bytepp)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- CARD32 swapper = info->ModeReg.surface_cntl;
+ CARD32 swapper = info->ModeReg->surface_cntl;
swapper &= ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP |
RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP);
@@ -345,7 +345,7 @@ static void RADEONRestoreByteswap(RADEONInfoPtr info)
{
unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
}
#endif /* X_BYTE_ORDER == X_BIG_ENDIAN */
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index 2a8873c..5e9a9c8 100644
--- a/src/radeon_tv.c
+++ b/src/radeon_tv.c
@@ -540,7 +540,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->dac_cntl &= ~RADEON_DAC_TVO_EN;
if (IS_R300_VARIANT)
- save->gpiopad_a = info->SavedReg.gpiopad_a & ~1;
+ save->gpiopad_a = info->SavedReg->gpiopad_a & ~1;
if (IsPrimary) {
save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
@@ -571,7 +571,7 @@ void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
Bool reloadTable;
- RADEONSavePtr restore = &info->ModeReg;
+ RADEONSavePtr restore = info->ModeReg;
reloadTable = RADEONInitTVRestarts(output, restore, mode);
diff --git a/src/radeon_tv.h b/src/radeon_tv.h
index 5c8c8c9..c4b7838 100644
--- a/src/radeon_tv.h
+++ b/src/radeon_tv.h
@@ -3,11 +3,6 @@
* Federico Ulivi <fulivi at lycos.com>
*/
-/*
- * Maximum length of horizontal/vertical code timing tables for state storage
- */
-#define MAX_H_CODE_TIMING_LEN 32
-#define MAX_V_CODE_TIMING_LEN 32
/*
* Limits of h/v positions (hPos & vPos)
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 3f0209e..a84662e 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -1430,7 +1430,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn)
* 0 for PIXCLK < 175Mhz, and 1 (divide by 2)
* for higher clocks, sure makes life nicer
*/
- dot_clock = info->ModeReg.dot_clock_freq;
+ dot_clock = info->ModeReg->dot_clock_freq;
if (dot_clock < 17500)
info->ecp_div = 0;
@@ -2156,7 +2156,7 @@ RADEONCopyData(
{
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- unsigned int swapper = info->ModeReg.surface_cntl &
+ unsigned int swapper = info->ModeReg->surface_cntl &
~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP |
RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP);
@@ -2182,7 +2182,7 @@ RADEONCopyData(
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
}
}
@@ -2238,7 +2238,7 @@ RADEONCopyRGB24Data(
{
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl
+ OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl
| RADEON_NONSURF_AP0_SWP_32BPP)
& ~RADEON_NONSURF_AP0_SWP_16BPP);
#endif
@@ -2254,7 +2254,7 @@ RADEONCopyRGB24Data(
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
}
}
@@ -2333,7 +2333,7 @@ RADEONCopyMungedData(
#if X_BYTE_ORDER == X_BIG_ENDIAN
unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl
+ OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl
| RADEON_NONSURF_AP0_SWP_32BPP)
& ~RADEON_NONSURF_AP0_SWP_16BPP);
#endif
@@ -2371,7 +2371,7 @@ RADEONCopyMungedData(
}
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
#endif
}
}
@@ -2552,9 +2552,9 @@ RADEONDisplayVideo(
/* Figure out which head we are on for dot clock */
if (radeon_crtc->crtc_id == 1)
- dot_clock = info->ModeReg.dot_clock_freq_2;
+ dot_clock = info->ModeReg->dot_clock_freq_2;
else
- dot_clock = info->ModeReg.dot_clock_freq;
+ dot_clock = info->ModeReg->dot_clock_freq;
if (dot_clock < 17500)
ecp_div = 0;
radeon-git-upstream-fixes.patch:
View full diff with command:
/usr/bin/cvs -f diff -kk -u -N -r 1.2 -r 1.3 radeon-git-upstream-fixes.patch
Index: radeon-git-upstream-fixes.patch
===================================================================
RCS file: radeon-git-upstream-fixes.patch
diff -N radeon-git-upstream-fixes.patch
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ radeon-git-upstream-fixes.patch 19 Dec 2007 05:11:57 -0000 1.3
@@ -0,0 +1,4789 @@
+commit ce4fa1cedec0cf56b9979dfaa12a8d3a7c643df4
+Author: Arkadiusz Miskiewicz <arekm at maven.pl>
+Date: Tue Dec 18 15:34:14 2007 -0500
+
+ RADEON: fix fd leak in lid detect code
+
+commit 20568f66f9a9a60a33bd9a69ccc14a891c656836
+Author: Arkadiusz Miskiewicz <arekm at maven.pl>
+Date: Tue Dec 18 15:32:10 2007 -0500
+
+ RADEON: more cleanups and warning fixes
+
+commit 1496194200adbcb044ec3977367a0908262e389c
+Author: Arkadiusz Miskiewicz <arekm at maven.pl>
+Date: Tue Dec 18 15:29:53 2007 -0500
+
+ RADEON: driver cleanups, warning fixes
+
+commit 44d07c4ccce9acb5bd21a17acb082e91f7225764
+Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
+Date: Mon Dec 17 18:56:12 2007 -0500
+
+ RADEON: typo from last commit
+
+commit 4da3782239921eb377216d4de4a9cc5bb55e0e8a
+Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
+Date: Mon Dec 17 18:51:31 2007 -0500
+
+ RADEON: add output enable masks
+
+ add output enable masks for outputs that drive
+ more than one connector. Make sure we don't turn off
+ an output that's driving another connector.
+
+commit 5c5d2d19b2b032a06dd333b4ecc029aac342fb93
+Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
+Date: Mon Dec 17 18:15:55 2007 -0500
+
+ RADEON: whitespace clean-ups
+
+commit 9f1d8220315c8894a17f2cc328025dc682b0c6e0
+Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
+Date: Mon Dec 17 18:04:05 2007 -0500
+
+ RADEON: more PLL fixes
+
+ - reduce the calculation accuracy
+ - certain LVDS panels seem to only like certain ref_divs
+ - add pll flags to handle special cases
+ - adjust the pll limits on legacy cards
+
+commit 4747c1f3cd4167b6a51d4864a297719ea48b9346
+Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
+Date: Sun Dec 16 14:07:29 2007 -0500
+
+ RADEON: Make sure LVDS_EN bit is set when enabling LVDS
+
+commit b653e5a628bfa4dfb168e96f93f41eb910f409fb
+Author: Michel Dänzer <michel at tungstengraphics.com>
+Date: Sat Dec 15 00:50:10 2007 +0100
+
+ radeon: Default to 1x again with non-v3 AGP cards.
+
+ Seems more reliable in general than what was set up by firmware - fingers
+ crossed...
+
+commit 6229825fa5d6715569098afbb21a40f7a2e7e6be
+Author: Michel Dänzer <michel at tungstengraphics.com>
+Date: Sat Dec 15 00:48:26 2007 +0100
+
+ radeon: Warning fixes.
+
+ The lid detection code probably wouldn't work on other non-x86 platforms
+ though...
+
+commit 818ccf0fd4b5879171c5f20526d5a58638f8fde5
+Author: Fredrik Höglund <fredrik at kde.org>
+Date: Fri Dec 14 23:56:12 2007 +0100
+
+ RADEON: Fix the vertex coordinates for transformed pictures
+
+ This partially fixes transformed pictures on R100/R200 based
+ cards. The texture still doesn't appear to be clamped correctly,
+ but since that doesn't matter for rotations at perpendicular
+ angles, I'm committing this now so randr rotation and reflection
+ will work properly.
+
+commit 3cfbcf4cafbdfdb33411d16e51fb1f77cd0f93dd
+Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
+Date: Fri Dec 14 17:11:00 2007 -0500
+
+ RADEON: Fix PLL set up on certain notebooks
+
+ Some LVDS panels require specific PLL dividers as
+ specified in the bios tables. Make sure to use them
+ if the output is LVDS.
+
+commit a84d446fd301d456bcea8f7abdc52e5a30776412
+Author: Alex Deucher <alex at botch2.(none)>
+Date: Fri Dec 14 02:17:14 2007 -0500
+
+ RADEON: select fb_div0 for LVDS on RV410 (x700) mobility
+
+ Fixes bug 8038
+ I wonder if desktop RV410 need a similar fix.
+ If your x700 laptop panel has problems after this let me know.
+
+commit 6ccf5b33d27218ae1c45ab93c122438ed536d8ba
+Author: Alex Deucher <alex at botch2.(none)>
+Date: Wed Dec 12 20:12:06 2007 -0500
+
+ RADEON: only enable vblanks if we want them
+
+ should fix bug 13610
+
+commit 1668f2056f56370f1b5681c13f1e14904e301216
+Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
+Date: Wed Dec 12 19:39:08 2007 -0500
+
+ RADEON: use /proc/acpi to determine lid status
+
+ Linux only
+
+commit 33a39947f7f79533cd90007a17d57b20126642c6
+Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
+Date: Wed Dec 12 18:50:18 2007 -0500
+
+ RADEON: fix cursors when using rotation
+
+ allocate separate cursor buffers for each crtc
+
+commit 9e5efdecd12092031a4aebce58747cb4a6f48f28
+Author: Arkadiusz Miskiewicz <arekm at maven.pl>
+Date: Tue Dec 11 23:53:03 2007 -0500
+
+ sparse fixes and cleanups from arekm
+
+commit f3d2ec3a5ae61215c792018320158750e7aa937c
+Author: Alex Deucher <alex at botch2.(none)>
+Date: Tue Dec 11 11:57:27 2007 -0500
+
+ RADEON: rewrite PLL computation
+
+ Algorithm adapted from BeOS radeon driver with some tweaks by me.
+ Actually calulate and use the reference divider rather than using the bios default.
+ Also, always calculate the PLL, rather than falling back to bios dividers.
+ This should fix bugs 12913, 13590, 13533, possibly others.
+
+commit 9b125312ab6edc585e4f5931a6a6de81e13b6acc
+Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
+Date: Mon Dec 10 13:53:15 2007 -0500
+
+ RADEON: only update crtc values when RMX is active
+
+commit 3a161e1b5d80361e318ced8da5c19e797749d693
+Author: Alex Deucher <alex at botch2.(none)>
+Date: Mon Dec 10 00:57:26 2007 -0500
+
+ RADEON: bios PLL cleanup
+
+commit 5896ca4097d439f59f90f397939132c061c3c364
+Author: LisaWu <liswu at ati.com>
+Date: Fri Dec 7 09:45:05 2007 +0100
+
+ radeon: Use %u instead of %d for unsigned value.
+
+commit df44f8380268c27d3978c4e91d736f093322b8b8
+Author: Michel Dänzer <michel at tungstengraphics.com>
+Date: Fri Dec 7 09:41:47 2007 +0100
+
+ radeon: Use gettimeofday instead of xf86getsecs.
+
+commit 64ab1cdf343a9a69e7e9e64f0bba77c54a94e9d0
+Author: James Cloos <cloos at jhcloos.com>
+Date: Thu Dec 6 15:51:12 2007 -0500
+
+ Add missing PHONY line for automatic ChangeLog generation
+
+commit 21ed435398e4a398dd8a0a5d7c1d4cc45e916332
+Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
+Date: Tue Dec 4 17:08:58 2007 -0500
+
+ RADEON: add MacModel imac-g5-isight for iMac G5 iSight
+
+ Thanks to Étienne Bersac for helping to figure this out.
+
+commit 54bfd522405d9fdfb69d3a59e111ac3d63483dbb
+Author: Étienne Bersac <bersace03 at laposte.net>
+Date: Tue Dec 4 14:22:42 2007 -0500
+
+ RADEON: fix typo
+
+commit 5022d006cfc06ca0395981526b2c2c94c6878567
[...4396 lines suppressed...]
+index 2653339..6e4e383 100644
+--- a/src/radeon_reg.h
++++ b/src/radeon_reg.h
+@@ -916,6 +916,7 @@
+ # define RADEON_LVDS_DISPLAY_DIS (1 << 1)
+ # define RADEON_LVDS_PANEL_TYPE (1 << 2)
+ # define RADEON_LVDS_PANEL_FORMAT (1 << 3)
++# define RADEON_LVDS_RST_FM (1 << 6)
+ # define RADEON_LVDS_EN (1 << 7)
+ # define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
+ # define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
+diff --git a/src/radeon_render.c b/src/radeon_render.c
+index 5074fe1..490dec1 100644
+--- a/src/radeon_render.c
++++ b/src/radeon_render.c
+@@ -392,7 +392,7 @@ static Bool FUNC_NAME(R100SetupTexture)(
+ #endif
+ ACCEL_PREAMBLE();
+
+- if ((width > 2048) || (height > 2048))
++ if ((width > 2047) || (height > 2047))
+ return FALSE;
+
+ txformat = RadeonGetTextureFormat(format);
+@@ -424,7 +424,7 @@ static Bool FUNC_NAME(R100SetupTexture)(
+ txformat |= ATILog2(width) << RADEON_TXFORMAT_WIDTH_SHIFT;
+ txformat |= ATILog2(height) << RADEON_TXFORMAT_HEIGHT_SHIFT;
+ } else {
+- tex_size = ((height - 1) << 16) | (width - 1);
++ tex_size = (height << 16) | width;
+ txformat |= RADEON_TXFORMAT_NON_POWER2;
+ }
+
+diff --git a/src/radeon_tv.c b/src/radeon_tv.c
+index 3a26a0a..2a8873c 100644
+--- a/src/radeon_tv.c
++++ b/src/radeon_tv.c
+@@ -434,7 +434,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
+
+ save->tv_vscaler_cntl2 = ((save->tv_vscaler_cntl2 & 0x00fffff0)
+ | (0x10 << 24)
+- | RADEON_DITHER_MODE
++ | RADEON_DITHER_MODE
+ | RADEON_Y_OUTPUT_DITHER_EN
+ | RADEON_UV_OUTPUT_DITHER_EN
+ | RADEON_UV_TO_BUF_DITHER_EN);
+@@ -444,10 +444,12 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
+ tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
+ save->tv_timing_cntl = tmp;
+
+- save->tv_dac_cntl = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | (8 << 16) | (6 << 20);
++ save->tv_dac_cntl = (RADEON_TV_DAC_NBLANK |
++ RADEON_TV_DAC_NHOLD |
++ radeon_output->tv_dac_adj /*(8 << 16) | (6 << 20)*/);
+
+ if (radeon_output->tvStd == TV_STD_NTSC ||
+- radeon_output->tvStd == TV_STD_NTSC_J)
++ radeon_output->tvStd == TV_STD_NTSC_J)
+ save->tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
+ else
+ save->tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
+diff --git a/src/radeon_video.c b/src/radeon_video.c
+index 26857a5..3f0209e 100644
+--- a/src/radeon_video.c
++++ b/src/radeon_video.c
+@@ -414,11 +414,11 @@ static XF86AttributeRec Attributes[NUM_DEC_ATTRIBUTES+1] =
+
+ #define FOURCC_RGB24 0x00000000
+
+-#define XVIMAGE_RGB24(byte_order) \
++#define XVIMAGE_RGB24 \
+ { \
+ FOURCC_RGB24, \
+ XvRGB, \
+- byte_order, \
++ LSBFirst, \
+ { 'R', 'G', 'B', 0, \
+ 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \
+ 24, \
+@@ -473,15 +473,14 @@ static XF86ImageRec Images[NUM_IMAGES] =
+ {
+ #if X_BYTE_ORDER == X_BIG_ENDIAN
+ XVIMAGE_RGBA32(MSBFirst),
+- XVIMAGE_RGB24(MSBFirst),
+ XVIMAGE_RGBT16(MSBFirst),
+ XVIMAGE_RGB16(MSBFirst),
+ #else
+ XVIMAGE_RGBA32(LSBFirst),
+- XVIMAGE_RGB24(LSBFirst),
+ XVIMAGE_RGBT16(LSBFirst),
+ XVIMAGE_RGB16(LSBFirst),
+ #endif
++ XVIMAGE_RGB24,
+ XVIMAGE_YUY2,
+ XVIMAGE_UYVY,
+ XVIMAGE_YV12,
+@@ -2199,7 +2198,7 @@ RADEONCopyRGB24Data(
+ unsigned int w
+ ){
+ CARD32 *dptr;
+- CARD8 *sptr = 0;
++ CARD8 *sptr;
+ int i,j;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ #ifdef XF86DRI
+@@ -2210,11 +2209,9 @@ RADEONCopyRGB24Data(
+ int x, y;
+ unsigned int hpass;
+
+- /* XXX Fix endian flip on R300 */
+-
+ RADEONHostDataParams( pScrn, dst, dstPitch, 4, &dstPitchOff, &x, &y );
+
+- while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitch,
++ while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitchOff,
+ &bufPitch, x, &y, &h,
+ &hpass )) )
+ {
+@@ -2224,11 +2221,11 @@ RADEONCopyRGB24Data(
+
+ for ( i = 0 ; i < w; i++, sptr += 3 )
+ {
+- *dptr++ = (sptr[0] << 24) | (sptr[1] << 16) | sptr[2];
++ dptr[i] = (sptr[2] << 16) | (sptr[1] << 8) | sptr[0];
+ }
+
+- src += hpass * srcPitch;
+- dptr += hpass * bufPitch;
++ src += srcPitch;
++ dptr += bufPitch / 4;
+ }
+ }
+
+@@ -2246,14 +2243,12 @@ RADEONCopyRGB24Data(
+ & ~RADEON_NONSURF_AP0_SWP_16BPP);
+ #endif
+
+- for(j=0;j<h;j++){
+- dptr=(CARD32 *)(dst+j*dstPitch);
+- sptr=src+j*srcPitch;
++ for (j = 0; j < h; j++) {
++ dptr = (CARD32 *)(dst + j * dstPitch);
++ sptr = src + j * srcPitch;
+
+- for(i=w;i>0;i--){
+- dptr[0]=((sptr[0])<<24)|((sptr[1])<<16)|(sptr[2]);
+- dptr++;
+- sptr+=3;
++ for (i = 0; i < w; i++, sptr += 3) {
++ dptr[i] = (sptr[2] << 16) | (sptr[1] << 8) | sptr[0];
+ }
+ }
+
+@@ -2927,17 +2922,17 @@ RADEONPutImage(
+
+ switch(id) {
+ case FOURCC_RGB24:
+- dstPitch=(width*4+0x0f)&(~0x0f);
+- srcPitch=width*3;
++ dstPitch = width * 4;
++ srcPitch = width * 3;
+ break;
+ case FOURCC_RGBA32:
+- dstPitch=(width*4+0x0f)&(~0x0f);
+- srcPitch=width*4;
++ dstPitch = width * 4;
++ srcPitch = width * 4;
+ break;
+ case FOURCC_RGB16:
+ case FOURCC_RGBT16:
+- dstPitch=(width*2+0x0f)&(~0x0f);
+- srcPitch=(width*2+3)&(~0x03);
++ dstPitch = width * 2;
++ srcPitch = (width * 2 + 3) & ~3;
+ break;
+ case FOURCC_YV12:
+ case FOURCC_I420:
+@@ -2950,11 +2945,20 @@ RADEONPutImage(
+ case FOURCC_UYVY:
+ case FOURCC_YUY2:
+ default:
+- dstPitch = ((width << 1) + 63) & ~63;
+- srcPitch = (width << 1);
++ dstPitch = width * 2;
++ srcPitch = width * 2;
+ break;
+ }
+
++#ifdef XF86DRI
++ if (info->directRenderingEnabled && info->DMAForXv) {
++ /* The upload blit only supports multiples of 64 bytes */
++ dstPitch = (dstPitch + 63) & ~63;
++ } else
++#endif
++ /* The overlay only supports multiples of 16 bytes */
++ dstPitch = (dstPitch + 15) & ~15;
++
+ new_size = dstPitch * height;
+ if (id == FOURCC_YV12 || id == FOURCC_I420) {
+ new_size += (dstPitch >> 1) * ((height + 1) & ~1);
Index: radeon.xinf
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/radeon.xinf,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -r1.3 -r1.4
--- radeon.xinf 27 Jul 2006 21:23:18 -0000 1.3
+++ radeon.xinf 19 Dec 2007 05:11:57 -0000 1.4
@@ -195,3 +195,135 @@
alias pcivideo:v00001002d00007834sv*sd*bc*sc*i* radeon # 9100 IGP
alias pcivideo:v00001002d00007835sv*sd*bc*sc*i* radeon # 9200 IGP
alias pcivideo:v00001002d00007C37sv*sd*bc*sc*i* radeon # RV350
+alias pcivideo:v00001002d00007100sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007101sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007102sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007103sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007104sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007105sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007106sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007108sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007109sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000710Asv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000710Bsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000710Csv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000710Esv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000710Fsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007140sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007141sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007142sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007143sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007144sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007145sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007146sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007147sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007149sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000714Asv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000714Bsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000714Csv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000714Dsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000714Esv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000714Fsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007151sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007152sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007153sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000715Esv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000715Fsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007180sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007181sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007183sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007186sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007187sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007188sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000718Asv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000718Bsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000718Csv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000718Dsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000718Fsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007193sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007196sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000719Bsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000719Fsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071C0sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071C1sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071C2sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071C3sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071C4sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071C5sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071C6sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071C7sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071CDsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071CEsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071D2sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071D4sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071D5sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071D6sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071DAsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000071DEsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007200sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007210sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007211sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007240sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007243sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007244sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007245sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007246sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007247sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007248sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007249sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000724Asv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000724Bsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000724Csv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000724Dsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000724Esv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000724Fsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007280sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007281sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007283sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007284sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007287sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007288sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007289sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000728Bsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000728Csv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007290sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007291sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007293sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00007297sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000791Esv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000791Fsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000796Csv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000796Dsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000796Esv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000796Fsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00009400sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00009401sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00009402sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00009403sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00009405sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000940Asv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000940Bsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000940Fsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000094C0sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000094C1sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000094C3sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000094C4sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000094C5sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000094C6sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000094C7sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000094C8sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000094C9sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000094CBsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d000094CCsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00009580sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00009581sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00009583sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00009586sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00009587sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00009588sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d00009589sv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000958Asv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000958Bsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000958Csv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000958Dsv*sd*bc*sc*i* radeon #
+alias pcivideo:v00001002d0000958Esv*sd*bc*sc*i* radeon #
Index: xorg-x11-drv-ati.spec
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/xorg-x11-drv-ati.spec,v
retrieving revision 1.71
retrieving revision 1.72
diff -u -r1.71 -r1.72
--- xorg-x11-drv-ati.spec 18 Dec 2007 00:26:06 -0000 1.71
+++ xorg-x11-drv-ati.spec 19 Dec 2007 05:11:57 -0000 1.72
@@ -5,7 +5,7 @@
Summary: Xorg X11 ati video driver
Name: xorg-x11-drv-ati
Version: 6.7.196
-Release: 2%{?dist}
+Release: 3%{?dist}
URL: http://www.x.org
License: MIT
Group: User Interface/X Hardware Support
@@ -17,14 +17,13 @@
Source3: radeon.xinf
# Radeon patches (0-99)
-Patch2: radeon-6.6.3-renderaccel-buglet.patch
+Patch2: radeon-git-upstream-fixes.patch
+Patch3: radeon-6.7.196-atombios-support.patch
Patch4: radeon-6.7.196-faster-ddc.patch
-Patch5: radeon-6.7.196-alloca.patch
# Rage 128 patches (100-199)
# mach64 patches (200-299)
-Patch200: ati-6.7.196-alloca.patch
# ati wrapperloader patches (300-399)
@@ -43,10 +42,9 @@
%prep
%setup -q -n %{tarball}-%{version}
-%patch2 -p1 -b .renderaccel
+%patch2 -p1 -b .upstream
+%patch3 -p1 -b .atombios
%patch4 -p1 -b .ddc
-%patch5 -p1 -b .alloca-radeon
-%patch200 -p1 -b .alloca-ati
%build
%configure --disable-static
@@ -88,6 +86,10 @@
%{_mandir}/man4/radeon.4*
%changelog
+* Wed Dec 19 2007 Dave Airlie <airlied at redhat.com> 6.7.196-3
+- radeon-git-upstream-fixes.patch - update for latest git master
+- radeon-6.7.196-atombios-support.patch - update for r500/r600
+
* Mon Dec 17 2007 Adam Jackson <ajax at redhat.com> 6.7.196-2
- *-6.7.196-alloca.patch: Fix ALLOCATE_LOCAL failures.
--- ati-6.7.196-alloca.patch DELETED ---
--- radeon-6.6.3-renderaccel-buglet.patch DELETED ---
--- radeon-6.7.196-alloca.patch DELETED ---
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