rpms/kernel/F-10 drm-modesetting-radeon.patch, 1.64, 1.65 kernel.spec, 1.1169, 1.1170
Dave Airlie
airlied at fedoraproject.org
Tue Dec 2 02:56:51 UTC 2008
Author: airlied
Update of /cvs/pkgs/rpms/kernel/F-10
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv12694
Modified Files:
drm-modesetting-radeon.patch kernel.spec
Log Message:
- radeon: fix IGP aperture sizing (#473895)
drm-modesetting-radeon.patch:
Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-10/drm-modesetting-radeon.patch,v
retrieving revision 1.64
retrieving revision 1.65
diff -u -r1.64 -r1.65
--- drm-modesetting-radeon.patch 30 Nov 2008 08:49:13 -0000 1.64
+++ drm-modesetting-radeon.patch 2 Dec 2008 02:56:50 -0000 1.65
@@ -1,16 +1,19 @@
-commit 418897b8fb962076f8d7f95fe32b2aadcf7b1c7c
-Author: Dave Airlie <airlied at linux.ie>
-Date: Sun Nov 30 18:45:58 2008 +1000
+commit 4a7eb33e9c27c28129c07123c0878e3e603c937e
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Dec 2 12:49:17 2008 +1000
- radeon: fixup AGP vs PCI/PCIE fallback for cards that need it
+ radeon: AGP fixes
+
+ 1. Proper PCIE fallback on PCIE cards.
+ 2. Setup agp base + location regs properly
-commit 97bbdd07e8abe3172715a4e9403e84341fb240ec
-Author: Dave Airlie <airlied at linux.ie>
-Date: Sun Nov 30 18:24:14 2008 +1000
+commit b7de4d48a3e45df7d4e0401bc7987089ce2165b2
+Author: Michal Schmidt <mschmidt at redhat.com>
+Date: Tue Dec 2 08:06:59 2008 +1000
- radeon: write agp base/location when kms is enabled
+ radeon: fix IGP GART calcs
- this hopefully will make AGP systems actually work
+ fedora bz 473895
commit 1ff222030a971f3d1274dfcb3742a35996ccc6c8
Author: Dave Airlie <airlied at redhat.com>
@@ -24266,7 +24269,7 @@
+ return NULL;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
-index dcebb4b..7ecbe7a 100644
+index dcebb4b..e0f7284 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -31,6 +31,7 @@
@@ -24596,7 +24599,7 @@
/* Initialize the memory controller. With new memory map, the fb location
* is not changed, it should have been properly initialized already. Part
-@@ -568,9 +724,22 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -568,9 +724,13 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
*/
if (!dev_priv->new_memmap)
radeon_write_fb_location(dev_priv,
@@ -24609,20 +24612,11 @@
+ if (dev_priv->mm.ring.bo) {
+ ring_start = dev_priv->mm.ring.bo->offset +
+ dev_priv->gart_vm_start;
-+#if __OS_HAS_AGP
-+ if (dev_priv->flags & RADEON_IS_AGP) {
-+ radeon_write_agp_base(dev_priv, dev->agp->base);
-+ radeon_write_agp_location(dev_priv,
-+ (((dev_priv->gart_vm_start - 1 +
-+ dev_priv->gart_size) & 0xffff0000) |
-+ (dev_priv->gart_vm_start >> 16)), 0);
-+#endif
-+ }
+ } else
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
radeon_write_agp_base(dev_priv, dev->agp->base);
-@@ -578,7 +747,7 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -578,7 +738,7 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
radeon_write_agp_location(dev_priv,
(((dev_priv->gart_vm_start - 1 +
dev_priv->gart_size) & 0xffff0000) |
@@ -24631,7 +24625,7 @@
ring_start = (dev_priv->cp_ring->offset
- dev->agp->base
-@@ -600,6 +769,12 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -600,6 +760,12 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
SET_RING_HEAD(dev_priv, cur_read_ptr);
dev_priv->ring.tail = cur_read_ptr;
@@ -24644,7 +24638,7 @@
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
-@@ -646,63 +821,79 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -646,63 +812,79 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
+ RADEON_SCRATCH_REG_OFFSET);
@@ -24684,23 +24678,23 @@
+
+ dev_priv->scratch[0] = 0;
+ RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
++
++ dev_priv->scratch[1] = 0;
++ RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
- dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
- RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
-+ dev_priv->scratch[1] = 0;
-+ RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
++ dev_priv->scratch[2] = 0;
++ RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
- dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
- RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
- dev_priv->sarea_priv->last_dispatch);
-+ dev_priv->scratch[2] = 0;
-+ RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
++ dev_priv->scratch[3] = 0;
++ RADEON_WRITE(RADEON_LAST_SWI_REG, 0);
- dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
- RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
-+ dev_priv->scratch[3] = 0;
-+ RADEON_WRITE(RADEON_LAST_SWI_REG, 0);
-+
+ dev_priv->scratch[4] = 0;
+ RADEON_WRITE(RADEON_SCRATCH_REG4, 0);
+
@@ -24753,7 +24747,7 @@
0xdeadbeef)
break;
DRM_UDELAY(1);
-@@ -720,10 +911,12 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
+@@ -720,10 +902,12 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
DRM_INFO("writeback forced off\n");
}
@@ -24769,7 +24763,7 @@
RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
}
}
-@@ -734,10 +927,25 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -734,10 +918,25 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
u32 temp;
if (on) {
@@ -24782,7 +24776,7 @@
+ (long)dev_priv->gart_info.bus_addr,
+ dev_priv->gart_size);
+
-+ switch(dev_priv->gart_size) {
++ switch(dev_priv->gart_size/(1024*1024)) {
+ case 32: size_reg = RS480_VA_SIZE_32MB; break;
+ case 64: size_reg = RS480_VA_SIZE_64MB; break;
+ case 128: size_reg = RS480_VA_SIZE_128MB; break;
@@ -24798,7 +24792,7 @@
temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
-@@ -747,8 +955,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -747,8 +946,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
else
IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
@@ -24808,7 +24802,7 @@
temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
-@@ -764,24 +971,31 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -764,24 +962,30 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
RS480_REQ_TYPE_SNOOP_DIS));
@@ -24822,7 +24816,7 @@
+ RADEON_WRITE(RS480_AGP_BASE_2, 0);
+ }
- dev_priv->gart_size = 32*1024*1024;
+- dev_priv->gart_size = 32*1024*1024;
- temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
- 0xffff0000) | (dev_priv->gart_vm_start >> 16));
+ temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
@@ -24846,7 +24840,7 @@
IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
RS480_GART_CACHE_INVALIDATE);
-@@ -791,7 +1005,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -791,7 +995,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
break;
DRM_UDELAY(1);
@@ -24855,7 +24849,7 @@
IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
} else {
-@@ -818,7 +1032,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
+@@ -818,7 +1022,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
dev_priv->gart_vm_start +
dev_priv->gart_size - 1);
@@ -24864,7 +24858,7 @@
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
RADEON_PCIE_TX_GART_EN);
-@@ -829,7 +1043,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
+@@ -829,7 +1033,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
}
/* Enable or disable PCI GART on the chip */
@@ -24873,7 +24867,7 @@
{
u32 tmp;
-@@ -863,7 +1077,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
+@@ -863,7 +1067,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
/* Turn off AGP aperture -- is this required for PCI GART?
*/
@@ -24882,7 +24876,7 @@
RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
} else {
RADEON_WRITE(RADEON_AIC_CNTL,
-@@ -871,9 +1085,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
+@@ -871,9 +1075,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
}
}
@@ -24895,7 +24889,7 @@
DRM_DEBUG("\n");
-@@ -911,17 +1127,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -911,17 +1117,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
*/
dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
@@ -24913,7 +24907,7 @@
dev_priv->do_boxes = 0;
dev_priv->cp_mode = init->cp_mode;
-@@ -969,9 +1174,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -969,9 +1164,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
*/
dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
(dev_priv->color_fmt << 10) |
@@ -24925,7 +24919,7 @@
dev_priv->depth_clear.rb3d_zstencilcntl =
(dev_priv->depth_fmt |
RADEON_Z_TEST_ALWAYS |
-@@ -998,8 +1202,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -998,8 +1192,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
dev_priv->buffers_offset = init->buffers_offset;
dev_priv->gart_textures_offset = init->gart_textures_offset;
@@ -24936,7 +24930,7 @@
DRM_ERROR("could not find sarea!\n");
radeon_do_cleanup_cp(dev);
return -EINVAL;
-@@ -1035,10 +1239,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1035,10 +1229,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
}
}
@@ -24947,7 +24941,7 @@
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
drm_core_ioremap(dev_priv->cp_ring, dev);
-@@ -1152,8 +1352,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1152,8 +1342,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
@@ -24957,7 +24951,7 @@
dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
-@@ -1168,28 +1367,41 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1168,28 +1357,41 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
/* if we have an offset set from userspace */
if (dev_priv->pcigart_offset_set) {
@@ -25019,7 +25013,7 @@
if (dev_priv->flags & RADEON_IS_IGPGART)
dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
else
-@@ -1198,12 +1410,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1198,12 +1400,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
DRM_ATI_GART_MAIN;
dev_priv->gart_info.addr = NULL;
dev_priv->gart_info.bus_addr = 0;
@@ -25033,7 +25027,7 @@
}
if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
-@@ -1216,6 +1423,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1216,6 +1413,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
radeon_set_pcigart(dev_priv, 1);
}
@@ -25043,7 +25037,7 @@
radeon_cp_load_microcode(dev_priv);
radeon_cp_init_ring_buffer(dev, dev_priv);
-@@ -1260,14 +1470,16 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
+@@ -1260,14 +1460,16 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
if (dev_priv->gart_info.bus_addr) {
/* Turn off PCI GART */
radeon_set_pcigart(dev_priv, 0);
@@ -25064,7 +25058,7 @@
}
}
/* only clear to the start of flags */
-@@ -1319,6 +1531,10 @@ static int radeon_do_resume_cp(struct drm_device * dev)
+@@ -1319,6 +1521,10 @@ static int radeon_do_resume_cp(struct drm_device * dev)
int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_init_t *init = data;
@@ -25075,7 +25069,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
-@@ -1329,7 +1545,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1329,7 +1535,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
case RADEON_INIT_CP:
case RADEON_INIT_R200_CP:
case RADEON_INIT_R300_CP:
@@ -25084,7 +25078,7 @@
case RADEON_CLEANUP_CP:
return radeon_do_cleanup_cp(dev);
}
-@@ -1342,6 +1558,9 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -1342,6 +1548,9 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -25094,7 +25088,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (dev_priv->cp_running) {
-@@ -1369,6 +1588,9 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1369,6 +1578,9 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
int ret;
DRM_DEBUG("\n");
@@ -25104,7 +25098,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (!dev_priv->cp_running)
-@@ -1407,6 +1629,9 @@ void radeon_do_release(struct drm_device * dev)
+@@ -1407,6 +1619,9 @@ void radeon_do_release(struct drm_device * dev)
drm_radeon_private_t *dev_priv = dev->dev_private;
int i, ret;
@@ -25114,7 +25108,7 @@
if (dev_priv) {
if (dev_priv->cp_running) {
/* Stop the cp */
-@@ -1440,6 +1665,9 @@ void radeon_do_release(struct drm_device * dev)
+@@ -1440,6 +1655,9 @@ void radeon_do_release(struct drm_device * dev)
radeon_mem_takedown(&(dev_priv->gart_heap));
radeon_mem_takedown(&(dev_priv->fb_heap));
@@ -25124,7 +25118,7 @@
/* deallocate kernel resources */
radeon_do_cleanup_cp(dev);
}
-@@ -1452,6 +1680,9 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -1452,6 +1670,9 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -25134,7 +25128,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (!dev_priv) {
-@@ -1472,7 +1703,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1472,7 +1693,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -25145,7 +25139,7 @@
return radeon_do_cp_idle(dev_priv);
}
-@@ -1482,6 +1715,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1482,6 +1705,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
@@ -25155,7 +25149,7 @@
return radeon_do_resume_cp(dev);
}
-@@ -1489,6 +1725,9 @@ int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *fil
+@@ -1489,6 +1715,9 @@ int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *fil
{
DRM_DEBUG("\n");
@@ -25165,7 +25159,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
return radeon_do_engine_reset(dev);
-@@ -1711,6 +1950,732 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
+@@ -1711,6 +1940,739 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
return ret;
}
@@ -25730,6 +25724,13 @@
+ if (dev_priv->chip_family < CHIP_R200) {
+ RADEON_WRITE(RADEON_AGP_CNTL, RADEON_READ(RADEON_AGP_CNTL) | 0x000e0000);
+ }
++
++ radeon_write_agp_base(dev_priv, dev->agp->base);
++
++ radeon_write_agp_location(dev_priv,
++ (((dev_priv->gart_vm_start - 1 +
++ dev_priv->gart_size) & 0xffff0000) |
++ (dev_priv->gart_vm_start >> 16)), 0);
+ return 0;
+}
+
@@ -25898,7 +25899,7 @@
int radeon_driver_load(struct drm_device *dev, unsigned long flags)
{
drm_radeon_private_t *dev_priv;
-@@ -1724,6 +2689,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1724,6 +2686,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
dev->dev_private = (void *)dev_priv;
dev_priv->flags = flags;
@@ -25907,7 +25908,7 @@
switch (flags & RADEON_FAMILY_MASK) {
case CHIP_R100:
case CHIP_RV200:
-@@ -1744,6 +2711,18 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1744,6 +2708,18 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
break;
}
@@ -25926,7 +25927,7 @@
if (drm_device_is_agp(dev))
dev_priv->flags |= RADEON_IS_AGP;
else if (drm_device_is_pcie(dev))
-@@ -1751,9 +2730,32 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1751,9 +2727,34 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
else
dev_priv->flags |= RADEON_IS_PCI;
@@ -25942,7 +25943,9 @@
+ if (radeon_agpmode == -1) {
+ dev_priv->flags &= ~RADEON_IS_AGP;
+ if (dev_priv->chip_family > CHIP_RV515 ||
-+ dev_priv->chip_family == CHIP_RV380) {
++ dev_priv->chip_family == CHIP_RV380 ||
++ dev_priv->chip_family == CHIP_RV410 ||
++ dev_priv->chip_family == CHIP_R423) {
+ DRM_INFO("Forcing AGP to PCIE mode\n");
+ dev_priv->flags |= RADEON_IS_PCIE;
+ } else {
@@ -25960,7 +25963,7 @@
if (ret != 0)
return ret;
-@@ -1763,28 +2765,122 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1763,28 +2764,122 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
return ret;
}
@@ -26094,7 +26097,7 @@
return 0;
}
-@@ -1793,6 +2889,18 @@ int radeon_driver_unload(struct drm_device *dev)
+@@ -1793,6 +2888,18 @@ int radeon_driver_unload(struct drm_device *dev)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -26113,7 +26116,7 @@
DRM_DEBUG("\n");
drm_rmmap(dev, dev_priv->mmio);
-@@ -1802,3 +2910,63 @@ int radeon_driver_unload(struct drm_device *dev)
+@@ -1802,3 +2909,63 @@ int radeon_driver_unload(struct drm_device *dev)
dev->dev_private = NULL;
return 0;
}
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-10/kernel.spec,v
retrieving revision 1.1169
retrieving revision 1.1170
diff -u -r1.1169 -r1.1170
--- kernel.spec 1 Dec 2008 01:14:24 -0000 1.1169
+++ kernel.spec 2 Dec 2008 02:56:50 -0000 1.1170
@@ -1932,6 +1932,9 @@
%kernel_variant_files -k vmlinux %{with_kdump} kdump
%changelog
+* Tue Dec 02 2008 Dave Airlie <airlied at redhat.com> 2.6.27.7-134
+- radeon: fix IGP aperture sizing (#473895)
+
* Mon Dec 01 2008 Dave Airlie <airlied at redhat.com> 2.6.27.7-133
- drm-next.patch: drm/intel: fix VT switch issue harder.
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