rpms/kernel/F-10 drm-modesetting-radeon.patch, 1.65, 1.66 kernel.spec, 1.1171, 1.1172

Dave Airlie airlied at fedoraproject.org
Wed Dec 3 00:25:44 UTC 2008 

Author: airlied

Update of /cvs/pkgs/rpms/kernel/F-10
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv28324

Modified Files:
	drm-modesetting-radeon.patch kernel.spec 
Log Message:
- radeon: fix AGP harder than the last time.


drm-modesetting-radeon.patch:

Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-10/drm-modesetting-radeon.patch,v
retrieving revision 1.65
retrieving revision 1.66
diff -u -r1.65 -r1.66
--- drm-modesetting-radeon.patch	2 Dec 2008 02:56:50 -0000	1.65
+++ drm-modesetting-radeon.patch	3 Dec 2008 00:25:39 -0000	1.66
@@ -1,3 +1,13 @@
+commit 09daed1f3e4942496793c3411aee485cb97eb694
+Author: Dave Airlie <airlied at redhat.com>
+Date:   Wed Dec 3 20:28:05 2008 +1000
+
+    radeon: AGP fixes round 2.
+    
+    More I can't believe its not AGP fixes.
+    Limit the AGP aperture to the GART size, and init the registers
+    in the right place
+
 commit 4a7eb33e9c27c28129c07123c0878e3e603c937e
 Author: Dave Airlie <airlied at redhat.com>
 Date:   Tue Dec 2 12:49:17 2008 +1000
@@ -24269,7 +24279,7 @@
 +	return NULL;
 +}
 diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
-index dcebb4b..e0f7284 100644
+index dcebb4b..7688cde 100644
 --- a/drivers/gpu/drm/radeon/radeon_cp.c
 +++ b/drivers/gpu/drm/radeon/radeon_cp.c
 @@ -31,6 +31,7 @@
@@ -24306,7 +24316,7 @@
  }
  
  u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
-@@ -86,33 +104,71 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
+@@ -86,39 +104,77 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  	else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
  		 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
  		return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
@@ -24366,7 +24376,7 @@
  }
  
 -static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
-+static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc, u32 agp_loc_hi)
++void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc, u32 agp_loc_hi)
  {
  	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  		R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
@@ -24381,6 +24391,13 @@
  		R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
  	else
  		RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
+ }
+ 
+-static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
++void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
+ {
+ 	u32 agp_base_hi = upper_32_bits(agp_base);
+ 	u32 agp_base_lo = agp_base & 0xffffffff;
 @@ -144,20 +200,116 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
  	}
  }
@@ -24405,7 +24422,9 @@
 +		RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 +	} /* PCIE cards appears to not need this */
 +}
-+
+ 
+-	RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
+-	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 +void radeon_pll_errata_after_index(struct drm_radeon_private *dev_priv)
 +{
 +	if (!(dev_priv->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS))
@@ -24442,9 +24461,7 @@
 +u32 RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr)
 +{
 +	uint32_t data;
- 
--	RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
--	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
++
 +	RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
 +	radeon_pll_errata_after_index(dev_priv);
 +	data = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
@@ -24675,26 +24692,26 @@
 -		RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 -	} /* PCIE cards appears to not need this */
 +	radeon_enable_bm(dev_priv);
-+
-+	dev_priv->scratch[0] = 0;
-+	RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
-+
-+	dev_priv->scratch[1] = 0;
-+	RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
  
 -	dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 -	RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
-+	dev_priv->scratch[2] = 0;
-+	RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
++	dev_priv->scratch[0] = 0;
++	RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
  
 -	dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 -	RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
 -		     dev_priv->sarea_priv->last_dispatch);
-+	dev_priv->scratch[3] = 0;
-+	RADEON_WRITE(RADEON_LAST_SWI_REG, 0);
++	dev_priv->scratch[1] = 0;
++	RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
  
 -	dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 -	RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
++	dev_priv->scratch[2] = 0;
++	RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
++
++	dev_priv->scratch[3] = 0;
++	RADEON_WRITE(RADEON_LAST_SWI_REG, 0);
++
 +	dev_priv->scratch[4] = 0;
 +	RADEON_WRITE(RADEON_SCRATCH_REG4, 0);
 +
@@ -25159,7 +25176,7 @@
  	LOCK_TEST_WITH_RETURN(dev, file_priv);
  
  	return radeon_do_engine_reset(dev);
-@@ -1711,6 +1940,739 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
+@@ -1711,6 +1940,632 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
  	return ret;
  }
  
@@ -25639,108 +25656,6 @@
 +	return 0;
 +}
 +
-+#if __OS_HAS_AGP
-+int radeon_modeset_agp_init(struct drm_device *dev)
-+{
-+	drm_radeon_private_t *dev_priv = dev->dev_private;
-+	struct drm_agp_mode mode;
-+	struct drm_agp_info info;
-+	int ret;
-+	int default_mode;
-+	uint32_t agp_status;
-+	bool is_v3;
-+
-+	/* Acquire AGP. */
-+	ret = drm_agp_acquire(dev);
-+	if (ret) {
-+		DRM_ERROR("Unable to acquire AGP: %d\n", ret);
-+		return ret;
-+	}
-+
-+	ret = drm_agp_info(dev, &info);
-+	if (ret) {
-+		DRM_ERROR("Unable to get AGP info: %d\n", ret);
-+		return ret;
-+ 	}
-+
-+	mode.mode = info.mode;
-+
-+	agp_status = (RADEON_READ(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
-+	is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
-+
-+	if (is_v3) {
-+		default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
-+	} else {
-+		if (agp_status & RADEON_AGP_4X_MODE) default_mode = 4;
-+		else if (agp_status & RADEON_AGP_2X_MODE) default_mode = 2;
-+		else default_mode = 1;
-+	}
-+
-+	if (radeon_agpmode > 0) {
-+		if ((radeon_agpmode < (is_v3 ? 4 : 1)) ||
-+		    (radeon_agpmode > (is_v3 ? 8 : 4)) ||
-+		    (radeon_agpmode & (radeon_agpmode - 1))) {
-+			DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n",
-+				  radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4",
-+				  default_mode);
-+			radeon_agpmode = default_mode;
-+		}
-+		else
-+			DRM_INFO("AGP mode requested: %d\n", radeon_agpmode);
-+	} else
-+		radeon_agpmode = default_mode;
-+
-+	mode.mode &= ~RADEON_AGP_MODE_MASK;
-+	if (is_v3) {
-+		switch(radeon_agpmode) {
-+		case 8:
-+			mode.mode |= RADEON_AGPv3_8X_MODE;
-+			break;
-+		case 4:
-+		default:
-+			mode.mode |= RADEON_AGPv3_4X_MODE;
-+			break;
-+		}
-+	} else {
-+		switch(radeon_agpmode) {
-+		case 4: mode.mode |= RADEON_AGP_4X_MODE;
-+		case 2: mode.mode |= RADEON_AGP_2X_MODE;
-+		case 1:
-+		default:
-+			mode.mode |= RADEON_AGP_1X_MODE;
-+			break;
-+		}
-+	}
-+
-+	mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */
-+
-+	ret = drm_agp_enable(dev, mode);
-+	if (ret) {
-+		DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
-+		return ret;
-+	}
-+
-+	/* workaround some hw issues */
-+	if (dev_priv->chip_family < CHIP_R200) {
-+		RADEON_WRITE(RADEON_AGP_CNTL, RADEON_READ(RADEON_AGP_CNTL) | 0x000e0000);
-+	}
-+
-+	radeon_write_agp_base(dev_priv, dev->agp->base);
-+
-+	radeon_write_agp_location(dev_priv,
-+				  (((dev_priv->gart_vm_start - 1 +
-+				  dev_priv->gart_size) & 0xffff0000) |
-+				  (dev_priv->gart_vm_start >> 16)), 0);
-+	return 0;
-+}
-+
-+void radeon_modeset_agp_destroy(struct drm_device *dev)
-+{
-+	if (dev->agp->acquired)
-+		drm_agp_release(dev);
-+}
-+#endif
-+
 +int radeon_modeset_cp_init(struct drm_device *dev)
 +{
 +	drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -25775,11 +25690,6 @@
 +	/* turn off HDP read cache for now */
 +	RADEON_WRITE(RADEON_HOST_PATH_CNTL, RADEON_READ(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS);
 +	      
-+#if __OS_HAS_AGP
-+	if (dev_priv->flags & RADEON_IS_AGP)
-+		radeon_modeset_agp_init(dev);
-+#endif
-+	
 +	return radeon_modeset_cp_resume(dev);
 +}
 +
@@ -25899,7 +25809,7 @@
  int radeon_driver_load(struct drm_device *dev, unsigned long flags)
  {
  	drm_radeon_private_t *dev_priv;
-@@ -1724,6 +2686,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1724,6 +2579,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
  	dev->dev_private = (void *)dev_priv;
  	dev_priv->flags = flags;
  
@@ -25908,7 +25818,7 @@
  	switch (flags & RADEON_FAMILY_MASK) {
  	case CHIP_R100:
  	case CHIP_RV200:
-@@ -1744,6 +2708,18 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1744,6 +2601,18 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
  		break;
  	}
  
@@ -25927,7 +25837,7 @@
  	if (drm_device_is_agp(dev))
  		dev_priv->flags |= RADEON_IS_AGP;
  	else if (drm_device_is_pcie(dev))
-@@ -1751,9 +2727,34 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1751,9 +2620,34 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
  	else
  		dev_priv->flags |= RADEON_IS_PCI;
  
@@ -25963,7 +25873,7 @@
  	if (ret != 0)
  		return ret;
  
-@@ -1763,28 +2764,122 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1763,28 +2657,122 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
  		return ret;
  	}
  
@@ -26097,7 +26007,7 @@
  
  	return 0;
  }
-@@ -1793,6 +2888,18 @@ int radeon_driver_unload(struct drm_device *dev)
+@@ -1793,6 +2781,14 @@ int radeon_driver_unload(struct drm_device *dev)
  {
  	drm_radeon_private_t *dev_priv = dev->dev_private;
  
@@ -26105,10 +26015,6 @@
 +		drm_irq_uninstall(dev);
 +		radeon_modeset_cleanup(dev);
 +		radeon_gem_mm_fini(dev);
-+#if __OS_HAS_AGP
-+		if (dev_priv->flags & RADEON_IS_AGP)
-+			radeon_modeset_agp_destroy(dev);
-+#endif
 +	}
 +
 +	drm_rmmap(dev, dev_priv->mmio);
@@ -26116,7 +26022,7 @@
  	DRM_DEBUG("\n");
  
  	drm_rmmap(dev, dev_priv->mmio);
-@@ -1802,3 +2909,63 @@ int radeon_driver_unload(struct drm_device *dev)
+@@ -1802,3 +2798,63 @@ int radeon_driver_unload(struct drm_device *dev)
  	dev->dev_private = NULL;
  	return 0;
  }
@@ -27942,7 +27848,7 @@
  }
  
 diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
-index 7a18378..dec86db 100644
+index 7a18378..58c71fa 100644
 --- a/drivers/gpu/drm/radeon/radeon_drv.h
 +++ b/drivers/gpu/drm/radeon/radeon_drv.h
 @@ -34,6 +34,8 @@
@@ -28598,7 +28504,7 @@
  
  #define OUT_RING( x ) do {						\
  	if ( RADEON_VERBOSE ) {						\
-@@ -1443,4 +1625,149 @@ do {									\
+@@ -1443,4 +1625,151 @@ do {									\
  	write &= mask;						\
  } while (0)
  
@@ -28747,6 +28653,8 @@
 +extern int r300_check_range(unsigned reg, int count);
 +extern int r300_get_reg_flags(unsigned reg);
 +int radeon_gem_prelocate(struct drm_radeon_cs_parser *parser);
++void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc, u32 agp_loc_hi);
++void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
  #endif				/* __RADEON_DRV_H__ */
 diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
 new file mode 100644
@@ -30901,10 +30809,10 @@
 +
 diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
 new file mode 100644
-index 0000000..9980a9f
+index 0000000..e5e21a5
 --- /dev/null
 +++ b/drivers/gpu/drm/radeon/radeon_gem.c
-@@ -0,0 +1,1677 @@
+@@ -0,0 +1,1797 @@
 +/*
 + * Copyright 2008 Red Hat Inc.
 + *
@@ -31538,6 +31446,17 @@
 +	/* gart values setup - start the GART */
 +	if (dev_priv->flags & RADEON_IS_AGP) {
 +		radeon_set_pcigart(dev_priv, 0);
++		/* enable AGP GART bits */
++		
++		DRM_INFO("setting agp_base to %x\n", dev->agp->base);
++		radeon_write_agp_base(dev_priv, dev->agp->base);
++
++		DRM_INFO("setting agp_location to %x\n", dev_priv->gart_vm_start);
++		radeon_write_agp_location(dev_priv,
++					  (((dev_priv->gart_vm_start - 1 +
++					     dev_priv->gart_size) & 0xffff0000) |
++					   (dev_priv->gart_vm_start >> 16)), 0);
++
 +	} else {
 +		radeon_set_pcigart(dev_priv, 1);
 +	}
@@ -31870,6 +31789,101 @@
 +
 +}
 +
++#if __OS_HAS_AGP
++int radeon_modeset_agp_init(struct drm_device *dev)
++{
++	drm_radeon_private_t *dev_priv = dev->dev_private;
++	struct drm_agp_mode mode;
++	struct drm_agp_info info;
++	int ret;
++	int default_mode;
++	uint32_t agp_status;
++	bool is_v3;
++
++	/* Acquire AGP. */
++	ret = drm_agp_acquire(dev);
++	if (ret) {
++		DRM_ERROR("Unable to acquire AGP: %d\n", ret);
++		return ret;
++	}
++
++	ret = drm_agp_info(dev, &info);
++	if (ret) {
++		DRM_ERROR("Unable to get AGP info: %d\n", ret);
++		return ret;
++ 	}
++
++	mode.mode = info.mode;
++
++	agp_status = (RADEON_READ(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
++	is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
++
++	if (is_v3) {
++		default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
++	} else {
++		if (agp_status & RADEON_AGP_4X_MODE) default_mode = 4;
++		else if (agp_status & RADEON_AGP_2X_MODE) default_mode = 2;
++		else default_mode = 1;
++	}
++
++	if (radeon_agpmode > 0) {
++		if ((radeon_agpmode < (is_v3 ? 4 : 1)) ||
++		    (radeon_agpmode > (is_v3 ? 8 : 4)) ||
++		    (radeon_agpmode & (radeon_agpmode - 1))) {
++			DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n",
++				  radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4",
++				  default_mode);
++			radeon_agpmode = default_mode;
++		}
++		else
++			DRM_INFO("AGP mode requested: %d\n", radeon_agpmode);
++	} else
++		radeon_agpmode = default_mode;
++
++	mode.mode &= ~RADEON_AGP_MODE_MASK;
++	if (is_v3) {
++		switch(radeon_agpmode) {
++		case 8:
++			mode.mode |= RADEON_AGPv3_8X_MODE;
++			break;
++		case 4:
++		default:
++			mode.mode |= RADEON_AGPv3_4X_MODE;
++			break;
++		}
++	} else {
++		switch(radeon_agpmode) {
++		case 4: mode.mode |= RADEON_AGP_4X_MODE;
++		case 2: mode.mode |= RADEON_AGP_2X_MODE;
++		case 1:
++		default:
++			mode.mode |= RADEON_AGP_1X_MODE;
++			break;
++		}
++	}
++
++	mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */
++
++	ret = drm_agp_enable(dev, mode);
++	if (ret) {
++		DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
++		return ret;
++	}
++
++	/* workaround some hw issues */
++	if (dev_priv->chip_family < CHIP_R200) {
++		RADEON_WRITE(RADEON_AGP_CNTL, RADEON_READ(RADEON_AGP_CNTL) | 0x000e0000);
++	}
++	return 0;
++}
++
++void radeon_modeset_agp_destroy(struct drm_device *dev)
++{
++	if (dev->agp->acquired)
++		drm_agp_release(dev);
++}
++#endif
++
 +/* init memory manager - start with all of VRAM and a 32MB GART aperture for now */
 +int radeon_gem_mm_init(struct drm_device *dev)
 +{
@@ -31895,6 +31909,15 @@
 +		       ((dev_priv->mm.vram_visible) >> PAGE_SHIFT) - 16,
 +		       0);
 +
++	/* need AGP to work out sizes */
++#if __OS_HAS_AGP
++	if (dev_priv->flags & RADEON_IS_AGP) {
++		radeon_modeset_agp_init(dev);
++
++		if (dev->agp->agp_info.aper_size < radeon_gart_size)
++			radeon_gart_size = dev->agp->agp_info.aper_size;
++	}
++#endif
 +
 +	if (dev_priv->chip_family > CHIP_R600) {
 +		dev_priv->mm_enabled = true;
@@ -31958,6 +31981,11 @@
 +		}
 +	}
 +
++#if __OS_HAS_AGP
++	if (dev_priv->flags & RADEON_IS_AGP)
++		radeon_modeset_agp_destroy(dev);
++#endif
++
 +	if (drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM, 1)) {
 +		DRM_DEBUG("delaying takedown of VRAM memory\n");
 +	}


Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-10/kernel.spec,v
retrieving revision 1.1171
retrieving revision 1.1172
diff -u -r1.1171 -r1.1172
--- kernel.spec	2 Dec 2008 21:32:49 -0000	1.1171
+++ kernel.spec	3 Dec 2008 00:25:40 -0000	1.1172
@@ -1929,6 +1929,9 @@
 %kernel_variant_files -k vmlinux %{with_kdump} kdump
 
 %changelog
+* Tue Dec 03 2008 Dave Airlie <airlied at redhat.com> 2.6.27.7-136
+- radeon: fix AGP harder than the last time.
+
 * Tue Dec 02 2008 John W. Linville <linville at redhat.com> 2.6.27.7-135
 - Backported ath9k DMA fixes from pre-2.6.28
 - Drop patch to disable ath9k when swiotlb is in use

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