rpms/xorg-x11-drv-ati/F-10 radeon-modeset.patch, 1.48, 1.49 xorg-x11-drv-ati.spec, 1.162, 1.163
Dave Airlie
airlied at fedoraproject.org
Tue Dec 9 03:35:17 UTC 2008
Author: airlied
Update of /cvs/pkgs/rpms/xorg-x11-drv-ati/F-10
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv11366
Modified Files:
radeon-modeset.patch xorg-x11-drv-ati.spec
Log Message:
- radeon-modeset.patch: fix resume with no DRI + another 2D/3D issue
radeon-modeset.patch:
Index: radeon-modeset.patch
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/F-10/radeon-modeset.patch,v
retrieving revision 1.48
retrieving revision 1.49
diff -u -r1.48 -r1.49
--- radeon-modeset.patch 2 Dec 2008 09:13:33 -0000 1.48
+++ radeon-modeset.patch 9 Dec 2008 03:34:45 -0000 1.49
@@ -1,3 +1,15 @@
+commit 97461ae1187e31f402a55d63fd55428abcc72ed8
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Dec 9 13:29:18 2008 +1000
+
+ radeon: upstream fix for Init3D vs switch to/from 2d/3d
+
+commit 654092013c6ca2b666ec08e4046ab0b4d327b4c5
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Dec 8 14:19:47 2008 +1000
+
+ radeon: only update dri buffers if DRI enabled
+
commit c14f510c877c5ccfb38ebc11b910891a4bcf40ba
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Dec 1 15:31:08 2008 +1100
@@ -805,12 +817,6 @@
instead of trying to do them all in userspace.
useful steps towards getting kernel modesetting
-
-commit 12e71eaf7999520d23d50cfbcfc0299b2bdf7a9d
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Jul 4 10:39:34 2008 +1000
-
- port to using drm header files
diff --git a/configure.ac b/configure.ac
index b8c18a6..8b126b5 100644
--- a/configure.ac
@@ -1812,7 +1818,7 @@
+#endif
+#endif
diff --git a/src/radeon.h b/src/radeon.h
-index f7ae1a8..a437b55 100644
+index 5455d57..a364e4a 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -46,6 +46,8 @@
@@ -1832,22 +1838,33 @@
/* Render support */
#ifdef RENDER
#include "picturestr.h"
-@@ -404,6 +407,14 @@ typedef enum {
-
- typedef struct _atomBiosHandle *atomBiosHandlePtr;
-
-+#define RADEON_POOL_GART 0
-+#define RADEON_POOL_VRAM 1
-+
+@@ -407,22 +410,9 @@ typedef struct _atomBiosHandle *atomBiosHandlePtr;
+ #define RADEON_POOL_GART 0
+ #define RADEON_POOL_VRAM 1
+
+-struct radeon_memory {
+- int pool; // memory is VRAM vs GART
+- unsigned long offset;
+- unsigned long end;
+-
+- unsigned long size;
+- unsigned long allocated_size;
+- uint64_t bus_addr;
+- int key;
+-
+- Bool bound;
+- unsigned long agp_offset;
+- unsigned int pitch;
+- char *name;
+- struct radeon_memory *next, *prev;
+- uint32_t kernel_bo_handle;
+struct radeon_exa_pixmap_priv {
+ dri_bo *bo;
+ int flags;
-+};
-+
+ };
+
typedef struct {
- uint32_t pci_device_id;
- RADEONChipFamily chip_family;
-@@ -414,7 +425,27 @@ typedef struct {
+@@ -435,7 +425,27 @@ typedef struct {
int singledac;
} RADEONCardInfo;
@@ -1875,7 +1892,7 @@
struct radeon_cp {
Bool CPRuns; /* CP is running */
Bool CPInUse; /* CP has been used by X server */
-@@ -428,6 +459,10 @@ struct radeon_cp {
+@@ -449,6 +459,10 @@ struct radeon_cp {
drmBufPtr indirectBuffer;
int indirectStart;
@@ -1886,7 +1903,7 @@
/* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */
int dma_begin_count;
char *dma_debug_func;
-@@ -494,13 +529,13 @@ struct radeon_dri {
+@@ -515,13 +529,13 @@ struct radeon_dri {
drm_handle_t ringHandle; /* Handle from drmAddMap */
drmSize ringMapSize; /* Size of map */
int ringSize; /* Size of ring (in MB) */
@@ -1902,7 +1919,7 @@
/* CP vertex/indirect buffer data */
unsigned long bufStart; /* Offset into GART space */
-@@ -519,7 +554,6 @@ struct radeon_dri {
+@@ -540,7 +554,6 @@ struct radeon_dri {
drmAddress gartTex; /* Map */
int log2GARTTexGran;
@@ -1910,7 +1927,7 @@
int fbX;
int fbY;
int backX;
-@@ -836,6 +870,44 @@ typedef struct {
+@@ -857,6 +870,44 @@ typedef struct {
Bool r600_shadow_fb;
void *fb_shadow;
@@ -1955,7 +1972,7 @@
} RADEONInfoRec, *RADEONInfoPtr;
#define RADEONWaitForFifo(pScrn, entries) \
-@@ -1078,6 +1150,23 @@ extern void
+@@ -1099,6 +1150,23 @@ extern void
radeon_legacy_free_memory(ScrnInfoPtr pScrn,
void *mem_struct);
@@ -1979,7 +1996,7 @@
#ifdef XF86DRI
# ifdef USE_XAA
/* radeon_accelfuncs.c */
-@@ -1096,7 +1185,9 @@ do { \
+@@ -1117,7 +1185,9 @@ do { \
#define RADEONCP_RELEASE(pScrn, info) \
do { \
@@ -1990,7 +2007,7 @@
RADEON_PURGE_CACHE(); \
RADEON_WAIT_UNTIL_IDLE(); \
RADEONCPReleaseIndirect(pScrn); \
-@@ -1130,7 +1221,7 @@ do { \
+@@ -1151,7 +1221,7 @@ do { \
#define RADEONCP_REFRESH(pScrn, info) \
do { \
@@ -1999,7 +2016,7 @@
if (info->cp->needCacheFlush) { \
RADEON_PURGE_CACHE(); \
RADEON_PURGE_ZCACHE(); \
-@@ -1157,6 +1248,13 @@ do { \
+@@ -1178,6 +1248,13 @@ do { \
#define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0
#define BEGIN_RING(n) do { \
@@ -2013,7 +2030,7 @@
if (RADEON_VERBOSE) { \
xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
"BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\
-@@ -1169,13 +1267,6 @@ do { \
+@@ -1190,13 +1267,6 @@ do { \
} \
info->cp->dma_debug_func = __FILE__; \
info->cp->dma_debug_lineno = __LINE__; \
@@ -2027,7 +2044,7 @@
__expected = n; \
__head = (pointer)((char *)info->cp->indirectBuffer->address + \
info->cp->indirectBuffer->used); \
-@@ -1218,6 +1309,14 @@ do { \
+@@ -1239,6 +1309,14 @@ do { \
OUT_RING(val); \
} while (0)
@@ -2042,6 +2059,50 @@
#define FLUSH_RING() \
do { \
if (RADEON_VERBOSE) \
+@@ -1310,6 +1388,43 @@ do { \
+
+ #endif /* XF86DRI */
+
++#if defined(XF86DRI) && defined(USE_EXA)
++#define RADEON_SWITCH_TO_2D() \
++do { \
++ uint32_t flush = 0; \
++ switch (info->accel_state->engineMode) { \
++ case EXA_ENGINEMODE_UNKNOWN: \
++ case EXA_ENGINEMODE_3D: \
++ flush = 1; \
++ case EXA_ENGINEMODE_2D: \
++ break; \
++ } \
++ if (flush && info->directRenderingEnabled) \
++ RADEONCPFlushIndirect(pScrn, 1); \
++ info->accel_state->engineMode = EXA_ENGINEMODE_2D; \
++} while (0);
++
++#define RADEON_SWITCH_TO_3D() \
++do { \
++ uint32_t flush = 0; \
++ switch (info->accel_state->engineMode) { \
++ case EXA_ENGINEMODE_UNKNOWN: \
++ case EXA_ENGINEMODE_2D: \
++ flush = 1; \
++ case EXA_ENGINEMODE_3D: \
++ break; \
++ } \
++ if (flush && info->directRenderingEnabled) { \
++ RADEONCPFlushIndirect(pScrn, 1); \
++ RADEONInit3DEngine(pScrn); \
++ } \
++ info->accel_state->engineMode = EXA_ENGINEMODE_3D; \
++} while (0);
++#else
++#define RADEON_SWITCH_TO_2D()
++#define RADEON_SWITCH_TO_3D()
++#endif
++
+ static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn)
+ {
+ #ifdef USE_EXA
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index a6e332d..c65125c 100644
--- a/src/radeon_accel.c
@@ -3297,7 +3358,7 @@
xf86CrtcPtr crtc = xf86_config->crtc[c];
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
-index 5542d2b..a4e8dea 100644
+index 7892ae3..a4e8dea 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -40,6 +40,8 @@
@@ -3309,16 +3370,7 @@
/* Driver data structures */
#include "radeon.h"
-@@ -50,6 +52,8 @@
- #include "radeon_dri.h"
- #include "radeon_version.h"
-
-+#include "radeon_drm.h"
-+
- /* X and server generic header files */
- #include "xf86.h"
- #include "xf86PciInfo.h"
-@@ -67,16 +71,31 @@ static size_t radeon_drm_page_size;
+@@ -69,16 +71,31 @@ static size_t radeon_drm_page_size;
extern void GlxSetVisualConfigs(int nconfigs, __GLXvisualConfig *configs,
void **configprivs);
@@ -3352,7 +3404,7 @@
static void RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num);
#endif
#endif
-@@ -349,6 +368,126 @@ static void RADEONDestroyContext(ScreenPtr pScreen, drm_context_t hwContext,
+@@ -351,6 +368,126 @@ static void RADEONDestroyContext(ScreenPtr pScreen, drm_context_t hwContext,
#endif
}
@@ -3479,7 +3531,7 @@
/* Called when the X server is woken up to allow the last client's
* context to be saved and the X server's context to be loaded. This is
* not necessary for the Radeon since the client detects when it's
-@@ -698,25 +837,35 @@ static void RADEONDRIInitGARTValues(RADEONInfoPtr info)
+@@ -700,25 +837,35 @@ static void RADEONDRIInitGARTValues(RADEONInfoPtr info)
info->dri->gartOffset = 0;
@@ -3534,7 +3586,7 @@
}
/* Set AGP transfer mode according to requests and constraints */
-@@ -888,6 +1037,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -890,6 +1037,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] ring handle = 0x%08x\n", info->dri->ringHandle);
@@ -3543,7 +3595,7 @@
if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
&info->dri->ring) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n");
-@@ -896,9 +1047,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -898,9 +1047,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Ring mapped at 0x%08lx\n",
(unsigned long)info->dri->ring);
@@ -3555,7 +3607,7 @@
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not add ring read ptr mapping\n");
return FALSE;
-@@ -907,6 +1059,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -909,6 +1059,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[agp] ring read ptr handle = 0x%08x\n",
info->dri->ringReadPtrHandle);
@@ -3564,7 +3616,7 @@
if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize,
&info->dri->ringReadPtr) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
-@@ -916,6 +1070,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -918,6 +1070,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Ring read ptr mapped at 0x%08lx\n",
(unsigned long)info->dri->ringReadPtr);
@@ -3572,7 +3624,7 @@
if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize,
DRM_AGP, 0, &info->dri->bufHandle) < 0) {
-@@ -991,6 +1146,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -993,6 +1146,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] ring handle = 0x%08x\n", info->dri->ringHandle);
@@ -3580,7 +3632,7 @@
if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
&info->dri->ring) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n");
-@@ -1002,6 +1158,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1004,6 +1158,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring contents 0x%08lx\n",
*(unsigned long *)(pointer)info->dri->ring);
@@ -3588,7 +3640,7 @@
if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize,
DRM_SCATTER_GATHER, flags, &info->dri->ringReadPtrHandle) < 0) {
-@@ -1013,8 +1170,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1015,8 +1170,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[pci] ring read ptr handle = 0x%08x\n",
info->dri->ringReadPtrHandle);
@@ -3599,7 +3651,7 @@
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not map ring read ptr\n");
return FALSE;
-@@ -1025,6 +1184,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1027,6 +1184,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring read ptr contents 0x%08lx\n",
*(unsigned long *)(pointer)info->dri->ringReadPtr);
@@ -3607,7 +3659,7 @@
if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize,
DRM_SCATTER_GATHER, 0, &info->dri->bufHandle) < 0) {
-@@ -1077,6 +1237,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1079,6 +1237,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
*/
static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
@@ -3617,7 +3669,7 @@
/* Map registers */
info->dri->registerSize = info->MMIOSize;
if (drmAddMap(info->dri->drmFD, info->MMIOAddr, info->dri->registerSize,
-@@ -1115,20 +1278,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1117,20 +1278,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
drmInfo.fb_bpp = info->CurrentLayout.pixel_code;
drmInfo.depth_bpp = (info->dri->depthBits - 8) * 2;
@@ -3655,7 +3707,7 @@
if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT,
&drmInfo, sizeof(drm_radeon_init_t)) < 0)
return FALSE;
-@@ -1137,7 +1303,8 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1139,7 +1303,8 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
* registers back to their default values, so we need to restore
* those engine register here.
*/
@@ -3665,7 +3717,7 @@
return TRUE;
}
-@@ -1333,12 +1500,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
+@@ -1335,12 +1500,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
/* Get DRM version & close DRM */
info->dri->pKernelDRMVersion = drmGetVersion(fd);
@@ -3679,7 +3731,7 @@
}
/* Now check if we qualify */
-@@ -1372,10 +1538,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
+@@ -1374,10 +1538,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
req_patch);
drmFreeVersion(info->dri->pKernelDRMVersion);
info->dri->pKernelDRMVersion = NULL;
@@ -3710,7 +3762,7 @@
}
Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
-@@ -1384,6 +1569,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
+@@ -1386,6 +1569,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int value = 0;
@@ -3720,7 +3772,7 @@
if (!info->want_vblank_interrupts)
on = FALSE;
-@@ -1403,6 +1591,48 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
+@@ -1405,6 +1591,48 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
return TRUE;
}
@@ -3769,7 +3821,7 @@
/* Initialize the screen-specific data structures for the DRI and the
* Radeon. This is the main entry point to the device-specific
-@@ -1466,10 +1696,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+@@ -1468,10 +1696,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4;
pDRIInfo->ddxDriverMinorVersion = 3;
pDRIInfo->ddxDriverPatchVersion = 0;
@@ -3796,7 +3848,7 @@
pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES;
pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES
< RADEON_MAX_DRAWABLES
-@@ -1522,9 +1764,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+@@ -1524,9 +1764,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d;
pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d;
pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d;
@@ -3807,7 +3859,7 @@
pDRIInfo->ClipNotify = RADEONDRIClipNotify;
#endif
-@@ -1556,57 +1796,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+@@ -1558,78 +1796,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo = NULL;
return FALSE;
}
@@ -3844,38 +3896,57 @@
- {
- void *scratch_ptr;
- int scratch_int;
+-
+- DRIGetDeviceInfo(pScreen, &info->dri->fbHandle,
+- &scratch_int, &scratch_int,
+- &scratch_int, &scratch_int,
+- &scratch_ptr);
+- }
+ /* Now, nuke dri.c's dummy frontbuffer map setup if we did that. */
+ if (pDRIInfo->frameBufferSize != 0 && info->drm_mm) {
+ int tmp;
+ drm_handle_t fb_handle;
+ void *ptmp;
-- DRIGetDeviceInfo(pScreen, &info->dri->fbHandle,
-- &scratch_int, &scratch_int,
-- &scratch_int, &scratch_int,
-- &scratch_ptr);
-- }
--
- /* FIXME: When are these mappings unmapped? */
--
-- if (!RADEONInitVisualConfigs(pScreen)) {
-- RADEONDRICloseScreen(pScreen);
-- return FALSE;
+ /* With the compat method, it will continue to report
+ * the wrong map out of GetDeviceInfo, which will break AIGLX.
+ */
+ DRIGetDeviceInfo(pScreen, &fb_handle, &tmp, &tmp, &tmp, &tmp, &ptmp);
+ drmRmMap(info->dri->drmFD, fb_handle);
-+
+
+- if (!RADEONInitVisualConfigs(pScreen)) {
+- RADEONDRICloseScreen(pScreen);
+- return FALSE;
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Removed DRI frontbuffer mapping in compatibility mode.\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "DRIGetDeviceInfo will report incorrect frontbuffer "
+ "handle.\n");
-+ }
+ }
+- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] Visual configs initialized\n");
+-
+- {
+- int page_size = getpagesize();
+- struct drm_radeon_gem_init init_args;
+-
+
+ if (info->drm_mm) {
-+ int ret;
+ int ret;
+-
+- unsigned long aperStart = ((info->pciAperSize * 1024 * 1024) - (16384 * 1024)) / page_size;
+- unsigned long aperEnd = ((info->pciAperSize * 1024 * 1024)) / page_size;
+-
+- init_args.gtt_start = aperStart;
+- init_args.gtt_end = aperEnd;
+- init_args.vram_start = info->FbMapSize / page_size;
+- init_args.vram_end = (pScrn->videoRam * 1024) / page_size;
+-
+- ErrorF("initing %llx %llx %llx %llx\n", init_args.gtt_start,
+- init_args.gtt_end, init_args.vram_start, init_args.vram_end);
+- ret = drmCommandWriteRead(info->drmFD, DRM_RADEON_GEM_INIT, &init_args, sizeof(init_args));
+- if (ret)
+- ErrorF("ioctl failed %d\n", ret);
+ ret = radeon_dri_gart_init(pScreen);
+ if (!ret) {
+ xf86DrvMsg(pScreen->myNum, X_ERROR,
@@ -3903,7 +3974,6 @@
+ return FALSE;
+ }
}
-- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] Visual configs initialized\n");
return TRUE;
}
@@ -3912,7 +3982,7 @@
static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
-@@ -1648,14 +1891,18 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
+@@ -1671,14 +1891,18 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
return FALSE;
}
@@ -3937,7 +4007,7 @@
/* Initialize kernel GART memory manager */
RADEONDRIGartHeapInit(info, pScreen);
-@@ -1667,6 +1914,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
+@@ -1690,6 +1914,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
pSAREAPriv = (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScreen);
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
@@ -3948,7 +4018,7 @@
pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate;
pRADEONDRI->deviceID = info->Chipset;
-@@ -1823,6 +2074,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
+@@ -1846,6 +2074,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
drmUnmap(info->dri->buf, info->dri->bufMapSize);
info->dri->buf = NULL;
}
@@ -3957,7 +4027,7 @@
if (info->dri->ringReadPtr) {
drmUnmap(info->dri->ringReadPtr, info->dri->ringReadMapSize);
info->dri->ringReadPtr = NULL;
-@@ -1831,6 +2084,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
+@@ -1854,6 +2084,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
drmUnmap(info->dri->ring, info->dri->ringMapSize);
info->dri->ring = NULL;
}
@@ -3965,23 +4035,32 @@
if (info->dri->agpMemHandle != DRM_AGP_NO_HANDLE) {
drmAgpUnbind(info->dri->drmFD, info->dri->agpMemHandle);
drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle);
-@@ -2237,3 +2491,16 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
- &radeonsetparam, sizeof(drm_radeon_setparam_t));
+@@ -2261,18 +2492,15 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
return ret;
}
-+
+
+-int RADEONAllocateKernelVRAM(ScrnInfoPtr pScrn, int size, int alignment, Boolean no_backing_store, uint32_t *handle)
+static Bool radeon_dri_gart_init(ScreenPtr pScreen)
-+{
+ {
+- struct drm_radeon_gem_create args;
+-
+- args.size = size;
+- args.alignment = alignment;
+- args.initial_domain = RADEON_GEM_DOMAIN_GPU;
+- args.no_backing_store = no_backing_store;
+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
-+
+
+ RADEONDRIInitGARTValues(info);
-+
+
+- ret = drmCommandWriteRead(info->drmFD, DRM_RADEON_GEM_CREATE, &args, sizeof(args));
+ /* so we want to allocate the buffers/gart texmap */
+ /* ignore ring stuff */
+ return radeon_setup_gart_mem(pScreen);
-+
-+}
+
+- *handle = args.handle;
+- return ret;
+ }
diff --git a/src/radeon_dri_bufmgr.c b/src/radeon_dri_bufmgr.c
new file mode 100644
index 0000000..f6154dc
@@ -4463,7 +4542,7 @@
+
+#endif
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
-index c759bd6..0ec78c4 100644
+index 33c4090..9ff2988 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -67,7 +67,7 @@
@@ -4487,15 +4566,17 @@
}
static Bool
RADEONCreateScreenResources (ScreenPtr pScreen)
-@@ -1620,6 +1623,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
- }
+@@ -1621,9 +1624,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
pScrn->videoRam &= ~1023;
-+
+
+- /* half video RAM for TTM */
info->FbMapSize = pScrn->videoRam * 1024;
+- info->FbMapSize /= 2;
/* if the card is PCI Express reserve the last 32k for the gart table */
-@@ -1747,56 +1751,62 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
+ #ifdef XF86DRI
+@@ -1750,56 +1751,62 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
from = X_PROBED;
info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffUL;
pScrn->memPhysBase = info->LinearAddr;
@@ -4600,25 +4681,7 @@
#ifdef XF86DRI
/* AGP/PCI */
-@@ -1989,6 +1999,9 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
- if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
- int errmaj = 0, errmin = 0;
-
-+#if defined(USE_EXA)
-+ info->useEXA = TRUE;
-+#endif
- from = X_DEFAULT;
- #if defined(USE_EXA)
- #if defined(USE_XAA)
-@@ -1999,6 +2012,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
- info->useEXA = TRUE;
- } else if (xf86NameCmp(optstr, "XAA") == 0) {
- from = X_CONFIG;
-+ info->useEXA = FALSE;
- }
- }
- #else /* USE_XAA */
-@@ -2102,15 +2116,9 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10)
+@@ -2109,15 +2116,9 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10)
return TRUE;
}
@@ -4635,7 +4698,7 @@
if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n");
-@@ -2121,6 +2129,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
+@@ -2128,6 +2129,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n");
return FALSE;
}
@@ -4658,7 +4721,7 @@
info->cp->CPInUse = FALSE;
info->cp->CPStarted = FALSE;
info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
-@@ -2685,6 +2709,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = {
+@@ -2692,6 +2709,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = {
RADEONCRTCResize
};
@@ -4696,7 +4759,7 @@
Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
{
xf86CrtcConfigPtr xf86_config;
-@@ -2705,6 +2760,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2712,6 +2760,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
info = RADEONPTR(pScrn);
info->MMIO = NULL;
@@ -4705,7 +4768,7 @@
info->IsSecondary = FALSE;
info->IsPrimary = FALSE;
-@@ -2739,59 +2796,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2746,59 +2796,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
}
info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
@@ -4813,7 +4876,7 @@
if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive))
goto fail;
-@@ -2801,10 +2862,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2808,10 +2862,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR;
pScrn->monitor = pScrn->confScreen->monitor;
@@ -4830,7 +4893,7 @@
if (!RADEONPreInitVisual(pScrn))
goto fail;
-@@ -2818,136 +2881,197 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2825,136 +2881,197 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions));
xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
@@ -5133,7 +5196,7 @@
/* Get ScreenInit function */
if (!xf86LoadSubModule(pScrn, "fb")) return FALSE;
-@@ -2962,10 +3086,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2969,10 +3086,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
if (!RADEONPreInitXv(pScrn)) goto fail;
}
@@ -5150,7 +5213,7 @@
}
if (pScrn->modes == NULL) {
-@@ -3206,7 +3332,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3213,7 +3332,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
int subPixelOrder = SubPixelUnknown;
char* s;
#endif
@@ -5159,7 +5222,7 @@
info->accelOn = FALSE;
#ifdef USE_XAA
-@@ -3226,52 +3352,55 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3233,52 +3352,55 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
"RADEONScreenInit %lx %ld\n",
pScrn->memPhysBase, pScrn->fbOffset);
#endif
@@ -5249,7 +5312,7 @@
/* Visual setup */
miClearVisualTypes();
if (!miSetVisualTypes(pScrn->depth,
-@@ -3305,19 +3434,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3312,19 +3434,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
hasDRI = info->directRenderingEnabled;
#endif /* XF86DRI */
@@ -5284,7 +5347,7 @@
}
}
-@@ -3357,11 +3488,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3364,11 +3488,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (hasDRI) {
info->accelDFS = info->cardType != CARD_AGP;
@@ -5301,7 +5364,7 @@
/* Reserve approx. half of offscreen memory for local textures by
* default, can be overridden with Option "FBTexPercent".
* Round down to a whole number of texture regions.
-@@ -3390,7 +3526,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3397,7 +3526,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#endif
#if defined(XF86DRI) && defined(USE_XAA)
@@ -5310,7 +5373,7 @@
info->dri->textureSize = -1;
if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT,
&(info->dri->textureSize))) {
-@@ -3408,7 +3544,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3415,7 +3544,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#endif
#ifdef USE_XAA
@@ -5319,7 +5382,7 @@
return FALSE;
#endif
-@@ -3429,7 +3565,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3436,7 +3565,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
info->CurrentLayout.pixel_bytes);
int maxy = info->FbMapSize / width_bytes;
@@ -5328,7 +5391,7 @@
xf86DrvMsg(scrnIndex, X_ERROR,
"Static buffer allocation failed. Disabling DRI.\n");
xf86DrvMsg(scrnIndex, X_ERROR,
-@@ -3443,15 +3579,41 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3450,15 +3579,41 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
}
}
@@ -5373,7 +5436,7 @@
#endif
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Initializing fb layer\n");
-@@ -3475,7 +3637,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3482,7 +3637,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (info->r600_shadow_fb == FALSE) {
/* Init fb layer */
@@ -5382,7 +5445,7 @@
pScrn->virtualX, pScrn->virtualY,
pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
pScrn->bitsPerPixel))
-@@ -3517,8 +3679,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3524,8 +3679,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* restore the memory map here otherwise we may get a hang when
* initializing the drm below
*/
@@ -5395,7 +5458,7 @@
/* Backing store setup */
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-@@ -3528,7 +3692,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3535,7 +3692,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* DRI finalisation */
#ifdef XF86DRI
@@ -5404,7 +5467,7 @@
info->dri->pKernelDRMVersion->version_minor >= 19)
{
if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0)
-@@ -3547,11 +3711,17 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3554,11 +3711,17 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen);
}
if (info->directRenderingEnabled) {
@@ -5423,7 +5486,7 @@
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
-@@ -3649,10 +3819,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3656,10 +3819,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
return FALSE;
}
}
@@ -5433,15 +5496,15 @@
- if (!xf86SetDesiredModes (pScrn))
+ if (info->drm_mode_setting) {
+ if (!drmmode_set_desired_modes(pScrn, &info->drmmode))
-+ return FALSE;
+ return FALSE;
+ } else {
+ if (!xf86SetDesiredModes (pScrn))
- return FALSE;
++ return FALSE;
+ }
/* Provide SaveScreen & wrap BlockHandler and CloseScreen */
/* Wrap CloseScreen */
-@@ -5133,7 +5309,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5140,7 +5309,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
#ifdef XF86DRI
Bool CPStarted = info->cp->CPStarted;
@@ -5450,7 +5513,7 @@
DRILock(pScrn->pScreen, 0);
RADEONCP_STOP(pScrn, info);
}
-@@ -5156,8 +5332,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5163,8 +5332,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
#endif
}
@@ -5463,7 +5526,7 @@
ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0);
-@@ -5169,15 +5347,18 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5176,15 +5347,18 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
/* xf86SetRootClip would do, but can't access that here */
}
@@ -5489,7 +5552,7 @@
}
#endif
-@@ -5375,6 +5556,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
+@@ -5382,6 +5556,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
xf86OutputPtr output = config->output[config->compat_output];
xf86CrtcPtr crtc = output->crtc;
@@ -5501,7 +5564,7 @@
#ifdef XF86DRI
if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0);
#endif
-@@ -5410,67 +5596,91 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
+@@ -5417,67 +5596,92 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONEnterVT\n");
@@ -5587,7 +5650,8 @@
- for (i = 0; i < config->num_crtc; i++)
- radeon_crtc_modeset_ioctl(config->crtc[i], TRUE);
-+ radeon_update_dri_buffers(pScrn->pScreen);
++ if (info->directRenderingEnabled)
++ radeon_update_dri_buffers(pScrn->pScreen);
pScrn->vtSema = TRUE;
@@ -5638,7 +5702,7 @@
}
#endif
/* this will get XVideo going again, but only if XVideo was initialised
-@@ -5482,7 +5692,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
+@@ -5489,7 +5693,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
RADEONEngineRestore(pScrn);
#ifdef XF86DRI
@@ -5647,7 +5711,7 @@
RADEONCP_START(pScrn, info);
DRIUnlock(pScrn->pScreen);
}
-@@ -5505,17 +5715,18 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+@@ -5512,17 +5716,18 @@ void RADEONLeaveVT(int scrnIndex, int flags)
"RADEONLeaveVT\n");
#ifdef XF86DRI
if (RADEONPTR(pScrn)->directRenderingInited) {
@@ -5677,7 +5741,7 @@
/* Make sure 3D clients will re-upload textures to video RAM */
if (info->dri->textureSize) {
-@@ -5531,6 +5742,11 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+@@ -5538,6 +5743,11 @@ void RADEONLeaveVT(int scrnIndex, int flags)
i = list[i].next;
} while (i != 0);
}
@@ -5689,7 +5753,7 @@
}
#endif
-@@ -5551,10 +5767,18 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+@@ -5558,10 +5768,18 @@ void RADEONLeaveVT(int scrnIndex, int flags)
xf86_hide_cursors (pScrn);
@@ -5711,7 +5775,7 @@
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Ok, leaving now...\n");
-@@ -5599,7 +5823,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
+@@ -5606,7 +5824,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
#endif /* USE_XAA */
if (pScrn->vtSema) {
@@ -5721,7 +5785,7 @@
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-@@ -5634,6 +5859,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
+@@ -5641,6 +5860,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
info->DGAModes = NULL;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Unmapping memory\n");
@@ -6049,7 +6113,7 @@
+
#endif
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
-index 0f86fdd..9fb0f75 100644
+index 6c3bf92..48a1640 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -43,7 +43,11 @@
@@ -6157,7 +6221,7 @@
/* Front buffer is always set with proper swappers */
if (offset == 0)
return;
-@@ -291,42 +341,124 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index)
+@@ -291,43 +341,93 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index)
OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, 0);
OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, 0);
swapper_surfaces[index] = 0;
@@ -6236,68 +6300,56 @@
+ }
+ return FALSE;
+}
-+
-+static Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix)
-+{
-+ struct radeon_exa_pixmap_priv *driver_priv;
-+
-+ driver_priv = exaGetPixmapDriverPrivate(pPix);
-+
-+ if (!driver_priv)
-+ return FALSE;
-+ if (driver_priv->bo)
-+ return TRUE;
-+ return FALSE;
-+}
- #define RADEON_SWITCH_TO_2D() \
- do { \
+-#define RADEON_SWITCH_TO_2D() \
+-do { \
- uint32_t wait_until = 0; \
- BEGIN_ACCEL(1); \
-+ uint32_t flush = 0; \
- switch (info->accel_state->engineMode) { \
- case EXA_ENGINEMODE_UNKNOWN: \
+- switch (info->accel_state->engineMode) { \
+- case EXA_ENGINEMODE_UNKNOWN: \
- wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN; \
- case EXA_ENGINEMODE_3D: \
+- case EXA_ENGINEMODE_3D: \
- wait_until |= RADEON_WAIT_3D_IDLECLEAN; \
-+ flush = 1; \
- case EXA_ENGINEMODE_2D: \
- break; \
- } \
+- case EXA_ENGINEMODE_2D: \
+- break; \
+- } \
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \
- FINISH_ACCEL(); \
- info->accel_state->engineMode = EXA_ENGINEMODE_2D; \
-+ if (flush) { \
-+ RADEONCPFlushIndirect(pScrn, 1); \
-+ } \
-+ info->accel_state->engineMode = EXA_ENGINEMODE_2D; \
- } while (0);
-
- #define RADEON_SWITCH_TO_3D() \
- do { \
+-} while (0);
+-
+-#define RADEON_SWITCH_TO_3D() \
+-do { \
- uint32_t wait_until = 0; \
- BEGIN_ACCEL(1); \
-+ uint32_t flush = 0; \
- switch (info->accel_state->engineMode) { \
- case EXA_ENGINEMODE_UNKNOWN: \
+- switch (info->accel_state->engineMode) { \
+- case EXA_ENGINEMODE_UNKNOWN: \
- wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \
- case EXA_ENGINEMODE_2D: \
+- case EXA_ENGINEMODE_2D: \
- wait_until |= RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE; \
-+ flush = 1; \
- case EXA_ENGINEMODE_3D: \
- break; \
- } \
+- case EXA_ENGINEMODE_3D: \
+- break; \
+- } \
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \
- FINISH_ACCEL(); \
- info->accel_state->engineMode = EXA_ENGINEMODE_3D; \
-+ if (flush) { \
-+ RADEONCPFlushIndirect(pScrn, 1); \
-+ } \
-+ info->accel_state->engineMode = EXA_ENGINEMODE_3D; \
- } while (0);
+-} while (0);
++static Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix)
++{
++ struct radeon_exa_pixmap_priv *driver_priv;
++
++ driver_priv = exaGetPixmapDriverPrivate(pPix);
++
++ if (!driver_priv)
++ return FALSE;
++ if (driver_priv->bo)
++ return TRUE;
++ return FALSE;
++}
#define ENTER_DRAW(x) TRACE
-@@ -338,6 +470,7 @@ do { \
+ #define LEAVE_DRAW(x) TRACE
+@@ -338,6 +438,7 @@ do { \
#define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n))
#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
#define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val))
@@ -6305,7 +6357,7 @@
#define FINISH_ACCEL()
#ifdef RENDER
-@@ -351,6 +484,7 @@ do { \
+@@ -351,6 +452,7 @@ do { \
#undef OUT_ACCEL_REG
#undef OUT_ACCEL_REG_F
#undef FINISH_ACCEL
@@ -6313,7 +6365,7 @@
#ifdef XF86DRI
-@@ -361,6 +495,7 @@ do { \
+@@ -361,6 +463,7 @@ do { \
#define BEGIN_ACCEL(n) BEGIN_RING(2*(n))
#define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
#define FINISH_ACCEL() ADVANCE_RING()
@@ -6321,7 +6373,7 @@
#define OUT_RING_F(x) OUT_RING(F_TO_DW(x))
-@@ -378,6 +513,8 @@ do { \
+@@ -378,6 +481,8 @@ do { \
#endif /* XF86DRI */
@@ -6330,7 +6382,7 @@
/*
* Once screen->off_screen_base is set, this function
* allocates the remaining memory appropriately
-@@ -399,122 +536,126 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
+@@ -399,122 +504,126 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
if (info->accel_state->exa == NULL)
return FALSE;
@@ -6560,7 +6612,7 @@
return TRUE;
}
-@@ -527,10 +668,21 @@ extern void ExaOffscreenMarkUsed(PixmapPtr);
+@@ -527,17 +636,21 @@ extern void ExaOffscreenMarkUsed(PixmapPtr);
unsigned long long
RADEONTexOffsetStart(PixmapPtr pPix)
{
@@ -6585,6 +6637,13 @@
+ return offset;
}
#endif
+-
+-Bool RADEONSetupMemEXAKernel(ScreenPtr pScreen)
+-{
+-
+-
+-}
+-
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 62224d0..eba325e 100644
--- a/src/radeon_exa_funcs.c
@@ -7247,7 +7306,7 @@
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n");
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
-index 97199ae..5399906 100644
+index 97199ae..3dcb420 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -54,6 +54,10 @@
@@ -7325,7 +7384,7 @@
}
FINISH_ACCEL();
-@@ -523,10 +549,52 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
+@@ -523,12 +549,51 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
uint32_t dst_format, dst_offset, dst_pitch, colorpitch;
uint32_t pp_cntl, blendcntl, cblend, ablend;
int pixel_shift;
@@ -7338,6 +7397,8 @@
TRACE;
+- if (!info->accel_state->XInited3D)
+- RADEONInit3DEngine(pScrn);
+ retry:
+ if (info->new_cs) {
+
@@ -7374,11 +7435,10 @@
+ goto retry;
+ }
+ }
-+
- if (!info->accel_state->XInited3D)
- RADEONInit3DEngine(pScrn);
-@@ -540,15 +608,13 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
+ if (!RADEONGetDestFormat(pDstPicture, &dst_format))
+ return FALSE;
+@@ -540,22 +605,23 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
@@ -7396,13 +7456,23 @@
RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)dst_offset));
if (((dst_pitch >> pixel_shift) & 0x7) != 0)
RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch));
-@@ -569,11 +635,19 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
+
++
+ if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE))
+ return FALSE;
+
++ RADEON_SWITCH_TO_3D();
++
+ if (!FUNC_NAME(R100TextureSetup)(pSrcPicture, pSrc, 0))
+ return FALSE;
+ pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE;
+@@ -568,12 +634,18 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
+ info->accel_state->is_transform[1] = FALSE;
}
- RADEON_SWITCH_TO_3D();
+- RADEON_SWITCH_TO_3D();
-
- BEGIN_ACCEL(8);
-+
+ qwords = info->new_cs ? 9 : 8;
+ BEGIN_ACCEL(qwords);
OUT_ACCEL_REG(RADEON_PP_CNTL, pp_cntl);
@@ -7419,7 +7489,7 @@
OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch);
/* IN operator: Multiply src by mask components or mask alpha.
-@@ -669,13 +743,17 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+@@ -669,13 +741,17 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
Bool repeat = pPict->repeat &&
!(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y));
int i;
@@ -7440,7 +7510,7 @@
if ((txpitch & 0x1f) != 0)
RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
-@@ -718,7 +796,8 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+@@ -718,7 +794,8 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
if (repeat)
txfilter |= R200_CLAMP_S_WRAP | R200_CLAMP_T_WRAP;
@@ -7450,7 +7520,7 @@
if (unit == 0) {
OUT_ACCEL_REG(R200_PP_TXFILTER_0, txfilter);
OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat);
-@@ -726,7 +805,15 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+@@ -726,7 +803,15 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
OUT_ACCEL_REG(R200_PP_TXSIZE_0, (pPix->drawable.width - 1) |
((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT));
OUT_ACCEL_REG(R200_PP_TXPITCH_0, txpitch - 32);
@@ -7467,7 +7537,7 @@
} else {
OUT_ACCEL_REG(R200_PP_TXFILTER_1, txfilter);
OUT_ACCEL_REG(R200_PP_TXFORMAT_1, txformat);
-@@ -734,7 +821,17 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+@@ -734,7 +819,17 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
OUT_ACCEL_REG(R200_PP_TXSIZE_1, (pPix->drawable.width - 1) |
((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT));
OUT_ACCEL_REG(R200_PP_TXPITCH_1, txpitch - 32);
@@ -7486,7 +7556,7 @@
}
FINISH_ACCEL();
-@@ -823,10 +920,53 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -823,12 +918,52 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
uint32_t dst_format, dst_offset, dst_pitch;
uint32_t pp_cntl, blendcntl, cblend, ablend, colorpitch;
int pixel_shift;
@@ -7499,6 +7569,8 @@
TRACE;
+- if (!info->accel_state->XInited3D)
+- RADEONInit3DEngine(pScrn);
+ retry:
+ if (info->new_cs) {
+
@@ -7536,11 +7608,10 @@
+ }
+ }
+
-+
- if (!info->accel_state->XInited3D)
- RADEONInit3DEngine(pScrn);
-@@ -840,13 +980,13 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
+ if (!RADEONGetDestFormat(pDstPicture, &dst_format))
+ return FALSE;
+@@ -840,13 +975,13 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
@@ -7556,10 +7627,21 @@
RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)dst_offset));
if (((dst_pitch >> pixel_shift) & 0x7) != 0)
RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch));
-@@ -868,11 +1008,22 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -854,6 +989,8 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
+ if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE))
+ return FALSE;
- RADEON_SWITCH_TO_3D();
++ RADEON_SWITCH_TO_3D();
++
+ if (!FUNC_NAME(R200TextureSetup)(pSrcPicture, pSrc, 0))
+ return FALSE;
+ pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE;
+@@ -866,13 +1003,22 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
+ info->accel_state->is_transform[1] = FALSE;
+ }
+- RADEON_SWITCH_TO_3D();
+-
- BEGIN_ACCEL(11);
+ qwords = info->new_cs ? 12 : 11;
+ BEGIN_ACCEL(qwords);
@@ -7581,7 +7663,7 @@
OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY);
if (pMask)
-@@ -941,6 +1092,10 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict,
+@@ -941,6 +1087,10 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict,
int unit,
Bool is_r500)
{
@@ -7592,7 +7674,7 @@
int w = pPict->pDrawable->width;
int h = pPict->pDrawable->height;
int i;
-@@ -966,8 +1121,17 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict,
+@@ -966,8 +1116,17 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict,
RADEON_FALLBACK(("Unsupported picture format 0x%x\n",
(int)pPict->format));
@@ -7611,7 +7693,7 @@
if (pPict->filter != PictFilterNearest &&
pPict->filter != PictFilterBilinear)
-@@ -999,15 +1163,19 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+@@ -999,15 +1158,19 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
int w = pPict->pDrawable->width;
int h = pPict->pDrawable->height;
int i, pixel_shift;
@@ -7634,7 +7716,7 @@
if ((txpitch & 0x1f) != 0)
RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
-@@ -1068,13 +1236,26 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+@@ -1068,13 +1231,26 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
}
@@ -7663,7 +7745,7 @@
if (!pPict->repeat)
OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0);
FINISH_ACCEL();
-@@ -1173,6 +1354,7 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
+@@ -1173,6 +1349,7 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
return TRUE;
}
@@ -7671,7 +7753,7 @@
#endif /* ONLY_ONCE */
static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
-@@ -1184,10 +1366,51 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -1184,12 +1361,50 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
uint32_t txenable, colorpitch;
uint32_t blendcntl;
int pixel_shift;
@@ -7684,6 +7766,8 @@
-
TRACE;
+- if (!info->accel_state->XInited3D)
+- RADEONInit3DEngine(pScrn);
+ retry:
+ if (info->new_cs) {
+
@@ -7720,11 +7804,10 @@
+ goto retry;
+ }
+ }
-+
- if (!info->accel_state->XInited3D)
- RADEONInit3DEngine(pScrn);
-@@ -1201,7 +1424,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+ if (!R300GetDestFormat(pDstPicture, &dst_format))
+ return FALSE;
+@@ -1201,7 +1416,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
@@ -7733,7 +7816,7 @@
dst_pitch = exaGetPixmapPitch(pDst);
colorpitch = dst_pitch >> pixel_shift;
-@@ -1210,7 +1433,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -1210,7 +1425,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
colorpitch |= dst_format;
@@ -7742,7 +7825,7 @@
RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)dst_offset));
if (((dst_pitch >> pixel_shift) & 0x7) != 0)
RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch));
-@@ -1218,6 +1441,11 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -1218,6 +1433,11 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE))
return FALSE;
@@ -7754,7 +7837,7 @@
if (!FUNC_NAME(R300TextureSetup)(pSrcPicture, pSrc, 0))
return FALSE;
txenable = R300_TEX_0_ENABLE;
-@@ -1230,7 +1458,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -1230,7 +1450,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
info->accel_state->is_transform[1] = FALSE;
}
@@ -7762,7 +7845,7 @@
/* setup the VAP */
if (info->accel_state->has_tcl) {
-@@ -1829,9 +2056,18 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -1829,9 +2048,18 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
FINISH_ACCEL();
}
@@ -7783,7 +7866,7 @@
OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
-@@ -1839,12 +2075,22 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -1839,12 +2067,22 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
FINISH_ACCEL();
@@ -7809,7 +7892,7 @@
#ifdef ACCEL_CP
#define VTX_OUT_MASK(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \
-@@ -1953,11 +2199,6 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
+@@ -1953,11 +2191,6 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
else
vtx_count = VTX_COUNT;
@@ -7821,7 +7904,7 @@
#ifdef ACCEL_CP
if (info->ChipFamily < CHIP_FAMILY_R200) {
-@@ -2037,9 +2278,10 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
+@@ -2037,9 +2270,10 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0]);
}
@@ -7833,7 +7916,7 @@
#ifdef ACCEL_CP
ADVANCE_RING();
-@@ -2121,14 +2363,24 @@ static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst)
+@@ -2121,14 +2355,24 @@ static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst)
ENTER_DRAW(0);
if (IS_R300_3D || IS_R500_3D) {
Index: xorg-x11-drv-ati.spec
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/F-10/xorg-x11-drv-ati.spec,v
retrieving revision 1.162
retrieving revision 1.163
diff -u -r1.162 -r1.163
--- xorg-x11-drv-ati.spec 2 Dec 2008 09:13:33 -0000 1.162
+++ xorg-x11-drv-ati.spec 9 Dec 2008 03:34:45 -0000 1.163
@@ -5,7 +5,7 @@
Summary: Xorg X11 ati video driver
Name: xorg-x11-drv-ati
Version: 6.9.0
-Release: 61%{?dist}
+Release: 62%{?dist}
URL: http://www.x.org
License: MIT
Group: User Interface/X Hardware Support
@@ -86,6 +86,9 @@
%{_mandir}/man4/radeon.4*
%changelog
+* Tue Dec 09 2008 Dave Airlie <airlied at redhat.com> 6.9.0-62
+- radeon-modeset.patch: fix resume with no DRI + another 2D/3D issue
+
* Tue Dec 02 2008 Dave Airlie <airlied at redhat.com> 6.9.0-61
- radeon-modeset.patch: fix some DFS issues on r5xx - better fix for rs4xx
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