rpms/xorg-x11-drv-sis/devel sis-pciaccess.patch, NONE, 1.1 .cvsignore, 1.8, 1.9 sources, 1.8, 1.9 xorg-x11-drv-sis.spec, 1.22, 1.23
Dave Airlie (airlied)
fedora-extras-commits at redhat.com
Wed Jan 16 03:45:31 UTC 2008
Author: airlied
Update of /cvs/pkgs/rpms/xorg-x11-drv-sis/devel
In directory cvs-int.fedora.redhat.com:/tmp/cvs-serv28356
Modified Files:
.cvsignore sources xorg-x11-drv-sis.spec
Added Files:
sis-pciaccess.patch
Log Message:
* Wed Jan 16 2008 Dave Airlie <airlied at redhat.com> - 0.9.4-1
- new upstream version
- sis-pciaccess.patch - add initial pciaccess port
sis-pciaccess.patch:
--- NEW FILE sis-pciaccess.patch ---
diff --git a/configure.ac b/configure.ac
index f4cc38c..0d99151 100644
--- a/configure.ac
+++ b/configure.ac
@@ -101,6 +101,19 @@ fi
# technically this should be a configure flag. meh.
AC_DEFINE(XF86EXA, 1, [Build support for Exa])
+SAVE_CPPFLAGS="$CPPFLAGS"
+CPPFLAGS="$CPPFLAGS $XORG_CFLAGS"
+AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
+ [XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
+ [#include "xorg-server.h"])
+CPPFLAGS="$SAVE_CPPFLAGS"
+
+if test "x$XSERVER_LIBPCIACCESS" = xyes; then
+ PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.8.0])
+ XORG_CFLAGS="$XORG_CFLAGS $PCIACCESS_CFLAGS"
+fi
+AM_CONDITIONAL(XSERVER_LIBPCIACCESS, test "x$XSERVER_LIBPCIACCESS" = xyes)
+
AC_SUBST([DRI_CFLAGS])
AC_SUBST([XORG_CFLAGS])
AC_SUBST([moduledir])
diff --git a/src/init.c b/src/init.c
index 9f6bea0..f2b48a0 100644
--- a/src/init.c
+++ b/src/init.c
@@ -2505,7 +2505,7 @@ SiS_SetCRT1FIFO_630(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
#ifdef SIS_LINUX_KERNEL
templ = sisfb_read_nbridge_pci_dword(SiS_Pr, 0x50);
#else
- templ = pciReadLong(0x00000000, 0x50);
+ templ = sis_pci_read_host_bridge_u32(0x50);
#endif
if(SiS_Pr->ChipType == SIS_730) {
@@ -2530,8 +2530,8 @@ SiS_SetCRT1FIFO_630(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
sisfb_write_nbridge_pci_dword(SiS_Pr, 0x50, templ);
templ = sisfb_read_nbridge_pci_dword(SiS_Pr, 0xA0);
#else
- pciWriteLong(0x00000000, 0x50, templ);
- templ = pciReadLong(0x00000000, 0xA0);
+ sis_pci_write_host_bridge_u32(0x50, templ);
+ templ = sis_pci_read_host_bridge_u32(0xA0);
#endif
/* GUI grant timer (PCI config 0xA3) */
@@ -2551,7 +2551,7 @@ SiS_SetCRT1FIFO_630(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
#ifdef SIS_LINUX_KERNEL
sisfb_write_nbridge_pci_dword(SiS_Pr, 0xA0, templ);
#else
- pciWriteLong(0x00000000, 0xA0, templ);
+ sis_pci_write_host_bridge_u32(0xA0, templ);
#endif
}
#endif /* SIS300 */
@@ -3169,7 +3169,7 @@ SiS_Handle760(struct SiS_Private *SiS_Pr)
#ifdef SIS_LINUX_KERNEL
somebase = sisfb_read_mio_pci_word(SiS_Pr, 0x74);
#else
- somebase = pciReadWord(0x00001000, 0x74);
+ somebase = sis_pci_read_device_u32(2, 0x74);
#endif
somebase &= 0xffff;
@@ -3190,8 +3190,8 @@ SiS_Handle760(struct SiS_Private *SiS_Pr)
sisfb_write_nbridge_pci_byte(SiS_Pr, 0x7e, temp1);
sisfb_write_nbridge_pci_byte(SiS_Pr, 0x8d, temp2);
#else
- pciWriteByte(0x00000000, 0x7e, temp1);
- pciWriteByte(0x00000000, 0x8d, temp2);
+ sis_pci_write_host_bridge_u8(0x7e, temp1);
+ sis_pci_write_host_bridge_u8(0x8d, temp2);
#endif
SiS_SetRegByte((somebase + 0x85), temp3);
diff --git a/src/init301.c b/src/init301.c
index 161d8de..2eded9f 100644
--- a/src/init301.c
+++ b/src/init301.c
@@ -932,7 +932,7 @@ SiS_SetChrontelGPIO(struct SiS_Private *SiS_Pr, unsigned short myvbinfo)
#ifdef SIS_LINUX_KERNEL
acpibase = sisfb_read_lpc_pci_dword(SiS_Pr, 0x74);
#else
- acpibase = pciReadLong(0x00000800, 0x74);
+ acpibase = sis_pci_read_device_u32(1, 0x74);
#endif
acpibase &= 0xFFFF;
if(!acpibase) return;
@@ -5220,8 +5220,8 @@ SiS_SetCRT2FIFO_300(struct SiS_Private *SiS_Pr,unsigned short ModeNo)
pci50 = sisfb_read_nbridge_pci_dword(SiS_Pr, 0x50);
pciA0 = sisfb_read_nbridge_pci_dword(SiS_Pr, 0xa0);
#else
- pci50 = pciReadLong(0x00000000, 0x50);
- pciA0 = pciReadLong(0x00000000, 0xA0);
+ pci50 = sis_pci_read_host_bridge_u32(0x50);
+ pciA0 = sis_pci_read_host_bridge_u32(0xA0);
#endif
if(SiS_Pr->ChipType == SIS_730) {
diff --git a/src/sis.h b/src/sis.h
index f17b5cb..0da6e0f 100644
--- a/src/sis.h
+++ b/src/sis.h
@@ -39,6 +39,11 @@
#include <string.h>
#include <math.h>
#include <setjmp.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <sys/ioctl.h>
+
+#include <sispcirename.h>
#define SISDRIVERVERSIONYEAR 5
#define SISDRIVERVERSIONMONTH 9
@@ -850,15 +855,15 @@ typedef struct {
ULong masterFbSize;
ULong slaveFbAddress;
ULong slaveFbSize;
- UChar *FbBase; /* VRAM linear address */
+ void *FbBase; /* VRAM linear address */
UChar *RealFbBase; /* Real VRAM linear address (for DHM, SiS76x UMA skipping) */
- UChar *IOBase; /* MMIO linear address */
+ void *IOBase; /* MMIO linear address */
UShort MapCountIOBase; /* map/unmap queue counter */
UShort MapCountFbBase; /* map/unmap queue counter */
Bool forceUnmapIOBase; /* ignore counter and unmap */
Bool forceUnmapFbBase; /* ignore counter and unmap */
#ifdef __alpha__
- UChar *IOBaseDense; /* MMIO for Alpha platform */
+ void *IOBaseDense; /* MMIO for Alpha platform */
UShort MapCountIOBaseDense;
Bool forceUnmapIOBaseDense; /* ignore counter and unmap */
#endif
@@ -921,7 +926,7 @@ typedef struct {
unsigned int CPUFlags;
#ifdef SIS_NEED_MAP_IOP
CARD32 IOPAddress; /* I/O port physical address */
- UChar *IOPBase; /* I/O port linear address */
+ void *IOPBase; /* I/O port linear address */
UShort MapCountIOPBase; /* map/unmap queue counter */
Bool forceUnmapIOPBase; /* ignore counter and unmap */
#endif
@@ -962,13 +967,13 @@ typedef struct {
int DSTN; /* For 550 FSTN/DSTN; set by option, no detection */
ULong FbAddress; /* VRAM physical address (in DHM: for each Fb!) */
ULong realFbAddress; /* For DHM/PCI mem mapping: store global FBAddress */
- UChar *FbBase; /* VRAM virtual linear address */
- UChar *RealFbBase; /* Real VRAM virtual linear address (for DHM and SiS76x UMA skipping) */
+ void *FbBase; /* VRAM virtual linear address */
+ void *RealFbBase; /* Real VRAM virtual linear address (for DHM and SiS76x UMA skipping) */
CARD32 IOAddress; /* MMIO physical address */
- UChar *IOBase; /* MMIO linear address */
+ void *IOBase; /* MMIO linear address */
IOADDRESS IODBase; /* Base of PIO memory area */
#ifdef __alpha__
- UChar *IOBaseDense; /* MMIO for Alpha platform */
+ void *IOBaseDense; /* MMIO for Alpha platform */
#endif
SISIOADDRESS RelIO; /* Relocated IO Ports baseaddress */
UChar *BIOS;
@@ -1376,7 +1381,7 @@ typedef struct {
Bool SCLogQuiet;
#ifdef SIS_NEED_MAP_IOP
CARD32 IOPAddress; /* I/O port physical address */
- UChar *IOPBase; /* I/O port linear address */
+ void *IOPBase; /* I/O port linear address */
#endif
#ifdef SISMERGED
Bool MergedFB, MergedFBAuto;
@@ -1570,6 +1575,12 @@ extern int SiS_GetTVyscale(ScrnInfoPtr pScrn);
extern int SiS_GetSISCRT1SaturationGain(ScrnInfoPtr pScrn);
extern void SiS_SetSISCRT1SaturationGain(ScrnInfoPtr pScrn, int val);
+extern unsigned int sis_pci_read_device_u32(int device, int offset);
+extern unsigned char sis_pci_read_device_u8(int device, int offset);
+extern unsigned int sis_pci_read_host_bridge_u32(int offset);
+extern unsigned char sis_pci_read_host_bridge_u8(int offset);
+extern void sis_pci_write_host_bridge_u8(int offset, unsigned char value);
+extern void sis_pci_write_host_bridge_u32(int offset, unsigned int value);
#endif /* _SIS_H_ */
diff --git a/src/sis_dac.c b/src/sis_dac.c
index 70cce7c..eff0900 100644
--- a/src/sis_dac.c
+++ b/src/sis_dac.c
@@ -545,8 +545,8 @@ SiS300Save(ScrnInfoPtr pScrn, SISRegPtr sisReg)
/* Save FQBQ and GUI timer settings */
if(pSiS->Chipset == PCI_CHIP_SIS630) {
- sisReg->sisRegsPCI50 = pciReadLong(0x00000000, 0x50);
- sisReg->sisRegsPCIA0 = pciReadLong(0x00000000, 0xA0);
+ sisReg->sisRegsPCI50 = sis_pci_read_host_bridge_u32(0x50);
+ sisReg->sisRegsPCIA0 = sis_pci_read_host_bridge_u32(0xA0);
#ifdef TWDEBUG
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"PCI Config 50 = %lx\n", sisReg->sisRegsPCI50);
@@ -687,9 +687,9 @@ SiS300Restore(ScrnInfoPtr pScrn, SISRegPtr sisReg)
/* Restore FQBQ and GUI timer settings */
if(pSiS->Chipset == PCI_CHIP_SIS630) {
- temp1 = pciReadLong(0x00000000, 0x50);
- temp2 = pciReadLong(0x00000000, 0xA0);
- if(pciReadLong(0x00000000, 0x00) == 0x06301039) {
+ temp1 = sis_pci_read_host_bridge_u32(0x50);
+ temp2 = sis_pci_read_host_bridge_u32(0xA0);
+ if(sis_pci_read_host_bridge_u32(0x00) == 0x06301039) {
temp1 &= 0xf0ffffff;
temp1 |= (sisReg->sisRegsPCI50 & ~0xf0ffffff);
temp2 &= 0xf0ffffff;
@@ -700,8 +700,8 @@ SiS300Restore(ScrnInfoPtr pScrn, SISRegPtr sisReg)
temp2 &= 0x00ffffff;
temp2 |= (sisReg->sisRegsPCIA0 & ~0x00ffffff);
}
- pciWriteLong(0x00000000, 0x50, temp1);
- pciWriteLong(0x00000000, 0xA0, temp2);
+ sis_pci_write_host_bridge_u32(0x50, temp1);
+ sis_pci_write_host_bridge_u32(0xA0, temp2);
}
/* Restore panel link/video bridge registers */
diff --git a/src/sis_dri.c b/src/sis_dri.c
index 4ce678f..ec8a808 100644
--- a/src/sis_dri.c
+++ b/src/sis_dri.c
@@ -59,8 +59,10 @@ extern Bool drmSiSAgpInit(int driSubFD, int offset, int size);
#ifdef XORG_VERSION_CURRENT
#define SISHAVECREATEBUSID
#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(6,7,99,1,0)
+#ifndef XSERVER_LIBPCIACCESS
extern char *DRICreatePCIBusID(pciVideoPtr PciInfo);
#endif
+#endif
#else
# if XF86_VERSION_CURRENT < XF86_VERSION_NUMERIC(4,4,99,9,0)
# undef SISHAVECREATEBUSID
@@ -861,7 +863,7 @@ SISDRISwapContext(ScreenPtr pScreen, DRISyncType syncType,
break;
#endif
case SIS_300_VGA:
- *(pSiS->IOBase + 0x8B50) = 0xff;
+ *((unsigned char *)pSiS->IOBase + 0x8B50) = 0xff;
*(CARD32 *)(pSiS->IOBase + 0x8B60) = 0xffffffff;
break;
}
diff --git a/src/sis_driver.c b/src/sis_driver.c
index 3cc3be8..0b3225a 100644
--- a/src/sis_driver.c
+++ b/src/sis_driver.c
@@ -555,7 +555,7 @@ SiS_SiSFB_Lock(ScrnInfoPtr pScrn, Bool lock)
if(!pSiS->sisfbfound) return;
if(!pSiS->sisfb_havelock) return;
- if((fd = open(pSiS->sisfbdevname, 'r')) != -1) {
+ if((fd = open(pSiS->sisfbdevname, O_RDONLY)) != -1) {
parm = lock ? 1 : 0;
ioctl(fd, SISFB_SET_LOCK, &parm);
close(fd);
@@ -614,6 +614,7 @@ SISProbe(DriverPtr drv, int flags)
* All of the cards this driver supports are PCI, so the "probing" just
* amounts to checking the PCI data that the server has already collected.
*/
+#ifndef XSERVER_LIBPCIACCESS
if(xf86GetPciVideoInfo() == NULL) {
/*
* We won't let anything in the config file override finding no
@@ -621,6 +622,7 @@ SISProbe(DriverPtr drv, int flags)
*/
return FALSE;
}
+#endif
numUsedSiS = xf86MatchPciInstances(SIS_NAME, PCI_VENDOR_SIS,
SISChipsets, SISPciChipsets, devSections,
@@ -2983,7 +2985,7 @@ SiS_MapVGAMem(ScrnInfoPtr pScrn)
/* If card is secondary or if a0000-address decoding
* is disabled, set Phys to beginning of our video RAM.
*/
- pSiS->VGAMapPhys = pSiS->PciInfo->memBase[0];
+ pSiS->VGAMapPhys = PCI_REGION_BASE(pSiS->PciInfo, 0, REGION_MEM);
}
if(!SiSVGAMapMem(pScrn)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
@@ -3032,7 +3034,7 @@ SiS_CheckKernelFB(ScrnInfoPtr pScrn)
sprintf(name, "/dev/fb/%1d", (i - 8));
}
- if((fd = open(name, 'r')) != -1) {
+ if((fd = open(name, O_RDONLY)) != -1) {
Bool gotit = FALSE;
@@ -3380,10 +3382,13 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
/* Find the PCI info for this screen */
pSiS->PciInfo = xf86GetPciInfoForEntity(pSiS->pEnt->index);
- pSiS->PciBus = ((pciConfigPtr)pSiS->PciInfo->thisCard)->busnum; /*SIS_PCI_BUS(pSiS->PciInfo);*/
- pSiS->PciDevice = ((pciConfigPtr)pSiS->PciInfo->thisCard)->devnum; /*SIS_PCI_DEVICE(pSiS->PciInfo);*/
- pSiS->PciFunc = ((pciConfigPtr)pSiS->PciInfo->thisCard)->funcnum; /*SIS_PCI_FUNC(pSiS->PciInfo);*/
- pSiS->PciTag = ((pciConfigPtr)pSiS->PciInfo->thisCard)->tag; /*SIS_PCI_TAG(pSiS->PciInfo);*/
+ pSiS->PciBus = PCI_CFG_BUS(pSiS->PciInfo); /*SIS_PCI_BUS(pSiS->PciInfo);*/
+ pSiS->PciDevice = PCI_CFG_DEV(pSiS->PciInfo); /*SIS_PCI_DEVICE(pSiS->PciInfo);*/
+ pSiS->PciFunc = PCI_CFG_FUNC(pSiS->PciInfo); /*SIS_PCI_FUNC(pSiS->PciInfo);*/
+
+ pSiS->PciTag = pciTag(PCI_DEV_BUS(pSiS->PciInfo),
+ PCI_DEV_DEV(pSiS->PciInfo),
+ PCI_DEV_FUNC(pSiS->PciInfo));
#ifdef SIS_NEED_MAP_IOP
/********************************************/
@@ -3433,7 +3438,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
{
SymTabRec *myChipsets = SISChipsets;
- if(pSiS->PciInfo->vendor == PCI_VENDOR_XGI) {
+ if(PCI_DEV_VENDOR_ID(pSiS->PciInfo) == PCI_VENDOR_XGI) {
myChipsets = XGIChipsets;
}
@@ -3451,7 +3456,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
pSiS->Chipset);
} else {
- pSiS->Chipset = pSiS->PciInfo->chipType;
+ pSiS->Chipset = PCI_DEV_DEVICE_ID(pSiS->PciInfo);
pScrn->chipset = (char *)xf86TokenToString(myChipsets, pSiS->Chipset);
}
@@ -3464,7 +3469,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
pSiS->ChipRev);
} else {
- pSiS->ChipRev = pSiS->PciInfo->chipRev;
+ pSiS->ChipRev = PCI_DEV_REVISION(pSiS->PciInfo);
}
@@ -3648,7 +3653,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
* by the BIOS. So we can pretty much rely on that these
* are enabled.
*/
- pSiS->RelIO = (SISIOADDRESS)(pSiS->PciInfo->ioBase[2] + pSiS->IODBase);
+ pSiS->RelIO = (SISIOADDRESS)(PCI_REGION_BASE(pSiS->PciInfo, 2, REGION_IO) + pSiS->IODBase);
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Relocated I/O registers at 0x%lX\n",
(ULong)pSiS->RelIO);
@@ -3769,7 +3774,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
break;
case PCI_CHIP_SIS630: /* 630 + 730 */
pSiS->ChipType = SIS_630;
- if(pciReadLong(0x00000000, 0x00) == 0x07301039) {
+ if(sis_pci_read_host_bridge_u32(0x00) == 0x07301039) {
pSiS->ChipType = SIS_730;
}
pSiS->SiS_SD_Flags |= SiS_SD_IS300SERIES;
@@ -3808,7 +3813,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
break;
case PCI_CHIP_SIS650: /* 650 + 740 */
pSiS->ChipType = SIS_650;
- if(pciReadLong(0x00000000, 0x00) == 0x07401039) {
+ if(sis_pci_read_host_bridge_u32(0x00) == 0x07401039) {
pSiS->ChipType = SIS_740;
}
pSiS->ChipFlags |= (SiSCF_Integrated | SiSCF_Real256ECore | SiSCF_MMIOPalette);
@@ -3826,7 +3831,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
break;
case PCI_CHIP_SIS660: /* 660, 661, 741, 760, 761, 670(?) */
{
- ULong hpciid = pciReadLong(0x00000000, 0x00);
+ ULong hpciid = sis_pci_read_host_bridge_u32(0x00);
switch(hpciid) {
case 0x06601039:
pSiS->ChipType = SIS_660;
@@ -4067,7 +4072,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
case PCI_CHIP_SIS6326:
pSiS->oldChipset = OC_SIS6326; break;
case PCI_CHIP_SIS530:
- if(pciReadLong(0x00000000, 0x00) == 0x06201039) {
+ if(sis_pci_read_host_bridge_u32(0x00) == 0x06201039) {
pSiS->oldChipset = OC_SIS620;
} else {
if((pSiS->ChipRev & 0x0f) < 0x0a)
@@ -4214,7 +4219,6 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Could not allocate memory for video BIOS image\n");
} else {
- ULong segstart;
UShort mypciid = pSiS->Chipset;
UShort mypcivendor = (pSiS->ChipFlags & SiSCF_IsXGI) ? PCI_VENDOR_XGI : PCI_VENDOR_SIS;
Bool found = FALSE, readpci = FALSE;
@@ -4237,7 +4241,15 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
biossize = 0x8000;
break;
}
-
+#if XSERVER_LIBPCIACCESS
+ if(readpci) {
+ pSiS->PciInfo->rom_size = biossize;
+ pci_device_read_rom(pSiS->PciInfo, pSiS->BIOS);
+ if(SISCheckBIOS(pSiS, mypciid, mypcivendor, biossize)) {
+ found = TRUE;
+ }
+ }
+#else
if(readpci) {
xf86ReadPciBIOS(0, pSiS->PciTag, 0, pSiS->BIOS, biossize);
if(SISCheckBIOS(pSiS, mypciid, mypcivendor, biossize)) {
@@ -4246,6 +4258,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
}
if(!found) {
+ ULong segstart;
for(segstart = BIOS_BASE; segstart < 0x000f0000; segstart += 0x00001000) {
#if XF86_VERSION_CURRENT < XF86_VERSION_NUMERIC(4,2,99,0,0)
@@ -4260,7 +4273,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
break;
}
}
-
+#endif
if(found) {
UShort romptr = pSiS->BIOS[0x16] | (pSiS->BIOS[0x17] << 8);
pSiS->SiS_Pr->VirtualRomBase = pSiS->BIOS;
@@ -4522,7 +4535,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
pSiS->FbAddress = pSiS->pEnt->device->MemBase;
from = X_CONFIG;
} else {
- pSiS->FbAddress = pSiS->PciInfo->memBase[0] & 0xFFFFFFF0;
+ pSiS->FbAddress = PCI_REGION_BASE(pSiS->PciInfo, 0, REGION_MEM) & 0xFFFFFFF0;
from = X_PROBED;
}
@@ -4546,7 +4559,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
pSiS->IOAddress = pSiS->pEnt->device->IOBase;
from = X_CONFIG;
} else {
- pSiS->IOAddress = pSiS->PciInfo->memBase[1] & 0xFFFFFFF0;
+ pSiS->IOAddress = PCI_REGION_BASE(pSiS->PciInfo, 1, REGION_MEM) & 0xFFFFFFF0;
from = X_PROBED;
}
xf86DrvMsg(pScrn->scrnIndex, from, "MMIO registers at 0x%lX (size %ldK)\n",
@@ -5064,15 +5077,15 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
if(pSiS->Chipset == PCI_CHIP_SIS630) {
int i = 0;
do {
- if(mychswtable[i].subsysVendor == pSiS->PciInfo->subsysVendor &&
- mychswtable[i].subsysCard == pSiS->PciInfo->subsysCard) {
+ if(mychswtable[i].subsysVendor == PCI_SUB_VENDOR_ID(pSiS->PciInfo) &&
+ mychswtable[i].subsysCard == PCI_SUB_DEVICE_ID(pSiS->PciInfo)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"PCI subsystem ID found in list for Chrontel/GPIO setup:\n");
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"\tVendor/Card: %s %s (ID %04x)\n",
mychswtable[i].vendorName,
mychswtable[i].cardName,
- pSiS->PciInfo->subsysCard);
+ PCI_SUB_DEVICE_ID(pSiS->PciInfo));
pSiS->SiS_Pr->SiS_ChSW = TRUE;
break;
}
@@ -5105,8 +5118,8 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
((!SiS_customttable[i].bioschksum) ||
(pSiS->SiS_Pr->UseROM &&
(SiS_customttable[i].bioschksum == chksum))) &&
- (SiS_customttable[i].pcisubsysvendor == pSiS->PciInfo->subsysVendor) &&
- (SiS_customttable[i].pcisubsyscard == pSiS->PciInfo->subsysCard) ) {
+ (SiS_customttable[i].pcisubsysvendor == PCI_SUB_VENDOR_ID(pSiS->PciInfo)) &&
+ (SiS_customttable[i].pcisubsyscard == PCI_SUB_DEVICE_ID(pSiS->PciInfo)) ) {
footprint = TRUE;
for(j=0; j<5; j++) {
if(SiS_customttable[i].biosFootprintAddr[j]) {
@@ -5834,14 +5847,14 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
if(pSiS->SiS_Pr->PDC == -1) {
int i=0;
do {
- if(mypdctable[i].subsysVendor == pSiS->PciInfo->subsysVendor &&
- mypdctable[i].subsysCard == pSiS->PciInfo->subsysCard) {
+ if(mypdctable[i].subsysVendor == PCI_SUB_VENDOR_ID(pSiS->PciInfo) &&
+ mypdctable[i].subsysCard == PCI_SUB_DEVICE_ID(pSiS->PciInfo)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"PCI card/vendor identified for non-default PanelDelayCompensation\n");
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Vendor: %s, card: %s (ID %04x), PanelDelayCompensation: 0x%02x\n",
mypdctable[i].vendorName, mypdctable[i].cardName,
- pSiS->PciInfo->subsysCard, mypdctable[i].pdc);
+ PCI_SUB_DEVICE_ID(pSiS->PciInfo), mypdctable[i].pdc);
if(pSiS->PDC == -1) {
pSiS->PDC = mypdctable[i].pdc;
} else {
@@ -7144,15 +7157,48 @@ SISMapIOPMem(ScrnInfoPtr pScrn)
pSiSEnt->MapCountIOPBase++;
if(!(pSiSEnt->IOPBase)) {
/* Only map if not mapped previously */
+#ifndef XSERVER_LIBPCIACCESS
pSiSEnt->IOPBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_MMIO,
pSiS->PciTag, pSiS->IOPAddress, 128);
+#else
+ {
+ void **result = (void **)&pSiSEnt->IOPBase;
+ int err = pci_device_map_range(pSiS->PciInfo,
+ pSiS->IOPAddress,
+ 128,
+ PCI_DEV_MAP_FLAG_WRITABLE,
+ result);
+
+ if (err) {
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
+ "Unable to map IO aperture. %s (%d)\n",
+ strerror (err), err);
+ }
+ }
+#endif
}
pSiS->IOPBase = pSiSEnt->IOPBase;
} else
#endif
- pSiS->IOPBase = xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
- pSiS->PciTag, pSiS->IOPAddress, 128);
-
+#ifndef XSERVER_LIBPCIACCESS
+ pSiS->IOPBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_MMIO,
+ pSiS->PciTag, pSiS->IOPAddress, 128);
+#else
+ {
+ void **result = (void **)&pSiS->IOPBase;
+ int err = pci_device_map_range(pSiS->PciInfo,
+ pSiS->IOPAddress,
+ 128,
+ PCI_DEV_MAP_FLAG_WRITABLE,
+ result);
+
+ if (err) {
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
+ "Unable to map IO aperture. %s (%d)\n",
+ strerror (err), err);
+ }
+ }
+#endif
if(pSiS->IOPBase == NULL) {
SISErrorLog(pScrn, "Could not map I/O port area\n");
return FALSE;
@@ -7222,14 +7268,46 @@ SISMapMem(ScrnInfoPtr pScrn)
pSiSEnt->MapCountIOBase++;
if(!(pSiSEnt->IOBase)) {
/* Only map if not mapped previously */
+#ifndef XSERVER_LIBPCIACCESS
pSiSEnt->IOBase = xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
pSiS->PciTag, pSiS->IOAddress, (pSiS->mmioSize * 1024));
+#else
+ void **result = (void **)&pSiSEnt->IOBase;
+ int err = pci_device_map_range(pSiS->PciInfo,
+ pSiS->IOAddress,
+ (pSiS->mmioSize * 1024),
+ PCI_DEV_MAP_FLAG_WRITABLE,
+ result);
+
+ if (err) {
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
+ "Unable to map IO aperture. %s (%d)\n",
+ strerror (err), err);
+ }
+#endif
}
pSiS->IOBase = pSiSEnt->IOBase;
} else
#endif
+#ifndef XSERVER_LIBPCIACCESS
pSiS->IOBase = xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
pSiS->PciTag, pSiS->IOAddress, (pSiS->mmioSize * 1024));
+#else
+ {
+ void **result = (void **)&pSiSEnt->IOBase;
+ int err = pci_device_map_range(pSiS->PciInfo,
+ pSiS->IOAddress,
+ (pSiS->mmioSize * 1024),
+ PCI_DEV_MAP_FLAG_WRITABLE,
+ result);
+
+ if (err) {
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
+ "Unable to map IO aperture. %s (%d)\n",
+ strerror (err), err);
+ }
+ }
+#endif
if(pSiS->IOBase == NULL) {
SISErrorLog(pScrn, "Could not map MMIO area\n");
@@ -7246,14 +7324,42 @@ SISMapMem(ScrnInfoPtr pScrn)
pSiSEnt->MapCountIOBaseDense++;
if(!(pSiSEnt->IOBaseDense)) {
/* Only map if not mapped previously */
+#ifndef XSERVER_LIBPCIACCESS
pSiSEnt->IOBaseDense = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_MMIO,
pSiS->PciTag, pSiS->IOAddress, (pSiS->mmioSize * 1024));
+#else
+ void **result = (void **)&pSiSEnt->IOBaseDense;
+ int err = pci_device_map_range(pSiS->PciInfo,
+ pSiS->IOAddress,
+ (pSiS->mmioSize * 1024),
+ PCI_DEV_MAP_FLAG_WRITABLE,
+ result);
+
+ if (err) {
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
+ "Unable to map IO dense aperture. %s (%d)\n",
+ strerror (err), err);
+#endif
}
pSiS->IOBaseDense = pSiSEnt->IOBaseDense;
} else
#endif
- pSiS->IOBaseDense = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_MMIO,
+#ifndef XSERVER_LIBPCIACCESS
+ pSiS->IOBaseDense = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_MMIO,
pSiS->PciTag, pSiS->IOAddress, (pSiS->mmioSize * 1024));
+#else
+ void **result = (void **)&pSiSEnt->IOBaseDense;
+ int err = pci_device_map_range(pSiS->PciInfo,
+ pSiS->IOAddress,
+ (pSiS->mmioSize * 1024),
+ PCI_DEV_MAP_FLAG_WRITABLE,
+ result);
+
+ if (err) {
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
+ "Unable to map IO dense aperture. %s (%d)\n",
+ strerror (err), err);
+#endif
if(pSiS->IOBaseDense == NULL) {
SISErrorLog(pScrn, "Could not map MMIO dense area\n");
@@ -7266,21 +7372,55 @@ SISMapMem(ScrnInfoPtr pScrn)
pSiSEnt->MapCountFbBase++;
if(!(pSiSEnt->FbBase)) {
/* Only map if not mapped previously */
+#ifndef XSERVER_LIBPCIACCESS
pSiSEnt->FbBase = pSiSEnt->RealFbBase =
xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER,
pSiS->PciTag, (ULong)pSiS->realFbAddress,
pSiS->FbMapSize);
+#else
+ int err = pci_device_map_range(pSiS->PciInfo,
+ (ULong)pSiS->realFbAddress,
+ pSiS->FbMapSize,
+ PCI_DEV_MAP_FLAG_WRITABLE |
+ PCI_DEV_MAP_FLAG_WRITE_COMBINE,
+ (void *)&pSiSEnt->FbBase);
+ if (err) {
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
+ "Unable to map FB aperture. %s (%d)\n",
+ strerror (err), err);
+ return FALSE;
+ }
+ pSiSEnt->RealFbBase = pSiSEnt->FbBase;
+#endif
}
pSiS->FbBase = pSiS->RealFbBase = pSiSEnt->FbBase;
/* Adapt FbBase (for DHM and SiS76x UMA skipping; dhmOffset is 0 otherwise) */
pSiS->FbBase += pSiS->dhmOffset;
} else {
#endif
- pSiS->FbBase = pSiS->RealFbBase =
- xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER,
+
+#ifndef XSERVER_LIBPCIACCESS
+ pSiSEnt->FbBase = pSiSEnt->RealFbBase =
+ xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER,
pSiS->PciTag, (ULong)pSiS->realFbAddress,
pSiS->FbMapSize);
+#else
+ int err = pci_device_map_range(pSiS->PciInfo,
+ (ULong)pSiS->realFbAddress,
+ pSiS->FbMapSize,
+ PCI_DEV_MAP_FLAG_WRITABLE |
+ PCI_DEV_MAP_FLAG_WRITE_COMBINE,
+ (void *)&pSiSEnt->FbBase);
+ if (err) {
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
+ "Unable to map FB aperture. %s (%d)\n",
+ strerror (err), err);
+ return FALSE;
+ }
+ pSiSEnt->RealFbBase = pSiSEnt->FbBase;
+#endif
pSiS->FbBase += pSiS->dhmOffset;
+
#ifdef SISDUALHEAD
}
#endif
@@ -7847,7 +7987,7 @@ SiSRestore_SiSFB_TVParms(ScrnInfoPtr pScrn)
if(!pSiS->sisfb_tvposvalid) return;
if(!(pSiS->sisfbdevname[0])) return;
- if((fd = open(pSiS->sisfbdevname, 'r')) != -1) {
+ if((fd = open(pSiS->sisfbdevname, O_RDONLY)) != -1) {
parm = (CARD32)((pSiS->sisfb_tvxpos << 16) | (pSiS->sisfb_tvypos & 0xffff));
ioctl(fd, SISFB_SET_TVPOSOFFSET, &parm);
close(fd);
diff --git a/src/sis_setup.c b/src/sis_setup.c
index 58d929c..c84a38d 100644
--- a/src/sis_setup.c
+++ b/src/sis_setup.c
@@ -99,6 +99,140 @@ static const struct _sis6326mclk {
{134, 0, 0x4a, 0xa3 }
};
+#ifdef XSERVER_LIBPCIACCESS
+struct pci_device *
+sis_get_device (int device)
+{
+ struct pci_slot_match bridge_match = {
+ 0, 0, device, PCI_MATCH_ANY, 0
+ };
+ struct pci_device_iterator *slot_iterator;
+ struct pci_device *bridge;
+
+ slot_iterator = pci_slot_match_iterator_create (&bridge_match);
+ bridge = pci_device_next (slot_iterator);
+ pci_iterator_destroy (slot_iterator);
+ return bridge;
+}
+
+unsigned int
+sis_pci_read_device_u32(int device, int offset)
+{
+ struct pci_device *host_bridge = sis_get_device(device);
+ unsigned int result;
+
+ pci_device_cfg_read_u32(host_bridge, &result, offset);
+ return result;
+}
+
+unsigned char
+sis_pci_read_device_u8(int device, int offset)
+{
+ struct pci_device *host_bridge = sis_get_device(device);
+ unsigned char result;
+
+ pci_device_cfg_read_u8(host_bridge, &result, offset);
+ return result;
+}
+
+void
+sis_pci_write_host_bridge_u32(int offset, unsigned int value)
+{
+ struct pci_device *host_bridge = sis_get_device(0);
+ pci_device_cfg_write_u32(host_bridge, value, offset);
+}
+
+void
+sis_pci_write_host_bridge_u8(int offset, unsigned char value)
+{
+ struct pci_device *host_bridge = sis_get_device(0);
+ pci_device_cfg_write_u8(host_bridge, value, offset);
+}
+
+#else
+unsigned int
+sis_pci_read_device_u32(int device, int offset)
+{
+ PCITAG tag = pciTag(0, device, 0);
+ return pciReadLong(tag, offset);
+}
+
+unsigned char
+sis_pci_read_device_u8(int device, int offset)
+{
+ PCITAG tag = pciTag(0, device, 0);
+ return pciReadByte(tag, offset);
+}
+
+void
+sis_pci_write_host_bridge_u32(int offset, unsigned int value)
+{
+ pciWriteLong(0x00000000, offset, value);
+}
+
+void
+sis_pci_write_host_bridge_u8(int offset, unsigned char value)
+{
+ pciWriteByte(0x00000000, offset, value);
+}
+
+
+#endif
+
+unsigned int
+sis_pci_read_host_bridge_u32(int offset)
+{
+ return sis_pci_read_device_u32(0, offset);
+}
+
+unsigned char
+sis_pci_read_host_bridge_u8(int offset)
+{
+ return sis_pci_read_device_u8(0, offset);
+}
+
+static int sisESSPresent(ScrnInfoPtr pScrn)
+{
+ int flags = 0;
+#ifndef XSERVER_LIBPCIACCESS
+ int i;
+ pciConfigPtr pdptr, *systemPCIdevices = NULL;
+
+ if((systemPCIdevices = xf86GetPciConfigInfo())) {
+ i = 0;
+ while((pdptr = systemPCIdevices[i])) {
+ if((pdptr->pci_vendor == 0x1274) &&
+ ((pdptr->pci_device == 0x5000) ||
+ ((pdptr->pci_device & 0xFFF0) == 0x1370))) {
+ flags |= ESS137xPRESENT;
+ break;
+ }
+ i++;
+ }
+ }
+ return flags;
+#else
+ struct pci_id_match id_match = { 0x1274, PCI_MATCH_ANY,
+ PCI_MATCH_ANY, PCI_MATCH_ANY,
+ PCI_MATCH_ANY, PCI_MATCH_ANY,
+ 0 };
+ struct pci_device_iterator *id_iterator;
+ struct pci_device *ess137x;
+
+ id_iterator = pci_id_match_iterator_create(&id_match);
+
+ ess137x = pci_device_next(id_iterator);
+ while (ess137x) {
+ if ((ess137x->device_id == 0x5000) ||
+ ((ess137x->device_id & 0xfff0) == 0x1370)) {
+ flags |= ESS137xPRESENT;
+ }
+ ess137x = pci_device_next(id_iterator);
+ }
+ return flags;
+#endif
+}
+
/* For old chipsets, 5597, 6326, 530/620 */
static void
sisOldSetup(ScrnInfoPtr pScrn)
@@ -113,7 +247,7 @@ sisOldSetup(ScrnInfoPtr pScrn)
#if 0
UChar newsr13, newsr28, newsr29;
#endif
- pciConfigPtr pdptr, *systemPCIdevices = NULL;
+
if(pSiS->oldChipset <= OC_SIS6225) {
inSISIDXREG(SISSR, 0x0F, temp);
@@ -206,22 +340,11 @@ sisOldSetup(ScrnInfoPtr pScrn)
pSiS->Flags &= ~(ESS137xPRESENT);
if(pSiS->Chipset == PCI_CHIP_SIS530) {
if(pSiS->oldChipset == OC_SIS530A) {
- if((systemPCIdevices = xf86GetPciConfigInfo())) {
- i = 0;
- while((pdptr = systemPCIdevices[i])) {
- if((pdptr->pci_vendor == 0x1274) &&
- ((pdptr->pci_device == 0x5000) ||
- ((pdptr->pci_device & 0xFFF0) == 0x1370))) {
- pSiS->Flags |= ESS137xPRESENT;
- break;
- }
- i++;
- }
- }
- if(pSiS->Flags & ESS137xPRESENT) {
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "SiS530/620: Found ESS device\n");
- }
+ pSiS->Flags |= sisESSPresent(pScrn);
+ }
+ if(pSiS->Flags & ESS137xPRESENT) {
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
+ "SiS530/620: Found ESS device\n");
}
}
@@ -289,20 +412,20 @@ sis300Setup(ScrnInfoPtr pScrn)
case PCI_CHIP_SIS540:
case PCI_CHIP_SIS630:
pSiS->IsAGPCard = TRUE;
- pciconfig = pciReadByte(0x00000000, 0x63);
+ pciconfig = sis_pci_read_host_bridge_u8(0x63);
if(pciconfig & 0x80) {
pScrn->videoRam = (1 << (((pciconfig & 0x70) >> 4) + 21)) / 1024;
pSiS->BusWidth = 64;
- pciconfig = pciReadByte(0x00000000, 0x64);
+ pciconfig = sis_pci_read_host_bridge_u8(0x64);
if((pciconfig & 0x30) == 0x30) {
pSiS->BusWidth = 128;
pScrn->videoRam <<= 1;
}
- ramtype = pciReadByte(0x00000000,0x65);
+ ramtype = sis_pci_read_host_bridge_u8(0x65);
ramtype &= 0x03;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Shared Memory Area is on DIMM%d\n", ramtype);
- ramtype = pciReadByte(0x00000000,(0x60 + ramtype));
+ ramtype = sis_pci_read_host_bridge_u8(0x60 + ramtype);
if(ramtype & 0x80) ramtype = 9;
else ramtype = 4;
pSiS->UMAsize = pScrn->videoRam;
@@ -568,7 +691,7 @@ sis550Setup(ScrnInfoPtr pScrn)
/* UMA - shared fb */
pScrn->videoRam = 0;
- pciconfig = pciReadByte(0x00000000, 0x4c);
+ pciconfig = sis_pci_read_host_bridge_u8(0x4c);
if(pciconfig & 0xe0) {
pScrn->videoRam = (1 << (((pciconfig & 0xe0) >> 5) - 2)) * 32768;
pSiS->ChipFlags |= SiSCF_760UMA;
@@ -580,7 +703,8 @@ sis550Setup(ScrnInfoPtr pScrn)
}
/* LFB - local framebuffer: PCI reg hold total RAM (but configurable in BIOS) */
- pciconfig = pciReadByte(0x00000800, 0xcd);
+ /* TODO */
+ pciconfig = sis_pci_read_device_u8(1, 0xcd);
pciconfig = (pciconfig >> 1) & 0x03;
i = 0;
if(pciconfig == 0x01) i = 32768;
@@ -631,7 +755,7 @@ sis550Setup(ScrnInfoPtr pScrn)
dimmnum = 3;
}
- pciconfig = pciReadByte(0x00000000, 0x64);
+ pciconfig = sis_pci_read_host_bridge_u8(0x64);
if(pciconfig & 0x80) {
pScrn->videoRam = (1 << (((pciconfig & 0x70) >> 4) - 1)) * 32768;
pSiS->UMAsize = pScrn->videoRam;
@@ -643,7 +767,7 @@ sis550Setup(ScrnInfoPtr pScrn)
pSiS->BusWidth = 64;
for(i = 0; i <= (dimmnum - 1); i++) {
if(pciconfig & (1 << i)) {
- temp = pciReadByte(0x00000000, 0x60 + i);
+ temp = sis_pci_read_host_bridge_u8(0x60 + i);
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"DIMM%d is %s SDRAM\n",
i, (temp & 0x40) ? "DDR" : "SDR");
@@ -652,7 +776,7 @@ sis550Setup(ScrnInfoPtr pScrn)
"DIMM%d is not installed\n", i);
}
}
- pciconfig = pciReadByte(0x00000000, 0x7c);
+ pciconfig = sis_pci_read_host_bridge_u8(0x7c);
ramtype = (pciconfig & 0x02) ? 8 : 4;
alldone = TRUE;
}
@@ -662,14 +786,14 @@ sis550Setup(ScrnInfoPtr pScrn)
} else if(pSiS->Chipset == PCI_CHIP_SIS650) {
- pciconfig = pciReadByte(0x00000000, 0x64);
+ pciconfig = sis_pci_read_host_bridge_u8(0x64);
if(pciconfig & 0x80) {
pScrn->videoRam = (1 << (((pciconfig & 0x70) >> 4) + 22)) / 1024;
pSiS->UMAsize = pScrn->videoRam;
pSiS->BusWidth = 64;
for(i=0; i<=3; i++) {
if(pciconfig & (1 << i)) {
- temp = pciReadByte(0x00000000, 0x60 + i);
+ temp = sis_pci_read_host_bridge_u8(0x60 + i);
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"DIMM%d is %s SDRAM\n",
i, (temp & 0x40) ? "DDR" : "SDR");
@@ -678,20 +802,19 @@ sis550Setup(ScrnInfoPtr pScrn)
"DIMM%d is not installed\n", i);
}
}
- pciconfig = pciReadByte(0x00000000, 0x7c);
+ pciconfig = sis_pci_read_host_bridge_u8(0x7c);
if(pciconfig & 0x02) ramtype = 8;
else ramtype = 4;
alldone = TRUE;
}
} else {
-
- pciconfig = pciReadByte(0x00000000, 0x63);
+ pciconfig = sis_pci_read_host_bridge_u8(0x63);
if(pciconfig & 0x80) {
pScrn->videoRam = (1 << (((pciconfig & 0x70) >> 4) + 21)) / 1024;
pSiS->UMAsize = pScrn->videoRam;
pSiS->BusWidth = 64;
- ramtype = pciReadByte(0x00000000,0x65);
+ ramtype = sis_pci_read_host_bridge_u8(0x65);
ramtype &= 0x01;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Shared Memory Area is on DIMM%d\n", ramtype);
diff --git a/src/sis_vga.c b/src/sis_vga.c
index 9275f21..665db08 100644
--- a/src/sis_vga.c
+++ b/src/sis_vga.c
@@ -1717,8 +1717,17 @@ SiSVGAMapMem(ScrnInfoPtr pScrn)
if(pSiS->VGAMapPhys == 0) pSiS->VGAMapPhys = 0xA0000;
#if XF86_VERSION_CURRENT >= XF86_VERSION_NUMERIC(4,3,0,0,0)
+#if XSERVER_LIBPCIACCESS
+ /* XXX This is cacheable, right? Right? */
+ if(pci_device_map_range(pSiS->PciInfo, pSiS->VGAMapPhys, pSiS->VGAMapSize,
+ PCI_DEV_MAP_FLAG_WRITABLE|PCI_DEV_MAP_FLAG_CACHABLE,
+ &pSiS->VGAMemBase)) {
+ return FALSE;
+ }
+#else
pSiS->VGAMemBase = xf86MapDomainMemory(pScrn->scrnIndex, VIDMEM_MMIO_32BIT,
pSiS->PciTag, pSiS->VGAMapPhys, pSiS->VGAMapSize);
+#endif
#else
pSiS->VGAMemBase = xf86MapVidMem(pScrn->scrnIndex, VIDMEM_MMIO_32BIT,
pSiS->VGAMapPhys, pSiS->VGAMapSize);
@@ -1733,8 +1742,11 @@ SiSVGAUnmapMem(ScrnInfoPtr pScrn)
SISPtr pSiS = SISPTR(pScrn);
if(pSiS->VGAMemBase == NULL) return;
-
+#if XSERVER_LIBPCIACCESS
+ pci_device_unmap_range(pSiS->PciInfo, pSiS->VGAMemBase, pSiS->VGAMapSize);
+#else
xf86UnMapVidMem(pScrn->scrnIndex, pSiS->VGAMemBase, pSiS->VGAMapSize);
+#endif
pSiS->VGAMemBase = NULL;
}
#endif
diff --git a/src/sispcirename.h b/src/sispcirename.h
new file mode 100644
index 0000000..c4beac6
--- /dev/null
+++ b/src/sispcirename.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2007 George Sapountzis
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+ * Macros for porting drivers from legacy xfree86 PCI code to the pciaccess
+ * library. The main purpose being to facilitate source code compatibility.
+ */
+
+#ifndef SISPCIRENAME_H
+#define SISPCIRENAME_H
+
+enum region_type {
+ REGION_MEM,
+ REGION_IO
+};
+
+#ifndef XSERVER_LIBPCIACCESS
+
+/* pciVideoPtr */
+#define PCI_DEV_VENDOR_ID(_pcidev) ((_pcidev)->vendor)
+#define PCI_DEV_DEVICE_ID(_pcidev) ((_pcidev)->chipType)
+#define PCI_DEV_REVISION(_pcidev) ((_pcidev)->chipRev)
+
+#define PCI_SUB_VENDOR_ID(_pcidev) ((_pcidev)->subsysVendor)
+#define PCI_SUB_DEVICE_ID(_pcidev) ((_pcidev)->subsysCard)
+
+#define PCI_DEV_TAG(_pcidev) pciTag((_pcidev)->bus, \
+ (_pcidev)->device, \
+ (_pcidev)->func)
+#define PCI_DEV_BUS(_pcidev) ((_pcidev)->bus)
+#define PCI_DEV_DEV(_pcidev) ((_pcidev)->device)
+#define PCI_DEV_FUNC(_pcidev) ((_pcidev)->func)
+
+/* pciConfigPtr */
+#define PCI_CFG_TAG(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->tag)
+#define PCI_CFG_BUS(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->busnum)
+#define PCI_CFG_DEV(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->devnum)
+#define PCI_CFG_FUNC(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->funcnum)
+
+/* region addr: xfree86 uses different fields for memory regions and I/O ports */
+#define PCI_REGION_BASE(_pcidev, _b, _type) \
+ (((_type) == REGION_MEM) ? (_pcidev)->memBase[(_b)] \
+ : (_pcidev)->ioBase[(_b)])
+
+/* region size: xfree86 uses the log2 of the region size,
+ * but with zero meaning no region, not size of one XXX */
+#define PCI_REGION_SIZE(_pcidev, _b) \
+ (((_pcidev)->size[(_b)] > 0) ? (1 << (_pcidev)->size[(_b)]) : 0)
+
+/* read/write PCI configuration space */
+#define PCI_READ_BYTE(_pcidev, _value_ptr, _offset) \
+ *(_value_ptr) = pciReadByte(PCI_CFG_TAG(_pcidev), (_offset))
+
+#define PCI_READ_LONG(_pcidev, _value_ptr, _offset) \
+ *(_value_ptr) = pciReadLong(PCI_CFG_TAG(_pcidev), (_offset))
+
+#define PCI_WRITE_LONG(_pcidev, _value, _offset) \
+ pciWriteLong(PCI_CFG_TAG(_pcidev), (_offset), (_value))
+
+#else /* XSERVER_LIBPCIACCESS */
+
+typedef struct pci_device *pciVideoPtr;
+
+#define PCI_DEV_VENDOR_ID(_pcidev) ((_pcidev)->vendor_id)
+#define PCI_DEV_DEVICE_ID(_pcidev) ((_pcidev)->device_id)
+#define PCI_DEV_REVISION(_pcidev) ((_pcidev)->revision)
+
+#define PCI_SUB_VENDOR_ID(_pcidev) ((_pcidev)->subvendor_id)
+#define PCI_SUB_DEVICE_ID(_pcidev) ((_pcidev)->subdevice_id)
+
+/* pci-rework functions take a 'pci_device' parameter instead of a tag */
+#define PCI_DEV_TAG(_pcidev) (_pcidev)
+
+/* PCI_DEV macros, typically used in printf's, add domain ? XXX */
+#define PCI_DEV_BUS(_pcidev) ((_pcidev)->bus)
+#define PCI_DEV_DEV(_pcidev) ((_pcidev)->dev)
+#define PCI_DEV_FUNC(_pcidev) ((_pcidev)->func)
+
+/* pci-rework functions take a 'pci_device' parameter instead of a tag */
+#define PCI_CFG_TAG(_pcidev) (_pcidev)
+
+/* PCI_CFG macros, typically used in DRI init, contain the domain */
+#define PCI_CFG_BUS(_pcidev) (((_pcidev)->domain << 8) | \
+ (_pcidev)->bus)
+#define PCI_CFG_DEV(_pcidev) ((_pcidev)->dev)
+#define PCI_CFG_FUNC(_pcidev) ((_pcidev)->func)
+
+#define PCI_REGION_BASE(_pcidev, _b, _type) ((_pcidev)->regions[(_b)].base_addr)
+#define PCI_REGION_SIZE(_pcidev, _b) ((_pcidev)->regions[(_b)].size)
+
+#define PCI_READ_BYTE(_pcidev, _value_ptr, _offset) \
+ pci_device_cfg_read_u8((_pcidev), (_value_ptr), (_offset))
+
+#define PCI_READ_LONG(_pcidev, _value_ptr, _offset) \
+ pci_device_cfg_read_u32((_pcidev), (_value_ptr), (_offset))
+
+#define PCI_WRITE_LONG(_pcidev, _value, _offset) \
+ pci_device_cfg_write_u32((_pcidev), (_value), (_offset))
+
+#endif /* XSERVER_LIBPCIACCESS */
+
+#endif /* SISPCIRENAME_H */
Index: .cvsignore
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-sis/devel/.cvsignore,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -r1.8 -r1.9
--- .cvsignore 1 Dec 2006 21:01:35 -0000 1.8
+++ .cvsignore 16 Jan 2008 03:44:54 -0000 1.9
@@ -1 +1 @@
-xf86-video-sis-0.9.3.tar.bz2
+xf86-video-sis-0.9.4.tar.bz2
Index: sources
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-sis/devel/sources,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -r1.8 -r1.9
--- sources 1 Dec 2006 21:01:35 -0000 1.8
+++ sources 16 Jan 2008 03:44:54 -0000 1.9
@@ -1 +1 @@
-e35d817fa4ee7beb6cd5aa744b9c0783 xf86-video-sis-0.9.3.tar.bz2
+43f12cabf770b06170cdd1cdaafdc50f xf86-video-sis-0.9.4.tar.bz2
Index: xorg-x11-drv-sis.spec
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-sis/devel/xorg-x11-drv-sis.spec,v
retrieving revision 1.22
retrieving revision 1.23
diff -u -r1.22 -r1.23
--- xorg-x11-drv-sis.spec 22 Aug 2007 20:33:12 -0000 1.22
+++ xorg-x11-drv-sis.spec 16 Jan 2008 03:44:54 -0000 1.23
@@ -4,8 +4,8 @@
Summary: Xorg X11 sis video driver
Name: xorg-x11-drv-sis
-Version: 0.9.3
-Release: 4%{?dist}
+Version: 0.9.4
+Release: 1%{?dist}
URL: http://www.x.org
License: MIT
Group: User Interface/X Hardware Support
@@ -15,15 +15,17 @@
Source1: sis.xinf
Patch0: sis-0.9.1-assert.patch
+Patch1: sis-pciaccess.patch
ExcludeArch: s390 s390x
-BuildRequires: xorg-x11-server-sdk >= 1.3.0.0-6
+BuildRequires: automake autoconf libtool pkgconfig
+BuildRequires: xorg-x11-server-sdk >= 1.4.99.1
BuildRequires: mesa-libGL-devel >= 6.4-4
BuildRequires: libdrm-devel >= 2.0-1
Requires: hwdata
-Requires: xorg-x11-server-Xorg >= 1.3.0.0-6
+Requires: xorg-x11-server-Xorg >= 1.4.99.1
%description
X.Org X11 sis video driver.
@@ -31,8 +33,10 @@
%prep
%setup -q -n %{tarball}-%{version}
%patch0 -p1 -b .assert
+%patch1 -p1 -b .pciaccess
%build
+aclocal ; automake -a ; autoconf
%configure --disable-static
make
@@ -58,6 +62,10 @@
%{_mandir}/man4/sis.4*
%changelog
+* Wed Jan 16 2008 Dave Airlie <airlied at redhat.com> - 0.9.4-1
+- new upstream version
+- sis-pciaccess.patch - add initial pciaccess port
+
* Wed Aug 22 2007 Adam Jackson <ajax at redhat.com> - 0.9.3-4
- Rebuild for PPC toolchain bug
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