rpms/oprofile/devel oprofile-0.9.3-family10.patch, NONE, 1.1 oprofile.spec, 1.61, 1.62
William Eden Cohen (wcohen)
fedora-extras-commits at redhat.com
Fri Jan 18 16:37:20 UTC 2008
Author: wcohen
Update of /cvs/pkgs/rpms/oprofile/devel
In directory cvs-int.fedora.redhat.com:/tmp/cvs-serv20165
Modified Files:
oprofile.spec
Added Files:
oprofile-0.9.3-family10.patch
Log Message:
* Fri Jan 18 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-11
- Update AMD family 10h events to match AMD documentation Resolves: rhbz #232956
oprofile-0.9.3-family10.patch:
--- NEW FILE oprofile-0.9.3-family10.patch ---
Index: events/x86-64/family10/events
===================================================================
RCS file: /cvsroot/oprofile/oprofile/events/x86-64/family10/events,v
retrieving revision 1.1
retrieving revision 1.2
diff -U2 -u -r1.1 -r1.2
--- events/x86-64/family10/events 23 Mar 2007 19:28:59 -0000 1.1
+++ events/x86-64/family10/events 17 Oct 2007 12:01:13 -0000 1.2
@@ -5,23 +5,39 @@
#
# Copyright (c) Advanced Micro Devices, 2006, 2007
-# Contributed by Ray Bryant <raybry at amd.com>, and others.
+# Contributed by Ray Bryant <raybry at amd.com>,
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
#
+
+# default event
event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
+
+# Floating point events
+event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops
+event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_FPU_EMPTY : The number of cycles in which the PFU is empty
+event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : The number of FPU operations that use the fast flag interface
+event:0x03 counters:0,1,2,3 um:sse_ops minimum:500 name:RETIRED_SSE_OPS : The number of SSE ops or uops retired
+event:0x04 counters:0,1,2,3 um:move_ops minimum:500 name:RETIRED_MOVE_OPS : The number of move uops retired
+event:0x05 counters:0,1,2,3 um:serial_ops minimum:500 name:RETIRED_SERIALIZING_OPS : The number of serializing uops retired.
+event:0x06 counters:0,1,2,3 um:serial_ops_sched minimum:500 name:SERIAL_UOPS_IN_FP_SCHED : Number of cycles a serializing uop is in the FP scheduler
+
+# Load, Store, and TLB events
+event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment register loads
+event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
+event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
+event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 Full
+event:0x24 counters:0,1,2,3 um:lock_ops minimum:500 name:LOCKED_OPS : Locked operations
event:0x26 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CLFLUSH : Retired CLFLUSH instructions
event:0x27 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CPUID : Retired CPUID instructions
-event:0xc0 counters:0,1,2,3 um:zero minimum:3000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs)
-event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops
-event:0x80 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_FETCHES : Instruction cache fetches (RevE)
-event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
+event:0x2a counters:0,1,2,3 um:store_to_load minimum:500 name:CANCELLED_STORE_TO_LOAD : Counts the number of cancelled store to load forward operations
+event:0x2b counters:0,1,2,3 um:zero minimum:500 name:SMIS_RECEIVED : Counts the number of SMI received
+
+# Data Cache event
event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
# Note: unit mask 0x01 counts same events as event select 0x43
-event:0x42 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_SYSTEM : Data cache refills from L2 or system
-event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_SYSTEM : Data cache refills from system
-event:0x44 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_LINES_EVICTED : Data cache lines evicted
-event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts)
-event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired Mispredicted Branch Instructions
-event:0xc4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS : Retired taken branch instructions
-event:0xc5 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED : Retired taken branches mispredicted
+event:0x42 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE : Data cache refills from L2 or northbridge
+event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_NORTHBRIDGE : Data cache refills from northbridge
+event:0x44 counters:0,1,2,3 um:moesi_gh minimum:500 name:DATA_CACHE_LINES_EVICTED : Data cache lines evicted
event:0x45 counters:0,1,2,3 um:l1_dlb_miss_l2_hit minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits
event:0x46 counters:0,1,2,3 um:l1_l2_dlb_miss minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses
@@ -29,45 +45,45 @@
event:0x48 counters:0,1,2,3 um:zero minimum:500 name:MICRO_ARCH_LATE_CANCEL_ACCESS : Microarchitectural late cancel of an access
event:0x49 counters:0,1,2,3 um:zero minimum:500 name:MICRO_ARCH_EARLY_CANCEL_ACCESS : Microarchitectural early cancel of an access
-event:0x4a counters:0,1,2,3 um:ecc minimum:500 name:1_BIT_ECC_ERRORs : Single-bit ECC errors recorded by scrubber
+event:0x4a counters:0,1,2,3 um:ecc minimum:500 name:1_BIT_ECC_ERRORS : Single-bit ECC errors recorded by scrubber
event:0x4b counters:0,1,2,3 um:prefetch minimum:500 name:PREFETCH_INSTRUCTIONS_DISPATCHED : The number of prefetch instructions dispatched by the decoder
-event:0x4c counters:0,1,2,3 um:locked_instruction_dcache_miss minimum:500 name:LOCKED_INSTRUCTIONS_DCACHE_MISS : The number of dta cache misses by locked instructions.
-event:0x65 counters:0,1,2,3 um:memory_type_request minimum:500 name:NUMBER_OF_MEMORY_TYPE_REQUEST : Number of memory type requests
-event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB misses (and L2 ITLB hits)
-event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB Miss, L2 ITLB Miss
-event:0xc6 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_FAR_CONTROL_TRANSFERS : Retired far control transfers
-event:0xc7 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_RESYNCS : Retired branches resyncs (only non-control transfer branches)
-event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
-event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
-event:0xcf counters:0,1,2,3 um:zero minimum:10 name:INTERRUPTS_TAKEN : Number of taken hardware interrupts
-event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops
-event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles with no FPU ops retired
-event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface
-event:0x07 counters:0,1,2,3 um:control_modified minimum:500 name:CONTROL_MODIFIED : Number of times rounding control or precision control is modified
-event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment register loads
-event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
-event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
-event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 Full
-event:0x24 counters:0,1,2,3 um:lock_ops minimum:500 name:LOCKED_OPS : Locked operations
+event:0x4c counters:0,1,2,3 um:locked_instruction_dcache_miss minimum:500 name:LOCKED_INSTRUCTIONS_DCACHE_MISSES : The number of dta cache misses by locked instructions.
+event:0x4d counters:0,1,2,3 um:l1_dtlb_hit minimum:500 name:L1_DTLB_HIT : L1 DTLB hit
+event:0x52 counters:0,1,2,3 um:soft_prefetch minimum:500 name:INEFFECTIVE_SW_PREFETCHES : Number of software prefetches that did not fetch data outside of processor core
+event:0x54 counters:0,1,2,3 um:zero minimum:500 name:GLOBAL_TLB_FLUSHES : The number of global TLB flushes
+
+# L2 Cache and System Interface events
event:0x65 counters:0,1,2,3 um:memreqtype minimum:500 name:MEMORY_REQUESTS : Memory Requests by Type
event:0x67 counters:0,1,2,3 um:dataprefetch minimum:500 name:DATA_PREFETCHES : Data Prefetcher
-event:0x68 counters:0,1,2,3 um:mab_um minimum:500 name:MAB_REQUESTS : Number of L1 Cache misses handled by selected MAB
-event:0x69 counters:0,1,2,3 um:mab_um minimum:500 name:MAB_WAIT_CYCLES : Number of cycles spent waiting for the selected MAB
-event:0x6c counters:0,1,2,3 um:systemreadresponse minimum:500 name:SYSTEM_READ_RESPONSES : System Read Responses by Coherency State
-event:0x6d counters:0,1,2,3 um:quadword_transfer minimum:500 name:QUADWORD_WRITE_TRANSFERS : Quadwords Written to System
-event:0x6e counters:0,1,2,3 um:page_table_walker_1 minimum:500 name:PAGE_TABLE_WALKER_1 : Table walk accesses to the PDC and L2 cache on TLB refills
-event:0x6f counters:0,1,2,3 um:page_table_walker_2 minimum:500 name:PAGE_TABLE_WALKER_2 : Table walk accesses to the PDC and L2 cache on TLB refills
-event:0x73 counters:0,1,2,3 um:probe_hits_um minimum:500 name:Probe_Hits : Cache coherency probe hits by cache
-event:0x75 counters:0,1,2,3 um:cache_cross_invalidates_um minimum:500 name:Cache_Cross_Invalidates : IC or DC misses that hit in the DC or IC causing the line to be invalidated
-event:0x78 counters:0,1,2,3 um:tlb_flush minimum:500 name:TLB_FLUSH : TLB Flushes
+event:0x6c counters:0,1,2,3 um:systemreadresponse minimum:500 name:NORTHBRIDGE_READ_RESPONSES : Northbridge Read Responses by Coherency State
+event:0x6d counters:0,1,2,3 um:quadword_transfer minimum:500 name:OCTWORD_WRITE_TRANSFERS : Octwords Written to System
event:0x7d counters:0,1,2,3 um:l2_internal minimum:500 name:REQUESTS_TO_L2 : Requests to L2 Cache
event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 Cache Misses
event:0x7f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 Fill/Writeback
+
+# Instruction Cache events
+event:0x80 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_FETCHES : Instruction cache fetches (RevE)
+event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
event:0x82 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_L2 : Instruction Cache Refills from L2
event:0x83 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM : Instruction Cache Refills from System
+event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB misses (and L2 ITLB hits)
+event:0x85 counters:0,1,2,3 um:l1_l2_itlb_miss minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB Miss, L2 ITLB Miss
event:0x86 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE : Pipeline Restart Due to Instruction Stream Probe
event:0x87 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCH_STALL : Instruction fetch stall
event:0x88 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_HITS : Return stack hit
event:0x89 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_OVERFLOWS : Return stack overflow
-event:0x8d counters:0,1,2,3 um:instr_fetch minimum:500 name:INSTRUCTION_FETCH_STALLS : Number of cycles the instruction fetch engine stalled
+event:0x8b counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_VICTIMS : Number of instruction cachelines evicticed to L2
+event:0x8c counters:0,1,2,3 um:icache_invalidated minimum:500 name:INSTRUCTION_CHCHE_INVALIDATED : Instruction cache lines invalidated
+event:0x99 counters:0,1,2,3 um:zero minimum:500 name:ITLB_RELOADS : The number of ITLB reloads requests
+event:0x9a counters:0,1,2,3 um:zero minimum:500 name:ITLB_RELOADS_ABORTED : The number of ITLB reloads aborted
+
+# Execution Unit events
+event:0xc0 counters:0,1,2,3 um:zero minimum:3000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs)
+event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops
+event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts)
+event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired Mispredicted Branch Instructions
+event:0xc4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS : Retired taken branch instructions
+event:0xc5 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED : Retired taken branches mispredicted
+event:0xc6 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_FAR_CONTROL_TRANSFERS : Retired far control transfers
+event:0xc7 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_RESYNCS : Retired branches resyncs (only non-control transfer branches)
event:0xc8 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS : Retired near returns
event:0xc9 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS_MISPREDICTED : Retired near returns mispredicted
@@ -75,4 +91,7 @@
event:0xcb counters:0,1,2,3 um:fpu_instr minimum:500 name:RETIRED_MMX_FP_INSTRUCTIONS : Retired MMX/FP instructions
event:0xcc counters:0,1,2,3 um:fpu_fastpath minimum:500 name:RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS : Retired FastPath double-op instructions
+event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
+event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
+event:0xcf counters:0,1,2,3 um:zero minimum:10 name:INTERRUPTS_TAKEN : Number of taken hardware interrupts
event:0xd0 counters:0,1,2,3 um:zero minimum:500 name:DECODER_EMPTY : Nothing to dispatch (decoder empty)
event:0xd1 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALLS : Dispatch stalls
@@ -87,8 +106,10 @@
event:0xda counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC : Dispatch Stall for Far Transfer or Resync to Retire
event:0xdb counters:0,1,2,3 um:fpu_exceptions minimum:1 name:FPU_EXCEPTIONS : FPU exceptions
-event:0xdc counters:0,1,2,3 um:zero minimum:1 name:DR0_BREAKPOINTS : Number of breakpoints for DR0
-event:0xdd counters:0,1,2,3 um:zero minimum:1 name:DR1_BREAKPOINTS : Number of breakpoints for DR1
-event:0xde counters:0,1,2,3 um:zero minimum:1 name:DR2_BREAKPOINTS : Number of breakpoints for DR2
-event:0xdf counters:0,1,2,3 um:zero minimum:1 name:DR3_BREAKPOINTS : Number of breakpoints for DR3
+event:0xdc counters:0,1,2,3 um:zero minimum:1 name:DR0_BREAKPOINTS : The number of matches on the address in breakpoint register DR0
+event:0xdd counters:0,1,2,3 um:zero minimum:1 name:DR1_BREAKPOINTS : The number of matches on the address in breakpoint register DR1
+event:0xde counters:0,1,2,3 um:zero minimum:1 name:DR2_BREAKPOINTS : The number of matches on the address in breakpoint register DR2
+event:0xdf counters:0,1,2,3 um:zero minimum:1 name:DR3_BREAKPOINTS : The number of matches on the address in breakpoint register DR3
+
+# Memory Controler events
event:0xe0 counters:0,1,2,3 um:page_access minimum:500 name:DRAM_ACCESSES : DRAM Accesses
event:0xe1 counters:0,1,2,3 um:mem_page_overflow minimum:500 name:MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS : Memory controller page table overflows
@@ -96,25 +117,32 @@
event:0xe3 counters:0,1,2,3 um:turnaround minimum:500 name:MEMORY_CONTROLLER_TURNAROUNDS : Memory controller turnarounds
event:0xe4 counters:0,1,2,3 um:saturation minimum:500 name:MEMORY_CONTROLLER_BYPASS_COUNTER_SATURATION : Memory controller bypass saturation
-event:0xee counters:0,1,2,3 um:gart minimum:500 name:GART_EVENTS : GART Events
-event:0xe5 counters:0,1,2,3 um:cancel_requests minimum:500 name:MEMORY_CANCEL_REQUESTS : DRAM request cancellation activity, and sized read/write block sizes.
-event:0xe6 counters:0,1,2,3 um:write_combine minimum:500 name:MEMORY_CONTROLLER_WRITES_COMBINED : write-combining done by the memory controller
event:0xe8 counters:0,1,2,3 um:thermal_status minimum:500 name:THERMAL_STATUS : Thermal status
-event:0x1e8 counters:0,1,2,3 um:cpu_apic_2 minimum:500 name:CPU_REQUEST_APIC_2 : CPU requests to APIC
-event:0x1f0 counters:0,1,2,3 um:mem_control_request minimum:500 name:MEMORY_CONTROLLER_REQUESTS : Sized Read/Write activity.
event:0xe9 counters:0,1,2,3 um:cpiorequests minimum:500 name:CPU_IO_REQUESTS_TO_MEMORY_IO : CPU/IO Requests to Memory/IO (RevE)
event:0xea counters:0,1,2,3 um:cacheblock minimum:500 name:CACHE_BLOCK_COMMANDS : Cache Block Commands (RevE)
event:0xeb counters:0,1,2,3 um:sizecmds minimum:500 name:SIZED_COMMANDS : Sized Commands
event:0xec counters:0,1,2,3 um:probe minimum:500 name:PROBE_RESPONSES_AND_UPSTREAM_REQUESTS : Probe Responses and Upstream Requests
-event:0xef counters:0,1,2,3 um:srifull_cycles_1 minimum:500 name:SRI_TO_XBAR_BUFFER_FULL_CYCLES_1 : SRI-to-Crossbar full cycles
-event:0xf3 counters:0,1,2,3 um:srifull_cycles_2 minimum:500 name:SRI_TO_XBAR_BUFFER_FULL_CYCLES_2 : SRI-to-Crossbar full cycles
-event:0xf4 counters:0,1,2,3 um:xbarfull_cycles minimum:500 name:XBAR_TO_MCT_BUFFER_FULL_CYCLES : Crossbar to MCT buffer full cycles
-event:0xf5 counters:0,1,2,3 um:mctfull_cycles minimum:500 name:MCT_TO_XBAR_BUFFER_FULL_CYCLES : MCT to Crossbar buffer full cycles
-event:0xf0 counters:0,1,2,3 um:htfull minimum:500 name:HYPERTRANSPORT_LINK0_FULL_CYCLES : HyperTransport(tm) link 0 buffer full cycles
-event:0xf1 counters:0,1,2,3 um:htfull minimum:500 name:HYPERTRANSPORT_LINK1_FULL_CYCLES : HyperTransport(tm) link 0 buffer full cycles
-event:0xf2 counters:0,1,2,3 um:htfull minimum:500 name:HYPERTRANSPORT_LINK2_FULL_CYCLES : HyperTransport(tm) link 0 buffer full cycles
-event:0xf3 counters:0,1,2,3 um:htfull minimum:500 name:HYPERTRANSPORT_LINK3_FULL_CYCLES : HyperTransport(tm) link 0 buffer full cycles
+event:0xee counters:0,1,2,3 um:gart minimum:500 name:GART_EVENTS : GART Events
+event:0x1f0 counters:0,1,2,3 um:mem_control_request minimum:500 name:MEMORY_CONTROLLER_REQUESTS : Sized Read/Write activity.
+
+# Crossbar events
+event:0x1e0 counters:0,1,2,3 um:cpu_dram_req minimum:500 name:CPU_DRAM_REQUEST_TO_NODE : CPU to DRAM requests to target node
+event:0x1e1 counters:0,1,2,3 um:io_dram_req minimum:500 name:IO_DRAM_REQUEST_TO_NODE : IO to DRAM requests to target node
+event:0x1e2 counters:0,1,2,3 um:cpu_read_lat_0_3 minimum:500 name:CPU_READ_COMMAND_LATENCY_NODE_0_3 : Latency between the local node and remote node
+event:0x1e3 counters:0,1,2,3 um:cpu_read_lat_0_3 minimum:500 name:CPU_READ_COMMAND_REQUEST_NODE_0_3 : Number of requests that a latency measurment is made for Event 0x1E2
+event:0x1e4 counters:0,1,2,3 um:cpu_read_lat_4_7 minimum:500 name:CPU_READ_COMMAND_LATENCY_NODE_4_7 : Latency between the local node and remote node
+event:0x1e5 counters:0,1,2,3 um:cpu_read_lat_4_7 minimum:500 name:CPU_READ_COMMAND_REQUEST_NODE_4_7 : Number of requests that a latency measurment is made for Event 0x1E2
+event:0x1e6 counters:0,1,2,3 um:cpu_comm_lat minimum:500 name:CPU_COMMAND_LATENCY_TARGET : Determine latency between the local node and a remote node.
+event:0x1e7 counters:0,1,2,3 um:cpu_comm_lat minimum:500 name:CPU_REQUEST_TARGET : Number of requests that a latency measurement is made for Event 0x1E6
+
+# Link events
event:0xf6 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK0_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 0 transmit bandwidth
-event:0xf7 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 0 transmit bandwidth
-event:0xf8 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 0 transmit bandwidth
-event:0x1f9 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 0 transmit bandwidth
+event:0xf7 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 1 transmit bandwidth
+event:0xf8 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 2 transmit bandwidth
+event:0x1f9 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 3 transmit bandwidth
+
+# L3 Cache events
+event:0x4e0 counters:0,1,2,3 um:l3_cache minimum:500 name:READ_REQUEST_L3_CACHE : Tracks the red requests from each core to L3 cache
+event:0x4e1 counters:0,1,2,3 um:l3_cache minimum:500 name:L3_CACHE_MISSES : Tracks the L3 cache misses from each core
+event:0x4e2 counters:0,1,2,3 um:l3_fill minimum:500 name:L3_FILLS_CAUSED_BY_L2_EVICTIONS : Tracks the L3 fills caused by L2 evictions per core
+event:0x4e3 counters:0,1,2,3 um:l3_evict minimum:500 name:L3_EVICTIONS : Tracks the state of the L3 line when it was evicted
Index: events/x86-64/family10/unit_masks
===================================================================
RCS file: /cvsroot/oprofile/oprofile/events/x86-64/family10/unit_masks,v
retrieving revision 1.1
retrieving revision 1.2
diff -U2 -u -r1.1 -r1.2
--- events/x86-64/family10/unit_masks 23 Mar 2007 19:28:59 -0000 1.1
+++ events/x86-64/family10/unit_masks 17 Oct 2007 12:01:13 -0000 1.2
@@ -4,5 +4,7 @@
# Copyright OProfile authors
# Copyright (c) Advanced Micro Devices, 2006.
-# Contributed by Ray Bryant <raybry at amd.com>, and others.
+# Contributed by Ray Bryant <raybry at amd.com>
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
#
name:zero type:mandatory default:0x0
@@ -16,21 +18,18 @@
0x1f All cache states
name:moess type:bitmask default:0x1e
- 0x10 (M)odified cache state
- 0x08 (O)wner cache state
- 0x04 (E)xclusive cache state
- 0x02 (S)hared cache state
- 0x01 refill from system
- 0x1e All cache states except Invalid
+ 0x01 Refill from northbridge
+ 0x02 Shared-state line from L2
+ 0x04 Exclusive-state line from L2
+ 0x08 Owner-state line from L2
+ 0x10 Modified-state line from L2
+ 0x1e All cache states except refill from northbridge
name:fpu_ops type:bitmask default:0x3f
- 0x01 Add pipe ops
- 0x02 Multiply pipe
- 0x04 Store pipe ops
- 0x08 Add pipe load ops
- 0x10 Multiply pipe load ops
- 0x20 Store pipe load ops
-name:control_modified type:bitmask default:0x0d
- 0x01 Number of times SSE rounding control is changed
- 0x04 Number of times x87 rounding control is changed
- 0x08 Number of times x87 precision control is changed
+ 0x01 Add pipe ops excluding load ops and SSE move ops
+ 0x02 Multiply pipe ops excluding load ops and SSE move ops
+ 0x04 Store pipe ops excluding load ops and SSE move ops
+ 0x08 Add pipe load ops and SSE move ops
+ 0x10 Multiply pipe load ops and SSE move ops
+ 0x20 Store pipe load ops and SSE move ops
+ 0x3F all ops
name:segregload type:bitmask default:0x7f
0x01 ES register
@@ -41,9 +40,8 @@
0x20 GS register
0x40 HS register
-name:fpu_instr type:bitmask default:0x0f
+name:fpu_instr type:bitmask default:0x07
0x01 x87 instructions
- 0x02 Combined MMX & 3DNow instructions
- 0x04 Combined packed SSE & SSE2 instructions
- 0x08 Combined packed scalar SSE & SSE2 instructions
+ 0x02 MMX & 3DNow instructions
+ 0x04 SSE & SSE2 instructions
name:fpu_fastpath type:bitmask default:0x07
0x01 With low op in position 0
@@ -55,5 +53,5 @@
0x04 SSE reclass microfaults
0x08 SSE and x87 microtraps
-name:page_access type:bitmask default:0x07
+name:page_access type:bitmask default:0xff
0x01 DCT0 Page hit
0x02 DCT0 Page miss
@@ -68,13 +66,13 @@
0x02 DCT1 Page Table Overflow
name:turnaround type:bitmask default:0x3f
- 0x01 DCT0 DIMM turnaround
+ 0x01 DCT0 DIMM (chip select) turnaround
0x02 DCT0 Read to write turnaround
0x04 DCT0 Write to read turnaround
- 0x08 DCT1 DIMM turnaround
+ 0x08 DCT1 DIMM (chip select) turnaround
0x10 DCT1 Read to write turnaround
0x20 DCT1 Write to read turnaround
name:saturation type:bitmask default:0x0f
0x01 Memory controller high priority bypass
- 0x02 Memory controller low priority bypass
+ 0x02 Memory controller medium priority bypass
0x04 DCT0 DCQ bypass
0x08 DCT1 DCQ bypass
@@ -82,16 +80,14 @@
0x01 DCT0 Command slots missed
0x02 DCT2 Command slots missed
- 0x04 DRAM controller interface bypass
- 0x08 DRAM controller queue bypass
name:sizecmds type:bitmask default:0x3f
- 0x01 non-posted write byte
- 0x02 non-posted write dword
- 0x04 posted write byte
- 0x08 posted write dword
+ 0x01 non-posted write byte (1-32 bytes)
+ 0x02 non-posted write dword (1-16 dwords)
+ 0x04 posted write byte (1-32 bytes)
+ 0x08 posted write dword (1-16 dwords)
0x10 read byte (4 bytes)
0x20 read dword (1-16 dwords)
name:probe type:bitmask default:0xff
0x01 Probe miss
- 0x02 Probe hit
+ 0x02 Probe hit clean
0x04 Probe hit dirty without memory cancel
0x08 Probe hit dirty with memory cancel
@@ -100,17 +96,19 @@
0x40 Upstream ISOC writes
0x80 Upstream non-ISOC writes
-name:l2_internal type:bitmask default:0x1f
+name:l2_internal type:bitmask default:0x3f
0x01 IC fill
0x02 DC fill
- 0x04 TLB reload
+ 0x04 TLB fill (page table walks)
0x08 Tag snoop request
0x10 Canceled request
-name:l2_req_miss type:bitmask default:0x07
+ 0x20 Hardware prefetch from data cache
+name:l2_req_miss type:bitmask default:0x0f
0x01 IC fill
- 0x02 DC fill
- 0x04 TLB reload
+ 0x02 DC fill (includes possible replays)
+ 0x04 TLB page table walk
+ 0x08 Hardwareprefetch from data cache
name:l2_fill type:bitmask default:0x03
- 0x01 Dirty L2 victim
- 0x02 Victim from L1
+ 0x01 L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
+ 0x02 L2 Writebacks to system
name:gart type:bitmask default:0xff
0x01 GART aperture hit on access from CPU
@@ -148,42 +146,11 @@
0x04 Shared
0x10 Data Error
-name:mab_um type:exclusive default:0x09
- 0x01 Buffer 1
- 0x02 Buffer 2
- 0x03 Buffer 3
- 0x04 Buffer 4
- 0x05 Buffer 5
- 0x06 Buffer 6
- 0x07 Buffer 7
- 0x08 Buffer 8
- 0x09 Buffer 9
-name:page_table_walker_1 type:bitmask default:0x41
- 0x01 PDE refill hit in L2 cache
- 0x04 PDPE lookup misses in PDC
- 0x10 PML4E refill hit in L2 cache
- 0x40 PML4E lookup missed in PDC
-name:page_table_walker_2 type:bitmask default:0xd1
- 0x01 PTE refil hit in L2 cache
- 0x10 PDE refill hit in L2 cache
- 0x40 PDE lookup missed in PDC
- 0x80 PDE lookup in PDC
-name:probe_hits_um type:bitmask default:0x03
- 0x01 Probe hit Icache
- 0x02 Probe hit Dcache
-name:cache_cross_invalidates_um type:bitmask default:0x0f
- 0x01 DC Invalidates IC, modification of cached instructions, data too close to code
- 0x02 DC Invalidates DC, aliasing
- 0x04 IC Invalidates IC, aliasing
- 0x08 IC Invalidates DC, execution of recently modified code, modified data too close to code
-name:tlb_flush type:bitmask default:0x03
- 0x01 Actual TLB flushes
- 0x02 TLB flush requests
name:l1_dlb_miss_l2_hit type:bitmask default:0x03
0x01 L2 4K TLB hit
0x02 L2 2M TLB hit
-name:l1_l2_dlb_miss type:bitmask default:0x43
+name:l1_l2_dlb_miss type:bitmask default:0x07
0x01 4K TLB reload
0x02 2M TLB reload
- 0x40 1G TLB reload
+ 0x04 1G TLB reload
name:ecc type:bitmask default:0x0f
0x01 Scrubber error
@@ -199,10 +166,4 @@
name:quadword_transfer type:bitmask default:0x01
0x01 Quadword write transfer
-name:cancel_requests type:bitmask default:0x03
- 0x01 Total MemCancels seen
- 0x02 Read responses successfully canceled
-name:write_combine type:bitmask default:0x03
- 0x01 Sized Writes not combined
- 0x02 Sized writes combined
name:thermal_status type:bitmask default:0x7c
0x04 Number of times the HTC trip point is crossed
@@ -212,66 +173,140 @@
0x40 Number of clocks HTC P-state is active
name:mem_control_request type:bitmask default:0x78
+ 0x01 Write requests
+ 0x02 Read Requests including Prefetch
+ 0x04 Prefetch Request
0x08 32 Bytes Sized Writes
0x10 64 Bytes Sized Writes
0x20 32 Bytes Sized Reads
0x40 64 Byte Sized Reads
-name:srifull_cycles_1 type:bitmask default:0x5f
- 0x01 Request
- 0x02 Posted request
- 0x04 Response
- 0x08 Display refresh
- 0x10 Request data
- 0x40 Response data
-name:srifull_cycles_2 type:bitmask default:0x3f
- 0x01 Upstream request
- 0x02 Upstream posted request
- 0x04 Display refresh
- 0x08 Probe
- 0x10 Downstream request
- 0x20 Downstream posted request
-name:xbarfull_cycles type:bitmask default:0x15
- 0x01 Request
- 0x04 Display Refresh
- 0x10 Request data
-name:mctfull_cycles type:bitmask default:0x4c
- 0x04 Response
- 0x08 Probe
- 0x40 Response data
-name:htfull type:bitmask default:0xdf
- 0x01 Request buffer
- 0x02 Posted request buffer
- 0x04 Response buffer
- 0x08 Probe buffer
- 0x10 Request/posted request data buffer
- 0x40 Response data buffer
- 0x80 Sublink Mask
+ 0x80 Read Requests while writes pending in DCQ
name:httransmit type:bitmask default:0xbf
0x01 Command DWORD sent
- 0x02 Address extension DWORD sent
- 0x04 Data DWORD sent
- 0x08 Buffer release DWORD sent
- 0x10 Nop DW send, idle
+ 0x02 DWORD sent
+ 0x04 Buffer release DWORD sent
+ 0x08 Nop DW sent (idle)
+ 0x10 Address extension DWORD sent
0x20 Per packet CRC sent
0x80 SubLink Mask
-name:memory_type_request type:bitmask default:0xf3
- 0x01 UC
- 0x02 WC
- 0x10 WT
- 0x20 WP
- 0x40 WB
- 0x80 Streaming store
-name:instr_fetch type:bitmask default:0x0f
- 0x01 All stalls except stalls specified the other three unitmasks
- 0x02 Stalls caused when a branch is written to the branch array
- 0x04 Stalls caused when the branch array is full
- 0x08 Stalls caused when the instruction buffer is full
-name:cpu_apic_2 type:bitmask default:0x0f
- 0x01 Local APIC reads
- 0x02 Local APIC writes
- 0x04 APIC TPR writes
- 0x08 Fast APIC TPR writes
-name:lock_ops type:bitmask default:0x07
+name:lock_ops type:bitmask default:0x0f
0x01 Number of locked instructions executed
0x02 Cycles in speculative phase
- 0x04 Cycles in non-speculative phase
-
+ 0x04 Cycles in non-speculative phase (including cache miss penalty)
+ 0x08 Cache miss penalty in cycles
+name:sse_ops type:bitmask default:0x7f
+ 0x01 Single Precision add/subtract ops
+ 0x02 Single precision multiply ops
+ 0x04 Single precision divide/square root ops
+ 0x08 Double precision add/subtract ops
+ 0x10 Double precision multiply ops
+ 0x20 Double precision divide/square root ops
+ 0x40 OP type, 0=uops 1=FLOPS
+name:move_ops type:bitmask default:0x0f
+ 0x01 Merging low quadword move uops
+ 0x02 Merging high quadword move uops
+ 0x04 All other merging move uops
+ 0x08 All other move uops
+name:serial_ops type:bitmask default:0x0f
+ 0x01 SSE bottom-executing uops retired
+ 0x02 SSE bottom-serializing uops retired
+ 0x04 x87 bottom-executing uops retired
+ 0x08 x87 bottom-serializing uops retired
+name:serial_ops_sched type:bitmask default:0x03
+ 0x01 Number of cycles a bottom-execute uops in FP scheduler
+ 0x02 Number of cycles a bottom-serializing uops in FP scheduler
+name:store_to_load type:bitmask default:0x07
+ 0x01 Address mismatches (starting byte not the same)
+ 0x02 Store is smaller than load
+ 0x04 Misaligned
+name:moesi_gh type:bitmask default:0x1f
+ 0x01 (I)nvalid cache state
+ 0x02 (S)hared cache state
+ 0x04 (E)xclusive cache state
+ 0x08 (O)wner cache state
+ 0x10 (M)odified cache state
+ 0x20 Cache line evict brought by PrefetchNTA
+ 0x40 Cache line evict not brought by PrefetchNTA
+ 0x1f All cache states except PrefetchNTA
+name:l1_dtlb_hit type:bitmask default:0x07
+ 0x01 L1 4K TLB hit
+ 0x02 L1 2M TLB hit
+ 0x04 L1 1G TLB hit
+name:soft_prefetch type:bitmask default:0x09
+ 0x01 Hit in L1
+ 0x08 Hit in L2
+name:l1_l2_itlb_miss type:bitmask default:0x03
+ 0x01 Instruction fetches to 4K pages
+ 0x02 Instruction fetches to 2M pages
+name:cpu_dram_req type:bitmask default:0xff
+ 0x01 From local node to node 0
+ 0x02 From local node to node 1
+ 0x04 From local node to node 2
+ 0x08 From local node to node 3
+ 0x10 From local node to node 4
+ 0x20 From local node to node 5
+ 0x40 From local node to node 6
+ 0x80 From local node to node 7
+name:io_dram_req type:bitmask default:0xff
+ 0x01 From local node to node 0
+ 0x02 From local node to node 1
+ 0x04 From local node to node 2
+ 0x08 From local node to node 3
+ 0x10 From local node to node 4
+ 0x20 From local node to node 5
+ 0x40 From local node to node 6
+ 0x80 From local node to node 7
+name:cpu_read_lat_0_3 type:bitmask default:0xff
+ 0x01 Read block
+ 0x02 Read block shared
+ 0x04 Read block modified
+ 0x08 Change to dirty
+ 0x10 From local node to node 0
+ 0x20 From local node to node 1
+ 0x40 From local node to node 2
+ 0x80 From local node to node 3
+name:cpu_read_lat_4_7 type:bitmask default:0xff
+ 0x01 Read block
+ 0x02 Read block shared
+ 0x04 Read block modified
+ 0x08 Change to dirty
+ 0x10 From local node to node 4
+ 0x20 From local node to node 5
+ 0x40 From local node to node 6
+ 0x80 From local node to node 7
+name:cpu_comm_lat type:bitmask default:0xf7
+ 0x01 Read sized
+ 0x02 Write sized
+ 0x04 Victim block
+ 0x08 Node group select. 0=Nodes 0-3. 1=Nodes 4-7
+ 0x10 From local node to node 0/4
+ 0x20 From local node to node 1/5
+ 0x40 From local node to node 2/6
+ 0x80 From local node to node 3/7
+name:l3_cache type:bitmask default:0xf7
+ 0x01 Read Block Exclusive (Data cache read)
+ 0x02 Read Block Shared (Instruciton cache read)
+ 0x04 Read Block Modify
+ 0x10 Core 0 Select
+ 0x20 Core 1 Select
+ 0x40 Core 2 Select
+ 0x80 Core 3 Select
+name:l3_fill type:bitmask default:0xff
+ 0x01 Shared
+ 0x02 Exclusive
+ 0x04 Owned
+ 0x08 Modified
+ 0x10 Core 0 Select
+ 0x20 Core 1 Select
+ 0x40 Core 2 Select
+ 0x80 Core 3 Select
+name:l3_evict type:bitmask default:0x0f
+ 0x01 Shared
+ 0x02 Exclusive
+ 0x04 Owned
+ 0x08 Modified
+name:icache_invalidated type:bitmask default:0x0f
+ 0x01 Invalidating probe that did not hit any in-flight instructions
+ 0x02 Invalidating probe that hit one or more in-flight instructions
+ 0x04 SMC that did not hit any in-flight instructions
+ 0x08 SMC that hit one or more in-flight instructions
+
Index: oprofile.spec
===================================================================
RCS file: /cvs/pkgs/rpms/oprofile/devel/oprofile.spec,v
retrieving revision 1.61
retrieving revision 1.62
diff -u -r1.61 -r1.62
--- oprofile.spec 12 Nov 2007 22:18:21 -0000 1.61
+++ oprofile.spec 18 Jan 2008 16:36:36 -0000 1.62
@@ -3,7 +3,7 @@
Summary: System wide profiler
Name: oprofile
Version: 0.9.3
-Release: 7%{?dist}
+Release: 11%{?dist}
License: GPL
Group: Development/System
#
@@ -14,6 +14,7 @@
Patch63: oprofile-0.7-libs.patch
Patch83: oprofile-0.9.1-xen.patch
Patch92: oprofile-0.9.3-ld_options.patch
+Patch93: oprofile-0.9.3-family10.patch
URL: http://oprofile.sf.net
ExclusiveArch: %{ix86} ia64 x86_64 ppc ppc64 s390 s390x alpha alphaev6 sparc sparc64
@@ -67,6 +68,7 @@
#%patch90 -p0 -b .race
#%patch91 -p1 -b .k10
%patch92 -p0 -b .ld_option
+%patch93 -p0 -b .family10
./autogen.sh
@@ -181,6 +183,9 @@
%{_bindir}/oprof_start
%changelog
+* Fri Jan 18 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-11
+- Update AMD family 10h events to match AMD documentation Resolves: rhbz #232956
+
* Mon Nov 12 2007 Will Cohen <wcohen at redhat.com> - 0.9.3-7
- Should correct missing 'test' in patch.
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