rpms/kernel/F-9 drm-radeon-update.patch, 1.1, 1.2 kernel.spec, 1.683, 1.684
Dave Airlie (airlied)
fedora-extras-commits at redhat.com
Thu Jun 19 03:48:30 UTC 2008
Author: airlied
Update of /cvs/pkgs/rpms/kernel/F-9
In directory cvs-int.fedora.redhat.com:/tmp/cvs-serv28584
Modified Files:
drm-radeon-update.patch kernel.spec
Log Message:
* Thu Jun 19 2008 Dave Airlie <airlied at redhat.com> 2.6.25.7-65
- update radeon patches to newer upstream
drm-radeon-update.patch:
Index: drm-radeon-update.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-9/drm-radeon-update.patch,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -r1.1 -r1.2
--- drm-radeon-update.patch 28 May 2008 05:13:07 -0000 1.1
+++ drm-radeon-update.patch 19 Jun 2008 03:47:35 -0000 1.2
@@ -1,3 +1,239 @@
+commit 21efa2bac91b8d12064617c5a35492ec982544eb
+Author: Dave Airlie <airlied at redhat.com>
+Date: Thu Jun 19 13:01:58 2008 +1000
+
+ drm/radeon: add hier-z registers for r300 and r500 chipsets
+
+commit 5e35eff13f7dd0f5c1d82b3b4708b2f7a5f44113
+Author: Alex Deucher <alex at botchco.com>
+Date: Thu Jun 19 12:39:23 2008 +1000
+
+ drm/radeon: use DSTCACHE_CTLSTAT rather than RB2D_DSTCACHE_CTLSTAT
+
+ According to the hw guys, you should use DSTCACHE_CTLSTAT to flush
+ the 2D dst cache rather than RB2D_DSTCACHE_CTLSTAT.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 5cfb6956073a9e42d44a26790b7800980634d037
+Author: Alex Deucher <alex at botchco.com>
+Date: Thu Jun 19 12:38:29 2008 +1000
+
+ drm/radeon: switch IGP gart to use radeon_write_agp_base()
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 7ecabc53a29bb31689fa1852a926e021179a64a6
+Author: Dennis Kasprzyk <onestone at opencompositing.org>
+Date: Thu Jun 19 12:36:55 2008 +1000
+
+ drm/radeon: Restore sw interrupt on resume
+
+ Fixes performance drop after suspend/resume on some systems.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 70b13d510fc9d137e362b7db3ac5b14b50d78477
+Author: Dave Airlie <airlied at redhat.com>
+Date: Thu Jun 19 11:40:44 2008 +1000
+
+ drm/r500: add support for AGP based cards.
+
+ AGP registers weren't programmed properly for r500 cards.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 9156cf09f56150ed89f77eaa4c386a07789776a0
+Author: Roland Scheidegger <sroland at tungstengraphics.com>
+Date: Thu Jun 19 11:36:04 2008 +1000
+
+ drm/radeon: fix texture uploads with large 3d textures (bug 13980)
+
+ Texture uploads could hit the blitter coordinate limit, adjust the texture
+ offset when uploading the pieces. Make sure to check the end address of the
+ upload too.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit c0beb2a723d69934a53f51a9d664c5b1dbbf634b
+Author: Dave Airlie <airlied at redhat.com>
+Date: Wed May 28 13:52:28 2008 +1000
+
+ drm/radeon: add initial r500 support.
+
+ This contains all the command buffer processing for the r500 cards.
+ It doesn't yet contain vblank support.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 5b92c4045eaa42441b7ec249a406e4110ea400d4
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed May 28 11:57:40 2008 +1000
+
+ drm/radeon: init pipe setup in kernel code.
+
+ This inits the card pipes in the kernel and lets userspace getparam
+ the correct setup.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit d396db321bcaec54345e7e9e87cea8482d6ae3a8
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed May 28 11:54:06 2008 +1000
+
+ drm/radeon: fixup radeon_do_engine_reset
+
+ Cleanup do engine reset for different chip families.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 259434acccbc823ee8bc00b2d2689ccccd25e1fd
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed May 28 11:51:12 2008 +1000
+
+ drm/radeon: fix pixcache and purge/cache flushing registers
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit d7463eb41d88a39de2653fd41857c4ccddb8707b
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed May 28 11:46:36 2008 +1000
+
+ drm/radeon: write AGP_BASE_2 on chips that support it.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 45e519052e8f583a709edd442a23f59581d3fe42
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed May 28 13:28:59 2008 +1000
+
+ drm/radeon: merge IGP chip setup and fixup RS400 vs RS480 support
+
+ We only support RS480 (AMD based IGP) at the moment not
+ RS400 (Intel based IGP) ones.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 2735977b12cb0f113aae24afff04747b6d0f5bf1
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed May 28 12:54:16 2008 +1000
+
+ drm/radeon: IGP clean up register and magic numbers.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 3722bfc607d46275369865c02fe8694486d640b5
+Author: Dave Airlie <airlied at linux.ie>
+Date: Wed May 28 11:28:27 2008 +1000
+
+ drm/rs690: set base 2 to 0.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit fa0d71b967506031f7cb08ced6095d1c4f988594
+Author: Dave Airlie <airlied at linux.ie>
+Date: Wed May 28 11:27:01 2008 +1000
+
+ drm/rs690: set all of gart base address.
+
+ Docs state bits 4-11 maps to bits 32-39 of the 40-bit range
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 9f18409ea3d778a171a9505c0a849d846f352bd0
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed May 28 11:21:25 2008 +1000
+
+ radeon: add production microcode from AMD
+
+ This adds production microcode for r100->r500 from AMD.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 7ec700fcaf4f01ae72956df74a9e0d08938fd26e
+Author: Dave Airlie <airlied at redhat.com>
+Date: Thu Jun 19 11:27:23 2008 +1000
+
+ drm: pcigart use proper pci map interfaces.
+
+ Switch to using more correct pci dma mapping interfaces.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit b554305905d9bc2184b424aa67712119d5c9fb99
+Author: Dave Airlie <airlied at redhat.com>
+Date: Fri Jun 13 15:06:31 2008 +1000
+
+ drm: the sg alloc ioctl should write back the handle to userspace
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 41ee2ff404ec76194315aeed57ac973b010abe1d
+Author: Johannes Weiner <hannes at saeurebad.de>
+Date: Fri Jun 13 15:04:40 2008 +1000
+
+ drm: use drms ioctl cmd not what we get passed from userspace.
+
+ This enforces us to use the drm ioctl types so read/write works correctly and not believe
+ what userspace tells us.
+
+ It does this hopefully without breaking the drm api.
+
+ Fixes bug from thread: BUG: unable to handle kernel NULL pointer dereference (drm_getunique)
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c
+index b710426..c533d0c 100644
+--- a/drivers/char/drm/ati_pcigart.c
++++ b/drivers/char/drm/ati_pcigart.c
+@@ -76,7 +76,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info
+ for (i = 0; i < pages; i++) {
+ if (!entry->busaddr[i])
+ break;
+- pci_unmap_single(dev->pdev, entry->busaddr[i],
++ pci_unmap_page(dev->pdev, entry->busaddr[i],
+ PAGE_SIZE, PCI_DMA_TODEVICE);
+ }
+
+@@ -137,10 +137,8 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
+
+ for (i = 0; i < pages; i++) {
+ /* we need to support large memory configurations */
+- entry->busaddr[i] = pci_map_single(dev->pdev,
+- page_address(entry->
+- pagelist[i]),
+- PAGE_SIZE, PCI_DMA_TODEVICE);
++ entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
++ 0, PAGE_SIZE, PCI_DMA_TODEVICE);
+ if (entry->busaddr[i] == 0) {
+ DRM_ERROR("unable to map PCIGART pages!\n");
+ drm_ati_pcigart_cleanup(dev, gart_info);
+diff --git a/drivers/char/drm/drm.h b/drivers/char/drm/drm.h
+index 3a05c6d..38d3c6b 100644
+--- a/drivers/char/drm/drm.h
++++ b/drivers/char/drm/drm.h
+@@ -628,7 +628,7 @@ struct drm_set_version {
+ #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
+ #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
+
+-#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather)
++#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
+ #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
+
+ #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
+diff --git a/drivers/char/drm/drm_drv.c b/drivers/char/drm/drm_drv.c
+index fc54140..22957ac 100644
+--- a/drivers/char/drm/drm_drv.c
++++ b/drivers/char/drm/drm_drv.c
+@@ -475,6 +475,8 @@ int drm_ioctl(struct inode *inode, struct file *filp,
+ else
+ goto err_i1;
+
++ /* Do not trust userspace, use our own definition */
++ cmd = ioctl->cmd;
+ func = ioctl->func;
+ /* is there a local override? */
+ if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl)
diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index a6a499f..bad096f 100644
--- a/drivers/char/drm/drm_pciids.h
@@ -30,7 +266,7 @@
{0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
{0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c
-index f535812..329733a 100644
+index f535812..702df45 100644
--- a/drivers/char/drm/r300_cmdbuf.c
+++ b/drivers/char/drm/r300_cmdbuf.c
@@ -189,18 +189,12 @@ void r300_init_reg_flags(struct drm_device *dev)
@@ -39,8 +275,9 @@
ADD_RANGE(R300_RS_CNTL_0, 2);
- ADD_RANGE(R300_RS_INTERP_0, 8);
- ADD_RANGE(R300_RS_ROUTE_0, 8);
+- ADD_RANGE(0x43A4, 2);
+
- ADD_RANGE(0x43A4, 2);
++ ADD_RANGE(R300_SC_HYPERZ, 2);
ADD_RANGE(0x43E8, 1);
- ADD_RANGE(R300_PFS_CNTL_0, 3);
- ADD_RANGE(R300_PFS_NODE_0, 4);
@@ -55,7 +292,35 @@
ADD_RANGE(R300_RE_FOG_STATE, 1);
ADD_RANGE(R300_FOG_COLOR_R, 3);
ADD_RANGE(R300_PP_ALPHA_TEST, 2);
-@@ -241,7 +235,25 @@ void r300_init_reg_flags(struct drm_device *dev)
+@@ -215,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev)
+ ADD_RANGE(0x4E50, 9);
+ ADD_RANGE(0x4E88, 1);
+ ADD_RANGE(0x4EA0, 2);
+- ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
+- ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
+- ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
+- ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
+- ADD_RANGE(0x4F28, 1);
+- ADD_RANGE(0x4F30, 2);
+- ADD_RANGE(0x4F44, 1);
+- ADD_RANGE(0x4F54, 1);
++ ADD_RANGE(R300_ZB_CNTL, 3);
++ ADD_RANGE(R300_ZB_FORMAT, 4);
++ ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
++ ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
++ ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
++ ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
+
+ ADD_RANGE(R300_TX_FILTER_0, 16);
+ ADD_RANGE(R300_TX_FILTER1_0, 16);
+@@ -235,13 +227,32 @@ void r300_init_reg_flags(struct drm_device *dev)
+ ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
+
+ /* Sporadic registers used as primitives are emitted */
+- ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1);
++ ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
+ ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
+ ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
@@ -68,6 +333,7 @@
+ ADD_RANGE(R500_RS_INST_0, 16);
+ ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
+ ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
++ ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
+ } else {
+ ADD_RANGE(R300_PFS_CNTL_0, 3);
+ ADD_RANGE(R300_PFS_NODE_0, 4);
@@ -82,6 +348,18 @@
}
}
+@@ -707,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
+ BEGIN_RING(6);
+ OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+ OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
+- OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
+- OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03);
++ OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
++ OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE|
++ R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
+ OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
+ OUT_RING(0x0);
+ ADVANCE_RING();
@@ -829,6 +841,54 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
}
@@ -158,10 +436,38 @@
DRM_ERROR("bad cmd_type %i at %p\n",
header.header.cmd_type,
diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h
-index 8f664af..a883d10 100644
+index 8f664af..a6802f2 100644
--- a/drivers/char/drm/r300_reg.h
+++ b/drivers/char/drm/r300_reg.h
-@@ -1346,7 +1346,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
+@@ -702,6 +702,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
+ # define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)
+ /* END: Rasterization / Interpolators - many guesses */
+
++/* Hierarchical Z Enable */
++#define R300_SC_HYPERZ 0x43a4
++# define R300_SC_HYPERZ_DISABLE (0 << 0)
++# define R300_SC_HYPERZ_ENABLE (1 << 0)
++# define R300_SC_HYPERZ_MIN (0 << 1)
++# define R300_SC_HYPERZ_MAX (1 << 1)
++# define R300_SC_HYPERZ_ADJ_256 (0 << 2)
++# define R300_SC_HYPERZ_ADJ_128 (1 << 2)
++# define R300_SC_HYPERZ_ADJ_64 (2 << 2)
++# define R300_SC_HYPERZ_ADJ_32 (3 << 2)
++# define R300_SC_HYPERZ_ADJ_16 (4 << 2)
++# define R300_SC_HYPERZ_ADJ_8 (5 << 2)
++# define R300_SC_HYPERZ_ADJ_4 (6 << 2)
++# define R300_SC_HYPERZ_ADJ_2 (7 << 2)
++# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
++# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
++# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
++# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
++
++#define R300_SC_EDGERULE 0x43a8
++
+ /* BEGIN: Scissors and cliprects */
+
+ /* There are four clipping rectangles. Their corner coordinates are inclusive.
+@@ -1346,7 +1367,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Guess by Vladimir.
* Set to 0A before 3D operations, set to 02 afterwards.
*/
@@ -170,7 +476,236 @@
# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002
# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A
-@@ -1623,4 +1623,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
+@@ -1355,19 +1376,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * for this.
+ * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
+ */
+-#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00
+-# define R300_RB3D_Z_DISABLED_1 0x00000010
+-# define R300_RB3D_Z_DISABLED_2 0x00000014
+-# define R300_RB3D_Z_TEST 0x00000012
+-# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
+-# define R300_RB3D_Z_WRITE_ONLY 0x00000006
+-
+-# define R300_RB3D_Z_TEST 0x00000012
+-# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
+-# define R300_RB3D_Z_WRITE_ONLY 0x00000006
+-# define R300_RB3D_STENCIL_ENABLE 0x00000001
+-
+-#define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
++#define R300_ZB_CNTL 0x4F00
++# define R300_STENCIL_ENABLE (1 << 0)
++# define R300_Z_ENABLE (1 << 1)
++# define R300_Z_WRITE_ENABLE (1 << 2)
++# define R300_Z_SIGNED_COMPARE (1 << 3)
++# define R300_STENCIL_FRONT_BACK (1 << 4)
++
++#define R300_ZB_ZSTENCILCNTL 0x4f04
+ /* functions */
+ # define R300_ZS_NEVER 0
+ # define R300_ZS_LESS 1
+@@ -1387,52 +1403,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
+ # define R300_ZS_INVERT 5
+ # define R300_ZS_INCR_WRAP 6
+ # define R300_ZS_DECR_WRAP 7
++# define R300_Z_FUNC_SHIFT 0
+ /* front and back refer to operations done for front
+ and back faces, i.e. separate stencil function support */
+-# define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0
+-# define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3
+-# define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6
+-# define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9
+-# define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12
+-# define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15
+-# define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18
+-# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21
+-# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24
+-
+-#define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08
+-# define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0
+-# define R300_RB3D_ZS2_STENCIL_MASK 0xFF
+-# define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8
+-# define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16
++# define R300_S_FRONT_FUNC_SHIFT 3
++# define R300_S_FRONT_SFAIL_OP_SHIFT 6
++# define R300_S_FRONT_ZPASS_OP_SHIFT 9
++# define R300_S_FRONT_ZFAIL_OP_SHIFT 12
++# define R300_S_BACK_FUNC_SHIFT 15
++# define R300_S_BACK_SFAIL_OP_SHIFT 18
++# define R300_S_BACK_ZPASS_OP_SHIFT 21
++# define R300_S_BACK_ZFAIL_OP_SHIFT 24
++
++#define R300_ZB_STENCILREFMASK 0x4f08
++# define R300_STENCILREF_SHIFT 0
++# define R300_STENCILREF_MASK 0x000000ff
++# define R300_STENCILMASK_SHIFT 8
++# define R300_STENCILMASK_MASK 0x0000ff00
++# define R300_STENCILWRITEMASK_SHIFT 16
++# define R300_STENCILWRITEMASK_MASK 0x00ff0000
+
+ /* gap */
+
+-#define R300_RB3D_ZSTENCIL_FORMAT 0x4F10
+-# define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
+-# define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
+- /* 16 bit format or some aditional bit ? */
+-# define R300_DEPTH_FORMAT_UNK32 (32 << 0)
++#define R300_ZB_FORMAT 0x4f10
++# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
++# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
++# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
++/* reserved up to (15 << 0) */
++# define R300_INVERT_13E3_LEADING_ONES (0 << 4)
++# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
+
+-#define R300_RB3D_EARLY_Z 0x4F14
+-# define R300_EARLY_Z_DISABLE (0 << 0)
+-# define R300_EARLY_Z_ENABLE (1 << 0)
++#define R300_ZB_ZTOP 0x4F14
++# define R300_ZTOP_DISABLE (0 << 0)
++# define R300_ZTOP_ENABLE (1 << 0)
+
+ /* gap */
+
+-#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */
+-# define R300_RB3D_ZCACHE_UNKNOWN_01 0x1
+-# define R300_RB3D_ZCACHE_UNKNOWN_03 0x3
++#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
++# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
++# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
++# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
++# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
++# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
++# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
++
++#define R300_ZB_BW_CNTL 0x4f1c
++# define R300_HIZ_DISABLE (0 << 0)
++# define R300_HIZ_ENABLE (1 << 0)
++# define R300_HIZ_MIN (0 << 1)
++# define R300_HIZ_MAX (1 << 1)
++# define R300_FAST_FILL_DISABLE (0 << 2)
++# define R300_FAST_FILL_ENABLE (1 << 2)
++# define R300_RD_COMP_DISABLE (0 << 3)
++# define R300_RD_COMP_ENABLE (1 << 3)
++# define R300_WR_COMP_DISABLE (0 << 4)
++# define R300_WR_COMP_ENABLE (1 << 4)
++# define R300_ZB_CB_CLEAR_RMW (0 << 5)
++# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
++# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
++# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
++
++# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
++# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
++# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
++# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
++
++# define R500_BMASK_ENABLE (0 << 10)
++# define R500_BMASK_DISABLE (1 << 10)
++# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
++# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
++# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
++# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
++# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
++# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
++# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
++# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
++# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
++# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
++# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
++# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
++# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
++# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
++# define R500_PEQ_PACKING_DISABLE (0 << 18)
++# define R500_PEQ_PACKING_ENABLE (1 << 18)
++# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
++# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
++
+
+ /* gap */
+
+-#define R300_RB3D_DEPTHOFFSET 0x4F20
+-#define R300_RB3D_DEPTHPITCH 0x4F24
+-# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */
+-# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */
+-# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */
+-# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
+-# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
+-# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
++/* Z Buffer Address Offset.
++ * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
++ */
++#define R300_ZB_DEPTHOFFSET 0x4f20
++
++/* Z Buffer Pitch and Endian Control */
++#define R300_ZB_DEPTHPITCH 0x4f24
++# define R300_DEPTHPITCH_MASK 0x00003FFC
++# define R300_DEPTHMACROTILE_DISABLE (0 << 16)
++# define R300_DEPTHMACROTILE_ENABLE (1 << 16)
++# define R300_DEPTHMICROTILE_LINEAR (0 << 17)
++# define R300_DEPTHMICROTILE_TILED (1 << 17)
++# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
++# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
++# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
++# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
++# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
++
++/* Z Buffer Clear Value */
++#define R300_ZB_DEPTHCLEARVALUE 0x4f28
++
++#define R300_ZB_ZMASK_OFFSET 0x4f30
++#define R300_ZB_ZMASK_PITCH 0x4f34
++#define R300_ZB_ZMASK_WRINDEX 0x4f38
++#define R300_ZB_ZMASK_DWORD 0x4f3c
++#define R300_ZB_ZMASK_RDINDEX 0x4f40
++
++/* Hierarchical Z Memory Offset */
++#define R300_ZB_HIZ_OFFSET 0x4f44
++
++/* Hierarchical Z Write Index */
++#define R300_ZB_HIZ_WRINDEX 0x4f48
++
++/* Hierarchical Z Data */
++#define R300_ZB_HIZ_DWORD 0x4f4c
++
++/* Hierarchical Z Read Index */
++#define R300_ZB_HIZ_RDINDEX 0x4f50
++
++/* Hierarchical Z Pitch */
++#define R300_ZB_HIZ_PITCH 0x4f54
++
++/* Z Buffer Z Pass Counter Data */
++#define R300_ZB_ZPASS_DATA 0x4f58
++
++/* Z Buffer Z Pass Counter Address */
++#define R300_ZB_ZPASS_ADDR 0x4f5c
++
++/* Depth buffer X and Y coordinate offset */
++#define R300_ZB_DEPTHXY_OFFSET 0x4f60
++# define R300_DEPTHX_OFFSET_SHIFT 1
++# define R300_DEPTHX_OFFSET_MASK 0x000007FE
++# define R300_DEPTHY_OFFSET_SHIFT 17
++# define R300_DEPTHY_OFFSET_MASK 0x07FE0000
++
++/* Sets the fifo sizes */
++#define R500_ZB_FIFO_SIZE 0x4fd0
++# define R500_OP_FIFO_SIZE_FULL (0 << 0)
++# define R500_OP_FIFO_SIZE_HALF (1 << 0)
++# define R500_OP_FIFO_SIZE_QUATER (2 << 0)
++# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
++
++/* Stencil Reference Value and Mask for backfacing quads */
++/* R300_ZB_STENCILREFMASK handles front face */
++#define R500_ZB_STENCILREFMASK_BF 0x4fd4
++# define R500_STENCILREF_SHIFT 0
++# define R500_STENCILREF_MASK 0x000000ff
++# define R500_STENCILMASK_SHIFT 8
++# define R500_STENCILMASK_MASK 0x0000ff00
++# define R500_STENCILWRITEMASK_SHIFT 16
++# define R500_STENCILWRITEMASK_MASK 0x00ff0000
+
+ /* BEGIN: Vertex program instruction set */
+
+@@ -1623,4 +1753,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
@@ -192,7 +727,7 @@
+
#endif /* _R300_REG_H */
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
-index f6f6c92..5991875 100644
+index f6f6c92..e53158f 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -2,6 +2,7 @@
@@ -1055,7 +1590,7 @@
else
RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
}
-@@ -859,11 +104,11 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
+@@ -859,15 +104,39 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
{
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
@@ -1069,7 +1604,35 @@
else
RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
}
-@@ -882,15 +127,6 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
+
++static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
++{
++ u32 agp_base_hi = upper_32_bits(agp_base);
++ u32 agp_base_lo = agp_base & 0xffffffff;
++
++ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
++ R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
++ R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
++ } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
++ RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
++ RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
++ } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
++ R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
++ R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
++ } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
++ RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
++ RADEON_WRITE(RS480_AGP_BASE_2, 0);
++ } else {
++ RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
++ RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
++ }
++}
++
+ static int RADEON_READ_PLL(struct drm_device * dev, int addr)
+ {
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+@@ -882,15 +151,6 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
return RADEON_READ(RADEON_PCIE_DATA);
}
@@ -1085,7 +1648,7 @@
#if RADEON_FIFO_DEBUG
static void radeon_status(drm_radeon_private_t * dev_priv)
{
-@@ -925,16 +161,36 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
+@@ -925,16 +185,36 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
@@ -1115,12 +1678,12 @@
+ RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
+
+ /* 2D */
-+ tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
++ tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT);
+ tmp |= RADEON_RB3D_DC_FLUSH_ALL;
-+ RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
++ RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp);
+
+ for (i = 0; i < dev_priv->usec_timeout; i++) {
-+ if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
++ if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT)
+ & RADEON_RB3D_DC_BUSY)) {
+ return 0;
+ }
@@ -1130,7 +1693,7 @@
}
#if RADEON_FIFO_DEBUG
-@@ -991,6 +247,50 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
+@@ -991,6 +271,50 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
return -EBUSY;
}
@@ -1181,7 +1744,7 @@
/* ================================================================
* CP control, initialization
*/
-@@ -1004,8 +304,22 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
+@@ -1004,8 +328,22 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
radeon_do_wait_for_idle(dev_priv);
RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
@@ -1206,7 +1769,7 @@
DRM_INFO("Loading R200 Microcode\n");
for (i = 0; i < 256; i++) {
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-@@ -1013,7 +327,11 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
+@@ -1013,7 +351,11 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
R200_cp_microcode[i][0]);
}
@@ -1219,7 +1782,7 @@
DRM_INFO("Loading R300 Microcode\n");
for (i = 0; i < 256; i++) {
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-@@ -1021,12 +339,35 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
+@@ -1021,12 +363,35 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
R300_cp_microcode[i][0]);
}
@@ -1227,10 +1790,12 @@
+ } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
+ DRM_INFO("Loading R400 Microcode\n");
-+ for (i = 0; i < 256; i++) {
-+ RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+ for (i = 0; i < 256; i++) {
+ RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+- radeon_cp_microcode[i][1]);
+ R420_cp_microcode[i][1]);
-+ RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+ RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+- radeon_cp_microcode[i][0]);
+ R420_cp_microcode[i][0]);
+ }
+ } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
@@ -1248,17 +1813,15 @@
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
+ DRM_INFO("Loading R500 Microcode\n");
- for (i = 0; i < 256; i++) {
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-- radeon_cp_microcode[i][1]);
++ for (i = 0; i < 256; i++) {
++ RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+ R520_cp_microcode[i][1]);
- RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
-- radeon_cp_microcode[i][0]);
++ RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+ R520_cp_microcode[i][0]);
}
}
}
-@@ -1121,12 +462,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
+@@ -1121,12 +486,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
static int radeon_do_engine_reset(struct drm_device * dev)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1274,7 +1837,7 @@
clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
-@@ -1137,33 +479,39 @@ static int radeon_do_engine_reset(struct drm_device * dev)
+@@ -1137,33 +503,39 @@ static int radeon_do_engine_reset(struct drm_device * dev)
RADEON_FORCEON_YCLKB |
RADEON_FORCEON_MC |
RADEON_FORCEON_AIC));
@@ -1335,16 +1898,17 @@
/* Reset the CP ring */
radeon_do_cp_reset(dev_priv);
-@@ -1195,6 +543,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -1194,7 +566,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
- RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
-+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
-+ RADEON_WRITE(RADEON_AGP_BASE_2, 0);
+- RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
++ radeon_write_agp_base(dev_priv, dev->agp->base);
++
radeon_write_agp_location(dev_priv,
(((dev_priv->gart_vm_start - 1 +
dev_priv->gart_size) & 0xffff0000) |
-@@ -1339,102 +689,77 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
+@@ -1339,102 +712,70 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
/* Enable or disable IGP GART on the chip */
static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
{
@@ -1397,53 +1961,41 @@
- temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL);
- RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000);
--
-- RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
-- RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
--
-- temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID);
-- RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800);
--
-- RS690_WRITE_MCIND(RS690_MC_GART_BASE,
-- dev_priv->gart_info.bus_addr);
--
-- temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL);
-- RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000);
--
-- RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
-- (unsigned int)dev_priv->gart_vm_start);
+ temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+ IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
+ RS690_BLOCK_GFX_D3_EN));
+ else
+ IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
-+
+
+- RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
+- RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
+ IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
+ RS480_VA_SIZE_32MB));
-+
+
+- temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID);
+- RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800);
+ temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
+ IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
+ RS480_TLB_ENABLE |
+ RS480_GTW_LAC_EN |
+ RS480_1LEVEL_GART));
-+
+
+- RS690_WRITE_MCIND(RS690_MC_GART_BASE,
+- dev_priv->gart_info.bus_addr);
+ temp = dev_priv->gart_info.bus_addr & 0xfffff000;
+ temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
+ IGP_WRITE_MCIND(RS480_GART_BASE, temp);
-+
+
+- temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL);
+- RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000);
+ temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
+ IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
+ RS480_REQ_TYPE_SNOOP_DIS));
-+
-+ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
-+ IGP_WRITE_MCIND(RS690_MC_AGP_BASE,
-+ (unsigned int)dev_priv->gart_vm_start);
-+ IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
-+ } else {
-+ RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
-+ RADEON_WRITE(RS480_AGP_BASE_2, 0);
-+ }
+
+- RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
+- (unsigned int)dev_priv->gart_vm_start);
++ radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
dev_priv->gart_size = 32*1024*1024;
temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
@@ -1493,7 +2045,7 @@
}
}
-@@ -1472,12 +797,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
+@@ -1472,12 +813,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
{
u32 tmp;
@@ -1508,6 +2060,14 @@
radeon_set_igpgart(dev_priv, on);
return;
}
+@@ -1951,6 +1288,7 @@ static int radeon_do_resume_cp(struct drm_device * dev)
+ radeon_cp_init_ring_buffer(dev, dev_priv);
+
+ radeon_do_engine_reset(dev);
++ radeon_enable_interrupt(dev);
+
+ DRM_DEBUG("radeon_do_resume_cp() complete\n");
+
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h
index aab82e1..73ff51f 100644
--- a/drivers/char/drm/radeon_drm.h
@@ -1549,7 +2109,7 @@
typedef struct drm_radeon_getparam {
int param;
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
-index 173ae62..d0dc47c 100644
+index 173ae62..3f0eca9 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -38,7 +38,7 @@
@@ -1600,7 +2160,15 @@
} drm_radeon_private_t;
struct drm_radeon_master_private {
-@@ -444,13 +448,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -382,6 +386,7 @@ extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
+ extern void radeon_driver_irq_preinstall(struct drm_device * dev);
+ extern void radeon_driver_irq_postinstall(struct drm_device * dev);
+ extern void radeon_driver_irq_uninstall(struct drm_device * dev);
++extern void radeon_enable_interrupt(struct drm_device *dev);
+ extern int radeon_vblank_crtc_get(struct drm_device *dev);
+ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
+
+@@ -444,13 +449,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_PCIE_DATA 0x0034
#define RADEON_PCIE_TX_GART_CNTL 0x10
# define RADEON_PCIE_TX_GART_EN (1 << 0)
@@ -1621,7 +2189,7 @@
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
#define RADEON_PCIE_TX_GART_BASE 0x13
-@@ -459,14 +463,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -459,14 +464,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_PCIE_TX_GART_END_LO 0x16
#define RADEON_PCIE_TX_GART_END_HI 0x17
@@ -1639,7 +2207,7 @@
#define RS690_MC_INDEX 0x78
# define RS690_MC_INDEX_MASK 0x1ff
-@@ -474,32 +473,51 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -474,45 +474,91 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
# define RS690_MC_INDEX_WR_ACK 0x7f
#define RS690_MC_DATA 0x7c
@@ -1712,7 +2280,15 @@
#define R520_MC_IND_DATA 0x74
#define RV515_MC_FB_LOCATION 0x01
-@@ -511,8 +529,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+ #define RV515_MC_AGP_LOCATION 0x02
++#define RV515_MC_AGP_BASE 0x03
++#define RV515_MC_AGP_BASE_2 0x04
+
+ #define R520_MC_FB_LOCATION 0x04
+ #define R520_MC_AGP_LOCATION 0x05
++#define R520_MC_AGP_BASE 0x06
++#define R520_MC_AGP_BASE_2 0x07
+
#define RADEON_MPP_TB_CONFIG 0x01c0
#define RADEON_MEM_CNTL 0x0140
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
@@ -1744,7 +2320,25 @@
#define RADEON_RB3D_COLOROFFSET 0x1c40
#define RADEON_RB3D_COLORPITCH 0x1c48
-@@ -643,11 +684,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -616,11 +662,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+ #define RADEON_PP_TXFILTER_1 0x1c6c
+ #define RADEON_PP_TXFILTER_2 0x1c84
+
+-#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
+-# define RADEON_RB2D_DC_FLUSH (3 << 0)
+-# define RADEON_RB2D_DC_FREE (3 << 2)
+-# define RADEON_RB2D_DC_FLUSH_ALL 0xf
+-# define RADEON_RB2D_DC_BUSY (1 << 31)
++#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
++#define R300_DSTCACHE_CTLSTAT 0x1714
++# define R300_RB2D_DC_FLUSH (3 << 0)
++# define R300_RB2D_DC_FREE (3 << 2)
++# define R300_RB2D_DC_FLUSH_ALL 0xf
++# define R300_RB2D_DC_BUSY (1 << 31)
+ #define RADEON_RB3D_CNTL 0x1c3c
+ # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
+ # define RADEON_PLANE_MASK_ENABLE (1 << 1)
+@@ -643,11 +690,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
# define RADEON_RB3D_ZC_FREE (1 << 2)
# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
# define RADEON_RB3D_ZC_BUSY (1 << 31)
@@ -1763,7 +2357,7 @@
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
-@@ -1057,6 +1105,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -1057,6 +1111,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define R200_VAP_PVS_CNTL_1 0x22D0
@@ -1795,7 +2389,7 @@
/* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
-@@ -1078,42 +1151,50 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -1078,42 +1157,50 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
@@ -1866,7 +2460,7 @@
#define CP_PACKET0( reg, n ) \
(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
#define CP_PACKET0_TABLE( reg, n ) \
-@@ -1154,23 +1235,43 @@ do { \
+@@ -1154,23 +1241,43 @@ do { \
} while (0)
#define RADEON_FLUSH_CACHE() do { \
@@ -1918,6 +2512,19 @@
} while (0)
/* ================================================================
+diff --git a/drivers/char/drm/radeon_irq.c b/drivers/char/drm/radeon_irq.c
+index 009af38..ee40d19 100644
+--- a/drivers/char/drm/radeon_irq.c
++++ b/drivers/char/drm/radeon_irq.c
+@@ -234,7 +234,7 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr
+ return radeon_wait_irq(dev, irqwait->irq_seq);
+ }
+
+-static void radeon_enable_interrupt(struct drm_device *dev)
++void radeon_enable_interrupt(struct drm_device *dev)
+ {
+ drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
+
diff --git a/drivers/char/drm/radeon_microcode.h b/drivers/char/drm/radeon_microcode.h
new file mode 100644
index 0000000..a348c9e
@@ -3769,10 +4376,53 @@
+
+#endif
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
-index 6f75512..eee1357 100644
+index 6f75512..11c146b 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
-@@ -3037,6 +3037,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
+@@ -1662,7 +1662,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
+ u32 height;
+ int i;
+ u32 texpitch, microtile;
+- u32 offset;
++ u32 offset, byte_offset;
+ RING_LOCALS;
+
+ if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
+@@ -1727,6 +1727,13 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
+ } else
+ microtile = 0;
+
++ /* this might fail for zero-sized uploads - are those illegal? */
++ if (!radeon_check_offset(dev_priv, tex->offset + image->height *
++ blit_width - 1)) {
++ DRM_ERROR("Invalid final destination offset\n");
++ return -EINVAL;
++ }
++
+ DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
+
+ do {
+@@ -1840,6 +1847,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
+ }
+
+ #undef RADEON_COPY_MT
++ byte_offset = (image->y & ~2047) * blit_width;
+ buf->file_priv = file_priv;
+ buf->used = size;
+ offset = dev_priv->gart_buffers_offset + buf->offset;
+@@ -1854,9 +1862,9 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
+ RADEON_DP_SRC_SOURCE_MEMORY |
+ RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
+ OUT_RING((spitch << 22) | (offset >> 10));
+- OUT_RING((texpitch << 22) | (tex->offset >> 10));
++ OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
+ OUT_RING(0);
+- OUT_RING((image->x << 16) | image->y);
++ OUT_RING((image->x << 16) | (image->y % 2048));
+ OUT_RING((image->width << 16) | height);
+ RADEON_WAIT_UNTIL_2D_IDLE();
+ ADVANCE_RING();
+@@ -3037,6 +3045,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
case RADEON_PARAM_FB_LOCATION:
value = radeon_read_fb_location(dev_priv);
break;
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-9/kernel.spec,v
retrieving revision 1.683
retrieving revision 1.684
diff -u -r1.683 -r1.684
--- kernel.spec 17 Jun 2008 02:17:41 -0000 1.683
+++ kernel.spec 19 Jun 2008 03:47:35 -0000 1.684
@@ -1847,6 +1847,9 @@
%kernel_variant_files -a /%{image_install_path}/xen*-%{KVERREL}.xen -e /etc/ld.so.conf.d/kernelcap-%{KVERREL}.xen.conf %{with_xen} xen
%changelog
+* Thu Jun 19 2008 Dave Airlie <airlied at redhat.com> 2.6.25.7-65
+- update radeon patches to newer upstream
+
* Mon Jun 16 2008 Chuck Ebbert <cebbert at redhat.com> 2.6.25.7-64
- Linux 2.6.25.7
- Don't apply upstream-reverts patch to -vanilla kernels.
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