rpms/xorg-x11-drv-s3/devel s3-pciaccess.patch, NONE, 1.1 xorg-x11-drv-s3.spec, 1.21, 1.22

Dave Airlie (airlied) fedora-extras-commits at redhat.com
Mon Mar 10 02:24:17 UTC 2008


Author: airlied

Update of /cvs/pkgs/rpms/xorg-x11-drv-s3/devel
In directory cvs-int.fedora.redhat.com:/tmp/cvs-serv8377

Modified Files:
	xorg-x11-drv-s3.spec 
Added Files:
	s3-pciaccess.patch 
Log Message:
* Mon Mar 10 2008 Dave Airlie <airlied at redhat.com> 0.5.0-7
- pciaccess conversion


s3-pciaccess.patch:

--- NEW FILE s3-pciaccess.patch ---
diff --git a/configure.ac b/configure.ac
index c6f47b0..461313b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -58,10 +58,22 @@ PKG_CHECK_MODULES(XORG, [xorg-server >= 1.0.99.901 xproto fontsproto $REQUIRED_M
 sdkdir=$(pkg-config --variable=sdkdir xorg-server)
 
 # Checks for libraries.
+SAVE_CPPFLAGS="$CPPFLAGS"
+CPPFLAGS="$CPPFLAGS $XORG_CFLAGS"
+AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
+              [XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
+              [#include "xorg-server.h"])
+CPPFLAGS="$SAVE_CPPFLAGS"
 
 # Checks for header files.
 AC_HEADER_STDC
 
+if test "x$XSERVER_LIBPCIACCESS" = xyes; then
+    PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.8.0])
+    XORG_CFLAGS="$XORG_CFLAGS $PCIACCESS_CFLAGS"
+fi
+AM_CONDITIONAL(XSERVER_LIBPCIACCESS, test "x$XSERVER_LIBPCIACCESS" = xyes)
+
 AC_SUBST([XORG_CFLAGS])
 AC_SUBST([moduledir])
 
diff --git a/src/s3.h b/src/s3.h
index 814b76b..444fd3e 100644
--- a/src/s3.h
+++ b/src/s3.h
@@ -30,6 +30,7 @@
 #ifndef _S3_H
 #define _S3_H
 
+#include "s3_pcirename.h"
 #include <string.h>
 
 #include "xf86.h"
@@ -86,7 +87,9 @@ typedef struct {
 
 typedef struct _S3Rec {
         pciVideoPtr             PciInfo;
+#ifndef XSERVER_LIBPCIACCESS
         PCITAG                  PciTag;
+#endif
         EntityInfoPtr           pEnt;
         unsigned long           IOAddress;
         unsigned long           FBAddress; 
@@ -164,10 +167,10 @@ typedef struct _S3Rec {
 
 
 #define DRIVER_NAME     "s3"
-#define DRIVER_VERSION  "0.5.0"
-#define VERSION_MAJOR   0
-#define VERSION_MINOR   5
-#define PATCHLEVEL      0
+#define DRIVER_VERSION  PACKAGE_VERSION
+#define VERSION_MAJOR   PACKAGE_VERSION_MAJOR
+#define VERSION_MINOR   PACKAGE_VERSION_MINOR
+#define PATCHLEVEL      PACKAGE_VERSION_PATCHLEVEL
 #define S3_VERSION     ((VERSION_MAJOR << 24) | \
                         (VERSION_MINOR << 16) | PATCHLEVEL)
 
diff --git a/src/s3_Trio64DAC.c b/src/s3_Trio64DAC.c
index cb4de3a..5bb8b3c 100644
--- a/src/s3_Trio64DAC.c
+++ b/src/s3_Trio64DAC.c
@@ -327,7 +327,7 @@ void S3Trio64DAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode)
 			       135000, 270000);
 	else if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
 		S3TrioSetClock(pScrn, mode->Clock, 2, 1, 1, 31, 0, 3, 2,
-			       170000, 270000);
+			       170000, 340000);
 	else
 		S3TrioSetClock(pScrn, mode->Clock, 2, 1, 1, 31, 0, 3, 2,
 			       135000, 270000);
diff --git a/src/s3_bios.c b/src/s3_bios.c
index 5ef1eb3..8fe14dc 100644
--- a/src/s3_bios.c
+++ b/src/s3_bios.c
@@ -46,8 +46,13 @@ static unsigned char *find_bios_string(S3Ptr pS3, int BIOSbase,
 
 	if (!init) {
 		init = 1;
+#ifndef XSERVER_LIBPCIACCESS
 		if (xf86ReadDomainMemory(pS3->PciTag, BIOSbase, BIOS_BSIZE, bios) != BIOS_BSIZE)
 			return NULL;
+#else
+		if (pci_device_read_rom(pS3->PciInfo, bios))
+		        return NULL;
+#endif
 		if ((bios[0] != 0x55) || (bios[1] != 0xaa))
 			return NULL;
 	}
diff --git a/src/s3_driver.c b/src/s3_driver.c
index 924b073..c2ec292 100644
--- a/src/s3_driver.c
+++ b/src/s3_driver.c
@@ -499,7 +499,7 @@ static Bool S3PreInit(ScrnInfoPtr pScrn, int flags)
                 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipID override: 0x%04X\n",
                            pS3->Chipset);
         } else {
-                pS3->Chipset = pS3->PciInfo->chipType;   
+  	        pS3->Chipset = PCI_DEV_DEVICE_ID(pS3->PciInfo);
                 pScrn->chipset = (char *)xf86TokenToString(S3Chipsets,
                                                            pS3->Chipset);
         }                                                  
@@ -508,14 +508,16 @@ static Bool S3PreInit(ScrnInfoPtr pScrn, int flags)
                 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipRev override: %d\n",
                            pS3->ChipRev);
         } else
-                pS3->ChipRev = pS3->PciInfo->chipRev;    
+	        pS3->ChipRev = PCI_DEV_REVISION(pS3->PciInfo);
         
         xfree(pEnt);
         
         xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Chipset: \"%s\"\n", pScrn->chipset);
         
+#ifndef XSERVER_LIBPCIACCESS
         pS3->PciTag = pciTag(pS3->PciInfo->bus, pS3->PciInfo->device,
                              pS3->PciInfo->func);        
+#endif
 
 	switch (pS3->Chipset) {
 	case PCI_CHIP_964_0:
@@ -531,7 +533,7 @@ static Bool S3PreInit(ScrnInfoPtr pScrn, int flags)
 		break;
 	}
 
-	pS3->FBAddress = pS3->PciInfo->memBase[0];
+	pS3->FBAddress = PCI_REGION_BASE(pS3->PciInfo, 0, REGION_MEM);
 	pScrn->memPhysBase = pS3->FBAddress;
 	pScrn->fbOffset = 0;
 	
@@ -1016,9 +1018,25 @@ static Bool S3MapMem(ScrnInfoPtr pScrn)
 	S3Ptr pS3 = S3PTR(pScrn);
 
 	if (pS3->S3NewMMIO) {
+
+
+#ifndef XSERVER_LIBPCIACCESS
 		pS3->MMIOBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_MMIO,
 					      pS3->PciTag, pS3->IOAddress,
 					      S3_NEWMMIO_REGSIZE);
+#else
+		{
+			void** result = (void**)&pS3->MMIOBase;
+			int err = pci_device_map_range(pS3->PciInfo,
+						       pS3->IOAddress,
+						       S3_NEWMMIO_REGSIZE,
+						       PCI_DEV_MAP_FLAG_WRITABLE,
+						       result);
+			
+			if (err) 
+				return FALSE;
+		}
+#endif
 		if (!pS3->MMIOBase) {
 			xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 				   "Could not map MMIO\n");
@@ -1026,9 +1044,25 @@ static Bool S3MapMem(ScrnInfoPtr pScrn)
 		}
 	}
 
+#ifndef XSERVER_LIBPCIACCESS
 	pS3->FBBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER,
 				    pS3->PciTag, pS3->FBAddress,
 				    pScrn->videoRam * 1024);
+
+#else
+	{
+		void** result = (void**)&pS3->FBBase;
+		int err = pci_device_map_range(pS3->PciInfo,
+					       pS3->FBAddress,
+					       pS3->videoRam * 1024,
+					       PCI_DEV_MAP_FLAG_WRITABLE |
+					       PCI_DEV_MAP_FLAG_WRITE_COMBINE,
+					       result);
+		
+		if (err) 
+			return FALSE;
+	}
+#endif
 	if (!pS3->FBBase) {
 		xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 			   "Could not map framebuffer\n");
@@ -1045,11 +1079,21 @@ static void S3UnmapMem(ScrnInfoPtr pScrn)
 {
 	S3Ptr pS3 = S3PTR(pScrn);
 
-	if (pS3->S3NewMMIO)
+	if (pS3->S3NewMMIO) {
+#ifndef XSERVER_LIBPCIACCESS
 		xf86UnMapVidMem(pScrn->scrnIndex, (pointer)pS3->MMIOBase,
 				S3_NEWMMIO_REGSIZE);
+#else
+		pci_device_unmap_range(pS3->PciInfo, pS3->MMIOBase, S3_NEWMMIO_REGSIZE);
+#endif
+	}
+	
+#ifndef XSERVER_LIBPCIACCESS
 	xf86UnMapVidMem(pScrn->scrnIndex, (pointer)pS3->FBBase,
 			pScrn->videoRam * 1024);
+#else
+	pci_device_unmap_range(pS3->PciInfo, pS3->FBBase, pScrn->videoRam * 1024);
+#endif
 
 	return;
 }
@@ -1847,11 +1891,47 @@ void S3BankZero(ScrnInfoPtr pScrn)
 	outb(vgaCRReg, tmp);
 }
 
-
-
-static void S3DisplayPowerManagementSet(ScrnInfoPtr pScrn,
-					int PowerManagementMode, int flags)
+static void
+S3DisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode,
+			    int flags)
 {
-	vgaHWDPMSSet(pScrn, PowerManagementMode, flags);
+     S3Ptr pS3 = S3PTR(pScrn);
+     switch (pS3->Chipset) {
+     case PCI_CHIP_TRIO64V2_DXGX:
+     case PCI_CHIP_TRIO:
+     case PCI_CHIP_AURORA64VP:
+     case PCI_CHIP_TRIO64UVP:
+     {
+	  int srd;
+      
+	  outb(0x3c4, 0x08);
+	  outb(0x3c5, 0x06);	  /* unlock extended sequence registers */
+
+	  outb(0x3c4, 0x0d);
+	  srd = inb(0x3c5) & 0xf;  /* clear the sync control bits */
+  
+	  switch (PowerManagementMode) {
+	  case DPMSModeOn:
+	       /* Screen: On; HSync: On, VSync: On */
+	       break;
+	  case DPMSModeStandby:
+	       /* Screen: Off; HSync: Off, VSync: On */
+	       srd |= 0x10;
+	       break;
+	  case DPMSModeSuspend:
+	       /* Screen: Off; HSync: On, VSync: Off */
+	       srd |= 0x40;
+	       break;
+	  case DPMSModeOff:
+	       /* Screen: Off; HSync: Off, VSync: Off */
+	       srd |= 0x50;
+	       break;
+	  }
+	  outb(0x3c4, 0x0d);
+	  outb(0x3c5, srd);
+	  break;
+     }
+     default:
+	  vgaHWDPMSSet(pScrn, PowerManagementMode, flags);
+     }
 }
-
diff --git a/src/s3_pcirename.h b/src/s3_pcirename.h
new file mode 100644
index 0000000..9321046
--- /dev/null
+++ b/src/s3_pcirename.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2007 George Sapountzis
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+ * Macros for porting drivers from legacy xfree86 PCI code to the pciaccess
+ * library. The main purpose being to facilitate source code compatibility.
+ */
+
+#ifndef S3PCIRENAME_H
+#define S3PCIRENAME_H
+
+enum region_type {
+    REGION_MEM,
+    REGION_IO 
+};
+
+#ifndef XSERVER_LIBPCIACCESS
+
+/* pciVideoPtr */
+#define PCI_DEV_VENDOR_ID(_pcidev) ((_pcidev)->vendor)
+#define PCI_DEV_DEVICE_ID(_pcidev) ((_pcidev)->chipType)
+#define PCI_DEV_REVISION(_pcidev)  ((_pcidev)->chipRev)
+
+#define PCI_SUB_VENDOR_ID(_pcidev) ((_pcidev)->subsysVendor)
+#define PCI_SUB_DEVICE_ID(_pcidev) ((_pcidev)->subsysCard)
+
+#define PCI_DEV_TAG(_pcidev) pciTag((_pcidev)->bus,    \
+                                    (_pcidev)->device, \
+                                    (_pcidev)->func)
+#define PCI_DEV_BUS(_pcidev)       ((_pcidev)->bus)
+#define PCI_DEV_DEV(_pcidev)       ((_pcidev)->device)
+#define PCI_DEV_FUNC(_pcidev)      ((_pcidev)->func)
+
+/* pciConfigPtr */
+#define PCI_CFG_TAG(_pcidev)  (((pciConfigPtr)(_pcidev)->thisCard)->tag)
+#define PCI_CFG_BUS(_pcidev)  (((pciConfigPtr)(_pcidev)->thisCard)->busnum)
+#define PCI_CFG_DEV(_pcidev)  (((pciConfigPtr)(_pcidev)->thisCard)->devnum)
+#define PCI_CFG_FUNC(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->funcnum)
+
+/* region addr: xfree86 uses different fields for memory regions and I/O ports */
+#define PCI_REGION_BASE(_pcidev, _b, _type)             \
+    (((_type) == REGION_MEM) ? (_pcidev)->memBase[(_b)] \
+                             : (_pcidev)->ioBase[(_b)])
+
+/* region size: xfree86 uses the log2 of the region size,
+ * but with zero meaning no region, not size of one XXX */
+#define PCI_REGION_SIZE(_pcidev, _b) \
+    (((_pcidev)->size[(_b)] > 0) ? (1 << (_pcidev)->size[(_b)]) : 0)
+
+/* read/write PCI configuration space */
+#define PCI_READ_BYTE(_pcidev, _value_ptr, _offset) \
+    *(_value_ptr) = pciReadByte(PCI_CFG_TAG(_pcidev), (_offset))
+
+#define PCI_READ_LONG(_pcidev, _value_ptr, _offset) \
+    *(_value_ptr) = pciReadLong(PCI_CFG_TAG(_pcidev), (_offset))
+
+#define PCI_WRITE_LONG(_pcidev, _value, _offset) \
+    pciWriteLong(PCI_CFG_TAG(_pcidev), (_offset), (_value))
+
+#else /* XSERVER_LIBPCIACCESS */
+
+typedef struct pci_device *pciVideoPtr;
+
+#define PCI_DEV_VENDOR_ID(_pcidev) ((_pcidev)->vendor_id)
+#define PCI_DEV_DEVICE_ID(_pcidev) ((_pcidev)->device_id)
+#define PCI_DEV_REVISION(_pcidev)  ((_pcidev)->revision)
+
+#define PCI_SUB_VENDOR_ID(_pcidev) ((_pcidev)->subvendor_id)
+#define PCI_SUB_DEVICE_ID(_pcidev) ((_pcidev)->subdevice_id)
+
+/* pci-rework functions take a 'pci_device' parameter instead of a tag */
+#define PCI_DEV_TAG(_pcidev)        (_pcidev)
+
+/* PCI_DEV macros, typically used in printf's, add domain ? XXX */
+#define PCI_DEV_BUS(_pcidev)       ((_pcidev)->bus)
+#define PCI_DEV_DEV(_pcidev)       ((_pcidev)->dev)
+#define PCI_DEV_FUNC(_pcidev)      ((_pcidev)->func)
+
+/* pci-rework functions take a 'pci_device' parameter instead of a tag */
+#define PCI_CFG_TAG(_pcidev)        (_pcidev)
+
+/* PCI_CFG macros, typically used in DRI init, contain the domain */
+#define PCI_CFG_BUS(_pcidev)      (((_pcidev)->domain << 8) | \
+                                    (_pcidev)->bus)
+#define PCI_CFG_DEV(_pcidev)       ((_pcidev)->dev)
+#define PCI_CFG_FUNC(_pcidev)      ((_pcidev)->func)
+
+#define PCI_REGION_BASE(_pcidev, _b, _type) ((_pcidev)->regions[(_b)].base_addr)
+#define PCI_REGION_SIZE(_pcidev, _b)        ((_pcidev)->regions[(_b)].size)
+
+#define PCI_READ_BYTE(_pcidev, _value_ptr, _offset) \
+    pci_device_cfg_read_u8((_pcidev), (_value_ptr), (_offset))
+
+#define PCI_READ_LONG(_pcidev, _value_ptr, _offset) \
+    pci_device_cfg_read_u32((_pcidev), (_value_ptr), (_offset))
+
+#define PCI_WRITE_LONG(_pcidev, _value, _offset) \
+    pci_device_cfg_write_u32((_pcidev), (_value), (_offset))
+
+#endif /* XSERVER_LIBPCIACCESS */
+
+#endif /* CIRPCIRENAME_H */
diff --git a/src/s3_video.c b/src/s3_video.c
index 77f4930..8189fdf 100644
--- a/src/s3_video.c
+++ b/src/s3_video.c
@@ -30,6 +30,8 @@
 #include "config.h"
 #endif
 
+#define S3_NEWMMIO	/* previously defined in Imakefile in monolith */
+
 #include "xf86.h"
 #include "xf86_OSproc.h"
 


Index: xorg-x11-drv-s3.spec
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-s3/devel/xorg-x11-drv-s3.spec,v
retrieving revision 1.21
retrieving revision 1.22
diff -u -r1.21 -r1.22
--- xorg-x11-drv-s3.spec	20 Feb 2008 07:41:21 -0000	1.21
+++ xorg-x11-drv-s3.spec	10 Mar 2008 02:23:40 -0000	1.22
@@ -5,7 +5,7 @@
 Summary:   Xorg X11 s3 video driver
 Name:      xorg-x11-drv-s3
 Version:   0.5.0
-Release:   6%{?dist}
+Release:   7%{?dist}
 URL:       http://www.x.org
 License: MIT
 Group:     User Interface/X Hardware Support
@@ -15,9 +15,11 @@
 Source1:   s3.xinf
 
 Patch0: s3-0.5.0-newmmio.patch
+Patch1: s3-pciaccess.patch
 
 ExcludeArch: s390 s390x
 
+BuildRequires: automake autoconf libtool
 BuildRequires: xorg-x11-server-sdk >= 1.3.0.0-6
 
 Requires: hwdata
@@ -28,15 +30,17 @@
 
 %prep
 %setup -q -n %{tarball}-%{version}
-%patch -p1 -b .newmmio
+%patch0 -p1 -b .newmmio
+%patch1 -p1 -b .pciaccess
 
 %build
+autoreconf -v --install
 %configure --disable-static
 make
 
 %install
 rm -rf $RPM_BUILD_ROOT
-
+autoreconf -v --install
 make install DESTDIR=$RPM_BUILD_ROOT
 
 mkdir -p $RPM_BUILD_ROOT%{_datadir}/hwdata/videoaliases
@@ -55,6 +59,9 @@
 %{_datadir}/hwdata/videoaliases/s3.xinf
 
 %changelog
+* Mon Mar 10 2008 Dave Airlie <airlied at redhat.com> 0.5.0-7
+- pciaccess conversion
+
 * Wed Feb 20 2008 Fedora Release Engineering <rel-eng at fedoraproject.org> - 0.5.0-6
 - Autorebuild for GCC 4.3
 




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