rpms/xorg-x11-drv-chips/devel chips-pciaccess.patch, NONE, 1.1 xorg-x11-drv-chips.spec, 1.15, 1.16
Dave Airlie (airlied)
fedora-extras-commits at redhat.com
Mon Mar 10 04:40:46 UTC 2008
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Author: airlied
Update of /cvs/pkgs/rpms/xorg-x11-drv-chips/devel
In directory cvs-int.fedora.redhat.com:/tmp/cvs-serv27553
Modified Files:
xorg-x11-drv-chips.spec
Added Files:
chips-pciaccess.patch
Log Message:
* Mon Mar 10 2008 Dave Airlie <airlied at redhat.com> 1.1.1-7
- pciaccess conversion
chips-pciaccess.patch:
--- NEW FILE chips-pciaccess.patch ---
diff --git a/configure.ac b/configure.ac
index d5e02ba..8c87eb0 100644
--- a/configure.ac
+++ b/configure.ac
@@ -58,6 +58,20 @@ PKG_CHECK_MODULES(XORG, [xorg-server >= 1.0.99.901 xproto fontsproto $REQUIRED_M
sdkdir=$(pkg-config --variable=sdkdir xorg-server)
# Checks for libraries.
+SAVE_CPPFLAGS="$CPPFLAGS"
+CPPFLAGS="$CPPFLAGS $XORG_CFLAGS"
+AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
+ [XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
+ [#include "xorg-server.h"])
+AC_CHECK_HEADER(xf1bpp.h,[AC_DEFINE(HAVE_XF1BPP, 1, [Have 1bpp support])],[])
+AC_CHECK_HEADER(xf4bpp.h,[AC_DEFINE(HAVE_XF4BPP, 1, [Have 4bpp support])],[])
+CPPFLAGS="$SAVE_CPPFLAGS"
+
+if test "x$XSERVER_LIBPCIACCESS" = xyes; then
+ PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.8.0])
+ XORG_CFLAGS="$XORG_CFLAGS $PCIACCESS_CFLAGS"
+fi
+AM_CONDITIONAL(XSERVER_LIBPCIACCESS, test "x$XSERVER_LIBPCIACCESS" = xyes)
# Checks for header files.
AC_HEADER_STDC
diff --git a/src/ct_accel.c b/src/ct_accel.c
index d56f009..1ccb480 100644
--- a/src/ct_accel.c
+++ b/src/ct_accel.c
@@ -1182,7 +1182,7 @@ CTNAME(CacheMonoStipple)(ScrnInfoPtr pScrn, PixmapPtr pPix)
} else funcNo = 2;
pad = (((pCache->w * bpp) + 31) >> 5) << 2;
- dstPtr = data = (unsigned char*)ALLOCATE_LOCAL(pad * pCache->h);
+ dstPtr = data = (unsigned char*)xalloc(pad * pCache->h);
srcPtr = (unsigned char*)pPix->devPrivate.ptr;
StippleFunc = StippleTab[funcNo];
@@ -1210,7 +1210,7 @@ CTNAME(CacheMonoStipple)(ScrnInfoPtr pScrn, PixmapPtr pPix)
pScrn, pCache->x, pCache->y, pCache->w, pCache->h, data,
pad, bpp, pScrn->depth);
- DEALLOCATE_LOCAL(data);
+ xfree(data);
return pCache;
}
diff --git a/src/ct_driver.c b/src/ct_driver.c
index e905603..c05798f 100644
--- a/src/ct_driver.c
+++ b/src/ct_driver.c
@@ -113,8 +113,12 @@
/* Needed for the 1 and 4 bpp framebuffers */
+#ifdef HAVE_XF1BPP
#include "xf1bpp.h"
+#endif
+#ifdef HAVE_XF4BPP
#include "xf4bpp.h"
+#endif
/* Needed by Resources Access Control (RAC) */
#include "xf86RAC.h"
@@ -137,7 +141,12 @@
/* Mandatory functions */
static const OptionInfoRec * CHIPSAvailableOptions(int chipid, int busid);
static void CHIPSIdentify(int flags);
+#ifdef XSERVER_LIBPCIACCESS
+static Bool CHIPSPciProbe(DriverPtr drv, int entity_num,
+ struct pci_device *dev, intptr_t match_data);
+#else
static Bool CHIPSProbe(DriverPtr drv, int flags);
+#endif
static Bool CHIPSPreInit(ScrnInfoPtr pScrn, int flags);
static Bool CHIPSScreenInit(int Index, ScreenPtr pScreen, int argc,
char **argv);
@@ -465,9 +474,28 @@ static DisplayModeRec ChipsNTSCMode = {
#define CHIPS_VERSION 4000
#define CHIPS_NAME "CHIPS"
#define CHIPS_DRIVER_NAME "chips"
-#define CHIPS_MAJOR_VERSION 1
-#define CHIPS_MINOR_VERSION 1
-#define CHIPS_PATCHLEVEL 1
+#define CHIPS_MAJOR_VERSION PACKAGE_VERSION_MAJOR
+#define CHIPS_MINOR_VERSION PACKAGE_VERSION_MINOR
+#define CHIPS_PATCHLEVEL PACKAGE_VERSION_PATCHLEVEL
+
+
+#ifdef XSERVER_LIBPCIACCESS
+
+#define CHIPS_DEVICE_MATCH(d, i) \
+ { PCI_VENDOR_CHIPSTECH, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (i) }
+
+static const struct pci_id_match chips_device_match[] = {
+ CHIPS_DEVICE_MATCH(PCI_CHIP_65545, 0),
+ CHIPS_DEVICE_MATCH(PCI_CHIP_65548, 0),
+ CHIPS_DEVICE_MATCH(PCI_CHIP_65550, 0),
+ CHIPS_DEVICE_MATCH(PCI_CHIP_65554, 0),
+ CHIPS_DEVICE_MATCH(PCI_CHIP_65555, 0),
+ CHIPS_DEVICE_MATCH(PCI_CHIP_68554, 0),
+ CHIPS_DEVICE_MATCH(PCI_CHIP_69000, 0),
+ CHIPS_DEVICE_MATCH(PCI_CHIP_69030, 0),
+ { 0, 0, 0 },
+};
+#endif
/*
* This contains the functions needed by the server after loading the driver
@@ -481,10 +509,20 @@ _X_EXPORT DriverRec CHIPS = {
CHIPS_VERSION,
CHIPS_DRIVER_NAME,
CHIPSIdentify,
+#ifdef XSERVER_LIBPCIACCESS
+ NULL,
+#else
CHIPSProbe,
+#endif
CHIPSAvailableOptions,
NULL,
- 0
+ 0,
+ NULL,
+
+#ifdef XSERVER_LIBPCIACCESS
+ chips_device_match,
+ CHIPSPciProbe,
+#endif
};
static SymTabRec CHIPSChipsets[] = {
@@ -507,6 +545,7 @@ static SymTabRec CHIPSChipsets[] = {
{ -1, NULL }
};
+
/* Conversion PCI ID to chipset name */
static PciChipsets CHIPSPCIchipsets[] = {
{ CHIPS_CT65545, PCI_CHIP_65545, RES_SHARED_VGA },
@@ -685,8 +724,12 @@ static const char *vgahwSymbols[] = {
#ifdef XFree86LOADER
static const char *miscfbSymbols[] = {
+#ifdef HAVE_XF1BPP
"xf1bppScreenInit",
+#endif
+#ifdef HAVE_XF4BPP
"xf4bppScreenInit",
+#endif
"cfb8_16ScreenInit",
NULL
};
@@ -854,6 +897,68 @@ CHIPSAvailableOptions(int chipid, int busid)
}
/* Mandatory */
+#ifdef XSERVER_LIBPCIACCESS
+Bool
+CHIPSPciProbe(DriverPtr drv, int entity_num, struct pci_device * dev,
+ intptr_t match_data)
+{
+ ScrnInfoPtr pScrn = NULL;
+ EntityInfoPtr pEnt;
+ CHIPSPtr cPtr;
+
+ /* Allocate a ScrnInfoRec and claim the slot */
+ pScrn = xf86ConfigPciEntity(pScrn, 0, entity_num, CHIPSPCIchipsets, NULL,
+ NULL, NULL, NULL, NULL);
+ if (pScrn != NULL) {
+ /* Fill in what we can of the ScrnInfoRec */
+ pScrn->driverVersion = CHIPS_VERSION;
+ pScrn->driverName = CHIPS_DRIVER_NAME;
+ pScrn->name = CHIPS_NAME;
+ pScrn->Probe = NULL;
+ pScrn->PreInit = CHIPSPreInit;
+ pScrn->ScreenInit = CHIPSScreenInit;
+ pScrn->SwitchMode = CHIPSSwitchMode;
+ pScrn->AdjustFrame = CHIPSAdjustFrame;
+ pScrn->EnterVT = CHIPSEnterVT;
+ pScrn->LeaveVT = CHIPSLeaveVT;
+ pScrn->FreeScreen = CHIPSFreeScreen;
+ pScrn->ValidMode = CHIPSValidMode;
+
+ /*
+ * For cards that can do dual head per entity, mark the entity
+ * as sharable.
+ */
+ pEnt = xf86GetEntityInfo(entity_num);
+ if (pEnt->chipset == CHIPS_CT69030) {
+ CHIPSEntPtr cPtrEnt = NULL;
+ DevUnion *pPriv;
+
+ xf86SetEntitySharable(entity_num);
+ /* Allocate an entity private if necessary */
+ if (CHIPSEntityIndex < 0)
+ CHIPSEntityIndex = xf86AllocateEntityPrivateIndex();
+ pPriv = xf86GetEntityPrivate(pScrn->entityList[0], CHIPSEntityIndex);
+ if (!pPriv->ptr) {
+ pPriv->ptr = xnfcalloc(sizeof(CHIPSEntRec), 1);
+ cPtrEnt = pPriv->ptr;
+ cPtrEnt->lastInstance = -1;
+ } else {
+ cPtrEnt = pPriv->ptr;
+ }
+ /*
+ * Set the entity instance for this instance of the driver. For
+ * dual head per card, instance 0 is the "master" instance, driving
+ * the primary head, and instance 1 is the "slave".
+ */
+ cPtrEnt->lastInstance++;
+ xf86SetEntityInstanceForScreen(pScrn, pScrn->entityList[0],
+ cPtrEnt->lastInstance);
+ }
+ }
+
+ return (pScrn != NULL);
+}
+#else
static Bool
CHIPSProbe(DriverPtr drv, int flags)
{
@@ -974,6 +1079,7 @@ CHIPSProbe(DriverPtr drv, int flags)
xfree(devSections);
return foundScreen;
}
+#endif
static int
chipsFindIsaDevice(GDevPtr dev)
@@ -1107,9 +1213,11 @@ CHIPSPreInit(ScrnInfoPtr pScrn, int flags)
if (cPtr->pEnt->location.type == BUS_PCI) {
pciPtr = xf86GetPciInfoForEntity(cPtr->pEnt->index);
cPtr->PciInfo = pciPtr;
+#ifndef XSERVER_LIBPCIACCESS
cPtr->PciTag = pciTag(cPtr->PciInfo->bus,
cPtr->PciInfo->device,
cPtr->PciInfo->func);
+#endif
}
}
/* INT10 */
@@ -1290,6 +1398,7 @@ CHIPSPreInit(ScrnInfoPtr pScrn, int flags)
/* Load bpp-specific modules */
switch (pScrn->bitsPerPixel) {
+#ifdef HAVE_XF1BPP
case 1:
if (xf86LoadSubModule(pScrn, "xf1bpp") == NULL) {
vbeFree(cPtr->pVbe);
@@ -1299,6 +1408,8 @@ CHIPSPreInit(ScrnInfoPtr pScrn, int flags)
}
xf86LoaderReqSymbols("xf1bppScreenInit", NULL);
break;
+#endif
+#ifdef HAVE_XF4BPP
case 4:
if (xf86LoadSubModule(pScrn, "xf4bpp") == NULL) {
vbeFree(cPtr->pVbe);
@@ -1308,6 +1419,7 @@ CHIPSPreInit(ScrnInfoPtr pScrn, int flags)
}
xf86LoaderReqSymbols("xf4bppScreenInit", NULL);
break;
+#endif
case 16:
if (cPtr->Flags & ChipsOverlay8plus16) {
if (xf86LoadSubModule(pScrn, "xf8_16bpp") == NULL) {
@@ -1536,10 +1648,10 @@ chipsPreInitHiQV(ScrnInfoPtr pScrn, int flags)
/* Tack on 0x800000 to access the big-endian aperture? */
#if X_BYTE_ORDER == X_BIG_ENDIAN
if (BE_SWAP_APRETURE(pScrn,cPtr))
- cPtr->FbAddress = (cPtr->PciInfo->memBase[0] & 0xff800000) + 0x800000L;
+ cPtr->FbAddress = (PCI_REGION_BASE(cPtr->PciInfo, 0, REGION_MEM) & 0xff800000) + 0x800000L;
else
#endif
- cPtr->FbAddress = cPtr->PciInfo->memBase[0] & 0xff800000;
+ cPtr->FbAddress = PCI_REGION_BASE(cPtr->PciInfo, 0, REGION_MEM) & 0xff800000;
from = X_PROBED;
if (xf86RegisterResources(cPtr->pEnt->index,NULL,ResNone))
@@ -3108,7 +3220,7 @@ chipsPreInit655xx(ScrnInfoPtr pScrn, int flags)
mask &= 0xCF;
}
if (cPtr->pEnt->location.type == BUS_PCI) {
- cPtr->FbAddress = cPtr->PciInfo->memBase[0] & 0xff800000;
+ cPtr->FbAddress = PCI_REGION_BASE(cPtr->PciInfo, 0, REGION_MEM) & 0xff800000;
if (xf86RegisterResources(cPtr->pEnt->index,NULL,ResNone))
useLinear = FALSE;
from = X_PROBED;
@@ -4014,18 +4126,22 @@ CHIPSScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
}
switch (pScrn->bitsPerPixel) {
+#ifdef HAVE_XF1BPP
case 1:
ret = xf1bppScreenInit(pScreen, FBStart,
width,height,
pScrn->xDpi, pScrn->yDpi,
displayWidth);
break;
+#endif
+#ifdef HAVE_XF4BPP
case 4:
ret = xf4bppScreenInit(pScreen, FBStart,
width,height,
pScrn->xDpi, pScrn->yDpi,
displayWidth);
break;
+#endif
case 16:
if (cPtr->Flags & ChipsOverlay8plus16) {
ret = cfb8_16ScreenInit(pScreen, (unsigned char *)FBStart +
@@ -7028,6 +7144,7 @@ chipsMapMem(ScrnInfoPtr pScrn)
if (cPtr->Flags & ChipsLinearSupport) {
if (cPtr->UseMMIO) {
if (IS_HiQV(cPtr)) {
+#ifndef XSERVER_LIBPCIACCESS
if (cPtr->pEnt->location.type == BUS_PCI)
cPtr->MMIOBase = xf86MapPciMem(pScrn->scrnIndex,
VIDMEM_MMIO_32BIT,cPtr->PciTag, cPtr->IOAddress,
@@ -7035,7 +7152,20 @@ chipsMapMem(ScrnInfoPtr pScrn)
else
cPtr->MMIOBase = xf86MapVidMem(pScrn->scrnIndex,
VIDMEM_MMIO_32BIT, cPtr->IOAddress, 0x20000L);
+#else
+ {
+ void** result = (void**)&cPtr->MMIOBase;
+ int err = pci_device_map_range(cPtr->PciInfo,
+ cPtr->IOAddress,
+ 0x20000L,
+ PCI_DEV_MAP_FLAG_WRITABLE,
+ result);
+ if (err)
+ return FALSE;
+ }
+#endif
} else {
+#ifndef XSERVER_LIBPCIACCESS
if (cPtr->pEnt->location.type == BUS_PCI)
cPtr->MMIOBase = xf86MapPciMem(pScrn->scrnIndex,
VIDMEM_MMIO_32BIT, cPtr->PciTag, cPtr->IOAddress,
@@ -7043,6 +7173,18 @@ chipsMapMem(ScrnInfoPtr pScrn)
else
cPtr->MMIOBase = xf86MapVidMem(pScrn->scrnIndex,
VIDMEM_MMIO_32BIT, cPtr->IOAddress, 0x10000L);
+#else
+ {
+ void** result = (void**)&cPtr->MMIOBase;
+ int err = pci_device_map_range(cPtr->PciInfo,
+ cPtr->IOAddress,
+ 0x10000L,
+ PCI_DEV_MAP_FLAG_WRITABLE,
+ result);
+ if (err)
+ return FALSE;
+ }
+#endif
}
if (cPtr->MMIOBase == NULL)
@@ -7065,6 +7207,7 @@ chipsMapMem(ScrnInfoPtr pScrn)
}
}
+#ifndef XSERVER_LIBPCIACCESS
if (cPtr->pEnt->location.type == BUS_PCI)
cPtr->FbBase = xf86MapPciMem(pScrn->scrnIndex,VIDMEM_FRAMEBUFFER,
cPtr->PciTag, Addr, Map);
@@ -7072,14 +7215,32 @@ chipsMapMem(ScrnInfoPtr pScrn)
else
cPtr->FbBase = xf86MapVidMem(pScrn->scrnIndex,VIDMEM_FRAMEBUFFER,
Addr, Map);
+#else
+ {
+ void** result = (void**)&cPtr->FbBase;
+ int err = pci_device_map_range(cPtr->PciInfo,
+ Addr,
+ Map,
+ PCI_DEV_MAP_FLAG_WRITABLE |
+ PCI_DEV_MAP_FLAG_WRITE_COMBINE,
+ result);
+ if (err)
+ return FALSE;
+ }
+
+#endif
if (cPtr->FbBase == NULL)
return FALSE;
}
if (cPtr->Flags & ChipsFullMMIOSupport) {
+#ifndef XSERVER_LIBPCIACCESS
cPtr->MMIOBaseVGA = xf86MapPciMem(pScrn->scrnIndex,
VIDMEM_MMIO,cPtr->PciTag,
cPtr->IOAddress, 0x2000L);
+#else
+ cPtr->MMIOBaseVGA = cPtr->MMIOBase;
+#endif
/* 69030 MMIO Fix.
*
* The hardware lets us map the PipeB data registers
@@ -7089,9 +7250,22 @@ chipsMapMem(ScrnInfoPtr pScrn)
* pipe and to toggle between them as necessary. -GHB
*/
if (cPtr->Flags & ChipsDualChannelSupport)
+#ifndef XSERVER_LIBPCIACCESS
cPtr->MMIOBasePipeB = xf86MapPciMem(pScrn->scrnIndex,
VIDMEM_MMIO,cPtr->PciTag,
cPtr->IOAddress + 0x800000, 0x2000L);
+#else
+ {
+ void** result = (void**)&cPtr->MMIOBasePipeB;
+ int err = pci_device_map_range(cPtr->PciInfo,
+ cPtr->IOAddress + 0x800000,
+ 0x2000L,
+ PCI_DEV_MAP_FLAG_WRITABLE,
+ result);
+ if (err)
+ return FALSE;
+ }
+#endif
cPtr->MMIOBasePipeA = cPtr->MMIOBaseVGA;
}
@@ -7115,21 +7289,39 @@ chipsUnmapMem(ScrnInfoPtr pScrn)
if (cPtr->Flags & ChipsLinearSupport) {
if (IS_HiQV(cPtr)) {
+#ifndef XSERVER_LIBPCIACCESS
if (cPtr->MMIOBase)
xf86UnMapVidMem(pScrn->scrnIndex, (pointer)cPtr->MMIOBase,
0x20000);
if (cPtr->MMIOBasePipeB)
xf86UnMapVidMem(pScrn->scrnIndex, (pointer)cPtr->MMIOBasePipeB,
0x20000);
+#else
+ if (cPtr->MMIOBase)
+ pci_device_unmap_range(cPtr->PciInfo, cPtr->MMIOBase, 0x20000);
+
+ if (cPtr->MMIOBasePipeB)
+ pci_device_unmap_range(cPtr->PciInfo, cPtr->MMIOBasePipeB, 0x2000);
+
+#endif
cPtr->MMIOBasePipeB = NULL;
} else {
+#ifndef XSERVER_LIBPCIACCESS
if (cPtr->MMIOBase)
xf86UnMapVidMem(pScrn->scrnIndex, (pointer)cPtr->MMIOBase,
0x10000);
+#else
+ if (cPtr->MMIOBase)
+ pci_device_unmap_range(cPtr->PciInfo, cPtr->MMIOBase, 0x10000);
+#endif
}
cPtr->MMIOBase = NULL;
+#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(pScrn->scrnIndex, (pointer)cPtr->FbBase,
cPtr->FbMapSize);
+#else
+ pci_device_unmap_range(cPtr->PciInfo, cPtr->FbBase, cPtr->FbMapSize);
+#endif
}
cPtr->FbBase = NULL;
diff --git a/src/ct_driver.h b/src/ct_driver.h
index 0c5b604..2b5dc7a 100644
--- a/src/ct_driver.h
+++ b/src/ct_driver.h
@@ -28,6 +28,7 @@
#ifndef _CT_DRIVER_H_
#define _CT_DRIVER_H_
+#include "ct_pcirename.h"
#include "xaa.h"
#include "vbe.h"
#include "xaalocal.h" /* XAA internals as we replace some of XAA */
diff --git a/src/ct_pcirename.h b/src/ct_pcirename.h
new file mode 100644
index 0000000..f0f5cf8
--- /dev/null
+++ b/src/ct_pcirename.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2007 George Sapountzis
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+ * Macros for porting drivers from legacy xfree86 PCI code to the pciaccess
+ * library. The main purpose being to facilitate source code compatibility.
+ */
+
+#ifndef CIRPCIRENAME_H
+#define CIRPCIRENAME_H
+
+enum region_type {
+ REGION_MEM,
+ REGION_IO
+};
+
+#ifndef XSERVER_LIBPCIACCESS
+
+/* pciVideoPtr */
+#define PCI_DEV_VENDOR_ID(_pcidev) ((_pcidev)->vendor)
+#define PCI_DEV_DEVICE_ID(_pcidev) ((_pcidev)->chipType)
+#define PCI_DEV_REVISION(_pcidev) ((_pcidev)->chipRev)
+
+#define PCI_SUB_VENDOR_ID(_pcidev) ((_pcidev)->subsysVendor)
+#define PCI_SUB_DEVICE_ID(_pcidev) ((_pcidev)->subsysCard)
+
+#define PCI_DEV_TAG(_pcidev) pciTag((_pcidev)->bus, \
+ (_pcidev)->device, \
+ (_pcidev)->func)
+#define PCI_DEV_BUS(_pcidev) ((_pcidev)->bus)
+#define PCI_DEV_DEV(_pcidev) ((_pcidev)->device)
+#define PCI_DEV_FUNC(_pcidev) ((_pcidev)->func)
+
+/* pciConfigPtr */
+#define PCI_CFG_TAG(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->tag)
+#define PCI_CFG_BUS(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->busnum)
+#define PCI_CFG_DEV(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->devnum)
+#define PCI_CFG_FUNC(_pcidev) (((pciConfigPtr)(_pcidev)->thisCard)->funcnum)
+
+/* region addr: xfree86 uses different fields for memory regions and I/O ports */
+#define PCI_REGION_BASE(_pcidev, _b, _type) \
+ (((_type) == REGION_MEM) ? (_pcidev)->memBase[(_b)] \
+ : (_pcidev)->ioBase[(_b)])
+
+/* region size: xfree86 uses the log2 of the region size,
+ * but with zero meaning no region, not size of one XXX */
+#define PCI_REGION_SIZE(_pcidev, _b) \
+ (((_pcidev)->size[(_b)] > 0) ? (1 << (_pcidev)->size[(_b)]) : 0)
+
+/* read/write PCI configuration space */
+#define PCI_READ_BYTE(_pcidev, _value_ptr, _offset) \
+ *(_value_ptr) = pciReadByte(PCI_CFG_TAG(_pcidev), (_offset))
+
+#define PCI_READ_LONG(_pcidev, _value_ptr, _offset) \
+ *(_value_ptr) = pciReadLong(PCI_CFG_TAG(_pcidev), (_offset))
+
+#define PCI_WRITE_LONG(_pcidev, _value, _offset) \
+ pciWriteLong(PCI_CFG_TAG(_pcidev), (_offset), (_value))
+
+#else /* XSERVER_LIBPCIACCESS */
+
+typedef struct pci_device *pciVideoPtr;
+
+#define PCI_DEV_VENDOR_ID(_pcidev) ((_pcidev)->vendor_id)
+#define PCI_DEV_DEVICE_ID(_pcidev) ((_pcidev)->device_id)
+#define PCI_DEV_REVISION(_pcidev) ((_pcidev)->revision)
+
+#define PCI_SUB_VENDOR_ID(_pcidev) ((_pcidev)->subvendor_id)
+#define PCI_SUB_DEVICE_ID(_pcidev) ((_pcidev)->subdevice_id)
+
+/* pci-rework functions take a 'pci_device' parameter instead of a tag */
+#define PCI_DEV_TAG(_pcidev) (_pcidev)
+
+/* PCI_DEV macros, typically used in printf's, add domain ? XXX */
+#define PCI_DEV_BUS(_pcidev) ((_pcidev)->bus)
+#define PCI_DEV_DEV(_pcidev) ((_pcidev)->dev)
+#define PCI_DEV_FUNC(_pcidev) ((_pcidev)->func)
+
+/* pci-rework functions take a 'pci_device' parameter instead of a tag */
+#define PCI_CFG_TAG(_pcidev) (_pcidev)
+
+/* PCI_CFG macros, typically used in DRI init, contain the domain */
+#define PCI_CFG_BUS(_pcidev) (((_pcidev)->domain << 8) | \
+ (_pcidev)->bus)
+#define PCI_CFG_DEV(_pcidev) ((_pcidev)->dev)
+#define PCI_CFG_FUNC(_pcidev) ((_pcidev)->func)
+
+#define PCI_REGION_BASE(_pcidev, _b, _type) ((_pcidev)->regions[(_b)].base_addr)
+#define PCI_REGION_SIZE(_pcidev, _b) ((_pcidev)->regions[(_b)].size)
+
+#define PCI_READ_BYTE(_pcidev, _value_ptr, _offset) \
+ pci_device_cfg_read_u8((_pcidev), (_value_ptr), (_offset))
+
+#define PCI_READ_LONG(_pcidev, _value_ptr, _offset) \
+ pci_device_cfg_read_u32((_pcidev), (_value_ptr), (_offset))
+
+#define PCI_WRITE_LONG(_pcidev, _value, _offset) \
+ pci_device_cfg_write_u32((_pcidev), (_value), (_offset))
+
+#endif /* XSERVER_LIBPCIACCESS */
+
+#endif /* CIRPCIRENAME_H */
diff --git a/src/ct_video.c b/src/ct_video.c
index 19467d7..01b93ca 100644
--- a/src/ct_video.c
+++ b/src/ct_video.c
@@ -638,8 +638,8 @@ CHIPSDisplayVideo(
if (dblscan)
tmp = cPtr->VideoZoomMax >> 1;
if (drw_h > src_h)
- tmp = tmp * src_h / drw_h;
- cPtr->writeMR(cPtr, 0x33, tmp);
+ tmp = 256 * src_h / drw_h;
+ cPtr->writeMR(cPtr, 0x33, tmp & 0xFC);
}
cPtr->writeMR(cPtr, 0x1F, m1f);
cPtr->writeMR(cPtr, 0x1E, m1e);
Index: xorg-x11-drv-chips.spec
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-chips/devel/xorg-x11-drv-chips.spec,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -r1.15 -r1.16
--- xorg-x11-drv-chips.spec 20 Feb 2008 07:11:17 -0000 1.15
+++ xorg-x11-drv-chips.spec 10 Mar 2008 04:39:50 -0000 1.16
@@ -5,7 +5,7 @@
Summary: Xorg X11 chips video driver
Name: xorg-x11-drv-chips
Version: 1.1.1
-Release: 6%{?dist}
+Release: 7%{?dist}
URL: http://www.x.org
License: MIT
Group: User Interface/X Hardware Support
@@ -14,8 +14,11 @@
Source0: ftp://ftp.x.org/pub/individual/driver/%{tarball}-%{version}.tar.bz2
Source1: chips.xinf
+Patch0: chips-pciaccess.patch
+
ExcludeArch: s390 s390x
+BuildRequires: automake autoconf libtool
BuildRequires: xorg-x11-server-sdk >= 1.3.0.0-6
Requires: hwdata
@@ -26,8 +29,10 @@
%prep
%setup -q -n %{tarball}-%{version}
+%patch0 -p1 -b .pciaccess
%build
+autoreconf -v --install
%configure --disable-static
make
@@ -53,6 +58,9 @@
%{_mandir}/man4/chips.4*
%changelog
+* Mon Mar 10 2008 Dave Airlie <airlied at redhat.com> 1.1.1-7
+- pciaccess conversion
+
* Wed Feb 20 2008 Fedora Release Engineering <rel-eng at fedoraproject.org> - 1.1.1-6
- Autorebuild for GCC 4.3
- Previous message (by thread): rpms/libgnome/devel .cvsignore, 1.40, 1.41 libgnome.spec, 1.114, 1.115 sources, 1.40, 1.41 black-background.patch, 1.1, NONE libgnome-2.15.1-stat-homedir.patch, 1.1, NONE libgnome-2.20.1-default-filechooser-backend.patch, 1.2, NONE
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