rpms/kernel/F-10 drm-modesetting-radeon.patch, 1.50, 1.51 kernel.spec, 1.1127, 1.1128

Dave Airlie airlied at fedoraproject.org
Mon Nov 10 05:50:09 UTC 2008 

Author: airlied

Update of /cvs/pkgs/rpms/kernel/F-10
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv31797

Modified Files:
	drm-modesetting-radeon.patch kernel.spec 
Log Message:
- radeon modesetting - fix oops on powerpc + ring sizing bug


drm-modesetting-radeon.patch:

View full diff with command:
/usr/bin/cvs -f diff  -kk -u -N -r 1.50 -r 1.51 drm-modesetting-radeon.patch
Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-10/drm-modesetting-radeon.patch,v
retrieving revision 1.50
retrieving revision 1.51
diff -u -r1.50 -r1.51
--- drm-modesetting-radeon.patch	8 Nov 2008 04:49:47 -0000	1.50
+++ drm-modesetting-radeon.patch	10 Nov 2008 05:49:38 -0000	1.51
@@ -1,3 +1,27 @@
+commit 735cba61bd0bff256c6a01add80a78418f7ffa29
+Author: Dave Airlie <airlied at redhat.com>
+Date:   Mon Nov 10 15:39:25 2008 +1000
+
+    radeon: fix dumbness in cp ring check
+
+commit b138f1300f5781ccc432efa817e0a2e7817dbae1
+Author: Dave Airlie <airlied at redhat.com>
+Date:   Mon Nov 10 14:26:11 2008 +1000
+
+    radeon: add gart useable size to report to userspace
+
+commit fafafa93d2f78110826defa3ed1052159ab3f232
+Author: Dave Airlie <airlied at redhat.com>
+Date:   Sun Nov 9 20:34:49 2008 +1000
+
+    radeon: fix powerpc oops on rv280
+
+commit 63a8fbb9886095425a86e91fb5dd247e4f846dc5
+Author: Dave Airlie <airlied at redhat.com>
+Date:   Sun Nov 9 10:23:43 2008 +1000
+
+    radeon: upgrade atom headers
+
 commit 92c626a8e7c8c61c80acf3c687f4d7dbacc6f354
 Author: Dave Airlie <airlied at redhat.com>
 Date:   Sat Nov 8 14:39:41 2008 +1000
@@ -13065,10 +13089,10 @@
  
 diff --git a/drivers/gpu/drm/radeon/ObjectID.h b/drivers/gpu/drm/radeon/ObjectID.h
 new file mode 100644
-index 0000000..4b106cf
+index 0000000..f1f18a4
 --- /dev/null
 +++ b/drivers/gpu/drm/radeon/ObjectID.h
-@@ -0,0 +1,484 @@
+@@ -0,0 +1,518 @@
 +/*
 +* Copyright 2006-2007 Advanced Micro Devices, Inc.  
 +*
@@ -13149,6 +13173,10 @@
 +#define ENCODER_OBJECT_ID_DP_DP501                0x1D
 +#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY         0x1E
 +#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA   0x1F
++#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1        0x20
++#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY2        0x21
++
++#define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO    0xFF
 +
 +/****************************************************/
 +/* Connector Object ID Definition                   */
@@ -13189,6 +13217,8 @@
 +#define GRAPH_OBJECT_ENUM_ID2                     0x02
 +#define GRAPH_OBJECT_ENUM_ID3                     0x03
 +#define GRAPH_OBJECT_ENUM_ID4                     0x04
++#define GRAPH_OBJECT_ENUM_ID5                     0x05
++#define GRAPH_OBJECT_ENUM_ID6                     0x06
 +
 +/****************************************************/
 +/* Graphics Object ID Bit definition                */
@@ -13244,7 +13274,7 @@
 +#define ENCODER_SI178_ENUM_ID1                   0x2117 
 +#define ENCODER_MVPU_FPGA_ENUM_ID1               0x2118
 +#define ENCODER_INTERNAL_DDI_ENUM_ID1            0x2119
-+#define ENCODER_VT1625_ENUM_ID1               0x211A
++#define ENCODER_VT1625_ENUM_ID1                  0x211A
 +#define ENCODER_HDMI_SI1932_ENUM_ID1             0x211B
 +#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1       0x211C
 +#define ENCODER_DP_DP501_ENUM_ID1                0x211D
@@ -13394,6 +13424,26 @@
 +                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
 +                                                 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)  
 +
++#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
++
++#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                  ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
++
 +/****************************************************/
 +/* Connector Object ID definition - Shared with BIOS */
 +/****************************************************/
@@ -13524,6 +13574,14 @@
 +                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
 +                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
 +
++#define CONNECTOR_DISPLAYPORT_ENUM_ID3         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DISPLAYPORT_ENUM_ID4         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
++
 +/****************************************************/
 +/* Router Object ID definition - Shared with BIOS   */
 +/****************************************************/
@@ -15066,10 +15124,10 @@
 +#endif
 diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
 new file mode 100644
-index 0000000..2e7dc6c
+index 0000000..9932b09
 --- /dev/null
 +++ b/drivers/gpu/drm/radeon/atombios.h
-@@ -0,0 +1,4498 @@
+@@ -0,0 +1,5025 @@
 +/*
 + * Copyright 2006-2007 Advanced Micro Devices, Inc.  
 + *
@@ -15338,7 +15396,7 @@
 +  USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
 +  USHORT ExternalEncoderControl;                 //Atomic Table,  directly used by various SW components,latest version 2.1
 +  USHORT LVTMAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
-+  USHORT VRAM_BlockDetectionByStrap;
++  USHORT VRAM_BlockDetectionByStrap;             //Atomic Table,  used only by Bios
 +  USHORT MemoryCleanUp;                          //Atomic Table,  only used by Bios    
 +  USHORT ProcessI2cChannelTransaction;           //Function Table,only used by Bios
 +  USHORT WriteOneByteToHWAssistedI2C;            //Function Table,indirectly used by various SW components 
@@ -15348,9 +15406,9 @@
 +  USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 +  USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
 +  USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
-+  USHORT VRAM_GetCurrentInfoBlock;
++  USHORT VRAM_GetCurrentInfoBlock;               //Atomic Table,  used only by Bios
 +  USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
-+  USHORT MemoryTraining;
++  USHORT MemoryTraining;                         //Atomic Table,  used only by Bios
 +  USHORT EnableSpreadSpectrumOnPPLL;             //Atomic Table,  directly used by various SW components,latest version 1.2
 +  USHORT TMDSAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 +  USHORT SetVoltage;                             //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
@@ -15368,11 +15426,12 @@
 +  USHORT DPEncoderService;											 //Function Table,only used by Bios
 +}ATOM_MASTER_LIST_OF_COMMAND_TABLES;   
 +
++// For backward compatible 
 +#define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
-+
 +#define UNIPHYTransmitterControl						     DIG1TransmitterControl
 +#define LVTMATransmitterControl							     DIG2TransmitterControl
-+#define SetCRTC_DPM_State                                    GetConditionalGoldenSetting
++#define SetCRTC_DPM_State                        GetConditionalGoldenSetting
++#define SetUniphyInstance                        ASIC_StaticPwrMgtStatusChange
 +
 +typedef struct _ATOM_MASTER_COMMAND_TABLE
 +{
@@ -15380,6 +15439,9 @@
 +  ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
 +}ATOM_MASTER_COMMAND_TABLE;
 +
++/****************************************************************************/	
++// Structures used in every command table
++/****************************************************************************/	
 +typedef struct _ATOM_TABLE_ATTRIBUTE
 +{
 +#if ATOM_BIG_ENDIAN
@@ -15399,23 +15461,20 @@
 +  USHORT               susAccess;
 +}ATOM_TABLE_ATTRIBUTE_ACCESS;
 +
++/****************************************************************************/	
 +// Common header for all command tables.
-+//Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 
-+//And the pointer actually points to this header.
-+
++// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 
++// And the pointer actually points to this header.
++/****************************************************************************/	
 +typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
 +{
 +  ATOM_COMMON_TABLE_HEADER CommonHeader;
 +  ATOM_TABLE_ATTRIBUTE     TableAttribute;	
 +}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
 +
-+
-+typedef struct _ASIC_INIT_PARAMETERS
-+{
[...1619 lines suppressed...]
  #define RADEON_BUS_CNTL			0x0030
@@ -27516,7 +28106,7 @@
  
  #define RADEON_BUS_CNTL1		0x0034
  #	define RADEON_PMI_BM_DIS		(1 << 2)
-@@ -554,16 +709,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -554,16 +711,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
  #define R520_MC_IND_WR_EN (1 << 24)
  #define R520_MC_IND_DATA  0x74
  
@@ -27533,7 +28123,7 @@
  #define RADEON_MPP_TB_CONFIG		0x01c0
  #define RADEON_MEM_CNTL			0x0140
  #define RADEON_MEM_SDRAM_MODE_REG	0x0158
-@@ -628,14 +773,23 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -628,14 +775,23 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
  #define RADEON_SCRATCH_REG3		0x15ec
  #define RADEON_SCRATCH_REG4		0x15f0
  #define RADEON_SCRATCH_REG5		0x15f4
@@ -27560,7 +28150,7 @@
  
  #define RADEON_GEN_INT_CNTL		0x0040
  #	define RADEON_CRTC_VBLANK_MASK		(1 << 0)
-@@ -654,10 +808,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -654,10 +810,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
  #	define RADEON_SW_INT_FIRE		(1 << 26)
  #       define R500_DISPLAY_INT_STATUS          (1 << 0)
  
@@ -27578,7 +28168,7 @@
  
  #define RADEON_ISYNC_CNTL		0x1724
  #	define RADEON_ISYNC_ANY2D_IDLE3D	(1 << 0)
-@@ -696,12 +853,17 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -696,12 +855,17 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
  #define RADEON_PP_TXFILTER_1		0x1c6c
  #define RADEON_PP_TXFILTER_2		0x1c84
  
@@ -27602,7 +28192,7 @@
  #define RADEON_RB3D_CNTL		0x1c3c
  #	define RADEON_ALPHA_BLEND_ENABLE	(1 << 0)
  #	define RADEON_PLANE_MASK_ENABLE		(1 << 1)
-@@ -728,11 +890,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -728,11 +892,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
  #	define R300_ZC_FLUSH		        (1 << 0)
  #	define R300_ZC_FREE		        (1 << 1)
  #	define R300_ZC_BUSY		        (1 << 31)
@@ -27614,7 +28204,7 @@
  #define R300_RB3D_DSTCACHE_CTLSTAT              0x4e4c
  #	define R300_RB3D_DC_FLUSH		(2 << 0)
  #	define R300_RB3D_DC_FREE		(2 << 2)
-@@ -740,15 +897,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -740,15 +899,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
  #define RADEON_RB3D_ZSTENCILCNTL	0x1c2c
  #	define RADEON_Z_TEST_MASK		(7 << 4)
  #	define RADEON_Z_TEST_ALWAYS		(7 << 4)
@@ -27634,7 +28224,7 @@
  #define RADEON_RBBM_SOFT_RESET		0x00f0
  #	define RADEON_SOFT_RESET_CP		(1 <<  0)
  #	define RADEON_SOFT_RESET_HI		(1 <<  1)
-@@ -937,7 +1094,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -937,7 +1096,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
  
  #define RADEON_AIC_CNTL			0x01d0
  #	define RADEON_PCIGART_TRANSLATE_EN	(1 << 0)
@@ -27643,7 +28233,7 @@
  #define RADEON_AIC_STAT			0x01d4
  #define RADEON_AIC_PT_BASE		0x01d8
  #define RADEON_AIC_LO_ADDR		0x01dc
-@@ -1009,27 +1166,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1009,27 +1168,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
  #define RADEON_NUM_VERTICES_SHIFT		16
  
  #define RADEON_COLOR_FORMAT_CI8		2
@@ -27671,7 +28261,7 @@
  
  #define R200_PP_TXCBLEND_0                0x2f00
  #define R200_PP_TXCBLEND_1                0x2f10
-@@ -1140,16 +1276,44 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1140,16 +1278,44 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
  
  #define R200_SE_TCL_POINT_SPRITE_CNTL     0x22c4
  
@@ -27718,7 +28308,7 @@
  #define R500_D1CRTC_STATUS 0x609c
  #define R500_D2CRTC_STATUS 0x689c
  #define R500_CRTC_V_BLANK (1<<0)
-@@ -1190,19 +1354,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1190,19 +1356,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
  #define RADEON_RING_HIGH_MARK		128
  
  #define RADEON_PCIGART_TABLE_SIZE      (32*1024)
@@ -27762,7 +28352,7 @@
  #define RADEON_WRITE_PCIE(addr, val)					\
  do {									\
  	RADEON_WRITE8(RADEON_PCIE_INDEX,				\
-@@ -1259,7 +1440,7 @@ do {									\
+@@ -1259,7 +1442,7 @@ do {									\
  #define RADEON_WAIT_UNTIL_2D_IDLE() do {				\
  	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
  	OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |				\
@@ -27771,7 +28361,7 @@
  } while (0)
  
  #define RADEON_WAIT_UNTIL_3D_IDLE() do {				\
-@@ -1336,8 +1517,9 @@ do {									\
+@@ -1336,8 +1519,9 @@ do {									\
  } while (0)
  
  #define VB_AGE_TEST_WITH_RETURN( dev_priv )				\
@@ -27783,7 +28373,7 @@
  	if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) {		\
  		int __ret = radeon_do_cp_idle( dev_priv );		\
  		if ( __ret ) return __ret;				\
-@@ -1367,15 +1549,16 @@ do {									\
+@@ -1367,15 +1551,16 @@ do {									\
  
  #define RADEON_VERBOSE	0
  
@@ -27796,14 +28386,14 @@
  	}								\
 -	if ( dev_priv->ring.space <= (n) * sizeof(u32) ) {		\
 +	_align_nr = (n + 0xf) & ~0xf;					\
-+	if ( dev_priv->ring.space <= _align_nr ) {			\
++	if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) {	\
                  COMMIT_RING();						\
 -		radeon_wait_ring( dev_priv, (n) * sizeof(u32) );	\
-+		radeon_wait_ring( dev_priv, _align_nr );		\
++		radeon_wait_ring( dev_priv, _align_nr * sizeof(u32));	\
  	}								\
  	_nr = n; dev_priv->ring.space -= (n) * sizeof(u32);		\
  	ring = dev_priv->ring.start;					\
-@@ -1392,19 +1575,14 @@ do {									\
+@@ -1392,19 +1577,14 @@ do {									\
  		DRM_ERROR(						\
  			"ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n",	\
  			((dev_priv->ring.tail + _nr) & mask),		\
@@ -27826,7 +28416,7 @@
  
  #define OUT_RING( x ) do {						\
  	if ( RADEON_VERBOSE ) {						\
-@@ -1443,4 +1621,148 @@ do {									\
+@@ -1443,4 +1623,148 @@ do {									\
  	write &= mask;						\
  } while (0)
  
@@ -30128,10 +30718,10 @@
 +
 diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
 new file mode 100644
-index 0000000..f338e64
+index 0000000..2ed9bfc
 --- /dev/null
 +++ b/drivers/gpu/drm/radeon/radeon_gem.c
-@@ -0,0 +1,1603 @@
+@@ -0,0 +1,1608 @@
 +/*
 + * Copyright 2008 Red Hat Inc.
 + *
@@ -30202,7 +30792,7 @@
 +	args->vram_visible = dev_priv->mm.vram_visible;
 +
 +	args->gart_start = dev_priv->mm.gart_start;
-+	args->gart_size = dev_priv->mm.gart_size;
++	args->gart_size = dev_priv->mm.gart_useable;
 +
 +	return 0;
 +}
@@ -30814,6 +31404,8 @@
 +		  dev_priv->mm.ring.bo, dev_priv->mm.ring.bo->offset, dev_priv->mm.ring.kmap.virtual,
 +		  dev_priv->mm.ring_read.bo, dev_priv->mm.ring_read.bo->offset, dev_priv->mm.ring_read.kmap.virtual);
 +
++	dev_priv->mm.gart_useable -= RADEON_DEFAULT_RING_SIZE + PAGE_SIZE;
++
 +	/* init the indirect buffers */
 +	radeon_gem_ib_init(dev);
 +	radeon_gem_dma_bufs_init(dev);
@@ -31123,6 +31715,7 @@
 +
 +	dev_priv->mm.gart_size = (32 * 1024 * 1024);
 +	dev_priv->mm.gart_start = 0;
++	dev_priv->mm.gart_useable = dev_priv->mm.gart_size;
 +	ret = radeon_gart_init(dev);
 +	if (ret)
 +		return -EINVAL;
@@ -31427,6 +32020,7 @@
 +			goto free_all;
 +	}
 +
++	dev_priv->mm.gart_useable -= RADEON_IB_SIZE * RADEON_NUM_IB;
 +	dev_priv->ib_alloc_bitmap = 0;
 +
 +	dev_priv->cs.ib_get = radeon_gem_ib_get;
@@ -31663,6 +32257,7 @@
 +		DRM_ERROR("Failed to mmap DMA buffers\n");
 +		return -ENOMEM;
 +	}
++	dev_priv->mm.gart_useable -= size;
 +	DRM_DEBUG("\n");
 +	radeon_gem_addbufs(dev);
 +


Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-10/kernel.spec,v
retrieving revision 1.1127
retrieving revision 1.1128
diff -u -r1.1127 -r1.1128
--- kernel.spec	9 Nov 2008 22:38:20 -0000	1.1127
+++ kernel.spec	10 Nov 2008 05:49:38 -0000	1.1128
@@ -1892,6 +1892,9 @@
 %kernel_variant_files -k vmlinux %{with_kdump} kdump
 
 %changelog
+* Mon Nov 10 2008 Dave Airlie <airlied at redhat.com> 2.6.27.5-92
+- radeon modesetting - fix oops on powerpc + ring sizing bug
+
 * Sun Nov 09 2008 Chuck Ebbert <cebbert at redhat.com> 2.6.27.5-91
 - Fix up the CVE-2008-3528 patch so we get it from -stable.

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