rpms/kernel/devel drm-modesetting-radeon.patch, 1.24, 1.25 kernel.spec, 1.943, 1.944
Dave Airlie
airlied at fedoraproject.org
Wed Sep 10 04:54:36 UTC 2008
Author: airlied
Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv8139
Modified Files:
drm-modesetting-radeon.patch kernel.spec
Log Message:
* Tue Sep 09 2008 Dave Airlie <airlied at redhat.com>
- Update radeon modesetting - memory setup + ref count fail
drm-modesetting-radeon.patch:
Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-modesetting-radeon.patch,v
retrieving revision 1.24
retrieving revision 1.25
diff -u -r1.24 -r1.25
--- drm-modesetting-radeon.patch 9 Sep 2008 06:16:19 -0000 1.24
+++ drm-modesetting-radeon.patch 10 Sep 2008 04:54:35 -0000 1.25
@@ -1,3 +1,21 @@
+commit ed3d32c22ed856ef32594fe2efb88c55c8006627
+Author: Dave Airlie <airlied at redhat.com>
+Date: Wed Sep 10 14:35:43 2008 +1000
+
+ radeon: do proper memory controller init and setup
+
+commit b20aa3e4a453fe5132794e6fddd0e03d0209466a
+Author: Dave Airlie <airlied at redhat.com>
+Date: Wed Sep 10 14:35:08 2008 +1000
+
+ radeon: fix return value
+
+commit e64d245c67dce41434a5f9504d7f6f530cf7e5c2
+Author: Dave Airlie <airlied at redhat.com>
+Date: Wed Sep 10 14:34:39 2008 +1000
+
+ radeon: fixup reference counting properly
+
commit dc35ec837f7a0ff258e6fde4326ccae7fd77650b
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Sep 9 15:55:38 2008 +1000
@@ -28875,7 +28893,7 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
new file mode 100644
-index 0000000..bca9e13
+index 0000000..e791055
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -0,0 +1,1359 @@
@@ -29648,7 +29666,7 @@
+ return false;
+}
+
-+bool radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder)
++void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder)
+{
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
@@ -30612,7 +30630,7 @@
+ return NULL;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
-index 248ab4a..cc96220 100644
+index 248ab4a..a1d2290 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -31,6 +31,7 @@
@@ -30795,6 +30813,15 @@
#if RADEON_FIFO_DEBUG
static void radeon_status(drm_radeon_private_t * dev_priv)
{
+@@ -234,7 +356,7 @@ static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
+ return -EBUSY;
+ }
+
+-static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
++int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
+ {
+ int i, ret;
+
@@ -294,7 +416,7 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
}
@@ -33593,7 +33620,7 @@
}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
-index 0993816..c7a565c 100644
+index 0993816..e15a47a 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -34,6 +34,8 @@
@@ -33846,8 +33873,11 @@
extern struct drm_ioctl_desc radeon_ioctls[];
extern int radeon_max_ioctl;
-@@ -366,10 +488,6 @@ extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
+@@ -364,12 +486,9 @@ extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
+ extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
+
++extern int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv);
extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
-extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
@@ -33857,7 +33887,7 @@
extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
-@@ -397,13 +515,19 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
+@@ -397,13 +516,19 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
extern int radeon_driver_unload(struct drm_device *dev);
extern int radeon_driver_firstopen(struct drm_device *dev);
@@ -33880,7 +33910,7 @@
/* r300_cmdbuf.c */
extern void r300_init_reg_flags(struct drm_device *dev);
-@@ -411,6 +535,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -411,6 +536,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
struct drm_file *file_priv,
drm_radeon_kcmd_buffer_t * cmdbuf);
@@ -33892,7 +33922,7 @@
/* Flags for stats.boxes
*/
#define RADEON_BOX_DMA_IDLE 0x1
-@@ -419,10 +548,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -419,10 +549,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_BOX_WAIT_IDLE 0x8
#define RADEON_BOX_TEXTURE_LOAD 0x10
@@ -33907,7 +33937,7 @@
#define RADEON_AGP_COMMAND 0x0f60
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
# define RADEON_AGP_ENABLE (1<<8)
-@@ -525,16 +658,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -525,16 +659,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define R520_MC_IND_WR_EN (1 << 24)
#define R520_MC_IND_DATA 0x74
@@ -33924,7 +33954,7 @@
#define RADEON_MPP_TB_CONFIG 0x01c0
#define RADEON_MEM_CNTL 0x0140
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
-@@ -599,14 +722,23 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -599,14 +723,23 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_SCRATCH_REG3 0x15ec
#define RADEON_SCRATCH_REG4 0x15f0
#define RADEON_SCRATCH_REG5 0x15f4
@@ -33951,7 +33981,7 @@
#define RADEON_GEN_INT_CNTL 0x0040
# define RADEON_CRTC_VBLANK_MASK (1 << 0)
-@@ -623,11 +755,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -623,11 +756,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
# define RADEON_SW_INT_TEST (1 << 25)
# define RADEON_SW_INT_TEST_ACK (1 << 25)
# define RADEON_SW_INT_FIRE (1 << 26)
@@ -33969,7 +33999,7 @@
#define RADEON_ISYNC_CNTL 0x1724
# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
-@@ -666,12 +800,17 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -666,12 +801,17 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_PP_TXFILTER_1 0x1c6c
#define RADEON_PP_TXFILTER_2 0x1c84
@@ -33993,7 +34023,7 @@
#define RADEON_RB3D_CNTL 0x1c3c
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
# define RADEON_PLANE_MASK_ENABLE (1 << 1)
-@@ -698,11 +837,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -698,11 +838,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
# define R300_ZC_FLUSH (1 << 0)
# define R300_ZC_FREE (1 << 1)
# define R300_ZC_BUSY (1 << 31)
@@ -34005,7 +34035,7 @@
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
# define R300_RB3D_DC_FLUSH (2 << 0)
# define R300_RB3D_DC_FREE (2 << 2)
-@@ -710,15 +844,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -710,15 +845,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
@@ -34025,7 +34055,7 @@
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
-@@ -978,27 +1112,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -978,27 +1113,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_NUM_VERTICES_SHIFT 16
#define RADEON_COLOR_FORMAT_CI8 2
@@ -34053,7 +34083,7 @@
#define R200_PP_TXCBLEND_0 0x2f00
#define R200_PP_TXCBLEND_1 0x2f10
-@@ -1109,13 +1222,41 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -1109,13 +1223,41 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
@@ -34097,7 +34127,7 @@
#define R500_D1CRTC_STATUS 0x609c
#define R500_D2CRTC_STATUS 0x689c
#define R500_CRTC_V_BLANK (1<<0)
-@@ -1156,19 +1297,35 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -1156,19 +1298,35 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_RING_HIGH_MARK 128
#define RADEON_PCIGART_TABLE_SIZE (32*1024)
@@ -34140,7 +34170,7 @@
#define RADEON_WRITE_PCIE(addr, val) \
do { \
RADEON_WRITE8(RADEON_PCIE_INDEX, \
-@@ -1224,7 +1381,7 @@ do { \
+@@ -1224,7 +1382,7 @@ do { \
#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
@@ -34149,7 +34179,7 @@
} while (0)
#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
-@@ -1301,8 +1458,9 @@ do { \
+@@ -1301,8 +1459,9 @@ do { \
} while (0)
#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
@@ -34161,7 +34191,7 @@
if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
int __ret = radeon_do_cp_idle( dev_priv ); \
if ( __ret ) return __ret; \
-@@ -1408,4 +1566,142 @@ do { \
+@@ -1408,4 +1567,142 @@ do { \
write &= mask; \
} while (0)
@@ -36427,10 +36457,10 @@
+
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
new file mode 100644
-index 0000000..382d348
+index 0000000..58162e5
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
-@@ -0,0 +1,1381 @@
+@@ -0,0 +1,1561 @@
+/*
+ * Copyright 2008 Red Hat Inc.
+ *
@@ -36697,6 +36727,9 @@
+#endif
+out_unlock:
+ mutex_unlock(&obj_priv->bo->mutex);
++ mutex_lock(&dev->struct_mutex);
++ drm_gem_object_unreference(obj);
++ mutex_unlock(&dev->struct_mutex);
+ return ret;
+}
+
@@ -36755,14 +36788,7 @@
+ int flags = DRM_BO_FLAG_NO_EVICT;
+ int mask = DRM_BO_FLAG_NO_EVICT;
+
-+ obj = drm_gem_object_lookup(dev, file_priv, args->handle);
-+ if (obj == NULL)
-+ return -EINVAL;
-+
-+ obj_priv = obj->driver_private;
-+
-+ DRM_DEBUG("got here %p %p %d\n", obj, obj_priv->bo, atomic_read(&obj_priv->bo->usage));
-+ /* validate into a pin with no fence */
++ /* check for valid args */
+ if (args->pin_domain) {
+ mask |= DRM_BO_MASK_MEM;
+ if (args->pin_domain == RADEON_GEM_DOMAIN_GTT)
@@ -36773,6 +36799,14 @@
+ return -EINVAL;
+ }
+
++ obj = drm_gem_object_lookup(dev, file_priv, args->handle);
++ if (obj == NULL)
++ return -EINVAL;
++
++ obj_priv = obj->driver_private;
++
++ /* validate into a pin with no fence */
++ DRM_DEBUG("got here %p %p %d\n", obj, obj_priv->bo, atomic_read(&obj_priv->bo->usage));
+ if (!(obj_priv->bo->type != drm_bo_type_kernel && !DRM_SUSER(DRM_CURPROC))) {
+ ret = drm_bo_do_validate(obj_priv->bo, flags, mask,
+ DRM_BO_HINT_DONT_FENCE, 0);
@@ -37136,6 +37170,176 @@
+
+}
+
++static bool avivo_get_mc_idle(struct drm_device *dev)
++{
++ drm_radeon_private_t *dev_priv = dev->dev_private;
++
++ if (dev_priv->chip_family >= CHIP_R600) {
++ /* no idea where this is on r600 yet */
++ return true;
++ } else if (dev_priv->chip_family == CHIP_RV515) {
++ if (radeon_read_mc_reg(dev_priv, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE)
++ return true;
++ else
++ return false;
++ } else if (dev_priv->chip_family == CHIP_RS600) {
++ if (radeon_read_mc_reg(dev_priv, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE)
++ return true;
++ else
++ return false;
++ } else if ((dev_priv->chip_family == CHIP_RS690) ||
++ (dev_priv->chip_family == CHIP_RS740)) {
++ if (radeon_read_mc_reg(dev_priv, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE)
++ return true;
++ else
++ return false;
++ } else {
++ if (radeon_read_mc_reg(dev_priv, R520_MC_STATUS) & R520_MC_STATUS_IDLE)
++ return true;
++ else
++ return false;
++ }
++}
++
++
++static void avivo_disable_mc_clients(struct drm_device *dev)
++{
++ drm_radeon_private_t *dev_priv = dev->dev_private;
++ uint32_t tmp;
++ int timeout;
++
++ radeon_do_wait_for_idle(dev_priv);
++
++ RADEON_WRITE(AVIVO_D1VGA_CONTROL, RADEON_READ(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
++ RADEON_WRITE(AVIVO_D2VGA_CONTROL, RADEON_READ(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
++
++ tmp = RADEON_READ(AVIVO_D1CRTC_CONTROL);
++ RADEON_WRITE(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
++
++ tmp = RADEON_READ(AVIVO_D2CRTC_CONTROL);
++ RADEON_WRITE(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
++
++ tmp = RADEON_READ(AVIVO_D2CRTC_CONTROL);
++
++ udelay(1000);
++
++ timeout = 0;
++ while (!(avivo_get_mc_idle(dev))) {
++ if (++timeout > 100000) {
++ DRM_ERROR("Timeout waiting for memory controller to update settings\n");
++ DRM_ERROR("Bad things may or may not happen\n");
++ }
++ udelay(10);
++ }
++}
++
++static inline u32 radeon_busy_wait(struct drm_device *dev, uint32_t reg, uint32_t bits,
++ unsigned int timeout)
++{
++ drm_radeon_private_t *dev_priv = dev->dev_private;
++ u32 status;
++
++ do {
++ udelay(10);
++ status = RADEON_READ(reg);
++ timeout--;
++ } while(status != 0xffffffff && (status & bits) && (timeout > 0));
++
++ if (timeout == 0)
++ status = 0xffffffff;
++
++ return status;
++}
++
++/* Wait for vertical sync on primary CRTC */
++static void radeon_wait_for_vsync(struct drm_device *dev)
++{
++ drm_radeon_private_t *dev_priv = dev->dev_private;
++ uint32_t crtc_gen_cntl;
++ int ret;
++
++ crtc_gen_cntl = RADEON_READ(RADEON_CRTC_GEN_CNTL);
++ if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
++ !(crtc_gen_cntl & RADEON_CRTC_EN))
++ return;
++
++ /* Clear the CRTC_VBLANK_SAVE bit */
++ RADEON_WRITE(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
++
++ radeon_busy_wait(dev, RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE, 2000);
++
++}
++
++/* Wait for vertical sync on primary CRTC */
++static void radeon_wait_for_vsync2(struct drm_device *dev)
++{
++ drm_radeon_private_t *dev_priv = dev->dev_private;
++ uint32_t crtc2_gen_cntl;
++ struct timeval timeout;
++
++ crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
++ if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
++ !(crtc2_gen_cntl & RADEON_CRTC2_EN))
++ return;
++
++ /* Clear the CRTC_VBLANK_SAVE bit */
++ RADEON_WRITE(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
++
++ radeon_busy_wait(dev, RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE, 2000);
++}
++
++static void legacy_disable_mc_clients(struct drm_device *dev)
++{
++ drm_radeon_private_t *dev_priv = dev->dev_private;
++ uint32_t old_mc_status, status_idle;
++ uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
++ uint32_t status;
++
++ radeon_do_wait_for_idle(dev_priv);
++
++ if (dev_priv->flags & RADEON_IS_IGP)
++ return;
++
++ old_mc_status = RADEON_READ(RADEON_MC_STATUS);
++
++ /* stop display and memory access */
++ ov0_scale_cntl = RADEON_READ(RADEON_OV0_SCALE_CNTL);
++ RADEON_WRITE(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
++ crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
++ RADEON_WRITE(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
++ crtc_gen_cntl = RADEON_READ(RADEON_CRTC_GEN_CNTL);
++
++ radeon_wait_for_vsync(dev);
++
++ RADEON_WRITE(RADEON_CRTC_GEN_CNTL,
++ (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
++ RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
++
++ if (!(dev_priv->flags & RADEON_SINGLE_CRTC)) {
++ crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
++
++ radeon_wait_for_vsync2(dev);
++ RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,
++ (crtc2_gen_cntl &
++ ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
++ RADEON_CRTC2_DISP_REQ_EN_B);
++ }
++
++ udelay(500);
++
++ if (radeon_is_r300(dev_priv))
++ status_idle = R300_MC_IDLE;
++ else
++ status_idle = RADEON_MC_IDLE;
++
++ status = radeon_busy_wait(dev, RADEON_MC_STATUS, status_idle, 200000);
++ if (status == 0xffffffff) {
++ DRM_ERROR("Timeout waiting for memory controller to update settings\n");
++ DRM_ERROR("Bad things may or may not happen\n");
++ }
++}
++
++
+void radeon_init_memory_map(struct drm_device *dev)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -37205,6 +37409,14 @@
+ else
+ dev_priv->fb_location = (dev_priv->mc_fb_location & 0xffff) << 16;
+
++ /* updating mc regs here */
++ if (radeon_is_avivo(dev_priv))
++ avivo_disable_mc_clients(dev);
++ else
++ legacy_disable_mc_clients(dev);
++
++ radeon_write_fb_location(dev_priv, dev_priv->mc_fb_location);
++
+ if (radeon_is_avivo(dev_priv)) {
+ if (dev_priv->chip_family >= CHIP_R600)
+ RADEON_WRITE(R600_HDP_NONSURFACE_BASE, (dev_priv->mc_fb_location << 16) & 0xff0000);
@@ -37212,8 +37424,6 @@
+ RADEON_WRITE(AVIVO_HDP_FB_LOCATION, dev_priv->mc_fb_location);
+ }
+
-+ radeon_write_fb_location(dev_priv, dev_priv->mc_fb_location);
-+
+ dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
+ dev_priv->fb_size =
+ ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
@@ -37460,7 +37670,7 @@
+
+ obj = drm_gem_object_lookup(dev, file_priv, reloc[1]);
+ if (!obj)
-+ return false;
++ return -EINVAL;
+
+ obj_priv = obj->driver_private;
+ radeon_gem_set_domain(obj, read_domains, write_domain, &flags, false);
@@ -40457,7 +40667,7 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
new file mode 100644
-index 0000000..ef268a2
+index 0000000..a4ee78a
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -0,0 +1,337 @@
@@ -40755,7 +40965,7 @@
+extern void radeon_atombios_get_tmds_info(struct radeon_encoder *encoder);
+extern bool radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
+extern bool radeon_combios_get_tmds_info(struct radeon_encoder *encoder);
-+extern bool radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
++extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
+extern bool radeon_combios_get_tv_info(struct radeon_encoder *encoder);
+extern bool radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
+extern bool radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.943
retrieving revision 1.944
diff -u -r1.943 -r1.944
--- kernel.spec 10 Sep 2008 01:45:27 -0000 1.943
+++ kernel.spec 10 Sep 2008 04:54:35 -0000 1.944
@@ -1746,6 +1746,9 @@
%kernel_variant_files -k vmlinux %{with_kdump} kdump
%changelog
+* Tue Sep 09 2008 Dave Airlie <airlied at redhat.com>
+- Update radeon modesetting - memory setup + ref count fail
+
* Tue Sep 09 2008 Dave Jones <davej at redhat.com>
- 2.6.27-rc6
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