rpms/kernel/devel drm-modesetting-radeon.patch, 1.26, 1.27 kernel.spec, 1.954, 1.955
Dave Airlie
airlied at fedoraproject.org
Thu Sep 18 00:36:25 UTC 2008
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Author: airlied
Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv29276
Modified Files:
drm-modesetting-radeon.patch kernel.spec
Log Message:
* Thu Sep 18 2008 Dave Airlie <airlied at redhat.com>
- update radeon LVDS bits from AMD
drm-modesetting-radeon.patch:
Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-modesetting-radeon.patch,v
retrieving revision 1.26
retrieving revision 1.27
diff -u -r1.26 -r1.27
--- drm-modesetting-radeon.patch 11 Sep 2008 09:58:23 -0000 1.26
+++ drm-modesetting-radeon.patch 18 Sep 2008 00:36:24 -0000 1.27
@@ -1,3 +1,15 @@
+commit 41b33ad8bfd879c37f72e560e0b1e1b57f537093
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Thu Sep 18 09:55:14 2008 +1000
+
+ radeon: further LVDS fixes
+
+commit 882f9bc454b85149fdf96db79932a8f1d57b5136
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Thu Sep 18 09:54:12 2008 +1000
+
+ radeon: legacy lvds updates
+
commit 7d7949742ae5d6d0aca8857bfcab77b2fffaf0d7
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Sep 11 18:26:27 2008 +1000
@@ -28924,7 +28936,7 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
new file mode 100644
-index 0000000..e791055
+index 0000000..3219b99
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -0,0 +1,1359 @@
@@ -29590,14 +29602,14 @@
+ encoder->use_bios_dividers = true;
+
+ panel_setup = radeon_bios32(dev_priv, lcd_info + 0x39);
-+ encoder->lvds_gen_cntl = 0;
++ encoder->lvds_gen_cntl = 0xff00;
+ if (panel_setup & 0x1)
+ encoder->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
+
+ if ((panel_setup >> 4) & 0x1)
+ encoder->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
+
-+ switch ((panel_setup >> 8) & 0x8) {
++ switch ((panel_setup >> 8) & 0x7) {
+ case 0:
+ encoder->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
+ break;
@@ -39367,10 +39379,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
new file mode 100644
-index 0000000..c80e0b5
+index 0000000..1a1db53
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
-@@ -0,0 +1,1356 @@
+@@ -0,0 +1,1361 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
@@ -39597,23 +39609,15 @@
+ lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
+ RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
+ udelay(1000);
++
+ lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
+ lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
+ RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
+
-+ /* enable lvds, turn on voltage */
+ lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
-+ lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
-+ RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
-+ udelay(radeon_encoder->panel_digon_delay * 1000);
-+
-+ /* enable data */
++ lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
+ lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
-+ RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
-+ udelay(radeon_encoder->panel_blon_delay * 1000);
-+
-+ /* enable backlight */
-+ lvds_gen_cntl |= RADEON_LVDS_BLON;
++ udelay(radeon_encoder->panel_pwr_delay * 1000);
+ RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
+
+ /* update bios scratch regs */
@@ -39624,12 +39628,13 @@
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+ case DRM_MODE_DPMS_OFF:
-+ pixclks_cntl = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
++ pixclks_cntl = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
+ RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
-+ lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
-+ lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
-+ lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
-+ RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
++ lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
++ lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
++ lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
++ udelay(radeon_encoder->panel_pwr_delay * 1000);
++ RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
+ RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
+
+ bios_5_scratch &= ~RADEON_LCD1_ON;
@@ -39666,7 +39671,7 @@
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-+ uint32_t lvds_pll_cntl, lvds_gen_cntl;
++ uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
+
+ DRM_DEBUG("\n");
+
@@ -39685,6 +39690,8 @@
+ RADEON_LVDS_EN |
+ RADEON_LVDS_RST_FM);
+
++ DRM_INFO("bios LVDS_GEN_CNTL: 0x%x\n", radeon_encoder->lvds_gen_cntl);
++
+ if (radeon_is_r300(dev_priv))
+ lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
+
@@ -39695,15 +39702,25 @@
+ } else
+ lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
+ } else {
-+ if (radeon_is_r300(dev_priv)) {
++ if (radeon_is_r300(dev_priv))
+ lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
-+ } else
++ else
+ lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
+ }
+
+ RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
+ RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
+
++ lvds_ss_gen_cntl = RADEON_READ(RADEON_LVDS_SS_GEN_CNTL);
++ if (radeon_encoder->panel_digon_delay &&
++ radeon_encoder->panel_blon_delay) {
++ lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
++ (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
++ lvds_ss_gen_cntl |= ((radeon_encoder->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
++ (radeon_encoder->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
++ RADEON_WRITE(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
++ }
++
+ if (dev_priv->chip_family == CHIP_RV410)
+ RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, 0);
+}
@@ -41258,10 +41275,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
new file mode 100644
-index 0000000..5910897
+index 0000000..52fb0b9
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
-@@ -0,0 +1,5314 @@
+@@ -0,0 +1,5317 @@
+/*
+ * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
+ * VA Linux Systems Inc., Fremont, California.
@@ -42317,6 +42334,9 @@
+# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18)
+# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)
+# define R300_LVDS_SRC_SEL_RMX (2 << 18)
++#define RADEON_LVDS_SS_GEN_CNTL 0x02ec
++# define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT 16
++# define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT 20
+
+#define RADEON_MAX_LATENCY 0x0f3f /* PCI */
+#define RADEON_MC_AGP_LOCATION 0x014c
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.954
retrieving revision 1.955
diff -u -r1.954 -r1.955
--- kernel.spec 17 Sep 2008 18:45:22 -0000 1.954
+++ kernel.spec 18 Sep 2008 00:36:25 -0000 1.955
@@ -1758,6 +1758,9 @@
%kernel_variant_files -k vmlinux %{with_kdump} kdump
%changelog
+* Thu Sep 18 2008 Dave Airlie <airlied at redhat.com>
+- update radeon LVDS bits from AMD
+
* Wed Sep 17 2008 Dave Jones <davej at redhat.com>
- 2.6.27-rc6-git5
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