rpms/kernel/devel drm-modesetting-radeon.patch, 1.27, 1.28 kernel.spec, 1.957, 1.958 drm-add-more-drm-error-msg.patch, 1.1, NONE drm-allow-r300-dst-pipe-config.patch, 1.1, NONE drm-fix-pll-computation-precedence.patch, 1.2, NONE
Dave Airlie
airlied at fedoraproject.org
Thu Sep 18 23:32:42 UTC 2008
Author: airlied
Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv20091
Modified Files:
drm-modesetting-radeon.patch kernel.spec
Removed Files:
drm-add-more-drm-error-msg.patch
drm-allow-r300-dst-pipe-config.patch
drm-fix-pll-computation-precedence.patch
Log Message:
* Thu Sep 18 2008 Dave Airlie <airlied at redhat.com>
- Merge krh's patches + new patches from AMD
drm-modesetting-radeon.patch:
Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-modesetting-radeon.patch,v
retrieving revision 1.27
retrieving revision 1.28
diff -u -r1.27 -r1.28
--- drm-modesetting-radeon.patch 18 Sep 2008 00:36:24 -0000 1.27
+++ drm-modesetting-radeon.patch 18 Sep 2008 23:32:41 -0000 1.28
@@ -1,3 +1,33 @@
+commit 6a804321a2b1220143a64a3a78d72b03770fd285
+Author: Dave Airlie <airlied at linux.ie>
+Date: Fri Sep 19 09:17:36 2008 +1000
+
+ radeon: port Alexs patches from modesetting-gem
+
+commit 757bdeefa398c5b856d6321e3622436c676d04a5
+Author: Kristian Høgsberg <krh at redhat.com>
+Date: Thu Sep 18 16:10:29 2008 -0400
+
+ radeon: Add DRM_ERROR() messages to all EINVAL exits from DRM_RADEON_CS.
+
+ Shouldn't trigger under normal use and when something breaks, it will
+ be easier to debug.
+
+commit 90f000493d3f8ea7338756e06fd644e0dcf0aff6
+Author: Kristian Høgsberg <krh at redhat.com>
+Date: Thu Sep 18 16:07:50 2008 -0400
+
+ Allow R300_DST_PIPE_CONFIG for R420 and up.
+
+ The X server emits writes to R300_DST_PIPE_CONFIG for R420 chipsets during
+ accel init.
+
+commit af13076bbaad40f3553346a366b25942483f54fb
+Author: Kristian Høgsberg <krh at redhat.com>
+Date: Thu Sep 18 14:53:46 2008 -0400
+
+ radeon kms: Get precedence right when computing PLL values.
+
commit 41b33ad8bfd879c37f72e560e0b1e1b57f537093
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Thu Sep 18 09:55:14 2008 +1000
@@ -27158,10 +27188,10 @@
+#endif /* _ATOMBIOS_H */
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
new file mode 100644
-index 0000000..a618132
+index 0000000..aafd4c2
--- /dev/null
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
-@@ -0,0 +1,381 @@
+@@ -0,0 +1,400 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
@@ -27314,8 +27344,7 @@
+ atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&conv_param);
+}
+
-+void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode,
-+ int pll_flags)
++void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
+{
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct drm_device *dev = crtc->dev;
@@ -27327,13 +27356,26 @@
+ PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
+ uint32_t sclock = mode->clock;
+ uint32_t ref_div = 0, fb_div = 0, post_div = 0;
++ struct radeon_pll *pll;
++ int pll_flags = 0;
+
+ memset(&spc_param, 0, sizeof(SET_PIXEL_CLOCK_PS_ALLOCATION));
+
-+ pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
++ if (!radeon_is_avivo(dev_priv))
++ pll_flags |= RADEON_PLL_LEGACY;
++
++ if (mode->clock > 120000) /* range limits??? */
++ pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
++ else
++ pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
++
++ if (radeon_crtc->crtc_id == 0)
++ pll = &dev_priv->mode_info.p1pll;
++ else
++ pll = &dev_priv->mode_info.p2pll;
+
-+ radeon_compute_pll(&dev_priv->mode_info.pll, mode->clock,
-+ &sclock, &fb_div, &ref_div, &post_div, pll_flags);
++ radeon_compute_pll(pll, mode->clock, &sclock,
++ &fb_div, &ref_div, &post_div, pll_flags);
+
+ if (radeon_is_avivo(dev_priv)) {
+ uint32_t ss_cntl;
@@ -27450,6 +27492,12 @@
+ RADEON_WRITE(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
+ (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
+
++ if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
++ RADEON_WRITE(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
++ AVIVO_D1MODE_INTERLEAVE_EN);
++ else
++ RADEON_WRITE(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
++ 0);
+}
+
+void atombios_crtc_mode_set(struct drm_crtc *crtc,
@@ -27462,7 +27510,6 @@
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct drm_encoder *encoder;
+ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
-+ int pll_flags = 0;
+ /* TODO color tiling */
+
+ memset(&crtc_timing, 0, sizeof(crtc_timing));
@@ -27499,12 +27546,14 @@
+ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
+ crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
+
-+ atombios_crtc_set_pll(crtc, adjusted_mode, pll_flags);
-+
-+ atombios_crtc_set_timing(crtc, &crtc_timing);
-+
+ if (radeon_is_avivo(dev_priv))
+ atombios_crtc_set_base(crtc, x, y);
++ else
++ radeon_crtc_set_base(crtc, x, y);
++
++ atombios_crtc_set_pll(crtc, adjusted_mode);
++
++ atombios_crtc_set_timing(crtc, &crtc_timing);
+}
+
+static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
@@ -27544,7 +27593,7 @@
+ drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
+}
diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c
-index 4b27d9a..cd6db70 100644
+index 4b27d9a..422554e 100644
--- a/drivers/gpu/drm/radeon/r300_cmdbuf.c
+++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c
@@ -166,8 +166,6 @@ void r300_init_reg_flags(struct drm_device *dev)
@@ -27597,7 +27646,7 @@
ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
+ ADD_RANGE(R500_SU_REG_DEST, 1);
-+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV410) {
++ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
+ ADD_RANGE(R300_DST_PIPE_CONFIG, 1);
+ }
+
@@ -28030,10 +28079,10 @@
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
new file mode 100644
-index 0000000..4d98cba
+index 0000000..2848487
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
-@@ -0,0 +1,453 @@
+@@ -0,0 +1,528 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
@@ -28073,7 +28122,7 @@
+ struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
+};
+
-+static inline struct radeon_i2c_bus_rec radeon_lookup_gpio_for_ddc(struct drm_device *dev, uint8_t id)
++static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device *dev, uint8_t id)
+{
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct atom_context *ctx = dev_priv->mode_info.atom_context;
@@ -28196,13 +28245,13 @@
+ (dev_priv->chip_family == CHIP_RS740)) {
+ if ((i == ATOM_DEVICE_DFP2_INDEX) || (i == ATOM_DEVICE_DFP3_INDEX))
+ mode_info->bios_connector[i].ddc_i2c =
-+ radeon_lookup_gpio_for_ddc(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
++ radeon_lookup_gpio(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
+ else
+ mode_info->bios_connector[i].ddc_i2c =
-+ radeon_lookup_gpio_for_ddc(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
++ radeon_lookup_gpio(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
+ } else
+ mode_info->bios_connector[i].ddc_i2c =
-+ radeon_lookup_gpio_for_ddc(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
++ radeon_lookup_gpio(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
+
+ if (i == ATOM_DEVICE_DFP1_INDEX)
+ mode_info->bios_connector[i].tmds_type = TMDS_INT;
@@ -28313,32 +28362,79 @@
+ int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
+ union firmware_info *firmware_info;
+ uint8_t frev, crev;
-+ struct radeon_pll *pll = &mode_info->pll;
++ struct radeon_pll *p1pll = &mode_info->p1pll;
++ struct radeon_pll *p2pll = &mode_info->p2pll;
++ struct radeon_pll *spll = &mode_info->spll;
++ struct radeon_pll *mpll = &mode_info->mpll;
+ uint16_t data_offset;
+
+ atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
+
+ firmware_info = (union firmware_info *)(mode_info->atom_context->bios + data_offset);
+
-+ pll->reference_freq = le16_to_cpu(firmware_info->info.usReferenceClock);
-+ pll->reference_div = 0;
++ if (firmware_info) {
++ /* pixel clocks */
++ p1pll->reference_freq = le16_to_cpu(firmware_info->info.usReferenceClock);
++ p1pll->reference_div = 0;
+
-+ pll->pll_out_min = le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
-+ pll->pll_out_max = le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
++ p1pll->pll_out_min = le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
++ p1pll->pll_out_max = le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
+
-+ if (pll->pll_out_min == 0) {
-+ if (radeon_is_avivo(dev_priv))
-+ pll->pll_out_min = 64800;
-+ else
-+ pll->pll_out_min = 20000;
-+ }
++ if (p1pll->pll_out_min == 0) {
++ if (radeon_is_avivo(dev_priv))
++ p1pll->pll_out_min = 64800;
++ else
++ p1pll->pll_out_min = 20000;
++ }
+
-+ pll->pll_in_min = le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
-+ pll->pll_in_max = le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
++ p1pll->pll_in_min = le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
++ p1pll->pll_in_max = le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
+
-+ pll->xclk = le16_to_cpu(firmware_info->info.usMaxPixelClock);
++ *p2pll = *p1pll;
+
-+ return true;
++ /* system clock */
++ spll->reference_freq = le16_to_cpu(firmware_info->info.usReferenceClock);
++ spll->reference_div = 0;
++
++ spll->pll_out_min = le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
++ spll->pll_out_max = le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
++
++ /* ??? */
++ if (spll->pll_out_min == 0) {
++ if (radeon_is_avivo(dev_priv))
++ spll->pll_out_min = 64800;
++ else
++ spll->pll_out_min = 20000;
++ }
++
++ spll->pll_in_min = le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
++ spll->pll_in_max = le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
++
++
++ /* memory clock */
++ mpll->reference_freq = le16_to_cpu(firmware_info->info.usReferenceClock);
++ mpll->reference_div = 0;
++
++ mpll->pll_out_min = le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
++ mpll->pll_out_max = le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
++
++ /* ??? */
++ if (mpll->pll_out_min == 0) {
++ if (radeon_is_avivo(dev_priv))
++ mpll->pll_out_min = 64800;
++ else
++ mpll->pll_out_min = 20000;
++ }
++
++ mpll->pll_in_min = le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
++ mpll->pll_in_max = le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
++
++ mode_info->sclk = le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
++ mode_info->mclk = le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
++
++ return true;
++ }
++ return false;
+}
+
+
@@ -28362,11 +28458,11 @@
+ for (i = 0; i < 4; i++) {
+ encoder->tmds_pll[i].freq = le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
+ encoder->tmds_pll[i].value = tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
-+ encoder->tmds_pll[i].value |= (tmds_info->asMiscInfo[i].ucPLL_VCO_Gain & 0x3f << 6);
-+ encoder->tmds_pll[i].value |= (tmds_info->asMiscInfo[i].ucPLL_DutyCycle & 0xf << 12);
-+ encoder->tmds_pll[i].value |= (tmds_info->asMiscInfo[i].ucPLL_VoltageSwing & 0xf << 16);
++ encoder->tmds_pll[i].value |= (tmds_info->asMiscInfo[i].ucPLL_VCO_Gain & 0x3f) << 6;
++ encoder->tmds_pll[i].value |= (tmds_info->asMiscInfo[i].ucPLL_DutyCycle & 0xf) << 12;
++ encoder->tmds_pll[i].value |= (tmds_info->asMiscInfo[i].ucPLL_VoltageSwing & 0xf) << 16;
+
-+ DRM_DEBUG("TMDS PLL From BIOS %u %x\n",
++ DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
+ encoder->tmds_pll[i].freq,
+ encoder->tmds_pll[i].value);
+
@@ -28396,17 +28492,19 @@
+
+ lvds_info = (union lvds_info *)(mode_info->atom_context->bios + data_offset);
+
-+ encoder->dotclock = le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
-+ encoder->panel_xres = le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
-+ encoder->panel_yres = le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
-+ encoder->hblank = le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
-+ encoder->hoverplus = le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
-+ encoder->hsync_width = le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
-+
-+ encoder->vblank = le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
-+ encoder->voverplus = le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
-+ encoder->vsync_width = le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
-+ encoder->panel_pwr_delay = le16_to_cpu(lvds_info->info.usOffDelayInMs);
++ if (lvds_info) {
++ encoder->dotclock = le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
++ encoder->panel_xres = le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
++ encoder->panel_yres = le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
++ encoder->hblank = le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
++ encoder->hoverplus = le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
++ encoder->hsync_width = le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
++
++ encoder->vblank = le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
++ encoder->voverplus = le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
++ encoder->vsync_width = le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
++ encoder->panel_pwr_delay = le16_to_cpu(lvds_info->info.usOffDelayInMs);
++ }
+}
+
+void radeon_atom_dyn_clk_setup(struct drm_device *dev, int enable)
@@ -28435,6 +28533,32 @@
+ atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
+}
+
++void radeon_atom_set_engine_clock(struct drm_device *dev, int eng_clock)
++{
++ struct drm_radeon_private *dev_priv = dev->dev_private;
++ struct radeon_mode_info *mode_info = &dev_priv->mode_info;
++ struct atom_context *ctx = mode_info->atom_context;
++ SET_ENGINE_CLOCK_PS_ALLOCATION args;
++ int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
++
++ args.ulTargetEngineClock = eng_clock; /* 10 khz */
++
++ atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
++void radeon_atom_set_memory_clock(struct drm_device *dev, int mem_clock)
++{
++ struct drm_radeon_private *dev_priv = dev->dev_private;
++ struct radeon_mode_info *mode_info = &dev_priv->mode_info;
++ struct atom_context *ctx = mode_info->atom_context;
++ SET_MEMORY_CLOCK_PS_ALLOCATION args;
++ int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
++
++ args.ulTargetMemoryClock = mem_clock; /* 10 khz */
++
++ atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
++}
++
+void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
+{
+ struct drm_radeon_private *dev_priv = dev->dev_private;
@@ -28936,10 +29060,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
new file mode 100644
-index 0000000..3219b99
+index 0000000..19f274c
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
-@@ -0,0 +1,1359 @@
+@@ -0,0 +1,1404 @@
+/*
+ * Copyright 2004 ATI Technologies Inc., Markham, Ontario
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
@@ -29015,7 +29139,7 @@
+ COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
+ COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
+ COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
-+ COMBIOS_POWERPLAY_TABLE, /* offset from mobile info */
++ COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
+ COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
+ COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
+ COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
@@ -29267,7 +29391,7 @@
+ offset = check_offset;
+ }
+ break;
-+ case COMBIOS_POWERPLAY_TABLE: /* offset from mobile info */
++ case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
+ check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
+ if (check_offset) {
+ check_offset = radeon_bios16(dev_priv, check_offset + 0x11);
@@ -29369,33 +29493,72 @@
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct radeon_mode_info *mode_info = &dev_priv->mode_info;
+ uint16_t pll_info;
-+ struct radeon_pll *pll = &mode_info->pll;
++ struct radeon_pll *p1pll = &mode_info->p1pll;
++ struct radeon_pll *p2pll = &mode_info->p2pll;
++ struct radeon_pll *spll = &mode_info->spll;
++ struct radeon_pll *mpll = &mode_info->mpll;
+ int8_t rev;
++ uint16_t sclk, mclk;
+
+ pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
+ if (pll_info) {
+ rev = radeon_bios8(dev_priv, pll_info);
+
-+ pll->reference_freq = radeon_bios16(dev_priv, pll_info + 0xe);
-+ pll->reference_div = radeon_bios16(dev_priv, pll_info + 0x10);
-+ pll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x12);
-+ pll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x16);
++ /* pixel clocks */
++ p1pll->reference_freq = radeon_bios16(dev_priv, pll_info + 0xe);
++ p1pll->reference_div = radeon_bios16(dev_priv, pll_info + 0x10);
++ p1pll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x12);
++ p1pll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x16);
+
+ if (rev > 9) {
-+ pll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x36);
-+ pll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x3a);
++ p1pll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x36);
++ p1pll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x3a);
+ } else {
-+ pll->pll_in_min = 40;
-+ pll->pll_in_max = 500;
++ p1pll->pll_in_min = 40;
++ p1pll->pll_in_max = 500;
+ }
++ *p2pll = *p1pll;
+
-+ pll->xclk = radeon_bios16(dev_priv, pll_info + 0x08);
++ /* system clock */
++ spll->reference_freq = radeon_bios16(dev_priv, pll_info + 0x1a);
++ spll->reference_div = radeon_bios16(dev_priv, pll_info + 0x1c);
++ spll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x1e);
++ spll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x22);
++
++ if (rev > 10) {
++ spll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x48);
++ spll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x4c);
++ } else {
++ /* ??? */
++ spll->pll_in_min = 40;
++ spll->pll_in_max = 500;
++ }
++
++ /* memory clock */
++ mpll->reference_freq = radeon_bios16(dev_priv, pll_info + 0x26);
++ mpll->reference_div = radeon_bios16(dev_priv, pll_info + 0x28);
++ mpll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x2a);
++ mpll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x2e);
++
++ if (rev > 10) {
++ mpll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x5a);
++ mpll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x5e);
++ } else {
++ /* ??? */
++ mpll->pll_in_min = 40;
++ mpll->pll_in_max = 500;
++ }
+
-+ // sclk/mclk use fixed point
-+ //sclk = radeon_bios16(pll_info + 8) / 100.0;
-+ //mclk = radeon_bios16(pll_info + 10) / 100.0;
-+ //if (sclk == 0) sclk = 200;
-+ //if (mclk == 0) mclk = 200;
++ /* default sclk/mclk */
++ sclk = radeon_bios16(dev_priv, pll_info + 0x8);
++ mclk = radeon_bios16(dev_priv, pll_info + 0xa);
++ if (sclk == 0)
++ sclk = 200;
++ if (mclk == 0)
++ mclk = 200;
++
++ mode_info->sclk = sclk;
++ mode_info->mclk = mclk;
+
+ return true;
+ }
@@ -29686,6 +29849,9 @@
+ for (i = 0; i < n; i++) {
+ encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmds_info + i * 10 + 0x08);
+ encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmds_info + i * 10 + 0x10);
++ DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
++ encoder->tmds_pll[i].freq,
++ encoder->tmds_pll[i].value);
+ }
+ return true;
+ } else if (ver == 4) {
@@ -29700,6 +29866,9 @@
+ stride += 10;
+ else
+ stride += 6;
++ DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
++ encoder->tmds_pll[i].freq,
++ encoder->tmds_pll[i].value);
+ }
+ return true;
+ }
@@ -30673,7 +30842,7 @@
+ return NULL;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
-index 248ab4a..7870d0f 100644
+index 248ab4a..202ba8b 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -31,6 +31,7 @@
@@ -30754,7 +30923,7 @@
{
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
-@@ -138,12 +182,57 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
+@@ -138,20 +182,98 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
}
}
@@ -30815,8 +30984,10 @@
+ radeon_pll_errata_after_data(dev_priv);
}
- static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
-@@ -152,6 +241,39 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
+-static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
++u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
+ {
+ RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
return RADEON_READ(RADEON_PCIE_DATA);
}
@@ -32081,7 +32252,7 @@
+ if (dev_priv->chip_family == CHIP_R300 &&
+ (RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11)
+ dev_priv->pll_errata |= CHIP_ERRATA_R300_CG;
-+
++
+ if (dev_priv->chip_family == CHIP_RV200 ||
+ dev_priv->chip_family == CHIP_RS200)
+ dev_priv->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
@@ -32233,10 +32404,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
new file mode 100644
-index 0000000..c8b0c97
+index 0000000..b5a2be8
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
-@@ -0,0 +1,412 @@
+@@ -0,0 +1,417 @@
+/*
+ * Copyright 2008 Jerome Glisse.
+ * All Rights Reserved.
@@ -32293,6 +32464,7 @@
+ }
+ /* limit cs to 64K ib */
+ if (cs->dwords > (16 * 1024)) {
++ DRM_ERROR("cs->dwords too big: %d\n", cs->dwords);
+ return -EINVAL;
+ }
+ /* copy cs from userspace maybe we should copy into ib to save
@@ -32311,6 +32483,7 @@
+ /* get ib */
+ r = dev_priv->cs.ib_get(dev, &ib, cs->dwords, &card_offset);
+ if (r) {
++ DRM_ERROR("ib_get failed\n");
+ goto out;
+ }
+
@@ -32424,6 +32597,7 @@
+ packets[offset_dw + 2] = val;
+ }
+ default:
++ DRM_ERROR("reg is %x, not RADEON_CNTL_HOSTDATA_BLT\n", reg);
+ return -EINVAL;
+ }
+ return 0;
@@ -32485,14 +32659,16 @@
+ }
+
+ ret = radeon_cs_relocate_packet0(dev, file_priv, packets, offset_dw);
-+ if (ret)
++ if (ret) {
++ DRM_ERROR("failed to relocate packet\n");
+ return ret;
++ }
+ DRM_DEBUG("need to relocate %x %d\n", reg, flags);
+ /* okay it should be followed by a NOP */
+ } else if (flags == MARK_CHECK_SCISSOR) {
+ DRM_DEBUG("need to validate scissor %x %d\n", reg, flags);
+ } else {
-+ DRM_DEBUG("illegal register %x %d\n", reg, flags);
++ DRM_ERROR("illegal register %x %d\n", reg, flags);
+ return -EINVAL;
+ }
+ break;
@@ -32900,10 +33076,10 @@
+
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
new file mode 100644
-index 0000000..a2cb66a
+index 0000000..972f4d3
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_display.c
-@@ -0,0 +1,651 @@
+@@ -0,0 +1,738 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
@@ -33302,7 +33478,10 @@
+ (post_div == 7) ||
+ (post_div == 9) ||
+ (post_div == 10) ||
-+ (post_div == 11))
++ (post_div == 11) ||
++ (post_div == 13) ||
++ (post_div == 14) ||
++ (post_div == 15))
+ continue;
+ }
+
@@ -33354,7 +33533,12 @@
+ best_freq = current_freq;
+ best_error = error;
+ best_vco_diff = vco_diff;
-+ } else if ((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) {
++ } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
++ ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
++ ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
++ ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
++ ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
++ ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
+ best_post_div = post_div;
+ best_ref_div = ref_div;
+ best_feedback_div = feedback_div;
@@ -33381,7 +33565,10 @@
+void radeon_get_clock_info(struct drm_device *dev)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
-+ struct radeon_pll *pll = &dev_priv->mode_info.pll;
++ struct radeon_pll *p1pll = &dev_priv->mode_info.p1pll;
++ struct radeon_pll *p2pll = &dev_priv->mode_info.p2pll;
++ struct radeon_pll *spll = &dev_priv->mode_info.spll;
++ struct radeon_pll *mpll = &dev_priv->mode_info.mpll;
+ int ret;
+
+ if (dev_priv->is_atom_bios)
@@ -33390,25 +33577,101 @@
+ ret = radeon_combios_get_clock_info(dev);
+
+ if (ret) {
-+
-+ if (pll->reference_div < 2) pll->reference_div = 12;
++ if (p1pll->reference_div < 2)
++ p1pll->reference_div = 12;
++ if (p2pll->reference_div < 2)
++ p2pll->reference_div = 12;
+ } else {
+ // TODO FALLBACK
+ }
+
++ /* pixel clocks */
+ if (radeon_is_avivo(dev_priv)) {
-+ pll->min_post_div = 2;
-+ pll->max_post_div = 0x7f;
++ p1pll->min_post_div = 2;
++ p1pll->max_post_div = 0x7f;
++ p2pll->min_post_div = 2;
++ p2pll->max_post_div = 0x7f;
+ } else {
-+ pll->min_post_div = 1;
-+ pll->max_post_div = 12; // 16 on crtc 0??
-+ }
++ p1pll->min_post_div = 1;
++ p1pll->max_post_div = 16;
++ p2pll->min_post_div = 1;
++ p2pll->max_post_div = 12;
++ }
++
++ p1pll->min_ref_div = 2;
++ p1pll->max_ref_div = 0x3ff;
++ p1pll->min_feedback_div = 4;
++ p1pll->max_feedback_div = 0x7ff;
++ p1pll->best_vco = 0;
++
++ p2pll->min_ref_div = 2;
++ p2pll->max_ref_div = 0x3ff;
++ p2pll->min_feedback_div = 4;
++ p2pll->max_feedback_div = 0x7ff;
++ p2pll->best_vco = 0;
++
++ /* system clock */
++ spll->min_post_div = 1;
++ spll->max_post_div = 1;
++ spll->min_ref_div = 2;
++ spll->max_ref_div = 0xff;
++ spll->min_feedback_div = 4;
++ spll->max_feedback_div = 0xff;
++ spll->best_vco = 0;
++
++ /* memory clock */
++ mpll->min_post_div = 1;
++ mpll->max_post_div = 1;
++ mpll->min_ref_div = 2;
++ mpll->max_ref_div = 0xff;
++ mpll->min_feedback_div = 4;
++ mpll->max_feedback_div = 0xff;
++ mpll->best_vco = 0;
++
++}
++
++/* not sure of the best place for these */
++/* 10 khz */
++void radeon_legacy_set_engine_clock(struct drm_device *dev, int eng_clock)
++{
++ struct drm_radeon_private *dev_priv = dev->dev_private;
++ struct radeon_mode_info *mode_info = &dev_priv->mode_info;
++ struct radeon_pll *spll = &mode_info->spll;
++ uint32_t ref_div, fb_div;
++ uint32_t m_spll_ref_fb_div;
++
++ /* FIXME wait for idle */
+
-+ pll->min_ref_div = 2;
-+ pll->max_ref_div = 0x3ff;
-+ pll->min_feedback_div = 4;
-+ pll->max_feedback_div = 0x7ff;
-+ pll->best_vco = 0;
++ m_spll_ref_fb_div = RADEON_READ_PLL(dev_priv, RADEON_M_SPLL_REF_FB_DIV);
++ m_spll_ref_fb_div &= ((RADEON_M_SPLL_REF_DIV_MASK << RADEON_M_SPLL_REF_DIV_SHIFT) |
++ (RADEON_MPLL_FB_DIV_MASK << RADEON_MPLL_FB_DIV_SHIFT));
++ ref_div = m_spll_ref_fb_div & RADEON_M_SPLL_REF_DIV_MASK;
++
++ fb_div = radeon_div(eng_clock * ref_div, spll->reference_freq);
++ m_spll_ref_fb_div |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
++ RADEON_WRITE_PLL(dev_priv, RADEON_M_SPLL_REF_FB_DIV, m_spll_ref_fb_div);
++
++}
++
++/* 10 khz */
++void radeon_legacy_set_memory_clock(struct drm_device *dev, int mem_clock)
++{
++ struct drm_radeon_private *dev_priv = dev->dev_private;
++ struct radeon_mode_info *mode_info = &dev_priv->mode_info;
++ struct radeon_pll *mpll = &mode_info->mpll;
++ uint32_t ref_div, fb_div;
++ uint32_t m_spll_ref_fb_div;
++
++ /* FIXME wait for idle */
++
++ m_spll_ref_fb_div = RADEON_READ_PLL(dev_priv, RADEON_M_SPLL_REF_FB_DIV);
++ m_spll_ref_fb_div &= ((RADEON_M_SPLL_REF_DIV_MASK << RADEON_M_SPLL_REF_DIV_SHIFT) |
++ (RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT));
++ ref_div = m_spll_ref_fb_div & RADEON_M_SPLL_REF_DIV_MASK;
++
++ fb_div = radeon_div(mem_clock * ref_div, mpll->reference_freq);
++ m_spll_ref_fb_div |= (fb_div & RADEON_MPLL_FB_DIV_MASK) << RADEON_MPLL_FB_DIV_SHIFT;
++ RADEON_WRITE_PLL(dev_priv, RADEON_M_SPLL_REF_FB_DIV, m_spll_ref_fb_div);
+
+}
+
@@ -33671,7 +33934,7 @@
}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
-index 0993816..e15a47a 100644
+index 0993816..484642d 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -34,6 +34,8 @@
@@ -34178,7 +34441,7 @@
#define R500_D1CRTC_STATUS 0x609c
#define R500_D2CRTC_STATUS 0x689c
#define R500_CRTC_V_BLANK (1<<0)
-@@ -1156,19 +1298,35 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -1156,19 +1298,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define RADEON_RING_HIGH_MARK 128
#define RADEON_PCIGART_TABLE_SIZE (32*1024)
@@ -34199,6 +34462,7 @@
- RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
+extern u32 RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr);
+extern void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data);
++extern u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr);
+
+#define RADEON_WRITE_P(reg, val, mask) \
+do { \
@@ -34221,7 +34485,7 @@
#define RADEON_WRITE_PCIE(addr, val) \
do { \
RADEON_WRITE8(RADEON_PCIE_INDEX, \
-@@ -1224,7 +1382,7 @@ do { \
+@@ -1224,7 +1383,7 @@ do { \
#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
@@ -34230,7 +34494,7 @@
} while (0)
#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
-@@ -1301,8 +1459,9 @@ do { \
+@@ -1301,8 +1460,9 @@ do { \
} while (0)
#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
@@ -34242,7 +34506,7 @@
if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
int __ret = radeon_do_cp_idle( dev_priv ); \
if ( __ret ) return __ret; \
-@@ -1408,4 +1567,142 @@ do { \
+@@ -1408,4 +1568,142 @@ do { \
write &= mask; \
} while (0)
@@ -34387,10 +34651,10 @@
#endif /* __RADEON_DRV_H__ */
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
new file mode 100644
-index 0000000..e791ab7
+index 0000000..f39dcc1
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
-@@ -0,0 +1,1081 @@
+@@ -0,0 +1,1093 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
@@ -34910,9 +35174,15 @@
+}
+
+static bool radeon_atom_dac_mode_fixup(struct drm_encoder *encoder,
-+ struct drm_display_mode *mode,
-+ struct drm_display_mode *adjusted_mode)
++ struct drm_display_mode *mode,
++ struct drm_display_mode *adjusted_mode)
+{
++
++ /* hw bug */
++ if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
++ && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
++ adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
++
+ return true;
+}
+
@@ -35380,6 +35650,12 @@
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
++
++ /* hw bug */
++ if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
++ && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
++ adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
++
+ return true;
+}
+
@@ -38353,10 +38629,10 @@
radeon_enable_interrupt(dev);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
new file mode 100644
-index 0000000..58c2f9d
+index 0000000..d51fc52
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
-@@ -0,0 +1,1020 @@
+@@ -0,0 +1,1025 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
@@ -38760,7 +39036,7 @@
+ uint32_t post_divider = 0;
+ uint32_t freq = 0;
+ uint8_t pll_gain;
-+ int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV;
++ int pll_flags = RADEON_PLL_LEGACY;
+ bool use_bios_divs = false;
+ /* PLL registers */
+ uint32_t ppll_ref_div = 0;
@@ -38768,7 +39044,7 @@
+ uint32_t htotal_cntl = 0;
+ uint32_t vclk_ecp_cntl;
+
-+ struct radeon_pll *pll = &dev_priv->mode_info.pll;
++ struct radeon_pll *pll = &dev_priv->mode_info.p1pll;
+
+ struct {
+ int divider;
@@ -38790,6 +39066,11 @@
+ { 0, 0 }
+ };
+
++ if (mode->clock > 120000) /* range limits??? */
++ pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
++ else
++ pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
++
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ if (encoder->crtc == crtc) {
+ if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
@@ -38844,7 +39125,7 @@
+ vclk_ecp_cntl = (RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL) &
+ ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
+
-+ pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.pll.reference_freq,
++ pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.p1pll.reference_freq,
+ ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
+ ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK);
+
@@ -39171,7 +39452,7 @@
+ uint32_t htotal_cntl2 = 0;
+ uint32_t pixclks_cntl;
+
-+ struct radeon_pll *pll = &dev_priv->mode_info.pll;
++ struct radeon_pll *pll = &dev_priv->mode_info.p2pll;
+
+ struct {
+ int divider;
@@ -39241,7 +39522,7 @@
+ ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
+ RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
+
-+ pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.pll.reference_freq,
++ pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.p2pll.reference_freq,
+ p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
+ p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK);
+
@@ -40744,12 +41025,25 @@
+
+ return encoder;
+}
+diff --git a/drivers/gpu/drm/radeon/radeon_mem.c b/drivers/gpu/drm/radeon/radeon_mem.c
+index 4af5286..05bbb90 100644
+--- a/drivers/gpu/drm/radeon/radeon_mem.c
++++ b/drivers/gpu/drm/radeon/radeon_mem.c
+@@ -294,7 +294,7 @@ int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *fi
+ return -EFAULT;
+
+ if (*heap) {
+- DRM_ERROR("heap already initialized?");
++ DRM_ERROR("heap already initialized?\n");
+ return -EFAULT;
+ }
+
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
new file mode 100644
-index 0000000..a4ee78a
+index 0000000..d4b33dd
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
-@@ -0,0 +1,337 @@
+@@ -0,0 +1,348 @@
+/*
+ * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
+ * VA Linux Systems Inc., Fremont, California.
@@ -40889,11 +41183,16 @@
+
+#define RADEON_MAX_BIOS_CONNECTOR 16
+
-+#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
-+#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
-+#define RADEON_PLL_USE_REF_DIV (1 << 2)
-+#define RADEON_PLL_LEGACY (1 << 3)
-+#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
++#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
++#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
++#define RADEON_PLL_USE_REF_DIV (1 << 2)
++#define RADEON_PLL_LEGACY (1 << 3)
++#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
++#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
++#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
++#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
++#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
++#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
+
+struct radeon_pll {
+ uint16_t reference_freq;
@@ -40913,10 +41212,22 @@
+ uint32_t best_vco;
+};
+
++struct radeon_i2c_chan {
++ struct drm_device *dev;
++ struct i2c_adapter adapter;
++ struct i2c_algo_bit_data algo;
++ struct radeon_i2c_bus_rec rec;
++};
++
+struct radeon_mode_info {
+ struct atom_context *atom_context;
+ struct radeon_bios_connector bios_connector[RADEON_MAX_BIOS_CONNECTOR];
-+ struct radeon_pll pll;
++ struct radeon_pll p1pll;
++ struct radeon_pll p2pll;
++ struct radeon_pll spll;
++ struct radeon_pll mpll;
++ uint32_t mclk;
++ uint32_t sclk;
+};
+
+struct radeon_crtc {
@@ -40930,14 +41241,6 @@
+ struct drm_mode_set mode_set;
+};
+
-+struct radeon_i2c_chan {
-+ struct drm_device *dev;
-+ struct i2c_adapter adapter;
-+ struct i2c_algo_bit_data algo;
-+ struct radeon_i2c_bus_rec rec;
-+};
-+
-+
+#define RADEON_USE_RMX 1
+
+struct radeon_encoder {
@@ -41030,6 +41333,8 @@
+ int x, int y);
+extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
+
++extern void radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y);
++
+extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
+ struct drm_file *file_priv,
+ uint32_t handle,
@@ -41089,10 +41394,10 @@
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
new file mode 100644
-index 0000000..c7a57b9
+index 0000000..92d44b5
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
-@@ -0,0 +1,180 @@
+@@ -0,0 +1,240 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
@@ -41273,12 +41578,72 @@
+
+ return 0;
+}
++
++bool radeon_set_pcie_lanes(struct drm_device *dev, int lanes)
++{
++ drm_radeon_private_t *dev_priv = dev->dev_private;
++ uint32_t link_width_cntl, mask;
++
++ /* FIXME wait for idle */
++
++
++ switch (lanes) {
++ case 0:
++ mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
++ break;
++ case 1:
++ mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
++ break;
++ case 2:
++ mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
++ break;
++ case 4:
++ mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
++ break;
++ case 8:
++ mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
++ break;
++ case 12:
++ mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
++ break;
++ case 16:
++ default:
++ mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
++ break;
++ }
++
++ link_width_cntl = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
++
++ if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
++ (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
++ return true;
++
++ link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
++ RADEON_PCIE_LC_RECONFIG_NOW |
++ RADEON_PCIE_LC_RECONFIG_LATER |
++ RADEON_PCIE_LC_SHORT_RECONFIG_EN);
++ link_width_cntl |= mask;
++ RADEON_WRITE_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
++ RADEON_WRITE_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl | RADEON_PCIE_LC_RECONFIG_NOW);
++
++ /* wait for lane set to complete */
++ link_width_cntl = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
++ while (link_width_cntl == 0xffffffff)
++ link_width_cntl = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
++
++ if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
++ (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
++ return true;
++ else
++ return false;
++}
++
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
new file mode 100644
-index 0000000..52fb0b9
+index 0000000..3341d38
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
-@@ -0,0 +1,5317 @@
+@@ -0,0 +1,5343 @@
+/*
+ * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
+ * VA Linux Systems Inc., Fremont, California.
@@ -41555,6 +41920,24 @@
+#define RADEON_BUS_CNTL1 0x0034
+# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
+
++//#define RADEON_PCIE_INDEX 0x0030
++//#define RADEON_PCIE_DATA 0x0034
++#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */
++# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0
++# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7
++# define RADEON_PCIE_LC_LINK_WIDTH_X0 0
++# define RADEON_PCIE_LC_LINK_WIDTH_X1 1
++# define RADEON_PCIE_LC_LINK_WIDTH_X2 2
++# define RADEON_PCIE_LC_LINK_WIDTH_X4 3
++# define RADEON_PCIE_LC_LINK_WIDTH_X8 4
++# define RADEON_PCIE_LC_LINK_WIDTH_X12 5
++# define RADEON_PCIE_LC_LINK_WIDTH_X16 6
++# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4
++# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70
++# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)
++# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)
++# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)
++
+#define RADEON_CACHE_CNTL 0x1724
+#define RADEON_CACHE_LINE 0x0f0c /* PCI */
+#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
@@ -42812,6 +43195,13 @@
+#define RADEON_SC_TOP_LEFT_C 0x1c88
+# define RADEON_SC_SIGN_MASK_LO 0x8000
+# define RADEON_SC_SIGN_MASK_HI 0x80000000
++#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */
++# define RADEON_M_SPLL_REF_DIV_SHIFT 0
++# define RADEON_M_SPLL_REF_DIV_MASK 0xff
++# define RADEON_MPLL_FB_DIV_SHIFT 8
++# define RADEON_MPLL_FB_DIV_MASK 0xff
++# define RADEON_SPLL_FB_DIV_SHIFT 16
++# define RADEON_SPLL_FB_DIV_MASK 0xff
+#define RADEON_SCLK_CNTL 0x000d /* PLL */
+# define RADEON_SCLK_SRC_SEL_MASK 0x0007
+# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
@@ -44839,7 +45229,7 @@
+#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
+
+#define AVIVO_D1CRTC_CONTROL 0x6080
-+# define AVIVO_CRTC_EN (1<<0)
++# define AVIVO_CRTC_EN (1 << 0)
+#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
+#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
+#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
@@ -44851,30 +45241,30 @@
+
+#define AVIVO_D1GRPH_ENABLE 0x6100
+#define AVIVO_D1GRPH_CONTROL 0x6104
-+# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0)
-+# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0)
-+# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0)
-+# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0)
-+
-+# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8)
-+
-+# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8)
-+# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8)
-+# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8)
-+# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8)
-+# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8)
-+
-+# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8)
-+# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8)
-+# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8)
-+# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8)
-+
-+
-+# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8)
-+
-+# define AVIVO_D1GRPH_SWAP_RB (1<<16)
-+# define AVIVO_D1GRPH_TILED (1<<20)
-+# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21)
++# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0)
++# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0)
++# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0)
++# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0)
++
++# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8)
++
++# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8)
++# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1 << 8)
++# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2 << 8)
++# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3 << 8)
++# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4 << 8)
++
++# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8)
++# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1 << 8)
++# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2 << 8)
++# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3 << 8)
++
++
++# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8)
++
++# define AVIVO_D1GRPH_SWAP_RB (1 << 16)
++# define AVIVO_D1GRPH_TILED (1 << 20)
++# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21)
+
+#define AVIVO_D1GRPH_LUT_SEL 0x6108
+#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
@@ -44900,7 +45290,7 @@
+#define AVIVO_D1CUR_POSITION 0x6414
+#define AVIVO_D1CUR_HOT_SPOT 0x6418
+#define AVIVO_D1CUR_UPDATE 0x6424
-+# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16)
++# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16)
+
+#define AVIVO_DC_LUT_RW_SELECT 0x6480
+#define AVIVO_DC_LUT_RW_MODE 0x6484
@@ -44920,7 +45310,8 @@
+#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
+#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
+
-+
++#define AVIVO_D1MODE_DATA_FORMAT 0x6528
++# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
+#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
+#define AVIVO_D1MODE_VIEWPORT_START 0x6580
+#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
@@ -44930,7 +45321,7 @@
+#define AVIVO_D1SCL_SCALER_ENABLE 0x6590
+#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594
+#define AVIVO_D1SCL_UPDATE 0x65cc
-+# define AVIVO_D1SCL_UPDATE_LOCK (1<<16)
++# define AVIVO_D1SCL_UPDATE_LOCK (1 << 16)
+
+/* second crtc */
+#define AVIVO_D2CRTC_H_TOTAL 0x6800
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.957
retrieving revision 1.958
diff -u -r1.957 -r1.958
--- kernel.spec 18 Sep 2008 20:16:01 -0000 1.957
+++ kernel.spec 18 Sep 2008 23:32:41 -0000 1.958
@@ -1764,6 +1764,9 @@
%kernel_variant_files -k vmlinux %{with_kdump} kdump
%changelog
+* Thu Sep 18 2008 Dave Airlie <airlied at redhat.com>
+- Merge krh's patches + new patches from AMD
+
* Thu Sep 18 2008 Kristian Høgsberg <krh at redhat.com>
- Fix precedence in PLL value computation.
- Allow R300_DST_PIPE_CONFIG register write use by X.
--- drm-add-more-drm-error-msg.patch DELETED ---
--- drm-allow-r300-dst-pipe-config.patch DELETED ---
--- drm-fix-pll-computation-precedence.patch DELETED ---
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