rpms/xorg-x11-drv-ati/devel .cvsignore, 1.27, 1.28 radeon-6.12.0-git-fixes.patch, 1.1, 1.2 radeon-modeset.patch, 1.40, 1.41 sources, 1.27, 1.28 xorg-x11-drv-ati.spec, 1.162, 1.163
Dave Airlie
airlied at fedoraproject.org
Wed Apr 1 08:54:39 UTC 2009
Author: airlied
Update of /cvs/pkgs/rpms/xorg-x11-drv-ati/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv8131
Modified Files:
.cvsignore radeon-6.12.0-git-fixes.patch radeon-modeset.patch
sources xorg-x11-drv-ati.spec
Log Message:
* Wed Apr 01 2009 Dave Airlie <airlied at redhat.com> 6.12.1-1
- rebase to upstream + fix FUS on DRI2 + video on r100/r200 hopefully
Index: .cvsignore
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/.cvsignore,v
retrieving revision 1.27
retrieving revision 1.28
diff -u -r1.27 -r1.28
--- .cvsignore 14 Mar 2009 08:42:43 -0000 1.27
+++ .cvsignore 1 Apr 2009 08:54:08 -0000 1.28
@@ -1 +1 @@
-xf86-video-ati-6.12.0.tar.bz2
+xf86-video-ati-6.12.1.tar.bz2
radeon-6.12.0-git-fixes.patch:
View full diff with command:
/usr/bin/cvs -f diff -kk -u -N -r 1.1 -r 1.2 radeon-6.12.0-git-fixes.patch
Index: radeon-6.12.0-git-fixes.patch
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/radeon-6.12.0-git-fixes.patch,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -r1.1 -r1.2
--- radeon-6.12.0-git-fixes.patch 16 Mar 2009 02:17:17 -0000 1.1
+++ radeon-6.12.0-git-fixes.patch 1 Apr 2009 08:54:08 -0000 1.2
@@ -1,514 +1,2097 @@
+diff --git a/configure.ac b/configure.ac
+index 3848f4c..660ea1f 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -22,7 +22,7 @@
+
+ AC_PREREQ(2.57)
+ AC_INIT([xf86-video-ati],
+- 6.12.1,
++ 6.12.1.99,
+ [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
+ xf86-video-ati)
+
+diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
+index d532f16..f31cadb 100644
+--- a/src/ati_pciids_gen.h
++++ b/src/ati_pciids_gen.h
+@@ -429,3 +429,10 @@
+ #define PCI_CHIP_RS780_9612 0x9612
+ #define PCI_CHIP_RS780_9613 0x9613
+ #define PCI_CHIP_RS780_9614 0x9614
++#define PCI_CHIP_RS780_9615 0x9615
++#define PCI_CHIP_RS780_9616 0x9616
++#define PCI_CHIP_RS880_9710 0x9710
++#define PCI_CHIP_RS880_9711 0x9711
++#define PCI_CHIP_RS880_9712 0x9712
++#define PCI_CHIP_RS880_9713 0x9713
++#define PCI_CHIP_RS880_9714 0x9714
diff --git a/src/atombios_output.c b/src/atombios_output.c
-index 130ab93..70e716c 100644
+index 35d1767..4af04c1 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
-@@ -1019,30 +1019,11 @@ static void atom_rv515_force_tv_scaler(ScrnInfoPtr pScrn)
- static int
- atombios_output_yuv_setup(xf86OutputPtr output, Bool enable)
- {
-- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
- ENABLE_YUV_PS_ALLOCATION disp_data;
- AtomBiosArgRec data;
- unsigned char *space;
-- unsigned char *RADEONMMIO = info->MMIO;
-- uint32_t temp, reg;
--
-- if (info->ChipFamily >= CHIP_FAMILY_R600)
-- reg = R600_BIOS_3_SCRATCH;
-- else
-- reg = RADEON_BIOS_3_SCRATCH;
--
-- //fix up scratch reg handling
-- temp = INREG(reg);
-- if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT))
-- OUTREG(reg, (ATOM_S3_TV1_ACTIVE |
-- (radeon_crtc->crtc_id << 18)));
-- else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT))
-- OUTREG(reg, (ATOM_S3_CV_ACTIVE |
-- (radeon_crtc->crtc_id << 24)));
-- else
-- OUTREG(reg, 0);
-
- memset(&disp_data, 0, sizeof(disp_data));
-
-@@ -1055,15 +1036,10 @@ atombios_output_yuv_setup(xf86OutputPtr output, Bool enable)
- data.exec.pspace = &disp_data;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
--
-- OUTREG(reg, temp);
--
- ErrorF("crtc %d YUV %s setup success\n", radeon_crtc->crtc_id, enable ? "enable" : "disable");
- return ATOM_SUCCESS;
- }
-
-- OUTREG(reg, temp);
--
- ErrorF("crtc %d YUV %s setup failed\n", radeon_crtc->crtc_id, enable ? "enable" : "disable");
- return ATOM_NOT_IMPLEMENTED;
+@@ -1406,8 +1406,12 @@ atombios_set_output_crtc_source(xf86OutputPtr output)
+ default:
+ if (IS_AVIVO_VARIANT)
+ crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
+- else
+- crtc_src_param.ucCRTC = radeon_crtc->crtc_id << 2;
++ else {
++ if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)
++ crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
++ else
++ crtc_src_param.ucCRTC = radeon_crtc->crtc_id << 2;
++ }
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
+index 4d4e625..bff80ca 100644
+--- a/src/pcidb/ati_pciids.csv
++++ b/src/pcidb/ati_pciids.csv
+@@ -430,3 +430,10 @@
+ "0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics"
+ "0x9613","RS780_9613","RS780",,1,,,1,"ATI Radeon 3100 Graphics"
+ "0x9614","RS780_9614","RS780",,1,,,1,"ATI Radeon HD 3300 Graphics"
++"0x9615","RS780_9615","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics"
++"0x9616","RS780_9616","RS780",,1,,,1,"ATI Radeon 3000 Graphics"
++"0x9710","RS880_9710","RS880",,1,,,1,"ATI Radeon HD Graphics"
++"0x9711","RS880_9711","RS880",,1,,,1,"ATI Radeon Graphics"
++"0x9712","RS880_9712","RS880",1,1,,,1,"ATI Mobility Radeon HD Graphics"
++"0x9713","RS880_9713","RS880",1,1,,,1,"ATI Mobility Radeon Graphics"
++"0x9714","RS880_9714","RS880",,1,,,1,"ATI Radeon Graphics"
+diff --git a/src/r600_exa.c b/src/r600_exa.c
+index 40f02e1..2dc33a8 100644
+--- a/src/r600_exa.c
++++ b/src/r600_exa.c
+@@ -1098,6 +1098,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
+ unsigned int i;
+ tex_resource_t tex_res;
+ tex_sampler_t tex_samp;
++ int pix_r, pix_g, pix_b, pix_a;
-diff --git a/src/radeon_accel.c b/src/radeon_accel.c
-index dffbc57..a9a4848 100644
---- a/src/radeon_accel.c
-+++ b/src/radeon_accel.c
-@@ -688,8 +688,6 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard)
- drmBufPtr buffer = info->cp->indirectBuffer;
- int start = info->cp->indirectStart;
- drm_radeon_indirect_t indirect;
-- RING_LOCALS;
-- RADEONCP_REFRESH(pScrn, info);
-
- if (!buffer) return;
- if (start == buffer->used && !discard) return;
-@@ -700,10 +698,14 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard)
+ CLEAR (tex_res);
+ CLEAR (tex_samp);
+@@ -1142,46 +1143,102 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
+ switch (pPict->format) {
+ case PICT_a1r5g5b5:
+ case PICT_a8r8g8b8:
+- tex_res.dst_sel_x = SQ_SEL_Z; /* R */
+- tex_res.dst_sel_y = SQ_SEL_Y; /* G */
+- tex_res.dst_sel_z = SQ_SEL_X; /* B */
+- tex_res.dst_sel_w = SQ_SEL_W; /* A */
++ pix_r = SQ_SEL_Z; /* R */
++ pix_g = SQ_SEL_Y; /* G */
++ pix_b = SQ_SEL_X; /* B */
++ pix_a = SQ_SEL_W; /* A */
+ break;
+ case PICT_a8b8g8r8:
+- tex_res.dst_sel_x = SQ_SEL_X; /* R */
+- tex_res.dst_sel_y = SQ_SEL_Y; /* G */
+- tex_res.dst_sel_z = SQ_SEL_Z; /* B */
+- tex_res.dst_sel_w = SQ_SEL_W; /* A */
++ pix_r = SQ_SEL_X; /* R */
++ pix_g = SQ_SEL_Y; /* G */
++ pix_b = SQ_SEL_Z; /* B */
++ pix_a = SQ_SEL_W; /* A */
+ break;
+ case PICT_x8b8g8r8:
+- tex_res.dst_sel_x = SQ_SEL_X; /* R */
+- tex_res.dst_sel_y = SQ_SEL_Y; /* G */
+- tex_res.dst_sel_z = SQ_SEL_Z; /* B */
+- tex_res.dst_sel_w = SQ_SEL_1; /* A */
++ pix_r = SQ_SEL_X; /* R */
++ pix_g = SQ_SEL_Y; /* G */
++ pix_b = SQ_SEL_Z; /* B */
++ pix_a = SQ_SEL_1; /* A */
+ break;
+ case PICT_x1r5g5b5:
+ case PICT_x8r8g8b8:
+- tex_res.dst_sel_x = SQ_SEL_Z; /* R */
+- tex_res.dst_sel_y = SQ_SEL_Y; /* G */
+- tex_res.dst_sel_z = SQ_SEL_X; /* B */
+- tex_res.dst_sel_w = SQ_SEL_1; /* A */
+- break;
+ case PICT_r5g6b5:
+- tex_res.dst_sel_x = SQ_SEL_Z; /* R */
+- tex_res.dst_sel_y = SQ_SEL_Y; /* G */
+- tex_res.dst_sel_z = SQ_SEL_X; /* B */
+- tex_res.dst_sel_w = SQ_SEL_1; /* A */
++ pix_r = SQ_SEL_Z; /* R */
++ pix_g = SQ_SEL_Y; /* G */
++ pix_b = SQ_SEL_X; /* B */
++ pix_a = SQ_SEL_1; /* A */
+ break;
+ case PICT_a8:
+- tex_res.dst_sel_x = SQ_SEL_0; /* R */
+- tex_res.dst_sel_y = SQ_SEL_0; /* G */
+- tex_res.dst_sel_z = SQ_SEL_0; /* B */
+- tex_res.dst_sel_w = SQ_SEL_X; /* A */
++ pix_r = SQ_SEL_0; /* R */
[...2186 lines suppressed...]
++ (2 << R200_TXC_TFACTOR_SEL_SHIFT) |
++ R200_TXC_SCALE_2X |
++ (R200_TXC_REPL_RED << R200_TXC_REPL_ARG_B_SHIFT) |
++ R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
++ OUT_ACCEL_REG(R200_PP_TXABLEND_2,
++ R200_TXA_ARG_A_ZERO |
++ R200_TXA_ARG_B_ZERO |
++ R200_TXA_ARG_C_ZERO |
++ R200_TXA_COMP_ARG_C |
++ R200_TXA_OP_MADD);
++ OUT_ACCEL_REG(R200_PP_TXABLEND2_2,
++ R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
++
++ /* shader constants */
++ OUT_ACCEL_REG(R200_PP_TFACTOR_0, float4touint(1.0, /* src range [1, 2] */
++ yco - 1.0,
++ -yoff, /* range [-1, 0] */
++ 0.0));
++ OUT_ACCEL_REG(R200_PP_TFACTOR_1, float4touint(uco[0] * 0.125 + 0.5, /* range [-4, 4] */
++ uco[1] * 0.125 + 0.5,
++ uco[2] * 0.125 + 0.5,
++ 0.0));
++ OUT_ACCEL_REG(R200_PP_TFACTOR_2, float4touint(vco[0] * 0.25 + 0.5, /* range [-2, 2] */
++ vco[1] * 0.25 + 0.5,
++ vco[2] * 0.25 + 0.5,
++ 0.0));
++
++ FINISH_ACCEL();
+ }
- break;
- case ATOM_DEVICE_DFP2_SUPPORT:
-- if (connected)
-+ if (connected) {
- save->bios_4_scratch |= RADEON_DFP2_ATTACHED;
-- else
-+ save->bios_5_scratch |= RADEON_DFP2_ON;
-+ } else {
- save->bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
-+ save->bios_5_scratch &= ~RADEON_DFP2_ON;
++ else {
++ BEGIN_ACCEL(13);
++ OUT_ACCEL_REG(RADEON_PP_CNTL,
++ RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
++
++ OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY);
++ OUT_ACCEL_REG(R200_SE_VTX_FMT_1,
++ (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
++
++ OUT_ACCEL_REG(R200_PP_TXFILTER_0,
++ R200_MAG_FILTER_LINEAR |
++ R200_MIN_FILTER_LINEAR |
++ R200_CLAMP_S_CLAMP_LAST |
++ R200_CLAMP_T_CLAMP_LAST |
++ R200_YUV_TO_RGB);
++ OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat);
++ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0);
++ OUT_ACCEL_REG(R200_PP_TXSIZE_0,
++ (pPriv->w - 1) |
++ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
++ OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
++
++ OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset);
++
++ OUT_ACCEL_REG(R200_PP_TXCBLEND_0,
++ R200_TXC_ARG_A_ZERO |
++ R200_TXC_ARG_B_ZERO |
++ R200_TXC_ARG_C_R0_COLOR |
++ R200_TXC_OP_MADD);
++ OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,
++ R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
++ OUT_ACCEL_REG(R200_PP_TXABLEND_0,
++ R200_TXA_ARG_A_ZERO |
++ R200_TXA_ARG_B_ZERO |
++ R200_TXA_ARG_C_R0_ALPHA |
++ R200_TXA_OP_MADD);
++ OUT_ACCEL_REG(R200_PP_TXABLEND2_0,
++ R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
++ FINISH_ACCEL();
+ }
- break;
- }
- OUTREG(RADEON_BIOS_4_SCRATCH, save->bios_4_scratch);
-+ OUTREG(RADEON_BIOS_5_SCRATCH, save->bios_5_scratch);
+ } else {
+
+ info->accel_state->texW[0] = 1;
+ info->accel_state->texH[0] = 1;
+
+- BEGIN_ACCEL(8);
++ BEGIN_ACCEL(9);
++
++ OUT_ACCEL_REG(RADEON_PP_CNTL,
++ RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
+
+ OUT_ACCEL_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY |
+ RADEON_SE_VTX_FMT_ST0));
+@@ -1672,6 +2180,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+ ((float)srcX + (float)srcw * (((float)dsth / (float)dstw) + 1.0)) / info->accel_state->texW[0],
+ (float)srcY / info->accel_state->texH[0]);
+ }
++ } else if (isplanar) {
++ /*
++ * Just render a rect (using three coords).
++ * Filter is a bit a misnomer, it's just texcoords...
++ */
++ VTX_OUT_FILTER((float)dstX, (float)(dstY + dsth),
++ (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0],
++ (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]);
++ VTX_OUT_FILTER((float)(dstX + dstw), (float)(dstY + dsth),
++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0],
++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]);
++ VTX_OUT_FILTER((float)(dstX + dstw), (float)dstY,
++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0],
++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]);
+ } else {
+ /*
+ * Just render a rect (using three coords).
+diff --git a/src/radeon_tv.c b/src/radeon_tv.c
+index 98e3b0a..eef45d9 100644
+--- a/src/radeon_tv.c
++++ b/src/radeon_tv.c
+@@ -815,7 +815,9 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
+ save->tv_rgb_cntl = (RADEON_RGB_DITHER_EN
+ | RADEON_TVOUT_SCALE_EN
+ | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT)
+- | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT));
++ | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT)
++ | RADEON_RGB_ATTEN_SEL(0x3)
++ | RADEON_RGB_ATTEN_VAL(0xc));
+
+ if (IsPrimary) {
+ if (radeon_output->Flags & RADEON_USE_RMX)
+diff --git a/src/radeon_video.c b/src/radeon_video.c
+index 92d1a71..42aa036 100644
+--- a/src/radeon_video.c
++++ b/src/radeon_video.c
+@@ -297,22 +297,19 @@ void RADEONInitVideo(ScreenPtr pScreen)
+ RADEONInitOffscreenImages(pScreen);
}
- }
+- if (info->ChipFamily != CHIP_FAMILY_RV250) {
+- if ((info->ChipFamily < CHIP_FAMILY_RS400)
++ if ((info->ChipFamily < CHIP_FAMILY_RS400)
+ #ifdef XF86DRI
+- || (info->directRenderingEnabled)
++ || (info->directRenderingEnabled)
+ #endif
+- ) {
+- texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen);
+- if (texturedAdaptor != NULL) {
+- adaptors[num_adaptors++] = texturedAdaptor;
+- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n");
+- } else
+- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n");
++ ) {
++ texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen);
++ if (texturedAdaptor != NULL) {
++ adaptors[num_adaptors++] = texturedAdaptor;
++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n");
+ } else
+- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video requires CP on R5xx/R6xx/R7xx/IGP\n");
++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n");
+ } else
+- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video disabled on RV250 due to HW bug\n");
++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video requires CP on R5xx/R6xx/R7xx/IGP\n");
+
+ if(num_adaptors)
+ xf86XVScreenInit(pScreen, adaptors, num_adaptors);
+@@ -1070,11 +1067,11 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn,
+ OvGCr = CAdjGCr * gamma_curve_r100[gamma].OvGammaCont;
+ OvBCb = CAdjBCb * gamma_curve_r100[gamma].OvGammaCont;
+ OvBCr = CAdjBCr * gamma_curve_r100[gamma].OvGammaCont;
+- OvROff = CAdjOff * gamma_curve_r100[gamma].OvGammaCont -
++ OvROff = RedAdj + CAdjOff * gamma_curve_r100[gamma].OvGammaCont -
+ OvLuma * Loff - (OvRCb + OvRCr) * Coff;
+- OvGOff = CAdjOff * gamma_curve_r100[gamma].OvGammaCont -
++ OvGOff = GreenAdj + CAdjOff * gamma_curve_r100[gamma].OvGammaCont -
+ OvLuma * Loff - (OvGCb + OvGCr) * Coff;
+- OvBOff = CAdjOff * gamma_curve_r100[gamma].OvGammaCont -
++ OvBOff = BlueAdj + CAdjOff * gamma_curve_r100[gamma].OvGammaCont -
+ OvLuma * Loff - (OvBCb + OvBCr) * Coff;
+ #if 0 /* default constants */
+ OvROff = -888.5;
+diff --git a/src/radeon_video.h b/src/radeon_video.h
+index 7f1891e..34fb07f 100644
+--- a/src/radeon_video.h
++++ b/src/radeon_video.h
+@@ -90,6 +90,11 @@ typedef struct {
+ void *video_memory;
+ int video_offset;
+
++ Bool planar_hw;
++ Bool planar_state;
++ int planeu_offset;
++ int planev_offset;
++
+ /* bicubic filtering */
+ void *bicubic_memory;
+ int bicubic_offset;
radeon-modeset.patch:
Index: radeon-modeset.patch
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/radeon-modeset.patch,v
retrieving revision 1.40
retrieving revision 1.41
diff -u -r1.40 -r1.41
--- radeon-modeset.patch 1 Apr 2009 07:18:42 -0000 1.40
+++ radeon-modeset.patch 1 Apr 2009 08:54:08 -0000 1.41
@@ -1,5 +1,5 @@
diff --git a/configure.ac b/configure.ac
-index b094a50..29a19e3 100644
+index 660ea1f..4279b60 100644
--- a/configure.ac
+++ b/configure.ac
@@ -114,8 +114,19 @@ if test "$DRI" = yes; then
@@ -1067,7 +1067,7 @@
+#endif
+#endif
diff --git a/src/radeon.h b/src/radeon.h
-index 7bb720a..348ad3f 100644
+index d488429..09e15f4 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -46,6 +46,8 @@
@@ -1095,7 +1095,7 @@
/* Render support */
#ifdef RENDER
#include "picturestr.h"
-@@ -413,6 +417,14 @@ typedef enum {
+@@ -414,6 +418,14 @@ typedef enum {
typedef struct _atomBiosHandle *atomBiosHandlePtr;
@@ -1110,7 +1110,7 @@
typedef struct {
uint32_t pci_device_id;
RADEONChipFamily chip_family;
-@@ -423,7 +435,27 @@ typedef struct {
+@@ -424,7 +436,27 @@ typedef struct {
int singledac;
} RADEONCardInfo;
@@ -1138,7 +1138,7 @@
struct radeon_cp {
Bool CPRuns; /* CP is running */
Bool CPInUse; /* CP has been used by X server */
-@@ -437,6 +469,10 @@ struct radeon_cp {
+@@ -438,6 +470,10 @@ struct radeon_cp {
drmBufPtr indirectBuffer;
int indirectStart;
@@ -1149,7 +1149,7 @@
/* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */
int dma_begin_count;
char *dma_debug_func;
-@@ -503,13 +539,13 @@ struct radeon_dri {
+@@ -504,13 +540,13 @@ struct radeon_dri {
drm_handle_t ringHandle; /* Handle from drmAddMap */
drmSize ringMapSize; /* Size of map */
int ringSize; /* Size of ring (in MB) */
@@ -1165,7 +1165,7 @@
/* CP vertex/indirect buffer data */
unsigned long bufStart; /* Offset into GART space */
-@@ -528,7 +564,6 @@ struct radeon_dri {
+@@ -529,7 +565,6 @@ struct radeon_dri {
drmAddress gartTex; /* Map */
int log2GARTTexGran;
@@ -1173,7 +1173,7 @@
int fbX;
int fbY;
int backX;
-@@ -784,6 +819,7 @@ typedef struct {
+@@ -789,6 +824,7 @@ typedef struct {
RADEONCardType cardType; /* Current card is a PCI card */
struct radeon_cp *cp;
struct radeon_dri *dri;
@@ -1181,7 +1181,7 @@
#ifdef USE_EXA
Bool accelDFS;
#endif
-@@ -887,6 +923,45 @@ typedef struct {
+@@ -892,6 +928,45 @@ typedef struct {
Bool r4xx_atom;
@@ -1227,7 +1227,7 @@
} RADEONInfoRec, *RADEONInfoPtr;
#define RADEONWaitForFifo(pScrn, entries) \
-@@ -1140,6 +1215,24 @@ extern void
+@@ -1147,6 +1222,24 @@ extern void
radeon_legacy_free_memory(ScrnInfoPtr pScrn,
void *mem_struct);
@@ -1252,7 +1252,7 @@
#ifdef XF86DRI
# ifdef USE_XAA
/* radeon_accelfuncs.c */
-@@ -1158,7 +1251,9 @@ do { \
+@@ -1165,7 +1258,9 @@ do { \
#define RADEONCP_RELEASE(pScrn, info) \
do { \
@@ -1263,7 +1263,7 @@
RADEON_PURGE_CACHE(); \
RADEON_WAIT_UNTIL_IDLE(); \
RADEONCPReleaseIndirect(pScrn); \
-@@ -1193,7 +1288,7 @@ do { \
+@@ -1200,7 +1295,7 @@ do { \
#define RADEONCP_REFRESH(pScrn, info) \
do { \
@@ -1272,7 +1272,7 @@
if (info->cp->needCacheFlush) { \
RADEON_PURGE_CACHE(); \
RADEON_PURGE_ZCACHE(); \
-@@ -1220,6 +1315,13 @@ do { \
+@@ -1227,6 +1322,13 @@ do { \
#define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0
#define BEGIN_RING(n) do { \
@@ -1286,7 +1286,7 @@
if (RADEON_VERBOSE) { \
xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
"BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\
-@@ -1232,13 +1334,6 @@ do { \
+@@ -1239,13 +1341,6 @@ do { \
} \
info->cp->dma_debug_func = __FILE__; \
info->cp->dma_debug_lineno = __LINE__; \
@@ -1300,7 +1300,7 @@
__expected = n; \
__head = (pointer)((char *)info->cp->indirectBuffer->address + \
info->cp->indirectBuffer->used); \
-@@ -1281,6 +1376,14 @@ do { \
+@@ -1288,6 +1383,14 @@ do { \
OUT_RING(val); \
} while (0)
@@ -1316,7 +1316,7 @@
do { \
if (RADEON_VERBOSE) \
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
-index dffbc57..1531c81 100644
+index a9a4848..9d02ac8 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -92,6 +92,7 @@
@@ -1590,7 +1590,7 @@
#if 0
/* FIXME: pScrn->pScreen has not been initialized when this is first
-@@ -694,6 +817,11 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard)
+@@ -692,6 +815,11 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard)
if (!buffer) return;
if (start == buffer->used && !discard) return;
@@ -1602,7 +1602,7 @@
if (RADEON_VERBOSE) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Flushing buffer %d\n",
buffer->idx);
-@@ -749,10 +877,16 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn)
+@@ -750,10 +878,16 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn)
}
}
@@ -1619,7 +1619,7 @@
if (RADEON_VERBOSE) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Releasing buffer %d\n",
-@@ -879,6 +1013,7 @@ RADEONHostDataBlit(
+@@ -880,6 +1014,7 @@ RADEONHostDataBlit(
ret = ( uint8_t* )&__head[__count];
__count += dwords;
@@ -1627,7 +1627,7 @@
ADVANCE_RING();
*y += *hpass;
-@@ -1013,7 +1148,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen)
+@@ -1014,7 +1149,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen)
#ifdef USE_EXA
if (info->useEXA) {
# ifdef XF86DRI
@@ -1636,7 +1636,7 @@
if (info->ChipFamily >= CHIP_FAMILY_R600) {
if (!R600DrawInit(pScreen))
return FALSE;
-@@ -1046,7 +1181,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen)
+@@ -1047,7 +1182,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen)
}
#ifdef XF86DRI
@@ -1645,7 +1645,7 @@
RADEONAccelInitCP(pScreen, a);
else
#endif /* XF86DRI */
-@@ -1068,11 +1203,13 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn)
+@@ -1069,11 +1204,13 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR (pScrn);
#ifdef XF86DRI
@@ -1663,7 +1663,7 @@
RADEONInit3DEngineCP(pScrn);
} else
#endif
-@@ -1080,7 +1217,7 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn)
+@@ -1081,7 +1218,7 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn)
info->accel_state->XInited3D = TRUE;
}
@@ -2403,7 +2403,7 @@
+int radeon_bo_gem_name_buffer(dri_bo *bo, uint32_t *name);
+#endif
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
-index eabd87d..8712a74 100644
+index a9bc7d2..6c22339 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -62,12 +62,15 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
@@ -2601,7 +2601,7 @@
CURSOR_SWAPPING_START();
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
-index 9c9fc7f..aa6352e 100644
+index f6c6261..1699d8a 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -40,6 +40,8 @@
@@ -2845,7 +2845,7 @@
}
/* AGP Mode Quirk List - Certain hostbridge/gfx-card combos don't work with
-@@ -990,6 +1146,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -992,6 +1148,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[agp] ring handle = 0x%08x\n",
(unsigned int)info->dri->ringHandle);
@@ -2854,7 +2854,7 @@
if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
&info->dri->ring) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n");
-@@ -998,9 +1156,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1000,9 +1158,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Ring mapped at 0x%08lx\n",
(unsigned long)info->dri->ring);
@@ -2866,7 +2866,7 @@
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not add ring read ptr mapping\n");
return FALSE;
-@@ -1009,6 +1168,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1011,6 +1170,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[agp] ring read ptr handle = 0x%08x\n",
(unsigned int)info->dri->ringReadPtrHandle);
@@ -2875,7 +2875,7 @@
if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize,
&info->dri->ringReadPtr) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
-@@ -1018,6 +1179,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1020,6 +1181,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Ring read ptr mapped at 0x%08lx\n",
(unsigned long)info->dri->ringReadPtr);
@@ -2883,7 +2883,7 @@
if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize,
DRM_AGP, 0, &info->dri->bufHandle) < 0) {
-@@ -1095,6 +1257,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1097,6 +1259,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[pci] ring handle = 0x%08x\n",
(unsigned int)info->dri->ringHandle);
@@ -2891,7 +2891,7 @@
if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
&info->dri->ring) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n");
-@@ -1106,6 +1269,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1108,6 +1271,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring contents 0x%08lx\n",
*(unsigned long *)(pointer)info->dri->ring);
@@ -2899,7 +2899,7 @@
if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize,
DRM_SCATTER_GATHER, flags, &info->dri->ringReadPtrHandle) < 0) {
-@@ -1117,8 +1281,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1119,8 +1283,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[pci] ring read ptr handle = 0x%08x\n",
(unsigned int)info->dri->ringReadPtrHandle);
@@ -2910,7 +2910,7 @@
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not map ring read ptr\n");
return FALSE;
-@@ -1129,6 +1295,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1131,6 +1297,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring read ptr contents 0x%08lx\n",
*(unsigned long *)(pointer)info->dri->ringReadPtr);
@@ -2918,7 +2918,7 @@
if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize,
DRM_SCATTER_GATHER, 0, &info->dri->bufHandle) < 0) {
-@@ -1181,6 +1348,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1183,6 +1350,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
*/
static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
@@ -2928,7 +2928,7 @@
/* Map registers */
info->dri->registerSize = info->MMIOSize;
if (drmAddMap(info->dri->drmFD, info->MMIOAddr, info->dri->registerSize,
-@@ -1221,20 +1391,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1223,20 +1393,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
drmInfo.fb_bpp = info->CurrentLayout.pixel_code;
drmInfo.depth_bpp = (info->dri->depthBits - 8) * 2;
@@ -2966,7 +2966,7 @@
if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT,
&drmInfo, sizeof(drm_radeon_init_t)) < 0)
return FALSE;
-@@ -1243,8 +1416,9 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1245,8 +1418,9 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
* registers back to their default values, so we need to restore
* those engine register here.
*/
@@ -2978,7 +2978,7 @@
return TRUE;
}
-@@ -1442,12 +1616,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
+@@ -1444,12 +1618,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
/* Get DRM version & close DRM */
info->dri->pKernelDRMVersion = drmGetVersion(fd);
@@ -2992,7 +2992,7 @@
}
/* Now check if we qualify */
-@@ -1481,10 +1654,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
+@@ -1483,10 +1656,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
req_patch);
drmFreeVersion(info->dri->pKernelDRMVersion);
info->dri->pKernelDRMVersion = NULL;
@@ -3023,7 +3023,7 @@
}
Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
-@@ -1493,6 +1685,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
+@@ -1495,6 +1687,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int value = 0;
@@ -3033,7 +3033,7 @@
if (!info->want_vblank_interrupts)
on = FALSE;
-@@ -1512,6 +1707,52 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
+@@ -1514,6 +1709,52 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
return TRUE;
}
@@ -3086,7 +3086,7 @@
/* Initialize the screen-specific data structures for the DRI and the
* Radeon. This is the main entry point to the device-specific
-@@ -1575,10 +1816,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+@@ -1577,10 +1818,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4;
pDRIInfo->ddxDriverMinorVersion = 3;
pDRIInfo->ddxDriverPatchVersion = 0;
@@ -3113,7 +3113,7 @@
pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES;
pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES
< RADEON_MAX_DRAWABLES
-@@ -1631,9 +1884,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+@@ -1633,9 +1886,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d;
pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d;
pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d;
@@ -3124,7 +3124,7 @@
pDRIInfo->ClipNotify = RADEONDRIClipNotify;
#endif
-@@ -1665,57 +1916,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+@@ -1667,57 +1918,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo = NULL;
return FALSE;
}
@@ -3229,7 +3229,7 @@
static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
-@@ -1757,17 +2011,21 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
+@@ -1759,17 +2013,21 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
return FALSE;
}
@@ -3259,7 +3259,7 @@
/* Initialize and start the CP if required */
RADEONDRICPInit(pScrn);
-@@ -1776,6 +2034,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
+@@ -1778,6 +2036,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
pSAREAPriv = (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScreen);
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
@@ -3270,7 +3270,7 @@
pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate;
pRADEONDRI->deviceID = info->Chipset;
-@@ -1933,6 +2195,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
+@@ -1935,6 +2197,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
drmUnmap(info->dri->buf, info->dri->bufMapSize);
info->dri->buf = NULL;
}
@@ -3279,7 +3279,7 @@
if (info->dri->ringReadPtr) {
drmUnmap(info->dri->ringReadPtr, info->dri->ringReadMapSize);
info->dri->ringReadPtr = NULL;
-@@ -1941,6 +2205,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
+@@ -1943,6 +2207,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
drmUnmap(info->dri->ring, info->dri->ringMapSize);
info->dri->ring = NULL;
}
@@ -3287,7 +3287,7 @@
if (info->dri->agpMemHandle != DRM_AGP_NO_HANDLE) {
drmAgpUnbind(info->dri->drmFD, info->dri->agpMemHandle);
drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle);
-@@ -2350,3 +2615,11 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
+@@ -2352,3 +2617,11 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
&radeonsetparam, sizeof(drm_radeon_setparam_t));
return ret;
}
@@ -4058,7 +4058,7 @@
+
+#endif
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
-index c0f5e7b..aa60074 100644
+index 8673f5e..8d04d92 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -67,7 +67,7 @@
@@ -4070,7 +4070,7 @@
/* Driver data structures */
#include "radeon.h"
#include "radeon_reg.h"
-@@ -226,7 +226,10 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode,
+@@ -229,7 +229,10 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode,
stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8;
*size = stride;
@@ -4082,7 +4082,7 @@
}
static Bool
RADEONCreateScreenResources (ScreenPtr pScreen)
-@@ -247,6 +250,13 @@ RADEONCreateScreenResources (ScreenPtr pScreen)
+@@ -250,6 +253,13 @@ RADEONCreateScreenResources (ScreenPtr pScreen)
radeonShadowWindow, 0, NULL))
return FALSE;
}
@@ -4096,7 +4096,7 @@
return TRUE;
}
-@@ -1658,6 +1668,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
+@@ -1695,6 +1705,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
}
pScrn->videoRam &= ~1023;
@@ -4104,7 +4104,7 @@
info->FbMapSize = pScrn->videoRam * 1024;
/* if the card is PCI Express reserve the last 32k for the gart table */
-@@ -1787,59 +1798,61 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
+@@ -1824,59 +1835,61 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
"R500 support is under development. Please report any issues to xorg-driver-ati at lists.x.org\n");
}
@@ -4211,7 +4211,7 @@
#ifdef XF86DRI
/* AGP/PCI */
-@@ -2014,6 +2027,15 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
+@@ -2051,6 +2064,15 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
}
info->accel_state->fifo_slots = 0;
@@ -4227,7 +4227,7 @@
if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200) ||
(info->ChipFamily == CHIP_FAMILY_RS300) ||
-@@ -2038,6 +2060,9 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
+@@ -2075,6 +2097,9 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
int errmaj = 0, errmin = 0;
@@ -4237,7 +4237,7 @@
from = X_DEFAULT;
#if defined(USE_EXA)
#if defined(USE_XAA)
-@@ -2048,6 +2073,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
+@@ -2085,6 +2110,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
info->useEXA = TRUE;
} else if (xf86NameCmp(optstr, "XAA") == 0) {
from = X_CONFIG;
@@ -4245,7 +4245,7 @@
}
}
#else /* USE_XAA */
-@@ -2151,15 +2177,9 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10)
+@@ -2189,15 +2215,9 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10)
return TRUE;
}
@@ -4262,7 +4262,7 @@
if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n");
-@@ -2170,6 +2190,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
+@@ -2208,6 +2228,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n");
return FALSE;
}
@@ -4285,7 +4285,7 @@
info->cp->CPInUse = FALSE;
info->cp->CPStarted = FALSE;
info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
-@@ -2727,6 +2763,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = {
+@@ -2771,6 +2807,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = {
RADEONCRTCResize
};
@@ -4323,7 +4323,7 @@
Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
{
xf86CrtcConfigPtr xf86_config;
-@@ -2747,6 +2814,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2791,6 +2858,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
info = RADEONPTR(pScrn);
info->MMIO = NULL;
@@ -4332,7 +4332,7 @@
info->IsSecondary = FALSE;
info->IsPrimary = FALSE;
-@@ -2781,62 +2850,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2825,62 +2894,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
}
info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
@@ -4443,7 +4443,7 @@
if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive))
goto fail;
-@@ -2846,10 +2916,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2890,10 +2960,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR;
pScrn->monitor = pScrn->confScreen->monitor;
@@ -4460,7 +4460,7 @@
if (!RADEONPreInitVisual(pScrn))
goto fail;
-@@ -2863,164 +2935,224 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2907,167 +2979,227 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions));
xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
@@ -4561,6 +4561,11 @@
+
+ RADEONPostInt10Check(pScrn, int10_save);
+- /* Save BIOS scratch registers */
+- RADEONSaveBIOSRegisters(pScrn, info->SavedReg);
++ /* Save BIOS scratch registers */
++ RADEONSaveBIOSRegisters(pScrn, info->SavedReg);
+
+ if (!RADEONPreInitBIOS(pScrn, pInt10))
+ goto fail;
#ifdef XF86DRI
@@ -4812,7 +4817,7 @@
/* Get ScreenInit function */
if (!xf86LoadSubModule(pScrn, "fb")) return FALSE;
-@@ -3035,10 +3167,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -3082,10 +3214,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
if (!RADEONPreInitXv(pScrn)) goto fail;
}
@@ -4829,7 +4834,7 @@
}
if (pScrn->modes == NULL) {
-@@ -3191,6 +3325,9 @@ static void RADEONBlockHandler(int i, pointer blockData,
+@@ -3238,6 +3372,9 @@ static void RADEONBlockHandler(int i, pointer blockData,
#ifdef USE_EXA
info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
@@ -4839,7 +4844,7 @@
#endif
}
-@@ -3279,7 +3416,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3326,7 +3463,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
int subPixelOrder = SubPixelUnknown;
char* s;
#endif
@@ -4848,7 +4853,7 @@
info->accelOn = FALSE;
#ifdef USE_XAA
-@@ -3299,58 +3436,61 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3346,58 +3483,61 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
"RADEONScreenInit %lx %ld\n",
pScrn->memPhysBase, pScrn->fbOffset);
#endif
@@ -4949,7 +4954,7 @@
/* Visual setup */
miClearVisualTypes();
if (!miSetVisualTypes(pScrn->depth,
-@@ -3384,19 +3524,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3431,19 +3571,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
hasDRI = info->directRenderingEnabled;
#endif /* XF86DRI */
@@ -4983,7 +4988,7 @@
}
}
-@@ -3433,7 +3575,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3480,7 +3622,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#ifdef XF86DRI
if (hasDRI) {
info->accelDFS = xf86ReturnOptValBool(info->Options, OPTION_ACCEL_DFS,
@@ -4995,7 +5000,7 @@
/* Reserve approx. half of offscreen memory for local textures by
* default, can be overridden with Option "FBTexPercent".
-@@ -3459,7 +3604,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3506,7 +3651,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#endif
#if defined(XF86DRI) && defined(USE_XAA)
@@ -5004,7 +5009,7 @@
info->dri->textureSize = -1;
if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT,
&(info->dri->textureSize))) {
-@@ -3477,7 +3622,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3524,7 +3669,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#endif
#ifdef USE_XAA
@@ -5013,7 +5018,7 @@
return FALSE;
#endif
-@@ -3498,7 +3643,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3545,7 +3690,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
info->CurrentLayout.pixel_bytes);
int maxy = info->FbMapSize / width_bytes;
@@ -5022,7 +5027,7 @@
xf86DrvMsg(scrnIndex, X_ERROR,
"Static buffer allocation failed. Disabling DRI.\n");
xf86DrvMsg(scrnIndex, X_ERROR,
-@@ -3508,19 +3653,54 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3555,19 +3700,54 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024);
info->directRenderingEnabled = FALSE;
} else {
@@ -5081,7 +5086,7 @@
#endif
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Initializing fb layer\n");
-@@ -3544,7 +3724,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3591,7 +3771,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (info->r600_shadow_fb == FALSE) {
/* Init fb layer */
@@ -5090,7 +5095,7 @@
pScrn->virtualX, pScrn->virtualY,
pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
pScrn->bitsPerPixel))
-@@ -3586,8 +3766,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3633,8 +3813,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* restore the memory map here otherwise we may get a hang when
* initializing the drm below
*/
@@ -5103,7 +5108,7 @@
/* Backing store setup */
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-@@ -3597,7 +3779,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3644,7 +3826,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* DRI finalisation */
#ifdef XF86DRI
@@ -5112,7 +5117,7 @@
info->dri->pKernelDRMVersion->version_minor >= 19)
{
if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0)
-@@ -3613,14 +3795,24 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3660,14 +3842,24 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (info->directRenderingEnabled) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"DRI Finishing init !\n");
@@ -5138,7 +5143,7 @@
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
-@@ -3716,10 +3908,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3763,10 +3955,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
return FALSE;
}
}
@@ -5148,15 +5153,15 @@
- if (!xf86SetDesiredModes (pScrn))
+ if (info->drm_mode_setting) {
+ if (!drmmode_set_desired_modes(pScrn, &info->drmmode))
-+ return FALSE;
+ return FALSE;
+ } else {
+ if (!xf86SetDesiredModes (pScrn))
- return FALSE;
++ return FALSE;
+ }
/* Provide SaveScreen & wrap BlockHandler and CloseScreen */
/* Wrap CloseScreen */
-@@ -5296,7 +5494,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5336,7 +5534,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
#ifdef XF86DRI
Bool CPStarted = info->cp->CPStarted;
@@ -5165,7 +5170,7 @@
DRILock(pScrn->pScreen, 0);
RADEONCP_STOP(pScrn, info);
}
-@@ -5319,8 +5517,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5359,8 +5557,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
#endif
}
@@ -5178,7 +5183,7 @@
ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0);
-@@ -5332,16 +5532,19 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5372,16 +5572,19 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
/* xf86SetRootClip would do, but can't access that here */
}
@@ -5206,7 +5211,7 @@
}
#endif
-@@ -5539,6 +5742,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
+@@ -5579,6 +5782,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
xf86OutputPtr output = config->output[config->compat_output];
xf86CrtcPtr crtc = output->crtc;
@@ -5218,7 +5223,7 @@
/* not handled */
if (IS_AVIVO_VARIANT)
return;
-@@ -5578,76 +5786,101 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
+@@ -5618,76 +5826,101 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONEnterVT\n");
@@ -5370,7 +5375,7 @@
}
#endif
/* this will get XVideo going again, but only if XVideo was initialised
-@@ -5662,7 +5895,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
+@@ -5702,7 +5935,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
info->accel_state->XInited3D = FALSE;
#ifdef XF86DRI
@@ -5379,7 +5384,7 @@
if (info->ChipFamily >= CHIP_FAMILY_R600)
R600LoadShaders(pScrn);
RADEONCP_START(pScrn, info);
-@@ -5686,27 +5919,29 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+@@ -5726,27 +5959,29 @@ void RADEONLeaveVT(int scrnIndex, int flags)
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONLeaveVT\n");
#ifdef XF86DRI
@@ -5425,7 +5430,7 @@
/* Make sure 3D clients will re-upload textures to video RAM */
if (info->dri->textureSize) {
-@@ -5722,6 +5957,11 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+@@ -5762,6 +5997,11 @@ void RADEONLeaveVT(int scrnIndex, int flags)
i = list[i].next;
} while (i != 0);
}
@@ -5437,7 +5442,7 @@
}
#endif
-@@ -5748,10 +5988,18 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+@@ -5788,10 +6028,18 @@ void RADEONLeaveVT(int scrnIndex, int flags)
xf86_hide_cursors (pScrn);
@@ -5459,7 +5464,7 @@
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Ok, leaving now...\n");
-@@ -5805,7 +6053,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
+@@ -5845,7 +6093,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
#endif /* USE_XAA */
if (pScrn->vtSema) {
@@ -5469,7 +5474,7 @@
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-@@ -5840,6 +6089,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
+@@ -5880,6 +6129,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
info->DGAModes = NULL;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Unmapping memory\n");
@@ -7965,7 +7970,7 @@
+
+
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
-index afc8e21..6138f36 100644
+index a0c6b2c..30fee18 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -146,6 +146,27 @@ typedef struct
@@ -8006,7 +8011,7 @@
typedef struct _radeon_encoder {
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
-index 2df299f..ff16f26 100644
+index 79671c0..1ef8dc3 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -40,6 +40,7 @@
@@ -8017,7 +8022,7 @@
#include <X11/extensions/Xv.h>
#include "fourcc.h"
-@@ -124,6 +125,7 @@ static __inline__ uint32_t F_TO_24(float val)
+@@ -133,6 +134,7 @@ static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa)
#define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n))
#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
#define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val))
@@ -8025,7 +8030,7 @@
#define FINISH_ACCEL()
#include "radeon_textured_videofuncs.c"
-@@ -133,6 +135,7 @@ static __inline__ uint32_t F_TO_24(float val)
+@@ -142,6 +144,7 @@ static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa)
#undef BEGIN_ACCEL
#undef OUT_ACCEL_REG
#undef OUT_ACCEL_REG_F
@@ -8033,7 +8038,7 @@
#undef FINISH_ACCEL
#ifdef XF86DRI
-@@ -146,6 +149,7 @@ static __inline__ uint32_t F_TO_24(float val)
+@@ -155,6 +158,7 @@ static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa)
#define OUT_ACCEL_REG_F(reg, val) OUT_ACCEL_REG(reg, F_TO_DW(val))
#define FINISH_ACCEL() ADVANCE_RING()
#define OUT_RING_F(x) OUT_RING(F_TO_DW(x))
@@ -8041,7 +8046,7 @@
#include "radeon_textured_videofuncs.c"
-@@ -374,6 +378,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+@@ -412,6 +416,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
size * 2, 64);
if (pPriv->video_offset == 0)
return BadAlloc;
@@ -8050,8 +8055,8 @@
+ pPriv->src_bo = pPriv->video_memory;
}
- /* Bicubic filter setup */
-@@ -397,6 +404,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+ /* Bicubic filter loading */
+@@ -422,6 +429,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
pPriv->bicubic_src_offset = pPriv->bicubic_offset + info->fbLocation + pScrn->fbOffset;
if (pPriv->bicubic_offset == 0)
pPriv->bicubic_enabled = FALSE;
@@ -8061,7 +8066,7 @@
}
if (pDraw->type == DRAWABLE_WINDOW)
-@@ -426,11 +436,22 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+@@ -451,11 +461,22 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
left = (x1 >> 16) & ~1;
npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left;
@@ -8087,9 +8092,9 @@
+ pPriv->src_addr = (uint8_t *)(info->FB + pPriv->video_offset + (top * dstPitch));
+ }
pPriv->src_pitch = dstPitch;
- pPriv->size = size;
- pPriv->pDraw = pDraw;
-@@ -511,9 +532,24 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+ pPriv->planeu_offset = dstPitch * dst_height;
+ pPriv->planev_offset = pPriv->planeu_offset + dstPitch2 * ((dst_height + 1) >> 1);
+@@ -566,9 +587,24 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
/* Upload bicubic filter tex */
if (pPriv->bicubic_enabled) {
@@ -8117,7 +8122,7 @@
}
/* update cliplist */
-@@ -531,10 +567,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+@@ -586,10 +622,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
pPriv->w = width;
pPriv->h = height;
@@ -8132,10 +8137,24 @@
else
#endif
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
-index f55ae12..5d23ad9 100644
+index 05acb93..b7a8513 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
-@@ -92,6 +92,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+@@ -87,11 +87,25 @@ do { \
+
+ #endif /* !ACCEL_CP */
+
++#define OUT_TEXTURE_REG(reg, offset, bo) do { \
++ if (info->new_cs) { \
++ OUT_ACCEL_REG((reg), (offset)); \
++ OUT_RELOC((bo), RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); \
++ } else { \
++ OUT_ACCEL_REG((reg), (offset) + info->fbLocation + pScrn->fbOffset);} \
++ } while(0)
++
++
+ static void
+ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pPixmap = pPriv->pPixmap;
@@ -8147,7 +8166,7 @@
uint32_t txformat;
uint32_t txfilter, txformat0, txformat1, txoffset, txpitch;
uint32_t dst_offset, dst_pitch, dst_format;
-@@ -100,19 +105,57 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+@@ -101,19 +115,57 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
int dstxoff, dstyoff, pixel_shift, vtx_count;
BoxPtr pBox = REGION_RECTS(&pPriv->clip);
int nBox = REGION_NUM_RECTS(&pPriv->clip);
@@ -8208,7 +8227,7 @@
dst_pitch = pPixmap->devKind;
}
-@@ -143,7 +186,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+@@ -144,7 +196,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEON_WAIT_DMA_GUI_IDLE);
FINISH_ACCEL();
@@ -8217,9 +8236,15 @@
RADEONInit3DEngine(pScrn);
}
-@@ -213,13 +256,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+@@ -222,15 +274,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+ if (IS_R500_3D && ((pPriv->h - 1) & 0x800))
+ txpitch |= R500_TXHEIGHT_11;
- txoffset = pPriv->src_offset;
+- txoffset = pPriv->src_offset;
++ if (info->new_cs)
++ txoffset = 0;
++ else
++ txoffset = pPriv->src_offset;
- BEGIN_ACCEL(6);
+ qwords = info->new_cs ? 7 : 6;
@@ -8230,17 +8255,37 @@
OUT_ACCEL_REG(R300_TX_FORMAT1_0, txformat1);
OUT_ACCEL_REG(R300_TX_FORMAT2_0, txpitch);
- OUT_ACCEL_REG(R300_TX_OFFSET_0, txoffset);
-+ if (info->new_cs) {
-+ OUT_ACCEL_REG(R300_TX_OFFSET_0, 0);
-+ OUT_RELOC(pPriv->src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
-+ } else {
-+ txoffset += info->fbLocation + pScrn->fbOffset;
-+ OUT_ACCEL_REG(R300_TX_OFFSET_0, txoffset);
-+ }
++ OUT_TEXTURE_REG(R300_TX_OFFSET_0, txoffset, pPriv->src_bo);
FINISH_ACCEL();
txenable = R300_TEX_0_ENABLE;
-@@ -240,13 +290,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+@@ -246,19 +302,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+ R300_TX_MIN_FILTER_LINEAR |
+ R300_TX_MAG_FILTER_LINEAR);
+
+- BEGIN_ACCEL(12);
++ qwords = info->new_cs ? 14 : 12;
++ BEGIN_ACCEL(qwords);
+ OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter | (1 << R300_TX_ID_SHIFT));
+ OUT_ACCEL_REG(R300_TX_FILTER1_1, 0);
+ OUT_ACCEL_REG(R300_TX_FORMAT0_1, txformat0);
+ OUT_ACCEL_REG(R300_TX_FORMAT1_1, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_2);
+ OUT_ACCEL_REG(R300_TX_FORMAT2_1, txpitch);
+- OUT_ACCEL_REG(R300_TX_OFFSET_1, txoffset + pPriv->planeu_offset);
++ OUT_TEXTURE_REG(R300_TX_OFFSET_1, txoffset + pPriv->planeu_offset, pPriv->src_bo);
++
+ OUT_ACCEL_REG(R300_TX_FILTER0_2, txfilter | (2 << R300_TX_ID_SHIFT));
+ OUT_ACCEL_REG(R300_TX_FILTER1_2, 0);
+ OUT_ACCEL_REG(R300_TX_FORMAT0_2, txformat0);
+ OUT_ACCEL_REG(R300_TX_FORMAT1_2, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_3);
+ OUT_ACCEL_REG(R300_TX_FORMAT2_2, txpitch);
+- OUT_ACCEL_REG(R300_TX_OFFSET_2, txoffset + pPriv->planev_offset);
++ OUT_TEXTURE_REG(R300_TX_OFFSET_2, txoffset + pPriv->planev_offset, pPriv->src_bo);
++
+ FINISH_ACCEL();
+ txenable |= R300_TEX_1_ENABLE | R300_TEX_2_ENABLE;
+ }
+@@ -279,13 +338,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_TX_MAG_FILTER_NEAREST |
(1 << R300_TX_ID_SHIFT));
@@ -8262,12 +8307,12 @@
FINISH_ACCEL();
/* Enable tex 1 */
-@@ -1332,11 +1388,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+@@ -1536,11 +1601,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
}
}
- BEGIN_ACCEL(6);
-+ qwords = info->new_cs ? 7 : 6;
++ qwords = info->new_cs ? 8 : 6;
+ BEGIN_ACCEL(qwords);
OUT_ACCEL_REG(R300_TX_INVALTAGS, 0);
OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
@@ -8283,39 +8328,112 @@
OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO;
-@@ -1381,6 +1444,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
- RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
+@@ -1591,6 +1663,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+
OUT_ACCEL_REG(RADEON_RB3D_CNTL,
- dst_format | RADEON_ALPHA_BLEND_ENABLE);
+ dst_format /*| RADEON_ALPHA_BLEND_ENABLE*/);
+
+ dst_offset += info->fbLocation + pScrn->fbOffset;
OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, dst_offset);
OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch);
-@@ -1418,7 +1483,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
- ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
-
-- OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset);
-+ OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset +
-+ info->fbLocation + pScrn->fbOffset);
-
- OUT_ACCEL_REG(R200_PP_TXCBLEND_0,
- R200_TXC_ARG_A_ZERO |
-@@ -1451,8 +1517,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+@@ -1630,7 +1704,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+ R200_CLAMP_S_CLAMP_LAST |
+ R200_CLAMP_T_CLAMP_LAST;
+
+- BEGIN_ACCEL(36);
++ qwords = info->new_cs ? 39 : 36;
++ BEGIN_ACCEL(qwords);
+
+ OUT_ACCEL_REG(RADEON_PP_CNTL,
+ RADEON_TEX_0_ENABLE | RADEON_TEX_1_ENABLE | RADEON_TEX_2_ENABLE |
+@@ -1649,21 +1724,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+ (pPriv->w - 1) |
+ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
+ OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
+- OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset);
++ OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, pPriv->src_bo);
+
+ OUT_ACCEL_REG(R200_PP_TXFILTER_1, txfilter);
+ OUT_ACCEL_REG(R200_PP_TXFORMAT_1, txformat | R200_TXFORMAT_ST_ROUTE_STQ1);
+ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_1, 0);
+ OUT_ACCEL_REG(R200_PP_TXSIZE_1, txformat0);
+ OUT_ACCEL_REG(R200_PP_TXPITCH_1, txpitch);
+- OUT_ACCEL_REG(R200_PP_TXOFFSET_1, pPriv->src_offset + pPriv->planeu_offset);
++ OUT_TEXTURE_REG(R200_PP_TXOFFSET_1, txoffset + pPriv->planeu_offset, pPriv->src_bo);
+
+ OUT_ACCEL_REG(R200_PP_TXFILTER_2, txfilter);
+ OUT_ACCEL_REG(R200_PP_TXFORMAT_2, txformat | R200_TXFORMAT_ST_ROUTE_STQ1);
+ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_2, 0);
+ OUT_ACCEL_REG(R200_PP_TXSIZE_2, txformat0);
+ OUT_ACCEL_REG(R200_PP_TXPITCH_2, txpitch);
+- OUT_ACCEL_REG(R200_PP_TXOFFSET_2, pPriv->src_offset + pPriv->planev_offset);
++
++ OUT_TEXTURE_REG(R200_PP_TXOFFSET_2, txoffset + pPriv->planev_offset, pPriv->src_bo);
+
+ /* similar to r300 code. Note the big problem is that hardware constants
+ * are 8 bits only, representing 0.0-1.0. We can get that up (using bias
+@@ -1799,7 +1875,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+ R200_CLAMP_S_CLAMP_LAST |
+ R200_CLAMP_T_CLAMP_LAST;
+
+- BEGIN_ACCEL(24);
++ qwords = info->new_cs ? 25 : 24;
++ BEGIN_ACCEL(qwords);
+
+ OUT_ACCEL_REG(RADEON_PP_CNTL,
+ RADEON_TEX_0_ENABLE |
+@@ -1817,7 +1894,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+ (pPriv->w - 1) |
+ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
+ OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
+- OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset);
++ OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, pPriv->src_bo);
+
+ /* MAD temp1 / 2, const0.a * 2, temp0.ggg, -const0.rgb */
+ OUT_ACCEL_REG(R200_PP_TXCBLEND_0,
+@@ -1901,7 +1978,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+ FINISH_ACCEL();
+ }
+ else {
+- BEGIN_ACCEL(13);
++ qwords = info->new_cs ? 14 : 13;
++ BEGIN_ACCEL(qwords);
+ OUT_ACCEL_REG(RADEON_PP_CNTL,
+ RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
+
+@@ -1922,7 +2000,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
+ OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
+
+- OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset);
++ OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, pPriv->src_bo);
+
+ OUT_ACCEL_REG(R200_PP_TXCBLEND_0,
+ R200_TXC_ARG_A_ZERO |
+@@ -1945,7 +2023,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+ info->accel_state->texW[0] = 1;
+ info->accel_state->texH[0] = 1;
+
+- BEGIN_ACCEL(9);
++ qwords = info->new_cs ? 10 : 9;
++ BEGIN_ACCEL(qwords);
+
+ OUT_ACCEL_REG(RADEON_PP_CNTL,
+ RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
+@@ -1959,8 +2038,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEON_CLAMP_S_CLAMP_LAST |
RADEON_CLAMP_T_CLAMP_LAST |
RADEON_YUV_TO_RGB);
+
OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat);
- OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset);
-+ OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset +
-+ info->fbLocation + pScrn->fbOffset);
++ OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_0, txoffset, pPriv->src_bo);
OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0,
RADEON_COLOR_ARG_A_ZERO |
RADEON_COLOR_ARG_B_ZERO |
diff --git a/src/radeon_video.c b/src/radeon_video.c
-index 92d1a71..03f42a4 100644
+index 42aa036..bd6408d 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -287,7 +287,7 @@ void RADEONInitVideo(ScreenPtr pScreen)
@@ -8327,23 +8445,22 @@
overlayAdaptor = RADEONSetupImageVideo(pScreen);
if (overlayAdaptor != NULL) {
adaptors[num_adaptors++] = overlayAdaptor;
-@@ -297,10 +297,13 @@ void RADEONInitVideo(ScreenPtr pScreen)
+@@ -297,9 +297,12 @@ void RADEONInitVideo(ScreenPtr pScreen)
RADEONInitOffscreenImages(pScreen);
}
-- if (info->ChipFamily != CHIP_FAMILY_RV250) {
+- if ((info->ChipFamily < CHIP_FAMILY_RS400)
+ if (info->ChipFamily >= CHIP_FAMILY_R600 && info->drm_mode_setting) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Disabling textured video for KMS On R600+\n");
-+ } else if (info->ChipFamily != CHIP_FAMILY_RV250) {
- if ((info->ChipFamily < CHIP_FAMILY_RS400)
++ } else if ((info->ChipFamily < CHIP_FAMILY_RS400)
#ifdef XF86DRI
-- || (info->directRenderingEnabled)
-+ || (info->directRenderingEnabled || info->drm_mode_setting)
+- || (info->directRenderingEnabled)
++ || (info->directRenderingEnabled || info->drm_mode_setting)
#endif
- ) {
- texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen);
-@@ -2203,7 +2206,7 @@ RADEONCopyData(
+ ) {
+ texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen);
+@@ -2200,7 +2203,7 @@ RADEONCopyData(
#ifdef XF86DRI
@@ -8353,10 +8470,10 @@
uint8_t *buf;
uint32_t bufPitch, dstPitchOff;
diff --git a/src/radeon_video.h b/src/radeon_video.h
-index 7f1891e..7a5f740 100644
+index 34fb07f..7b75ec3 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
-@@ -116,6 +116,9 @@ typedef struct {
+@@ -121,6 +121,9 @@ typedef struct {
int w, h;
int drw_x, drw_y;
int vsync;
Index: sources
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/sources,v
retrieving revision 1.27
retrieving revision 1.28
diff -u -r1.27 -r1.28
--- sources 14 Mar 2009 08:42:44 -0000 1.27
+++ sources 1 Apr 2009 08:54:08 -0000 1.28
@@ -1 +1 @@
-540b25842f8e09164cf4d2376995dc68 xf86-video-ati-6.12.0.tar.bz2
+2adf5988c5e5b6df5f4cb61006fa2bf1 xf86-video-ati-6.12.1.tar.bz2
Index: xorg-x11-drv-ati.spec
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/xorg-x11-drv-ati.spec,v
retrieving revision 1.162
retrieving revision 1.163
diff -u -r1.162 -r1.163
--- xorg-x11-drv-ati.spec 1 Apr 2009 07:18:42 -0000 1.162
+++ xorg-x11-drv-ati.spec 1 Apr 2009 08:54:08 -0000 1.163
@@ -4,8 +4,8 @@
Summary: Xorg X11 ati video driver
Name: xorg-x11-drv-ati
-Version: 6.12.0
-Release: 3%{?dist}
+Version: 6.12.1
+Release: 1%{?dist}
URL: http://www.x.org
License: MIT
Group: User Interface/X Hardware Support
@@ -76,8 +76,8 @@
%{_mandir}/man4/radeon.4*
%changelog
-* Wed Apr 01 2009 Dave Airlie <airlied at redhat.com> 6.12.0-3
-- radeon-modeset: fix FUS on DRI22
+* Wed Apr 01 2009 Dave Airlie <airlied at redhat.com> 6.12.1-1
+- rebase to upstream + fix FUS on DRI2 + video on r100/r200 hopefully
* Mon Mar 16 2009 Dave Airlie <airlied at redhat.com> 6.12.0-2
- radeon-6.12.0-git-fixes: fixes from git upstream
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