rpms/kernel/F-11 drm-nouveau.patch, 1.38, 1.39 kernel.spec, 1.1547, 1.1548
Ben Skeggs
bskeggs at fedoraproject.org
Thu Apr 16 01:50:54 UTC 2009
Author: bskeggs
Update of /cvs/pkgs/rpms/kernel/F-11
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv20619
Modified Files:
drm-nouveau.patch kernel.spec
Log Message:
* Thu Apr 16 2009 Ben Skeggs <bskeggs at redhat.com>
- drm-nouveau.patch: use less vmalloc space (rh#495843)
drm-nouveau.patch:
Index: drm-nouveau.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-11/drm-nouveau.patch,v
retrieving revision 1.38
retrieving revision 1.39
diff -u -r1.38 -r1.39
--- drm-nouveau.patch 8 Apr 2009 05:01:16 -0000 1.38
+++ drm-nouveau.patch 16 Apr 2009 01:50:53 -0000 1.39
@@ -6534,10 +6534,10 @@
+
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c
new file mode 100644
-index 0000000..547ad94
+index 0000000..83b2f5e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.c
-@@ -0,0 +1,213 @@
+@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2007 Ben Skeggs.
+ * All Rights Reserved.
@@ -6697,13 +6697,9 @@
+ return 0;
+}
+
-+#define READ_GET() ((nv_rd32(chan->get) - chan->pushbuf_base) >> 2)
-+#define WRITE_PUT(val) nv_wr32(chan->put, ((val) << 2) + chan->pushbuf_base)
-+
+int
+nouveau_dma_wait(struct nouveau_channel *chan, int size)
+{
-+ struct drm_device *dev = chan->dev;
+ const int us_timeout = 100000;
+ int ret = -EBUSY, i;
+
@@ -6753,10 +6749,10 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h
new file mode 100644
-index 0000000..1953c39
+index 0000000..4383883
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.h
-@@ -0,0 +1,106 @@
+@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2007 Ben Skeggs.
+ * All Rights Reserved.
@@ -6843,18 +6839,19 @@
+ OUT_RING(chan, (subc << 13) | (size << 18) | mthd);
+}
+
++#define READ_GET() ((nvchan_rd32(0x44) - chan->pushbuf_base) >> 2)
++#define WRITE_PUT(val) nvchan_wr32(0x40, ((val) << 2) + chan->pushbuf_base)
++
+static inline void
+FIRE_RING(struct nouveau_channel *chan)
+{
-+ struct drm_device *dev = chan->dev;
-+
+ if (chan->dma.cur == chan->dma.put)
+ return;
+ chan->accel_done = true;
+
+ DRM_MEMORYBARRIER();
+ chan->dma.put = chan->dma.cur;
-+ nv_wr32(chan->put, (chan->dma.put << 2) + chan->pushbuf_base);
++ WRITE_PUT(chan->dma.put);
+}
+
+/* This should allow easy switching to a real fifo in the future. */
@@ -7061,10 +7058,10 @@
+MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
new file mode 100644
-index 0000000..c5ecceb
+index 0000000..ae93ea1
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
-@@ -0,0 +1,772 @@
+@@ -0,0 +1,776 @@
+/*
+ * Copyright 2005 Stephane Marchesin.
+ * All Rights Reserved.
@@ -7195,7 +7192,7 @@
+ /* mapping of the fifo itself */
+ struct drm_local_map *map;
+ /* mapping of the regs controling the fifo */
-+ struct drm_local_map *regs;
++ struct drm_local_map *user;
+
+ /* Fencing */
+ uint32_t next_sequence;
@@ -7205,12 +7202,6 @@
+ struct mem_block *pushbuf_mem;
+ uint32_t pushbuf_base;
+
-+ /* FIFO user control regs */
-+ uint32_t user, user_size;
-+ uint32_t put;
-+ uint32_t get;
-+ uint32_t ref_cnt;
-+
+ /* Notifier memory */
+ struct mem_block *notifier_block;
+ struct mem_block *notifier_heap;
@@ -7798,6 +7789,16 @@
+#define nv_out08(map,reg,val) DRM_WRITE8(NVDEV->map, (reg), (val))
+#define nv_in08(map,reg) DRM_READ8(NVDEV->map, (reg))
+
++/* channel control reg access */
++#if defined(__powerpc__)
++#define nvchan_wr32(reg,val) out_be32((void __iomem *)chan->user->handle, (reg), (val))
++#define nvchan_rd32(reg) in_be32((void __iomem *)chan->user->handle, (reg))
++#else
++#define nvchan_wr32(reg,val) DRM_WRITE32(chan->user, (reg), (val))
++#define nvchan_rd32(reg) DRM_READ32(chan->user, (reg))
++#endif
++
++
+/* register access */
+#define nv_rd32(reg) nv_in32(mmio, (reg))
+#define nv_wr32(reg,val) nv_out32(mmio, (reg), (val))
@@ -8947,7 +8948,7 @@
+
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
new file mode 100644
-index 0000000..34be1a2
+index 0000000..a24c137
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -0,0 +1,126 @@
@@ -9045,7 +9046,7 @@
+ }
+
+ if (1) {
-+ uint32_t sequence = nv_rd32(chan->ref_cnt);
++ uint32_t sequence = nvchan_rd32(0x48);
+
+ NV_DEBUG(dev, "got 0x%08x\n", sequence);
+ drm_fence_handler(dev, class, sequence, waiting_types, 0);
@@ -9079,10 +9080,10 @@
+};
diff --git a/drivers/gpu/drm/nouveau/nouveau_fifo.c b/drivers/gpu/drm/nouveau/nouveau_fifo.c
new file mode 100644
-index 0000000..8559bb9
+index 0000000..670ee1f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_fifo.c
-@@ -0,0 +1,703 @@
+@@ -0,0 +1,692 @@
+/*
+ * Copyright 2005-2006 Stephane Marchesin
+ * All Rights Reserved.
@@ -9345,11 +9346,11 @@
+ struct drm_file *file_priv, struct mem_block *pushbuf,
+ uint32_t vram_handle, uint32_t tt_handle)
+{
-+ int ret;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_engine *engine = &dev_priv->engine;
+ struct nouveau_channel *chan;
-+ int channel;
++ int channel, user;
++ int ret;
+
+ /*
+ * Alright, here is the full story
@@ -9384,26 +9385,18 @@
+ NV_INFO(dev, "Allocating FIFO number %d\n", channel);
+
+ /* Locate channel's user control regs */
-+ if (dev_priv->card_type < NV_40) {
-+ chan->user = NV03_USER(channel);
-+ chan->user_size = NV03_USER_SIZE;
-+ chan->put = NV03_USER_DMA_PUT(channel);
-+ chan->get = NV03_USER_DMA_GET(channel);
-+ chan->ref_cnt = NV03_USER_REF_CNT(channel);
-+ } else
-+ if (dev_priv->card_type < NV_50) {
-+ chan->user = NV40_USER(channel);
-+ chan->user_size = NV40_USER_SIZE;
-+ chan->put = NV40_USER_DMA_PUT(channel);
-+ chan->get = NV40_USER_DMA_GET(channel);
-+ chan->ref_cnt = NV40_USER_REF_CNT(channel);
-+ } else {
-+ chan->user = NV50_USER(channel);
-+ chan->user_size = NV50_USER_SIZE;
-+ chan->put = NV50_USER_DMA_PUT(channel);
-+ chan->get = NV50_USER_DMA_GET(channel);
-+ chan->ref_cnt = NV50_USER_REF_CNT(channel);
-+ }
++ if (dev_priv->card_type < NV_40)
++ user = NV03_USER(channel);
++ else
++ if (dev_priv->card_type < NV_50)
++ user = NV40_USER(channel);
++ else
++ user = NV50_USER(channel);
++
++ ret = drm_addmap(dev, drm_get_resource_start(dev, 0) + user,
++ PAGE_SIZE, _DRM_REGISTERS, _DRM_DRIVER |
++ (dev_priv->mm_enabled ? _DRM_READ_ONLY : 0),
++ &chan->user);
+
+ /* Allocate space for per-channel fixed notifier memory */
+ ret = nouveau_notifier_init_channel(chan);
@@ -9455,8 +9448,8 @@
+ /* setup channel's default get/put values
+ * XXX: quite possibly extremely pointless..
+ */
-+ nv_wr32(chan->get, chan->pushbuf_base);
-+ nv_wr32(chan->put, chan->pushbuf_base);
++ nvchan_wr32(0x44, chan->pushbuf_base);
++ nvchan_wr32(0x40, chan->pushbuf_base);
+
+ /* If this is the first channel, setup PFIFO ourselves. For any
+ * other case, the GPU will handle this when it switches contexts.
@@ -9630,6 +9623,9 @@
+
+ nouveau_notifier_takedown_channel(chan);
+
++ if (chan->user)
++ drm_rmmap(dev, chan->user);
++
+ dev_priv->fifos[chan->id] = NULL;
+ dev_priv->fifo_alloc_count--;
+ drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER);
@@ -9700,17 +9696,11 @@
+
+ /* make the fifo available to user space */
+ /* first, the fifo control regs */
-+ init->ctrl = dev_priv->mmio->offset + chan->user;
-+ init->ctrl_size = chan->user_size;
-+ res = drm_addmap(dev, init->ctrl, init->ctrl_size,
-+ _DRM_REGISTERS, 0, &chan->regs);
-+ if (res != 0)
-+ return res;
-+
-+ entry = drm_find_matching_map(dev, chan->regs);
++ entry = drm_find_matching_map(dev, chan->user);
+ if (!entry)
+ return -EINVAL;
+ init->ctrl = entry->user_token;
++ init->ctrl_size = chan->user->size;
+
+ /* pass back FIFO map info to the caller */
+ init->cmdbuf = chan->pushbuf_mem->map_handle;
@@ -16733,10 +16723,10 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
new file mode 100644
-index 0000000..ac03162
+index 0000000..3e69c36
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
-@@ -0,0 +1,1044 @@
+@@ -0,0 +1,1046 @@
+/*
+ * Copyright 2005 Stephane Marchesin
+ * Copyright 2008 Stuart Bennett
@@ -17269,11 +17259,13 @@
+ /* resource 2 is RAMIN (mmio regs + 0x1000000) */
+ /* resource 6 is bios */
+
-+ /* map the mmio regs */
++ /* Map 8MiB of the mmio regs, the only stuff beyond that we touch
++ * is the channel control regs, but we'll map them per-channel
++ * as required.
++ */
+ ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
-+ drm_get_resource_len(dev, 0),
-+ _DRM_REGISTERS, _DRM_READ_ONLY |
-+ _DRM_DRIVER, &dev_priv->mmio);
++ 0x00800000, _DRM_REGISTERS, _DRM_READ_ONLY |
++ _DRM_DRIVER, &dev_priv->mmio);
+ if (ret) {
+ NV_ERROR(dev, "Unable to initialize the mmio mapping (%d). "
+ "Please report your setup to " DRIVER_EMAIL "\n",
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-11/kernel.spec,v
retrieving revision 1.1547
retrieving revision 1.1548
diff -u -r1.1547 -r1.1548
--- kernel.spec 15 Apr 2009 22:53:45 -0000 1.1547
+++ kernel.spec 16 Apr 2009 01:50:53 -0000 1.1548
@@ -1969,6 +1969,9 @@
# and build.
%changelog
+* Thu Apr 16 2009 Ben Skeggs <bskeggs at redhat.com>
+- drm-nouveau.patch: use less vmalloc space (rh#495843)
+
* Wed Apr 15 2009 Marcelo Tosatti <mtosatti at redhat.com> 2.6.29.1-85
- Skip PIT-through-IOAPIC routing check on KVM guests.
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