rpms/kernel/F-11 drm-dont-frob-i2c.patch, 1.2, 1.3 drm-i915-enable-mchbar.patch, 1.2, 1.3 drm-intel-gem-use-dma32-on-pae.patch, 1.2, 1.3 drm-intel-gen3-fb-hack.patch, 1.2, 1.3 drm-intel-hdmi-edid-fix.patch, 1.2, 1.3 drm-intel-tv-fix.patch, 1.2, 1.3 drm-modesetting-radeon-fixes.patch, 1.2, 1.3 drm-pnp-add-resource-range-checker.patch, 1.2, 1.3 drm-radeon-cs-oops-fix.patch, 1.3, 1.4 drm-radeon-new-pciids.patch, 1.2, 1.3 drm-i915-resume-force-mode.patch, 1.2, 1.3 drm-intel-big-hammer.patch, 1.1, 1.2 drm-modesetting-radeon.patch, 1.83, 1.84 drm-no-gem-on-i8xx.patch, 1.3, 1.4 drm-nouveau.patch, 1.60, 1.61 kernel.spec, 1.1701, 1.1702
Kyle McMartin
kyle at fedoraproject.org
Wed Aug 12 16:49:53 UTC 2009
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Author: kyle
Update of /cvs/pkgs/rpms/kernel/F-11
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv30605
Modified Files:
drm-i915-resume-force-mode.patch drm-intel-big-hammer.patch
drm-modesetting-radeon.patch drm-no-gem-on-i8xx.patch
drm-nouveau.patch kernel.spec
Added Files:
drm-dont-frob-i2c.patch drm-i915-enable-mchbar.patch
drm-intel-gem-use-dma32-on-pae.patch
drm-intel-gen3-fb-hack.patch drm-intel-hdmi-edid-fix.patch
drm-intel-tv-fix.patch drm-modesetting-radeon-fixes.patch
drm-pnp-add-resource-range-checker.patch
drm-radeon-cs-oops-fix.patch drm-radeon-new-pciids.patch
Log Message:
* Wed Aug 12 2009 Kyle McMartin <kyle at redhat.com>
- DRM patch sync-up with F-11-2.6.29.y, ABI probably isn't right yet though...
- drm-modesetting-radeon.patch
- drm-nouveau.patch
- drm-no-gem-on-i8xx.patch
- drm-i915-resume-force-mode.patch
- drm-intel-big-hammer.patch
- drm-intel-gen3-fb-hack.patch
- drm-intel-hdmi-edid-fix.patch
- drm-modesetting-radeon-fixes.patch
- drm-radeon-new-pciids.patch
- drm-dont-frob-i2c.patch
- drm-intel-tv-fix.patch
- drm-radeon-cs-oops-fix.patch
- drm-pnp-add-resource-range-checker.patch
- drm-i915-enable-mchbar.patch
- The rest were merged upstream.
drm-dont-frob-i2c.patch:
drm_edid.c | 74 -------------------------------------------------------------
1 file changed, 1 insertion(+), 73 deletions(-)
Index: drm-dont-frob-i2c.patch
===================================================================
RCS file: drm-dont-frob-i2c.patch
diff -N drm-dont-frob-i2c.patch
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ drm-dont-frob-i2c.patch 12 Aug 2009 16:49:49 -0000 1.3
@@ -0,0 +1,91 @@
+diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
+index 6f6b264..801a0d0 100644
+--- a/drivers/gpu/drm/drm_edid.c
++++ b/drivers/gpu/drm/drm_edid.c
+@@ -589,85 +589,13 @@ int drm_do_probe_ddc_edid(struct i2c_adapter *adapter,
+ }
+ EXPORT_SYMBOL(drm_do_probe_ddc_edid);
+
+-/**
+- * Get EDID information.
+- *
+- * \param adapter : i2c device adaptor.
+- * \param buf : EDID data buffer to be filled
+- * \param len : EDID data buffer length
+- * \return 0 on success or -1 on failure.
+- *
+- * Initialize DDC, then fetch EDID information
+- * by calling drm_do_probe_ddc_edid function.
+- */
+-static int drm_ddc_read(struct i2c_adapter *adapter,
+- unsigned char *buf, int len)
+-{
+- struct i2c_algo_bit_data *algo_data = adapter->algo_data;
+- int i, j;
+- int ret = -1;
+-
+- algo_data->setscl(algo_data->data, 1);
+-
+- for (i = 0; i < 1; i++) {
+- /* For some old monitors we need the
+- * following process to initialize/stop DDC
+- */
+- algo_data->setsda(algo_data->data, 1);
+- msleep(13);
+-
+- algo_data->setscl(algo_data->data, 1);
+- for (j = 0; j < 5; j++) {
+- msleep(10);
+- if (algo_data->getscl(algo_data->data))
+- break;
+- }
+- if (j == 5)
+- continue;
+-
+- algo_data->setsda(algo_data->data, 0);
+- msleep(15);
+- algo_data->setscl(algo_data->data, 0);
+- msleep(15);
+- algo_data->setsda(algo_data->data, 1);
+- msleep(15);
+-
+- /* Do the real work */
+- ret = drm_do_probe_ddc_edid(adapter, buf, len);
+- algo_data->setsda(algo_data->data, 0);
+- algo_data->setscl(algo_data->data, 0);
+- msleep(15);
+-
+- algo_data->setscl(algo_data->data, 1);
+- for (j = 0; j < 10; j++) {
+- msleep(10);
+- if (algo_data->getscl(algo_data->data))
+- break;
+- }
+-
+- algo_data->setsda(algo_data->data, 1);
+- msleep(15);
+- algo_data->setscl(algo_data->data, 0);
+- algo_data->setsda(algo_data->data, 0);
+- if (ret == 0)
+- break;
+- }
+- /* Release the DDC lines when done or the Apple Cinema HD display
+- * will switch off
+- */
+- algo_data->setsda(algo_data->data, 1);
+- algo_data->setscl(algo_data->data, 1);
+-
+- return ret;
+-}
+-
+ static int drm_ddc_read_edid(struct drm_connector *connector,
+ struct i2c_adapter *adapter,
+ char *buf, int len)
+ {
+ int ret;
+
+- ret = drm_ddc_read(adapter, buf, len);
++ ret = drm_do_probe_ddc_edid(adapter, buf, len);
+ if (ret != 0) {
+ dev_info(&connector->dev->pdev->dev, "%s: no EDID data\n",
+ drm_get_connector_name(connector));
drm-i915-enable-mchbar.patch:
i915_drv.h | 2
i915_gem_tiling.c | 145 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 147 insertions(+)
Index: drm-i915-enable-mchbar.patch
===================================================================
RCS file: drm-i915-enable-mchbar.patch
diff -N drm-i915-enable-mchbar.patch
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ drm-i915-enable-mchbar.patch 12 Aug 2009 16:49:49 -0000 1.3
@@ -0,0 +1,197 @@
+diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
+index dcf5257..defe8a0 100644
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -143,6 +143,8 @@ typedef struct drm_i915_private {
+ drm_local_map_t hws_map;
+ struct drm_gem_object *hws_obj;
+
++ struct resource mch_res;
++
+ unsigned int cpp;
+ int back_offset;
+ int front_offset;
+diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
+index 540dd33..975b967 100644
+--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
++++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
+@@ -25,6 +25,8 @@
+ *
+ */
+
++#include <linux/acpi.h>
++#include <linux/pnp.h>
+ #include "linux/string.h"
+ #include "linux/bitops.h"
+ #include "drmP.h"
+@@ -81,6 +83,143 @@
+ * to match what the GPU expects.
+ */
+
++#define MCHBAR_I915 0x44
++#define MCHBAR_I965 0x48
++#define MCHBAR_SIZE (4*4096)
++
++#define DEVEN_REG 0x54
++#define DEVEN_MCHBAR_EN (1 << 28)
++
++/* Allocate space for the MCH regs if needed, return nonzero on error */
++static int
++intel_alloc_mchbar_resource(struct drm_device *dev)
++{
++ struct pci_dev *bridge_dev;
++ drm_i915_private_t *dev_priv = dev->dev_private;
++ int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
++ u32 temp_lo, temp_hi = 0;
++ u64 mchbar_addr;
++ int ret = 0;
++
++ bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
++ if (!bridge_dev) {
++ DRM_DEBUG("no bridge dev?!\n");
++ ret = -ENODEV;
++ goto out;
++ }
++
++ if (IS_I965G(dev))
++ pci_read_config_dword(bridge_dev, reg + 4, &temp_hi);
++ pci_read_config_dword(bridge_dev, reg, &temp_lo);
++ mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
++
++ /* If ACPI doesn't have it, assume we need to allocate it ourselves */
++ if (mchbar_addr &&
++ pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
++ ret = 0;
++ goto out_put;
++ }
++
++ /* Get some space for it */
++ ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res,
++ MCHBAR_SIZE, MCHBAR_SIZE,
++ PCIBIOS_MIN_MEM,
++ 0, pcibios_align_resource,
++ bridge_dev);
++ if (ret) {
++ DRM_DEBUG("failed bus alloc: %d\n", ret);
++ dev_priv->mch_res.start = 0;
++ goto out_put;
++ }
++
++ if (IS_I965G(dev))
++ pci_write_config_dword(bridge_dev, reg + 4,
++ upper_32_bits(dev_priv->mch_res.start));
++
++ pci_write_config_dword(bridge_dev, reg,
++ lower_32_bits(dev_priv->mch_res.start));
++out_put:
++ pci_dev_put(bridge_dev);
++out:
++ return ret;
++}
++
++/* Setup MCHBAR if possible, return true if we should disable it again */
++static bool
++intel_setup_mchbar(struct drm_device *dev)
++{
++ struct pci_dev *bridge_dev;
++ int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
++ u32 temp;
++ bool need_disable = false, enabled;
++
++ bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
++ if (!bridge_dev) {
++ DRM_DEBUG("no bridge dev?!\n");
++ goto out;
++ }
++
++ if (IS_I915G(dev) || IS_I915GM(dev)) {
++ pci_read_config_dword(bridge_dev, DEVEN_REG, &temp);
++ enabled = !!(temp & DEVEN_MCHBAR_EN);
++ } else {
++ pci_read_config_dword(bridge_dev, mchbar_reg, &temp);
++ enabled = temp & 1;
++ }
++
++ /* If it's already enabled, don't have to do anything */
++ if (enabled)
++ goto out_put;
++
++ if (intel_alloc_mchbar_resource(dev))
++ goto out_put;
++
++ need_disable = true;
++
++ /* Space is allocated or reserved, so enable it. */
++ if (IS_I915G(dev) || IS_I915GM(dev)) {
++ pci_write_config_dword(bridge_dev, DEVEN_REG,
++ temp | DEVEN_MCHBAR_EN);
++ } else {
++ pci_read_config_dword(bridge_dev, mchbar_reg, &temp);
++ pci_write_config_dword(bridge_dev, mchbar_reg, temp | 1);
++ }
++out_put:
++ pci_dev_put(bridge_dev);
++out:
++ return need_disable;
++}
++
++static void
++intel_teardown_mchbar(struct drm_device *dev, bool disable)
++{
++ drm_i915_private_t *dev_priv = dev->dev_private;
++ struct pci_dev *bridge_dev;
++ int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
++ u32 temp;
++
++ bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
++ if (!bridge_dev) {
++ DRM_DEBUG("no bridge dev?!\n");
++ return;
++ }
++
++ if (disable) {
++ if (IS_I915G(dev) || IS_I915GM(dev)) {
++ pci_read_config_dword(bridge_dev, DEVEN_REG, &temp);
++ temp &= ~DEVEN_MCHBAR_EN;
++ pci_write_config_dword(bridge_dev, DEVEN_REG, temp);
++ } else {
++ pci_read_config_dword(bridge_dev, mchbar_reg, &temp);
++ temp &= ~1;
++ pci_write_config_dword(bridge_dev, mchbar_reg, temp);
++ }
++ }
++
++ if (dev_priv->mch_res.start)
++ release_resource(&dev_priv->mch_res);
++}
++
+ /**
+ * Detects bit 6 swizzling of address lookup between IGD access and CPU
+ * access through main memory.
+@@ -91,6 +230,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
+ uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
++ bool need_disable;
+
+ if (!IS_I9XX(dev)) {
+ /* As far as we know, the 865 doesn't have these bit 6
+@@ -101,6 +241,9 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
+ } else if (IS_MOBILE(dev)) {
+ uint32_t dcc;
+
++ /* Try to make sure MCHBAR is enabled before poking at it */
++ need_disable = intel_setup_mchbar(dev);
++
+ /* On mobile 9xx chipsets, channel interleave by the CPU is
+ * determined by DCC. For single-channel, neither the CPU
+ * nor the GPU do swizzling. For dual channel interleaved,
+@@ -140,6 +283,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
+ swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
+ swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
+ }
++
++ intel_teardown_mchbar(dev, need_disable);
+ } else {
+ /* The 965, G33, and newer, have a very flexible memory
+ * configuration. It will enable dual-channel mode
drm-intel-gem-use-dma32-on-pae.patch:
drivers/gpu/drm/drm_gem.c | 3 +++
drivers/gpu/drm/i915/i915_dma.c | 8 ++++----
include/drm/drmP.h | 1 +
mm/shmem.c | 2 +-
4 files changed, 9 insertions(+), 5 deletions(-)
Index: drm-intel-gem-use-dma32-on-pae.patch
===================================================================
RCS file: drm-intel-gem-use-dma32-on-pae.patch
diff -N drm-intel-gem-use-dma32-on-pae.patch
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ drm-intel-gem-use-dma32-on-pae.patch 12 Aug 2009 16:49:49 -0000 1.3
@@ -0,0 +1,66 @@
+commit 91346b5fc75a8a0418e3393244e3d0750400af87
+Author: Kyle McMartin <kyle at phobos.i.jkkm.org>
+Date: Wed Aug 12 12:15:51 2009 -0400
+
+ drm-intel-gem-use-dma32-on-pae.patch
+
+diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
+index dee9b40..96eff54 100644
+--- a/drivers/gpu/drm/drm_gem.c
++++ b/drivers/gpu/drm/drm_gem.c
+@@ -142,6 +142,9 @@ drm_gem_object_alloc(struct drm_device *dev, size_t size)
+ return NULL;
+ }
+
++ if (dev->gem_flags)
++ mapping_set_gfp_mask(obj->filp->f_mapping, dev->gem_flags);
++
+ kref_init(&obj->refcount);
+ kref_init(&obj->handlecount);
+ obj->size = size;
+diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
+index 4560b8d..5da31e7 100644
+--- a/drivers/gpu/drm/i915/i915_dma.c
++++ b/drivers/gpu/drm/i915/i915_dma.c
+@@ -1145,12 +1145,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
+ }
+
+ #ifdef CONFIG_HIGHMEM64G
+- /* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */
+- dev_priv->has_gem = 0;
+-#else
++ /* set default allocation flags */
++ dev->gem_flags = GFP_USER | GFP_DMA32;
++#endif
++
+ /* enable GEM by default, except on I8xx */
+ dev_priv->has_gem = !IS_8XX(dev) ? 1 : 0;
+-#endif
+
+ dev->driver->get_vblank_counter = i915_get_vblank_counter;
+ if (IS_GM45(dev))
+diff --git a/include/drm/drmP.h b/include/drm/drmP.h
+index fb93588..b8dae8a 100644
+--- a/include/drm/drmP.h
++++ b/include/drm/drmP.h
+@@ -1043,6 +1043,7 @@ struct drm_device {
+ uint32_t gtt_total;
+ uint32_t invalidate_domains; /* domains pending invalidation */
+ uint32_t flush_domains; /* domains pending flush */
++ gfp_t gem_flags; /* object allocation flags */
+ /*@} */
+ };
+
+diff --git a/mm/shmem.c b/mm/shmem.c
+index b25f95c..e615887 100644
+--- a/mm/shmem.c
++++ b/mm/shmem.c
+@@ -1241,7 +1241,7 @@ repeat:
+ * Try to preload while we can wait, to not make a habit of
+ * draining atomic reserves; but don't latch on to this cpu.
+ */
+- error = radix_tree_preload(gfp & ~__GFP_HIGHMEM);
++ error = radix_tree_preload(gfp & ~(__GFP_HIGHMEM|__GFP_DMA32));
+ if (error)
+ goto failed;
+ radix_tree_preload_end();
drm-intel-gen3-fb-hack.patch:
intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Index: drm-intel-gen3-fb-hack.patch
===================================================================
RCS file: drm-intel-gen3-fb-hack.patch
diff -N drm-intel-gen3-fb-hack.patch
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ drm-intel-gen3-fb-hack.patch 12 Aug 2009 16:49:49 -0000 1.3
@@ -0,0 +1,15 @@
+diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
+index d0ac174..e4b7257 100644
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -2067,8 +2067,8 @@ void intel_modeset_init(struct drm_device *dev)
+ dev->mode_config.max_width = 8192;
+ dev->mode_config.max_height = 8192;
+ } else {
+- dev->mode_config.max_width = 2048;
+- dev->mode_config.max_height = 2048;
++ dev->mode_config.max_width = 4096;
++ dev->mode_config.max_height = 4096;
+ }
+
+ /* set memory base */
drm-intel-hdmi-edid-fix.patch:
intel_sdvo.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 79 insertions(+), 1 deletion(-)
Index: drm-intel-hdmi-edid-fix.patch
===================================================================
RCS file: drm-intel-hdmi-edid-fix.patch
diff -N drm-intel-hdmi-edid-fix.patch
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ drm-intel-hdmi-edid-fix.patch 12 Aug 2009 16:49:49 -0000 1.3
@@ -0,0 +1,103 @@
+diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
+index 3093b4d..1324fda 100644
+--- a/drivers/gpu/drm/i915/intel_sdvo.c
++++ b/drivers/gpu/drm/i915/intel_sdvo.c
+@@ -30,6 +30,7 @@
+ #include "drmP.h"
+ #include "drm.h"
+ #include "drm_crtc.h"
++#include "drm_edid.h"
+ #include "intel_drv.h"
+ #include "i915_drm.h"
+ #include "i915_drv.h"
+@@ -1399,12 +1400,89 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect
+ return connector_status_disconnected;
+ }
+
++#define MAX_EDID_EXT_NUM 4
++/**
++ * This function will fetch EDID by switch ddc bus, instead of drm_get_edid
++ * function.
++ */
++static struct edid *intel_sdvo_hdmi_get_edid(struct intel_output *intel_output)
++{
++ struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
++ struct edid *edid;
++ int ret = 0;
++
++ edid = kmalloc(EDID_LENGTH * (MAX_EDID_EXT_NUM + 1),
++ GFP_KERNEL);
++
++ if (edid == NULL) {
++ DRM_DEBUG("Failed to allocated EDID for SDVO HDMI\n");
++ goto end;
++ }
++
++ /* Read first EDID block */
++ ret = drm_do_probe_ddc_edid(&intel_output->ddc_bus->adapter,
++ (unsigned char *)edid, EDID_LENGTH);
++ if (ret != 0) {
++ DRM_DEBUG("Failed to read basic EDID for SDVO HDMI\n");
++ goto clean_up;
++ }
++
++ /* There are EDID extensions to be read */
++ if (edid->extensions != 0) {
++ int edid_ext_num = edid->extensions;
++
++ if (edid_ext_num > MAX_EDID_EXT_NUM) {
++ DRM_DEBUG("The number of extensions(%d) is "
++ "over max (%d), actually read number (%d)\n",
++ edid_ext_num, MAX_EDID_EXT_NUM,
++ MAX_EDID_EXT_NUM);
++ }
++ /* set the bus switch and get the modes */
++ intel_sdvo_set_control_bus_switch(intel_output,
++ sdvo_priv->ddc_bus);
++ /* Read EDID including extensions too */
++ ret = drm_do_probe_ddc_edid(&intel_output->ddc_bus->adapter,
++ (unsigned char *)edid,
++ EDID_LENGTH * (edid_ext_num + 1));
++ if (ret != 0) {
++ DRM_DEBUG("Failed to read EDID EXT for SDVO HDMI\n");
++ goto clean_up;
++ }
++ }
++ goto end;
++
++clean_up:
++ kfree(edid);
++ edid = NULL;
++end:
++ return edid;
++}
++
++static void intel_sdvo_hdmi_ddc_get_modes(struct intel_output *intel_output)
++{
++ struct edid *edid;
++
++ edid = intel_sdvo_hdmi_get_edid(intel_output);
++ if (edid != NULL) {
++ drm_mode_connector_update_edid_property(&intel_output->base,
++ edid);
++ drm_add_edid_modes(&intel_output->base, edid);
++ kfree(edid);
++ }
++}
++
+ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
+ {
+ struct intel_output *intel_output = to_intel_output(connector);
++ struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
+
+ /* set the bus switch and get the modes */
+- intel_ddc_get_modes(intel_output);
++ intel_sdvo_set_control_bus_switch(intel_output,
++ sdvo_priv->ddc_bus);
++ if (sdvo_priv->is_hdmi == true)
++ intel_sdvo_hdmi_ddc_get_modes(intel_output);
++ else
++ intel_ddc_get_modes(intel_output);
+
+ #if 0
+ struct drm_device *dev = encoder->dev;
drm-intel-tv-fix.patch:
intel_display.c | 2 ++
1 file changed, 2 insertions(+)
Index: drm-intel-tv-fix.patch
===================================================================
RCS file: drm-intel-tv-fix.patch
diff -N drm-intel-tv-fix.patch
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ drm-intel-tv-fix.patch 12 Aug 2009 16:49:49 -0000 1.3
@@ -0,0 +1,20 @@
+diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
+index e4b7257..60cc21a 100644
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -1596,6 +1596,7 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
+ }
+
+ encoder->crtc = crtc;
++ intel_output->base.encoder = encoder;
+ intel_output->load_detect_temp = true;
+
+ intel_crtc = to_intel_crtc(crtc);
+@@ -1631,6 +1632,7 @@ void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_
+
+ if (intel_output->load_detect_temp) {
+ encoder->crtc = NULL;
++ intel_output->base.encoder = NULL;
+ intel_output->load_detect_temp = false;
+ crtc->enabled = drm_helper_crtc_in_use(crtc);
+ drm_helper_disable_unused_functions(dev);
drm-modesetting-radeon-fixes.patch:
drm_page_alloc.c | 1 +
drm_ttm.c | 15 ++++-----------
radeon/radeon_cp.c | 11 +----------
radeon/radeon_drv.h | 2 ++
radeon/radeon_gem.c | 22 +++++++++++++++-------
radeon/radeon_pm.c | 3 +++
6 files changed, 26 insertions(+), 28 deletions(-)
Index: drm-modesetting-radeon-fixes.patch
===================================================================
RCS file: drm-modesetting-radeon-fixes.patch
diff -N drm-modesetting-radeon-fixes.patch
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ drm-modesetting-radeon-fixes.patch 12 Aug 2009 16:49:49 -0000 1.3
@@ -0,0 +1,170 @@
+diff --git a/drivers/gpu/drm/drm_page_alloc.c b/drivers/gpu/drm/drm_page_alloc.c
+index fad6ae3..73a3c6d 100644
+--- a/drivers/gpu/drm/drm_page_alloc.c
++++ b/drivers/gpu/drm/drm_page_alloc.c
+@@ -78,6 +78,7 @@ int drm_add_pages_locked(int num_pages, int cached)
+ #else
+ map_page_into_agp(page);
+ #endif
++ drm_clflush_pages(&page, 1);
+ list_add(&page->lru, &uncached_free_list);
+ drm_page_alloc_data.total_uncached_pages++;
+ drm_page_alloc_data.uncached_pages_in_list++;
+diff --git a/drivers/gpu/drm/drm_ttm.c b/drivers/gpu/drm/drm_ttm.c
+index ae64a83..dbc0cb3 100644
+--- a/drivers/gpu/drm/drm_ttm.c
++++ b/drivers/gpu/drm/drm_ttm.c
+@@ -89,21 +89,14 @@ static struct page *drm_ttm_alloc_page(struct drm_ttm *ttm, int cached)
+ * Change caching policy for the linear kernel map
+ * for range of pages in a ttm.
+ */
+-static int drm_ttm_set_caching(struct drm_ttm *ttm, int noncached, int alloc_cached)
++static int drm_ttm_set_caching(struct drm_ttm *ttm, int noncached)
+ {
+ int i;
+ struct page **cur_page;
+- int ret;
+
+ if ((ttm->page_flags & DRM_TTM_PAGE_UNCACHED) == noncached)
+ return 0;
+
+- {
+- ret = drm_ttm_populate(ttm, alloc_cached);
+- if (ret != 0)
+- return ret;
+- }
+-
+ if (noncached)
+ drm_clflush_pages(ttm->pages, ttm->num_pages);
+
+@@ -196,7 +189,7 @@ int drm_ttm_destroy(struct drm_ttm *ttm)
+ if (ttm->pages) {
+ if (ttm->page_flags & DRM_TTM_PAGE_USER) {
+ if (ttm->page_flags & DRM_TTM_PAGE_UNCACHED)
+- drm_ttm_set_caching(ttm, 0, 0);
++ drm_ttm_set_caching(ttm, 0);
+
+ drm_ttm_free_user_pages(ttm);
+ } else
+@@ -404,7 +397,7 @@ void drm_ttm_fixup_caching(struct drm_ttm *ttm)
+ struct drm_ttm_backend *be = ttm->be;
+ if (be->func->needs_ub_cache_adjust(be))
+ if (ttm->page_flags & DRM_TTM_PAGE_ALLOC_CACHED)
+- drm_ttm_set_caching(ttm, 0, 1);
++ drm_ttm_set_caching(ttm, 0);
+ ttm->state = ttm_unbound;
+ }
+ }
+@@ -452,7 +445,7 @@ int drm_ttm_bind(struct drm_ttm *ttm, struct drm_bo_mem_reg *bo_mem)
+ be = ttm->be;
+
+ if ((ttm->state == ttm_unbound || ttm->state == ttm_unpopulated) && !cached)
+- drm_ttm_set_caching(ttm, DRM_TTM_PAGE_UNCACHED, cached);
++ drm_ttm_set_caching(ttm, DRM_TTM_PAGE_UNCACHED);
+ else if ((bo_mem->flags & DRM_BO_FLAG_CACHED_MAPPED) &&
+ bo_driver->ttm_cache_flush)
+ bo_driver->ttm_cache_flush(ttm);
+diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
+index 179d408..2d18df9 100644
+--- a/drivers/gpu/drm/radeon/radeon_cp.c
++++ b/drivers/gpu/drm/radeon/radeon_cp.c
+@@ -2722,16 +2722,7 @@ int radeon_modeset_cp_resume(struct drm_device *dev)
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+
+ radeon_do_wait_for_idle(dev_priv);
+-#if __OS_HAS_AGP
+- if (dev_priv->flags & RADEON_IS_AGP) {
+- /* Turn off PCI GART */
+- radeon_set_pcigart(dev_priv, 0);
+- } else
+-#endif
+- {
+- /* Turn on PCI GART */
+- radeon_set_pcigart(dev_priv, 1);
+- }
++ radeon_gart_start(dev);
+ radeon_gart_flush(dev);
+
+ radeon_cp_load_microcode(dev_priv);
+diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
+index e3498a4..6a69864 100644
+--- a/drivers/gpu/drm/radeon/radeon_drv.h
++++ b/drivers/gpu/drm/radeon/radeon_drv.h
+@@ -2253,6 +2253,7 @@ extern int radeon_init_mem_type(struct drm_device * dev, uint32_t type,
+ extern int radeon_move(struct drm_buffer_object * bo,
+ int evict, int no_wait, struct drm_bo_mem_reg * new_mem);
+
++extern void radeon_gart_start(struct drm_device *drm);
+ extern void radeon_gart_flush(struct drm_device *dev);
+ extern uint64_t radeon_evict_flags(struct drm_buffer_object *bo);
+
+@@ -2330,6 +2331,7 @@ struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size,
+ int initial_domain, bool discardable);
+ int radeon_modeset_init(struct drm_device *dev);
+ void radeon_modeset_cleanup(struct drm_device *dev);
++int radeon_modeset_agp_init(struct drm_device *dev);
+ extern u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr);
+ void radeon_read_agp_location(drm_radeon_private_t *dev_priv, u32 *agp_lo, u32 *agp_hi);
+ void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc);
+diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
+index cb96470..4bfc316 100644
+--- a/drivers/gpu/drm/radeon/radeon_gem.c
++++ b/drivers/gpu/drm/radeon/radeon_gem.c
+@@ -563,8 +563,16 @@ static int radeon_gart_init(struct drm_device *dev)
+ dev_priv->gart_info.addr = dev_priv->gart_info.table_handle->vaddr;
+ dev_priv->gart_info.bus_addr = dev_priv->gart_info.table_handle->busaddr;
+ }
++
++ radeon_gart_start(dev);
+
+- /* gart values setup - start the GART */
++ return 0;
++}
++
++/* gart values setup - start the GART */
++void radeon_gart_start(struct drm_device *dev) {
++ drm_radeon_private_t *dev_priv = dev->dev_private;
++
+ if (dev_priv->flags & RADEON_IS_AGP) {
+ radeon_set_pcigart(dev_priv, 0);
+ /* enable AGP GART bits */
+@@ -581,8 +589,6 @@ static int radeon_gart_init(struct drm_device *dev)
+ } else {
+ radeon_set_pcigart(dev_priv, 1);
+ }
+-
+- return 0;
+ }
+
+ int radeon_alloc_gart_objects(struct drm_device *dev)
+@@ -1024,10 +1030,12 @@ int radeon_modeset_agp_init(struct drm_device *dev)
+ struct radeon_agpmode_quirk *p = radeon_agpmode_quirk_list;
+
+ /* Acquire AGP. */
+- ret = drm_agp_acquire(dev);
+- if (ret) {
+- DRM_ERROR("Unable to acquire AGP: %d\n", ret);
+- return ret;
++ if (!dev->agp->acquired) { /* don't need to repeat on resume */
++ ret = drm_agp_acquire(dev);
++ if (ret) {
++ DRM_ERROR("Unable to acquire AGP: %d\n", ret);
++ return ret;
++ }
+ }
+
+ ret = drm_agp_info(dev, &info);
+diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
+index 5a57056..684b7ca 100644
+--- a/drivers/gpu/drm/radeon/radeon_pm.c
++++ b/drivers/gpu/drm/radeon/radeon_pm.c
+@@ -156,6 +156,9 @@ int radeon_resume(struct drm_device *dev)
+ /* Turn on bus mastering -todo fix properly */
+ radeon_enable_bm(dev_priv);
+
++ if (dev_priv->flags & RADEON_IS_AGP)
++ radeon_modeset_agp_init(dev);
++
+ if (dev_priv->flags & RADEON_IS_PCIE) {
+ memcpy_toio(dev_priv->mm.pcie_table.kmap.virtual, dev_priv->mm.pcie_table_backup, dev_priv->gart_info.table_size);
+ }
drm-pnp-add-resource-range-checker.patch:
drivers/pnp/resource.c | 18 ++++++++++++++++++
include/linux/pnp.h | 2 ++
2 files changed, 20 insertions(+)
Index: drm-pnp-add-resource-range-checker.patch
===================================================================
RCS file: drm-pnp-add-resource-range-checker.patch
diff -N drm-pnp-add-resource-range-checker.patch
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ drm-pnp-add-resource-range-checker.patch 12 Aug 2009 16:49:51 -0000 1.3
@@ -0,0 +1,49 @@
+diff --git a/drivers/pnp/resource.c b/drivers/pnp/resource.c
+index f604061..ba97654 100644
+--- a/drivers/pnp/resource.c
++++ b/drivers/pnp/resource.c
+@@ -638,6 +638,24 @@ int pnp_possible_config(struct pnp_dev *dev, int type, resource_size_t start,
+ }
+ EXPORT_SYMBOL(pnp_possible_config);
+
++int pnp_range_reserved(resource_size_t start, resource_size_t end)
++{
++ struct pnp_dev *dev;
++ struct pnp_resource *pnp_res;
++ resource_size_t *dev_start, *dev_end;
++
++ pnp_for_each_dev(dev) {
++ list_for_each_entry(pnp_res, &dev->resources, list) {
++ dev_start = &pnp_res->res.start;
++ dev_end = &pnp_res->res.end;
++ if (ranged_conflict(&start, &end, dev_start, dev_end))
++ return 1;
++ }
++ }
++ return 0;
++}
++EXPORT_SYMBOL(pnp_range_reserved);
++
+ /* format is: pnp_reserve_irq=irq1[,irq2] .... */
+ static int __init pnp_setup_reserve_irq(char *str)
+ {
+diff --git a/include/linux/pnp.h b/include/linux/pnp.h
+index ca3c887..b063c73 100644
+--- a/include/linux/pnp.h
++++ b/include/linux/pnp.h
+@@ -446,6 +446,7 @@ int pnp_start_dev(struct pnp_dev *dev);
+ int pnp_stop_dev(struct pnp_dev *dev);
+ int pnp_activate_dev(struct pnp_dev *dev);
+ int pnp_disable_dev(struct pnp_dev *dev);
++int pnp_range_reserved(resource_size_t start, resource_size_t end);
+
+ /* protocol helpers */
+ int pnp_is_active(struct pnp_dev *dev);
+@@ -476,6 +477,7 @@ static inline int pnp_start_dev(struct pnp_dev *dev) { return -ENODEV; }
+ static inline int pnp_stop_dev(struct pnp_dev *dev) { return -ENODEV; }
+ static inline int pnp_activate_dev(struct pnp_dev *dev) { return -ENODEV; }
+ static inline int pnp_disable_dev(struct pnp_dev *dev) { return -ENODEV; }
++static inline int pnp_range_reserved(resource_size_t start, resource_size_t end) { return 0;}
+
+ /* protocol helpers */
+ static inline int pnp_is_active(struct pnp_dev *dev) { return 0; }
drm-radeon-cs-oops-fix.patch:
radeon_cs.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
Index: drm-radeon-cs-oops-fix.patch
===================================================================
RCS file: drm-radeon-cs-oops-fix.patch
diff -N drm-radeon-cs-oops-fix.patch
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ drm-radeon-cs-oops-fix.patch 12 Aug 2009 16:49:51 -0000 1.4
@@ -0,0 +1,38 @@
+diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
+index 1152552..3307387 100644
+--- a/drivers/gpu/drm/radeon/radeon_cs.c
++++ b/drivers/gpu/drm/radeon/radeon_cs.c
+@@ -41,22 +41,27 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
+ long size;
+ int r, i;
+
++ if (dev_priv == NULL) {
++ DRM_ERROR("called with no initialization\n");
++ return -EINVAL;
++ }
++
++ if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
++ DRM_ERROR("CS ioctl called without modesetting\n");
++ return -EINVAL;
++ }
++
+ mutex_lock(&dev_priv->cs.cs_mutex);
+ /* set command stream id to 0 which is fake id */
+ cs_id = 0;
+ cs->cs_id = cs_id;
+
+- if (dev_priv == NULL) {
+- DRM_ERROR("called with no initialization\n");
+- mutex_unlock(&dev_priv->cs.cs_mutex);
+- return -EINVAL;
+- }
++
+ if (!cs->num_chunks) {
+ mutex_unlock(&dev_priv->cs.cs_mutex);
+ return 0;
+ }
+
+-
+ chunk_array = drm_calloc(cs->num_chunks, sizeof(uint64_t), DRM_MEM_DRIVER);
+ if (!chunk_array) {
+ mutex_unlock(&dev_priv->cs.cs_mutex);
drm-radeon-new-pciids.patch:
drivers/gpu/drm/radeon/r600_cp.c | 42 +++++++++++++++++++++++++++++++-----
drivers/gpu/drm/radeon/radeon_drv.h | 1
include/drm/drm_pciids.h | 7 ++++++
3 files changed, 45 insertions(+), 5 deletions(-)
Index: drm-radeon-new-pciids.patch
===================================================================
RCS file: drm-radeon-new-pciids.patch
diff -N drm-radeon-new-pciids.patch
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ drm-radeon-new-pciids.patch 12 Aug 2009 16:49:51 -0000 1.3
@@ -0,0 +1,133 @@
+diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
+index c3f12e6..cbbfbbf 100644
+--- a/drivers/gpu/drm/radeon/r600_cp.c
++++ b/drivers/gpu/drm/radeon/r600_cp.c
+@@ -478,26 +478,27 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
+
+ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) {
+ RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+- DRM_INFO("Loading RV770 PFP Microcode\n");
++ DRM_INFO("Loading RV770/RV790 PFP Microcode\n");
+ for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
+ RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]);
+ RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+
+ RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+- DRM_INFO("Loading RV770 CP Microcode\n");
++ DRM_INFO("Loading RV770/RV790 CP Microcode\n");
+ for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
+ RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]);
+ RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+
+- } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730)) {
++ } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) {
+ RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+- DRM_INFO("Loading RV730 PFP Microcode\n");
++ DRM_INFO("Loading RV730/RV740 PFP Microcode\n");
+ for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
+ RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]);
+ RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+
+ RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+- DRM_INFO("Loading RV730 CP Microcode\n");
++ DRM_INFO("Loading RV730/RV740 CP Microcode\n");
+ for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
+ RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]);
+ RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+@@ -1324,6 +1325,10 @@ static void r700_gfx_init(struct drm_device *dev,
+ dev_priv->r700_sc_prim_fifo_size = 0xf9;
+ dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
+ dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
++ if (dev_priv->r600_sx_max_export_pos_size > 16) {
++ dev_priv->r600_sx_max_export_pos_size -= 16;
++ dev_priv->r600_sx_max_export_smx_size += 16;
++ }
+ break;
+ case CHIP_RV710:
+ dev_priv->r600_max_pipes = 2;
+@@ -1345,6 +1350,31 @@ static void r700_gfx_init(struct drm_device *dev,
+ dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
+ dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
+ break;
++ case CHIP_RV740:
++ dev_priv->r600_max_pipes = 4;
++ dev_priv->r600_max_tile_pipes = 4;
++ dev_priv->r600_max_simds = 8;
++ dev_priv->r600_max_backends = 4;
++ dev_priv->r600_max_gprs = 256;
++ dev_priv->r600_max_threads = 248;
++ dev_priv->r600_max_stack_entries = 512;
++ dev_priv->r600_max_hw_contexts = 8;
++ dev_priv->r600_max_gs_threads = 16 * 2;
++ dev_priv->r600_sx_max_export_size = 256;
++ dev_priv->r600_sx_max_export_pos_size = 32;
++ dev_priv->r600_sx_max_export_smx_size = 224;
++ dev_priv->r600_sq_num_cf_insts = 2;
++
++ dev_priv->r700_sx_num_of_sets = 7;
++ dev_priv->r700_sc_prim_fifo_size = 0x100;
++ dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
++ dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
++
++ if (dev_priv->r600_sx_max_export_pos_size > 16) {
++ dev_priv->r600_sx_max_export_pos_size -= 16;
++ dev_priv->r600_sx_max_export_smx_size += 16;
++ }
++ break;
+ default:
+ break;
+ }
+@@ -1493,6 +1523,7 @@ static void r700_gfx_init(struct drm_device *dev,
+ break;
+ case CHIP_RV730:
+ case CHIP_RV710:
++ case CHIP_RV740:
+ default:
+ sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
+ break;
+@@ -1569,6 +1600,7 @@ static void r700_gfx_init(struct drm_device *dev,
+ switch (dev_priv->flags & RADEON_FAMILY_MASK) {
+ case CHIP_RV770:
+ case CHIP_RV730:
++ case CHIP_RV740:
+ gs_prim_buffer_depth = 384;
+ break;
+ case CHIP_RV710:
+diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
+index 6a69864..07913ec 100644
+--- a/drivers/gpu/drm/radeon/radeon_drv.h
++++ b/drivers/gpu/drm/radeon/radeon_drv.h
+@@ -148,6 +148,7 @@ enum radeon_family {
+ CHIP_RV770,
+ CHIP_RV730,
+ CHIP_RV710,
++ CHIP_RV740,
+ CHIP_LAST,
+ };
+
+diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
+index fc55db7..71bfec9 100644
+--- a/include/drm/drm_pciids.h
++++ b/include/drm/drm_pciids.h
+@@ -254,6 +254,11 @@
+ {0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x94A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x94A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x94B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x94B3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x94B5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
+@@ -268,6 +273,8 @@
+ {0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x9460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x9462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x946B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x947A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
drm-i915-resume-force-mode.patch:
i915_suspend.c | 4 ++++
1 file changed, 4 insertions(+)
Index: drm-i915-resume-force-mode.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-11/drm-i915-resume-force-mode.patch,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -p -r1.2 -r1.3
--- drm-i915-resume-force-mode.patch 26 Mar 2009 18:46:43 -0000 1.2
+++ drm-i915-resume-force-mode.patch 12 Aug 2009 16:49:49 -0000 1.3
@@ -1,7 +1,7 @@
-http://lists.freedesktop.org/archives/intel-gfx/2009-February/001313.html
-
---- a/drivers/gpu/drm/i915/i915_suspend.c.orig 2009-02-18 22:59:19.000000000 -0500
-+++ b/drivers/gpu/drm/i915/i915_suspend.c 2009-02-18 22:59:58.000000000 -0500
+diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
+index ce8a213..7e90be3 100644
+--- a/drivers/gpu/drm/i915/i915_suspend.c
++++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -28,6 +28,7 @@
#include "drm.h"
#include "i915_drm.h"
@@ -10,41 +10,13 @@ http://lists.freedesktop.org/archives/in
static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
{
-@@ -519,6 +520,8 @@
-
- i915_restore_vga(dev);
-
-+ drm_helper_resume_force_mode(dev);
-+
- return 0;
- }
-
-From f5192bce8be69e5b33d7579bc282fef4d673e2c1 Mon Sep 17 00:00:00 2001
-From: Lubomir Rintel <lkundrak at v3.sk>
-Date: Sun, 15 Mar 2009 13:55:55 +0100
-Subject: [PATCH] Fix i915 nomodeset NULL deref. during PM resume
-
-drm_helper_resume_force_mode() would crash while attempting to
-iterate through crtc_list, which is uninitialized when is modesetting
-disabled.
----
- drivers/gpu/drm/i915/i915_suspend.c | 3 ++-
- 1 files changed, 2 insertions(+), 1 deletions(-)
-
-diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
-index ef5fb6e..b138032 100644
---- a/drivers/gpu/drm/i915/i915_suspend.c
-+++ b/drivers/gpu/drm/i915/i915_suspend.c
-@@ -520,7 +520,8 @@ int i915_restore_state(struct drm_device *dev)
+@@ -532,6 +533,9 @@ int i915_restore_state(struct drm_device *dev)
i915_restore_vga(dev);
-- drm_helper_resume_force_mode(dev);
+ if (drm_core_check_feature(dev, DRIVER_MODESET))
+ drm_helper_resume_force_mode(dev);
-
++
return 0;
}
---
-1.6.2
-
+
drm-intel-big-hammer.patch:
i915_gem.c | 5 +++++
1 file changed, 5 insertions(+)
Index: drm-intel-big-hammer.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-11/drm-intel-big-hammer.patch,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -p -r1.1 -r1.2
--- drm-intel-big-hammer.patch 11 Mar 2009 22:45:01 -0000 1.1
+++ drm-intel-big-hammer.patch 12 Aug 2009 16:49:49 -0000 1.2
@@ -1,13 +1,13 @@
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
-index 37427e4..08af9db 100644
+index 39f5c65..eec945a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
-@@ -2553,6 +2553,11 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
+@@ -3253,6 +3253,11 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
mutex_lock(&dev->struct_mutex);
+ /* We don't get the flushing right for these chipsets, use the
-+ * big hamer for now to avoid random crashiness. */
++ * big hammer for now to avoid random crashiness. */
+ if (IS_I855(dev) || IS_I865G(dev))
+ wbinvd();
+
drm-modesetting-radeon.patch:
arch/x86/mm/pat.c | 1
drivers/gpu/drm/Kconfig | 11
drivers/gpu/drm/Makefile | 3
drivers/gpu/drm/ati_pcigart.c | 267 +
drivers/gpu/drm/drm_agpsupport.c | 171
drivers/gpu/drm/drm_bo.c | 2161 +++++++++
drivers/gpu/drm/drm_bo_move.c | 709 +++
drivers/gpu/drm/drm_bufs.c | 12
drivers/gpu/drm/drm_crtc.c | 2
drivers/gpu/drm/drm_crtc_helper.c | 29
drivers/gpu/drm/drm_debugfs.c | 1
drivers/gpu/drm/drm_dma.c | 2
drivers/gpu/drm/drm_drv.c | 29
drivers/gpu/drm/drm_fence.c | 540 ++
drivers/gpu/drm/drm_fops.c | 5
drivers/gpu/drm/drm_info.c | 8
drivers/gpu/drm/drm_memory.c | 107
drivers/gpu/drm/drm_page_alloc.c | 171
drivers/gpu/drm/drm_page_alloc.h | 33
drivers/gpu/drm/drm_stub.c | 18
drivers/gpu/drm/drm_ttm.c | 476 ++
drivers/gpu/drm/drm_vm.c | 208
drivers/gpu/drm/i915/i915_irq.c | 3
drivers/gpu/drm/i915/intel_display.c | 22
drivers/gpu/drm/radeon/Makefile | 6
drivers/gpu/drm/radeon/ObjectID.h | 518 ++
drivers/gpu/drm/radeon/atom-bits.h | 48
drivers/gpu/drm/radeon/atom-names.h | 100
drivers/gpu/drm/radeon/atom-types.h | 42
drivers/gpu/drm/radeon/atom.c | 1141 +++++
drivers/gpu/drm/radeon/atom.h | 150
drivers/gpu/drm/radeon/atombios.h | 5025 ++++++++++++++++++++++
drivers/gpu/drm/radeon/atombios_crtc.c | 629 ++
drivers/gpu/drm/radeon/r300_cmdbuf.c | 153
drivers/gpu/drm/radeon/r300_reg.h | 16
drivers/gpu/drm/radeon/r600_cp.c | 2
drivers/gpu/drm/radeon/radeon_atombios.c | 1050 ++++
drivers/gpu/drm/radeon/radeon_buffer.c | 473 ++
drivers/gpu/drm/radeon/radeon_combios.c | 1768 +++++++
drivers/gpu/drm/radeon/radeon_connectors.c | 610 ++
drivers/gpu/drm/radeon/radeon_cp.c | 1546 ++++++
drivers/gpu/drm/radeon/radeon_cs.c | 684 +++
drivers/gpu/drm/radeon/radeon_cursor.c | 264 +
drivers/gpu/drm/radeon/radeon_display.c | 670 ++
drivers/gpu/drm/radeon/radeon_drv.c | 139
drivers/gpu/drm/radeon/radeon_drv.h | 500 +-
drivers/gpu/drm/radeon/radeon_encoders.c | 1716 +++++++
drivers/gpu/drm/radeon/radeon_fb.c | 934 ++++
drivers/gpu/drm/radeon/radeon_fence.c | 99
drivers/gpu/drm/radeon/radeon_fixed.h | 53
drivers/gpu/drm/radeon/radeon_gem.c | 1578 +++++++
drivers/gpu/drm/radeon/radeon_gem_debugfs.c | 179
drivers/gpu/drm/radeon/radeon_i2c.c | 205
drivers/gpu/drm/radeon/radeon_irq.c | 64
drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 1602 +++++++
drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 1284 +++++
drivers/gpu/drm/radeon/radeon_mem.c | 2
drivers/gpu/drm/radeon/radeon_mode.h | 398 +
drivers/gpu/drm/radeon/radeon_pm.c | 263 +
drivers/gpu/drm/radeon/radeon_reg.h | 5364 ++++++++++++++++++++++++
drivers/gpu/drm/radeon/radeon_state.c | 73
include/drm/drm.h | 1
include/drm/drmP.h | 96
include/drm/drm_crtc_helper.h | 2
include/drm/drm_objects.h | 913 ++++
include/drm/radeon_drm.h | 130
66 files changed, 35057 insertions(+), 422 deletions(-)
View full diff with command:
/usr/bin/cvs -n -f diff -kk -u -p -N -r 1.83 -r 1.84 drm-modesetting-radeon.patchIndex: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-11/drm-modesetting-radeon.patch,v
retrieving revision 1.83
retrieving revision 1.84
diff -u -p -r1.83 -r1.84
--- drm-modesetting-radeon.patch 25 Jul 2009 04:09:19 -0000 1.83
+++ drm-modesetting-radeon.patch 12 Aug 2009 16:49:49 -0000 1.84
@@ -1,1755 +1,5 @@
-commit dea27f6e83efabdc3e37bc5a91d29d6dab893853
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Mar 18 17:07:07 2009 +1000
-
- radeon: fixup encoder oops due to wrong ordering on init calls
-
-commit 4a90f1edefee2cba39d135f2866e1bacc1ac647e
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Mar 19 00:16:00 2009 +1000
-
- drm/ttm: re-org the whole cached/uncached allocator yet again.
-
- This removes the allocator type, and instead tracks when pages
- were allocated from which pool and frees them back into that pool
-
-commit c8ae93fa4ac69112f4fc16477f73e0a98bba2765
-Author: Dave Airlie <airlied at redhat.com>
-Date: Sun Mar 15 18:26:42 2009 +1000
-
- ttm: prefetch pages on pagefault
-
-commit f4df0e7870378ec40c268b95fb4b5d13533095fd
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Mon Mar 16 03:52:13 2009 -0400
-
- radeon: make sure to free connector priv when done
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit 96d923793eb924750b26e8ab2a4264131e17cd5b
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Mon Mar 16 03:36:16 2009 -0400
-
- radeon: fix combios asic init
-
- - igp chips don't have asic_init3/4 or ram reset tables
- - write out the detected ram size to the CONFIG_MEMSIZE register
- - some r1xx chips require ram detection rather than reading size
- from bios tables
- - asic_init5 table isn't needed
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit 68f14af742eda9fd28c920776ce5396e304f8a82
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Mon Mar 16 03:16:35 2009 -0400
-
- radeon: rework bios scratch regsiter handling
-
- split bios scratch reg handling into 3 functions:
-
- - connected/active
- - crtc to encoder mapping
- - encoder dpms state
-
- Hook the functions in at the appropriate places in
- the driver. DVI-I is a bit messy since we need to know
- digital vs analog so we have to update the scratch regs
- twice: once in detect() and again after we know digital/analog
- in get_modes().
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit 3ba04861b4d399a7c6e21f0a7279d5f087fc4a8c
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Sat Mar 14 16:43:14 2009 -0400
-
- radeon: rework combios encoder/connector setup
-
- - along the same lines as atom
- - re-enable atom and legacy paths for r4xx cards
- - remove bios_connector struct
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit 2ed15179f72e66a020a7f318cc4c3fa57865e4ba
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Thu Mar 12 16:02:01 2009 -0400
-
- radeon: fix misleading messages
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit cb917ec2b585f5ac873ab2e6938da9a3b730c0a1
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Thu Mar 12 14:27:06 2009 -0400
-
- atom: fix up encoder routines to deal with connector setup
-
- often times the links or lanes used are dependant on the
- connector rather than the encoder.
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit abe11890fc272189712f2e6268a8751e25b7b7b5
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Thu Mar 12 13:43:03 2009 -0400
-
- atom: re-enable quirks
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit 6a45dbd73c14735711f1803e8a3dd1063b7b3021
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Thu Mar 12 13:21:32 2009 -0400
-
- object table: don't add ddc for tv/cv
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit 6fb018a3740510f140bcd5b6b89904e9d3167811
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Thu Mar 12 13:10:50 2009 -0400
-
- radeon: major restructuring of atom output/connector setup
-
- - add connectors and encoders while parsing the bios tables.
- - pull in fixed up object header parsing for r6xx+
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit 034267381be779a1bbdb5f6f97c1471fb8538a04
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Wed Mar 4 13:02:26 2009 -0500
-
- RS600 doesn't have DFP quirk in connector table
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit b7936094db13c736e4bee7494c2b99a8e5ced042
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Thu Mar 5 16:37:57 2009 -0500
-
- R6xx/R7xx: don't mess with RADEON_HOST_PATH_CNTL
-
- these chips don't have this reg at this location.
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit a1fdbf2f4de3988f5e3319ee9f267f7b27e8fc6e
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Wed Mar 11 16:50:19 2009 -0400
-
- radeon: make sure to free enc_priv when done
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit d54586a52852497d82f322c536515d223697fdf4
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Wed Mar 11 15:43:16 2009 -0400
-
- radeon: restructure encoders
-
- move encoder specific data into encoder specific structs
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit 0215044d42faded71b8591a79550c0bf04908458
-Author: Alex Deucher <alexdeucher at gmail.com>
-Date: Wed Mar 11 11:23:16 2009 -0400
-
- radeon: atom modesetting updates
-
- Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
-
-commit 121d45a2e9562836138c658224def839bb166f68
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Mar 12 11:39:05 2009 +1000
-
- drm/radeon: Don't try to use agp symbols if we don't have AGP
-
- The radeon_buffer.c addition that gets pulled into the DRM driver as
- part of Kernel Mode Setting (even if you disable KMS for the Radeon
- driver) was assuming that it was safe to use symbols from the AGP code,
- but that isn't safe on platforms where __OS_HAS_AGP is 0. Such as
- sparc64. :)
-
- This patch gets the code building again. It probably should go into the
- actual kms patch, but if you would prefer this go as a separate patch, I
- can apply it. With this, we can get rawhide building for sparc64, so I'm
- eager to see it applied in one way or another.
-
- Signed-off-by: Tom "spot" Callaway <tcallawa at redhat.com>
-
-commit 36bbbdea9a2e77c1d1da7504bc5f03267d0e0d6c
-Author: Dave Airlie <airlied at dhcp-1-203.bne.redhat.com>
-Date: Thu Mar 12 10:58:05 2009 +1000
-
- radeon: fixup the IB getting routine
-
- This makes the IB get routine a lot smarter and hopefully
[...6099 lines suppressed...]
-+#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
-+#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
-+#define DRM_IOCTL_RADEON_GEM_WAIT_RENDERING DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_RENDERING, struct drm_radeon_gem_wait_rendering)
-+#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
-+
++/* KMS */
++#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
++#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
++#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
++#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
++#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
++#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
++#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
++#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
++#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
+
+
typedef struct drm_radeon_init {
enum {
- RADEON_INIT_CP = 0x01,
-@@ -680,6 +713,8 @@ typedef struct drm_radeon_indirect {
+@@ -682,6 +703,7 @@ typedef struct drm_radeon_indirect {
#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
-+#define RADEON_PARAM_KERNEL_MM 16
-+#define RADEON_PARAM_DEVICE_ID 17
++#define RADEON_PARAM_DEVICE_ID 16
typedef struct drm_radeon_getparam {
int param;
-@@ -734,6 +769,7 @@ typedef struct drm_radeon_setparam {
- #define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
- #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
- #define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
-+#define RADEON_SETPARAM_MM_INIT 7 /* DDX wants memory manager but has no modesetting */
- /* 1.14: Clients can allocate/free a surface
- */
- typedef struct drm_radeon_surface_alloc {
-@@ -749,4 +785,106 @@ typedef struct drm_radeon_surface_free {
+@@ -751,4 +773,112 @@ typedef struct drm_radeon_surface_free {
#define DRM_RADEON_VBLANK_CRTC1 1
#define DRM_RADEON_VBLANK_CRTC2 2
-+#define RADEON_GEM_DOMAIN_CPU 0x1 // Cached CPU domain
-+#define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed
-+#define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain
++/*
++ * Kernel modesetting world below.
++ */
++#define RADEON_GEM_DOMAIN_CPU 0x1
++#define RADEON_GEM_DOMAIN_GTT 0x2
++#define RADEON_GEM_DOMAIN_VRAM 0x4
+
-+/* return to userspace start/size of gtt and vram apertures */
+struct drm_radeon_gem_info {
-+ uint64_t gart_start;
-+ uint64_t gart_size;
-+ uint64_t vram_start;
-+ uint64_t vram_size;
-+ uint64_t vram_visible;
++ uint64_t gart_size;
++ uint64_t vram_size;
++ uint64_t vram_visible;
+};
+
++#define RADEON_GEM_NO_BACKING_STORE 1
++
+struct drm_radeon_gem_create {
-+ uint64_t size;
-+ uint64_t alignment;
-+ uint32_t handle;
-+ uint32_t initial_domain; // to allow VRAM to be created
-+ uint32_t no_backing_store; // for VRAM objects - select whether they need backing store
-+ // pretty much front/back/depth don't need it - other things do
++ uint64_t size;
++ uint64_t alignment;
++ uint32_t handle;
++ uint32_t initial_domain;
++ uint32_t flags;
+};
+
+struct drm_radeon_gem_mmap {
-+ uint32_t handle;
-+ uint32_t pad;
-+ uint64_t offset;
-+ uint64_t size;
-+ uint64_t addr_ptr;
++ uint32_t handle;
++ uint32_t pad;
++ uint64_t offset;
++ uint64_t size;
++ uint64_t addr_ptr;
+};
+
+struct drm_radeon_gem_set_domain {
-+ uint32_t handle;
-+ uint32_t read_domains;
-+ uint32_t write_domain;
++ uint32_t handle;
++ uint32_t read_domains;
++ uint32_t write_domain;
+};
+
-+struct drm_radeon_gem_wait_rendering {
-+ uint32_t handle;
-+};
-+
-+struct drm_radeon_gem_pin {
-+ uint32_t handle;
-+ uint32_t pin_domain;
-+ uint64_t alignment;
-+ uint64_t offset;
-+};
-+
-+struct drm_radeon_gem_unpin {
-+ uint32_t handle;
-+ uint32_t pad;
++struct drm_radeon_gem_wait_idle {
++ uint32_t handle;
++ uint32_t pad;
+};
+
+struct drm_radeon_gem_busy {
-+ uint32_t handle;
-+ uint32_t busy;
++ uint32_t handle;
++ uint32_t busy;
+};
+
+struct drm_radeon_gem_pread {
@@ -38670,7 +37375,8 @@ index 937a275..f716e0a 100644
+ /** Length of data to read */
+ uint64_t size;
+ /** Pointer to write the data into. */
-+ uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
++ /* void *, but pointers are not 32/64 compatible */
++ uint64_t data_ptr;
+};
+
+struct drm_radeon_gem_pwrite {
@@ -38682,28 +37388,43 @@ index 937a275..f716e0a 100644
+ /** Length of data to write */
+ uint64_t size;
+ /** Pointer to read the data from. */
-+ uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
++ /* void *, but pointers are not 32/64 compatible */
++ uint64_t data_ptr;
+};
+
-+
-+/* New interface which obsolete all previous interface.
-+ */
-+#define RADEON_CHUNK_ID_RELOCS 0x01
-+#define RADEON_CHUNK_ID_IB 0x02
-+#define RADEON_CHUNK_ID_OLD 0xff
++#define RADEON_CHUNK_ID_RELOCS 0x01
++#define RADEON_CHUNK_ID_IB 0x02
+
+struct drm_radeon_cs_chunk {
-+ uint32_t chunk_id;
-+ uint32_t length_dw;
-+ uint64_t chunk_data;
++ uint32_t chunk_id;
++ uint32_t length_dw;
++ uint64_t chunk_data;
+};
+
-+struct drm_radeon_cs {
-+ uint32_t num_chunks;
-+ uint32_t cs_id;
-+ uint64_t chunks; /* this points to uint64_t * which point to
-+ cs chunks */
++struct drm_radeon_cs_reloc {
++ uint32_t handle;
++ uint32_t read_domains;
++ uint32_t write_domain;
++ uint32_t flags;
+};
+
++struct drm_radeon_cs {
++ uint32_t num_chunks;
++ uint32_t cs_id;
++ /* this points to uint64_t * which point to cs chunks */
++ uint64_t chunks;
++ /* updates to the limits after this CS ioctl */
++ uint64_t gart_limit;
++ uint64_t vram_limit;
++};
++
++#define RADEON_INFO_DEVICE_ID 0x00
++#define RADEON_INFO_NUM_GB_PIPES 0x01
++
++struct drm_radeon_info {
++ uint32_t request;
++ uint32_t pad;
++ uint64_t value;
++};
+
#endif
drm-no-gem-on-i8xx.patch:
i915_dma.c | 4 ++--
i915_drv.h | 3 +++
2 files changed, 5 insertions(+), 2 deletions(-)
Index: drm-no-gem-on-i8xx.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-11/drm-no-gem-on-i8xx.patch,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -p -r1.3 -r1.4
--- drm-no-gem-on-i8xx.patch 25 Jul 2009 04:09:21 -0000 1.3
+++ drm-no-gem-on-i8xx.patch 12 Aug 2009 16:49:50 -0000 1.4
@@ -1,28 +1,28 @@
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
-index cc0adb4..9303063 100644
+index 0ccb63e..4560b8d 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
-@@ -1108,8 +1108,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1148,8 +1148,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
/* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */
dev_priv->has_gem = 0;
#else
- /* enable GEM by default */
- dev_priv->has_gem = 1;
+ /* enable GEM by default, except on I8xx */
-+ dev_priv->has_gem = !IS_I8XX(dev) ? 1 : 0;
++ dev_priv->has_gem = !IS_8XX(dev) ? 1 : 0;
#endif
- i915_gem_load(dev);
+ dev->driver->get_vblank_counter = i915_get_vblank_counter;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
-index a70bf77..84664fe 100644
+index c431fa5..dcf5257 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
-@@ -750,6 +750,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
+@@ -770,6 +770,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define IS_I855(dev) ((dev)->pci_device == 0x3582)
#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
-+#define IS_I8XX(dev) (IS_I830(dev) || IS_845G(dev) || IS_I85X(dev) || \
-+ IS_I855(dev) || IS_I865G(dev))
++#define IS_I8XX(dev) (IS_I830(dev) || IS_I845G(dev) || IS_I85X(dev) || \
++ IS_I855(dev))
+
#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
drm-nouveau.patch:
drivers/gpu/drm/Kconfig | 15
drivers/gpu/drm/Makefile | 1
drivers/gpu/drm/drm_bufs.c | 28
drivers/gpu/drm/drm_fence.c | 2
drivers/gpu/drm/drm_gem.c | 50
drivers/gpu/drm/nouveau/Makefile | 24
drivers/gpu/drm/nouveau/nouveau_backlight.c | 152
drivers/gpu/drm/nouveau/nouveau_bios.c | 4852 +++++
drivers/gpu/drm/nouveau/nouveau_bios.h | 223
drivers/gpu/drm/nouveau/nouveau_bo.c | 415
drivers/gpu/drm/nouveau/nouveau_calc.c | 622
drivers/gpu/drm/nouveau/nouveau_connector.h | 51
drivers/gpu/drm/nouveau/nouveau_crtc.h | 74
drivers/gpu/drm/nouveau/nouveau_display.c | 114
drivers/gpu/drm/nouveau/nouveau_dma.c | 209
drivers/gpu/drm/nouveau/nouveau_dma.h | 107
drivers/gpu/drm/nouveau/nouveau_drv.c | 194
drivers/gpu/drm/nouveau/nouveau_drv.h | 836
drivers/gpu/drm/nouveau/nouveau_encoder.h | 46
drivers/gpu/drm/nouveau/nouveau_fb.h | 44
drivers/gpu/drm/nouveau/nouveau_fbcon.c | 946 +
drivers/gpu/drm/nouveau/nouveau_fbcon.h | 48
drivers/gpu/drm/nouveau/nouveau_fence.c | 126
drivers/gpu/drm/nouveau/nouveau_fifo.c | 692
drivers/gpu/drm/nouveau/nouveau_gem.c | 729
drivers/gpu/drm/nouveau/nouveau_hw.c | 1019 +
drivers/gpu/drm/nouveau/nouveau_hw.h | 530
drivers/gpu/drm/nouveau/nouveau_i2c.c | 222
drivers/gpu/drm/nouveau/nouveau_i2c.h | 46
drivers/gpu/drm/nouveau/nouveau_ioc32.c | 72
drivers/gpu/drm/nouveau/nouveau_irq.c | 592
drivers/gpu/drm/nouveau/nouveau_mem.c | 1073 +
drivers/gpu/drm/nouveau/nouveau_notifier.c | 176
drivers/gpu/drm/nouveau/nouveau_object.c | 1236 +
drivers/gpu/drm/nouveau/nouveau_reg.h | 854
drivers/gpu/drm/nouveau/nouveau_sgdma.c | 340
drivers/gpu/drm/nouveau/nouveau_state.c | 1043 +
drivers/gpu/drm/nouveau/nouveau_swmthd.c | 190
drivers/gpu/drm/nouveau/nouveau_swmthd.h | 33
drivers/gpu/drm/nouveau/nv04_fb.c | 21
drivers/gpu/drm/nouveau/nv04_fifo.c | 144
drivers/gpu/drm/nouveau/nv04_graph.c | 521
drivers/gpu/drm/nouveau/nv04_instmem.c | 190
drivers/gpu/drm/nouveau/nv04_mc.c | 20
drivers/gpu/drm/nouveau/nv04_timer.c | 50
drivers/gpu/drm/nouveau/nv10_fb.c | 24
drivers/gpu/drm/nouveau/nv10_fifo.c | 175
drivers/gpu/drm/nouveau/nv10_graph.c | 912 +
drivers/gpu/drm/nouveau/nv20_graph.c | 907 +
drivers/gpu/drm/nouveau/nv40_fb.c | 62
drivers/gpu/drm/nouveau/nv40_fifo.c | 216
drivers/gpu/drm/nouveau/nv40_graph.c | 2179 ++
drivers/gpu/drm/nouveau/nv40_mc.c | 38
drivers/gpu/drm/nouveau/nv50_connector.c | 491
drivers/gpu/drm/nouveau/nv50_crtc.c | 810
drivers/gpu/drm/nouveau/nv50_cursor.c | 144
drivers/gpu/drm/nouveau/nv50_dac.c | 288
drivers/gpu/drm/nouveau/nv50_display.c | 637
drivers/gpu/drm/nouveau/nv50_display.h | 44
drivers/gpu/drm/nouveau/nv50_display_commands.h | 195
drivers/gpu/drm/nouveau/nv50_fbcon.c | 222
drivers/gpu/drm/nouveau/nv50_fifo.c | 343
drivers/gpu/drm/nouveau/nv50_graph.c | 336
drivers/gpu/drm/nouveau/nv50_grctx.h |20935 ++++++++++++++++++++++++
drivers/gpu/drm/nouveau/nv50_instmem.c | 382
drivers/gpu/drm/nouveau/nv50_mc.c | 40
drivers/gpu/drm/nouveau/nv50_sor.c | 303
drivers/gpu/drm/nouveau/nvreg.h | 495
include/drm/Kbuild | 1
include/drm/drmP.h | 2
include/drm/nouveau_drm.h | 299
71 files changed, 49410 insertions(+), 42 deletions(-)
View full diff with command:
/usr/bin/cvs -n -f diff -kk -u -p -N -r 1.60 -r 1.61 drm-nouveau.patchIndex: drm-nouveau.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-11/drm-nouveau.patch,v
retrieving revision 1.60
retrieving revision 1.61
diff -u -p -r1.60 -r1.61
--- drm-nouveau.patch 25 Jul 2009 04:09:21 -0000 1.60
+++ drm-nouveau.patch 12 Aug 2009 16:49:50 -0000 1.61
@@ -1,8 +1,8 @@
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
-index a74980b..36582ff 100644
+index f8d5074..3ada5e4 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
-@@ -133,3 +133,18 @@ config DRM_SAVAGE
+@@ -140,3 +140,18 @@ config DRM_SAVAGE
help
Choose this option if you have a Savage3D/4/SuperSavage/Pro/Twister
chipset. If M is selected the module will be called savage.
@@ -32,7 +32,7 @@ index d6788df..97aa0c8 100644
+obj-$(CONFIG_DRM_NOUVEAU) +=nouveau/
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
-index 4d2161f..ac503e2 100644
+index 07e0c51..9ac171c 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -51,38 +51,24 @@ resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resour
@@ -80,7 +80,7 @@ index 4d2161f..ac503e2 100644
static int drm_map_handle(struct drm_device *dev, struct drm_hash_item *hash,
unsigned long user_token, int hashed_handle, int shm)
-@@ -349,7 +335,7 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
+@@ -357,7 +343,7 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
/* We do it here so that dev->struct_mutex protects the increment */
user_token = (map->type == _DRM_SHM) ? (unsigned long)map->handle :
map->offset;
@@ -103,7 +103,7 @@ index f1c386c..fd62fd9 100644
if (mask & ~fence->type) {
DRM_ERROR("Wait trying to extend fence type"
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
-index c1173d8..2e4e667 100644
+index 4984aa8..dee9b40 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -280,48 +280,58 @@ drm_gem_close_ioctl(struct drm_device *dev, void *data,
@@ -185,58 +185,9 @@ index c1173d8..2e4e667 100644
mutex_lock(&dev->struct_mutex);
drm_gem_object_unreference(obj);
mutex_unlock(&dev->struct_mutex);
-diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
-index 5d45cbf..e3b0a76 100644
---- a/drivers/gpu/drm/drm_stub.c
-+++ b/drivers/gpu/drm/drm_stub.c
-@@ -406,14 +406,14 @@ int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
- if (dev->driver->load) {
- ret = dev->driver->load(dev, ent->driver_data);
- if (ret)
-- goto err_g3;
-+ goto err_g4;
- }
-
- /* setup the grouping for the legacy output */
- if (drm_core_check_feature(dev, DRIVER_MODESET)) {
- ret = drm_mode_group_init_legacy_group(dev, &dev->primary->mode_group);
- if (ret)
-- goto err_g3;
-+ goto err_g4;
- }
-
- list_add_tail(&dev->driver_item, &driver->device_list);
-@@ -424,8 +424,11 @@ int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
-
- return 0;
-
--err_g3:
-+err_g4:
- drm_put_minor(&dev->primary);
-+err_g3:
-+ if (drm_core_check_feature(dev, DRIVER_MODESET))
-+ drm_put_minor(&dev->control);
- err_g2:
- pci_disable_device(pdev);
- err_g1:
-@@ -507,11 +510,11 @@ void drm_put_dev(struct drm_device *dev)
- dev->agp = NULL;
- }
-
-- drm_ht_remove(&dev->map_hash);
-- drm_ctxbitmap_cleanup(dev);
--
- list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head)
- drm_rmmap(dev, r_list->map);
-+ drm_ht_remove(&dev->map_hash);
-+
-+ drm_ctxbitmap_cleanup(dev);
-
- if (drm_core_check_feature(dev, DRIVER_MODESET))
- drm_put_minor(&dev->control);
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
new file mode 100644
-index 0000000..12af41b
+index 0000000..06483d0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -0,0 +1,24 @@
@@ -249,8 +200,8 @@ index 0000000..12af41b
+ nouveau_object.o nouveau_irq.o nouveau_notifier.o \
+ nouveau_swmthd.o nouveau_sgdma.o nouveau_dma.o \
+ nouveau_bo.o nouveau_fence.o nouveau_gem.o \
-+ nouveau_bios.o nouveau_display.o nouveau_fbcon.o \
-+ nouveau_backlight.o \
++ nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \
++ nouveau_display.o nouveau_fbcon.o nouveau_backlight.o \
+ nv04_timer.o \
+ nv04_mc.o nv40_mc.o nv50_mc.o \
+ nv04_fb.o nv10_fb.o nv40_fb.o \
@@ -259,17 +210,17 @@ index 0000000..12af41b
+ nv40_graph.o nv50_graph.o \
+ nv04_instmem.o nv50_instmem.o \
+ nv50_crtc.o nv50_dac.o nv50_sor.o nv50_connector.o \
-+ nv50_cursor.o nv50_i2c.o nv50_display.o nv50_fbcon.o
++ nv50_cursor.o nv50_display.o nv50_fbcon.o
+
+nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
+
+obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c
new file mode 100644
-index 0000000..3fc521e
+index 0000000..e3d354f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
-@@ -0,0 +1,156 @@
+@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2009 Red Hat <mjg at redhat.com>
+ *
@@ -312,7 +263,6 @@ index 0000000..3fc521e
+static int nv40_get_intensity(struct backlight_device *bd)
+{
+ struct drm_device *dev = bl_get_data(bd);
-+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ int val = (nv_rd32(NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK) >> 16;
+
+ return val;
@@ -321,7 +271,6 @@ index 0000000..3fc521e
+static int nv40_set_intensity(struct backlight_device *bd)
+{
+ struct drm_device *dev = bl_get_data(bd);
-+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ int val = bd->props.brightness;
+ int reg = nv_rd32(NV40_PMC_BACKLIGHT);
+
@@ -340,7 +289,6 @@ index 0000000..3fc521e
+static int nv50_get_intensity(struct backlight_device *bd)
+{
+ struct drm_device *dev = bl_get_data(bd);
-+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+ return nv_rd32(NV50_PDISPLAY_BACKLIGHT);
+}
@@ -348,7 +296,6 @@ index 0000000..3fc521e
+static int nv50_set_intensity(struct backlight_device *bd)
+{
+ struct drm_device *dev = bl_get_data(bd);
-+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ int val = bd->props.brightness;
+
+ nv_wr32(NV50_PDISPLAY_BACKLIGHT, val | NV50_PDISPLAY_BACKLIGHT_ENABLE);
@@ -428,45 +375,66 @@ index 0000000..3fc521e
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
new file mode 100644
-index 0000000..bcbedb7
+index 0000000..d63baf3
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
-@@ -0,0 +1,854 @@
+@@ -0,0 +1,4852 @@
+/*
-+ * Copyright (C) 2005-2006 Erik Waling
-+ * Copyright (C) 2006 Stephane Marchesin
-+ * Copyright (C) 2007-2008 Stuart Bennett
-+ * Copyright (C) 2008 Maarten Maathuis.
-+ * All Rights Reserved.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining
-+ * a copy of this software and associated documentation files (the
-+ * "Software"), to deal in the Software without restriction, including
-+ * without limitation the rights to use, copy, modify, merge, publish,
-+ * distribute, sublicense, and/or sell copies of the Software, and to
-+ * permit persons to whom the Software is furnished to do so, subject to
-+ * the following conditions:
++ * Copyright 2005-2006 Erik Waling
++ * Copyright 2006 Stephane Marchesin
++ * Copyright 2007-2009 Stuart Bennett
+ *
-+ * The above copyright notice and this permission notice (including the
-+ * next paragraph) shall be included in all copies or substantial
[...22285 lines suppressed...]
++# define NV_PRAMDAC_CU_START_POS_Y 31:16
++#define NV_RAMDAC_NV10_CURSYNC 0x00680404
++
++#define NV_PRAMDAC_NVPLL_COEFF 0x00680500
++#define NV_PRAMDAC_MPLL_COEFF 0x00680504
++#define NV_PRAMDAC_VPLL_COEFF 0x00680508
++# define NV30_RAMDAC_ENABLE_VCO2 (8 << 4)
++
++#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050c
++# define NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE (4 << 0)
++# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL (1 << 8)
++# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL (2 << 8)
++# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL (4 << 8)
++# define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2 (8 << 8)
++# define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 (1 << 28)
++# define NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2 (2 << 28)
++
++#define NV_PRAMDAC_PLL_SETUP_CONTROL 0x00680510
++#define NV_RAMDAC_VPLL2 0x00680520
++#define NV_PRAMDAC_SEL_CLK 0x00680524
++#define NV_RAMDAC_DITHER_NV11 0x00680528
++#define NV_PRAMDAC_DACCLK 0x0068052c
++# define NV_PRAMDAC_DACCLK_SEL_DACCLK (1 << 0)
++
++#define NV_RAMDAC_NVPLL_B 0x00680570
++#define NV_RAMDAC_MPLL_B 0x00680574
++#define NV_RAMDAC_VPLL_B 0x00680578
++#define NV_RAMDAC_VPLL2_B 0x0068057c
++# define NV31_RAMDAC_ENABLE_VCO2 (8 << 28)
++#define NV_PRAMDAC_580 0x00680580
++# define NV_RAMDAC_580_VPLL1_ACTIVE (1 << 8)
++# define NV_RAMDAC_580_VPLL2_ACTIVE (1 << 28)
++
++#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600
++#define NV_PRAMDAC_TEST_CONTROL 0x00680608
++# define NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED (1 << 12)
++# define NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF (1 << 16)
++# define NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI (1 << 28)
++#define NV_PRAMDAC_TESTPOINT_DATA 0x00680610
++# define NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK (8 << 28)
++#define NV_PRAMDAC_630 0x00680630
++#define NV_PRAMDAC_634 0x00680634
++
++#define NV_PRAMDAC_FP_VDISPLAY_END 0x00680800
++#define NV_PRAMDAC_FP_VTOTAL 0x00680804
++#define NV_PRAMDAC_FP_VCRTC 0x00680808
++#define NV_PRAMDAC_FP_VSYNC_START 0x0068080c
++#define NV_PRAMDAC_FP_VSYNC_END 0x00680810
++#define NV_PRAMDAC_FP_VVALID_START 0x00680814
++#define NV_PRAMDAC_FP_VVALID_END 0x00680818
++#define NV_PRAMDAC_FP_HDISPLAY_END 0x00680820
++#define NV_PRAMDAC_FP_HTOTAL 0x00680824
++#define NV_PRAMDAC_FP_HCRTC 0x00680828
++#define NV_PRAMDAC_FP_HSYNC_START 0x0068082c
++#define NV_PRAMDAC_FP_HSYNC_END 0x00680830
++#define NV_PRAMDAC_FP_HVALID_START 0x00680834
++#define NV_PRAMDAC_FP_HVALID_END 0x00680838
++
++#define NV_RAMDAC_FP_DITHER 0x0068083c
++#define NV_PRAMDAC_FP_TG_CONTROL 0x00680848
++# define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS (1 << 0)
++# define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE (2 << 0)
++# define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS (1 << 4)
++# define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE (2 << 4)
++# define NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE (0 << 8)
++# define NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER (1 << 8)
++# define NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE (2 << 8)
++# define NV_PRAMDAC_FP_TG_CONTROL_READ_PROG (1 << 20)
++# define NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 (1 << 24)
++# define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS (1 << 28)
++# define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE (2 << 28)
++#define NV_PRAMDAC_850 0x00680850
++#define NV_PRAMDAC_85C 0x0068085c
++#define NV_PRAMDAC_FP_DEBUG_0 0x00680880
++# define NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE (1 << 0)
++# define NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE (1 << 4)
++/* This doesn't seem to be essential for tmds, but still often set */
++# define NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED (8 << 4)
++# define NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR (1 << 8)
++# define NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR (1 << 12)
++# define NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND (1 << 20)
++# define NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND (1 << 24)
++# define NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK (1 << 28)
++#define NV_PRAMDAC_FP_DEBUG_1 0x00680884
++# define NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE 11:0
++# define NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE (1 << 12)
++# define NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE 27:16
++# define NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE (1 << 28)
++#define NV_PRAMDAC_FP_DEBUG_2 0x00680888
++#define NV_PRAMDAC_FP_DEBUG_3 0x0068088C
++
++/* see NV_PRAMDAC_INDIR_TMDS in rules.xml */
++#define NV_PRAMDAC_FP_TMDS_CONTROL 0x006808b0
++# define NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE (1 << 16)
++#define NV_PRAMDAC_FP_TMDS_DATA 0x006808b4
++
++/* Some kind of switch */
++#define NV_PRAMDAC_900 0x00680900
++#define NV_PRAMDAC_A20 0x00680A20
++#define NV_PRAMDAC_A24 0x00680A24
++#define NV_PRAMDAC_A34 0x00680A34
++
++/* names fabricated from NV_USER_DAC info */
++#define NV_PRMDIO_PIXEL_MASK 0x006813c6
++# define NV_PRMDIO_PIXEL_MASK_MASK 0xff
++#define NV_PRMDIO_READ_MODE_ADDRESS 0x006813c7
++#define NV_PRMDIO_WRITE_MODE_ADDRESS 0x006813c8
++#define NV_PRMDIO_PALETTE_DATA 0x006813c9
++
++#define NV_PGRAPH_DEBUG_0 0x00400080
++#define NV_PGRAPH_DEBUG_1 0x00400084
++#define NV_PGRAPH_DEBUG_2_NV04 0x00400088
++#define NV_PGRAPH_DEBUG_2 0x00400620
++#define NV_PGRAPH_DEBUG_3 0x0040008c
++#define NV_PGRAPH_DEBUG_4 0x00400090
++#define NV_PGRAPH_INTR 0x00400100
++#define NV_PGRAPH_INTR_EN 0x00400140
++#define NV_PGRAPH_CTX_CONTROL 0x00400144
++#define NV_PGRAPH_CTX_CONTROL_NV04 0x00400170
++#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
++#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540
++#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544
++#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548
++#define NV_PGRAPH_BETA_AND 0x00400608
++#define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610
++#define NV_PGRAPH_BOFFSET0 0x00400640
++#define NV_PGRAPH_BOFFSET1 0x00400644
++#define NV_PGRAPH_BOFFSET2 0x00400648
++#define NV_PGRAPH_BLIMIT0 0x00400684
++#define NV_PGRAPH_BLIMIT1 0x00400688
++#define NV_PGRAPH_BLIMIT2 0x0040068c
++#define NV_PGRAPH_STATUS 0x00400700
++#define NV_PGRAPH_SURFACE 0x00400710
++#define NV_PGRAPH_STATE 0x00400714
++#define NV_PGRAPH_FIFO 0x00400720
++#define NV_PGRAPH_PATTERN_SHAPE 0x00400810
++#define NV_PGRAPH_TILE 0x00400b00
++
++#define NV_PVIDEO_INTR_EN 0x00008140
++#define NV_PVIDEO_BUFFER 0x00008700
++#define NV_PVIDEO_STOP 0x00008704
++#define NV_PVIDEO_UVPLANE_BASE(buff) (0x00008800+(buff)*4)
++#define NV_PVIDEO_UVPLANE_LIMIT(buff) (0x00008808+(buff)*4)
++#define NV_PVIDEO_UVPLANE_OFFSET_BUFF(buff) (0x00008820+(buff)*4)
++#define NV_PVIDEO_BASE(buff) (0x00008900+(buff)*4)
++#define NV_PVIDEO_LIMIT(buff) (0x00008908+(buff)*4)
++#define NV_PVIDEO_LUMINANCE(buff) (0x00008910+(buff)*4)
++#define NV_PVIDEO_CHROMINANCE(buff) (0x00008918+(buff)*4)
++#define NV_PVIDEO_OFFSET_BUFF(buff) (0x00008920+(buff)*4)
++#define NV_PVIDEO_SIZE_IN(buff) (0x00008928+(buff)*4)
++#define NV_PVIDEO_POINT_IN(buff) (0x00008930+(buff)*4)
++#define NV_PVIDEO_DS_DX(buff) (0x00008938+(buff)*4)
++#define NV_PVIDEO_DT_DY(buff) (0x00008940+(buff)*4)
++#define NV_PVIDEO_POINT_OUT(buff) (0x00008948+(buff)*4)
++#define NV_PVIDEO_SIZE_OUT(buff) (0x00008950+(buff)*4)
++#define NV_PVIDEO_FORMAT(buff) (0x00008958+(buff)*4)
++# define NV_PVIDEO_FORMAT_PLANAR (1 << 0)
++# define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8 (1 << 16)
++# define NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY (1 << 20)
++# define NV_PVIDEO_FORMAT_MATRIX_ITURBT709 (1 << 24)
++#define NV_PVIDEO_COLOR_KEY 0x00008B00
++
++/* NV04 overlay defines from VIDIX & Haiku */
++#define NV_PVIDEO_INTR_EN_0 0x00680140
++#define NV_PVIDEO_STEP_SIZE 0x00680200
++#define NV_PVIDEO_CONTROL_Y 0x00680204
++#define NV_PVIDEO_CONTROL_X 0x00680208
++#define NV_PVIDEO_BUFF0_START_ADDRESS 0x0068020c
++#define NV_PVIDEO_BUFF0_PITCH_LENGTH 0x00680214
++#define NV_PVIDEO_BUFF0_OFFSET 0x0068021c
++#define NV_PVIDEO_BUFF1_START_ADDRESS 0x00680210
++#define NV_PVIDEO_BUFF1_PITCH_LENGTH 0x00680218
++#define NV_PVIDEO_BUFF1_OFFSET 0x00680220
++#define NV_PVIDEO_OE_STATE 0x00680224
++#define NV_PVIDEO_SU_STATE 0x00680228
++#define NV_PVIDEO_RM_STATE 0x0068022c
++#define NV_PVIDEO_WINDOW_START 0x00680230
++#define NV_PVIDEO_WINDOW_SIZE 0x00680234
++#define NV_PVIDEO_FIFO_THRES_SIZE 0x00680238
++#define NV_PVIDEO_FIFO_BURST_LENGTH 0x0068023c
++#define NV_PVIDEO_KEY 0x00680240
++#define NV_PVIDEO_OVERLAY 0x00680244
++#define NV_PVIDEO_RED_CSC_OFFSET 0x00680280
++#define NV_PVIDEO_GREEN_CSC_OFFSET 0x00680284
++#define NV_PVIDEO_BLUE_CSC_OFFSET 0x00680288
++#define NV_PVIDEO_CSC_ADJUST 0x0068028c
++
++#endif
diff --git a/include/drm/Kbuild b/include/drm/Kbuild
index b940fdf..cfa6af4 100644
--- a/include/drm/Kbuild
@@ -42929,7 +49627,7 @@ index b940fdf..cfa6af4 100644
unifdef-y += via_drm.h
+unifdef-y += nouveau_drm.h
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
-index b61b0c6..5b7ce2d 100644
+index b0d024c..fb93588 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1267,6 +1267,8 @@ extern void drm_idlelock_release(struct drm_lock_data *lock_data);
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-11/kernel.spec,v
retrieving revision 1.1701
retrieving revision 1.1702
diff -u -p -r1.1701 -r1.1702
--- kernel.spec 12 Aug 2009 15:26:50 -0000 1.1701
+++ kernel.spec 12 Aug 2009 16:49:51 -0000 1.1702
@@ -656,11 +656,21 @@ Patch1700: agp-set_memory_ucwb.patch
# nouveau + drm fixes
Patch1811: drm-next.patch
Patch1812: drm-modesetting-radeon.patch
-Patch1813: drm-radeon-pm.patch
-Patch1814: drm-nouveau.patch
-Patch1816: drm-no-gem-on-i8xx.patch
-Patch1818: drm-i915-resume-force-mode.patch
-Patch1819: drm-intel-big-hammer.patch
+Patch1813: drm-nouveau.patch
+Patch1814: drm-no-gem-on-i8xx.patch
+Patch1815: drm-i915-resume-force-mode.patch
+Patch1816: drm-intel-big-hammer.patch
+Patch1817: drm-intel-gen3-fb-hack.patch
+Patch1818: drm-intel-hdmi-edid-fix.patch
+Patch1819: drm-intel-gem-use-dma32-on-pae.patch
+Patch1820: drm-modesetting-radeon-fixes.patch
+Patch1821: drm-radeon-new-pciids.patch
+Patch1822: drm-dont-frob-i2c.patch
+Patch1823: drm-intel-tv-fix.patch
+Patch1824: drm-radeon-cs-oops-fix.patch
+Patch1825: drm-pnp-add-resource-range-checker.patch
+Patch1826: drm-i915-enable-mchbar.patch
+
# kludge to make ich9 e1000 work
Patch2000: linux-2.6-e1000-ich9.patch
@@ -1261,16 +1271,24 @@ ApplyPatch linux-2.6-crash-driver.patch
# http://www.lirc.org/
ApplyPatch linux-2.6.29-lirc.patch
+# DRM patches
ApplyPatch agp-set_memory_ucwb.patch
-# Nouveau DRM + drm fixes
#ApplyPatch drm-next.patch
-#ApplyPatch drm-modesetting-radeon.patch
-#ApplyPatch drm-nouveau.patch
-# pm broken on my thinkpad t60p - airlied
-#ApplyPatch drm-radeon-pm.patch
+ApplyPatch drm-modesetting-radeon.patch
+ApplyPatch drm-nouveau.patch
ApplyPatch drm-no-gem-on-i8xx.patch
ApplyPatch drm-i915-resume-force-mode.patch
ApplyPatch drm-intel-big-hammer.patch
+ApplyPatch drm-intel-gen3-fb-hack.patch
+ApplyPatch drm-intel-hdmi-edid-fix.patch
+#ApplyPatch drm-intel-gem-use-dma32-on-pae.patch
+ApplyPatch drm-modesetting-radeon-fixes.patch
+ApplyPatch drm-radeon-new-pciids.patch
+ApplyPatch drm-dont-frob-i2c.patch
+ApplyPatch drm-intel-tv-fix.patch
+ApplyPatch drm-radeon-cs-oops-fix.patch
+ApplyPatch drm-pnp-add-resource-range-checker.patch
+ApplyPatch drm-i915-enable-mchbar.patch
# linux1394 git patches
#ApplyPatch linux-2.6-firewire-git-update.patch
@@ -1879,6 +1897,24 @@ fi
# and build.
%changelog
+* Wed Aug 12 2009 Kyle McMartin <kyle at redhat.com>
+- DRM patch sync-up with F-11-2.6.29.y, ABI probably isn't right yet though...
+ - drm-modesetting-radeon.patch
+ - drm-nouveau.patch
+ - drm-no-gem-on-i8xx.patch
+ - drm-i915-resume-force-mode.patch
+ - drm-intel-big-hammer.patch
+ - drm-intel-gen3-fb-hack.patch
+ - drm-intel-hdmi-edid-fix.patch
+ - drm-modesetting-radeon-fixes.patch
+ - drm-radeon-new-pciids.patch
+ - drm-dont-frob-i2c.patch
+ - drm-intel-tv-fix.patch
+ - drm-radeon-cs-oops-fix.patch
+ - drm-pnp-add-resource-range-checker.patch
+ - drm-i915-enable-mchbar.patch
+- The rest were merged upstream.
+
* Wed Aug 12 2009 John W. Linville <linville at redhat.com>
- iwlwifi: fix TX queue race
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