rpms/kernel/devel drm-intel-next.patch, 1.4, 1.5 kernel.spec, 1.1295, 1.1296

[Kristian Høgsberg]

Author: krh

Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv9276

Modified Files:
	drm-intel-next.patch kernel.spec 
Log Message:
* Fri Feb 13 2009 Kristian Høgsberg <krh at redhat.com>
- Update drm-intel-next patch with more modesetting fixes.


drm-intel-next.patch:

Index: drm-intel-next.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-intel-next.patch,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -r1.4 -r1.5
--- drm-intel-next.patch	11 Feb 2009 15:28:08 -0000	1.4
+++ drm-intel-next.patch	13 Feb 2009 23:44:29 -0000	1.5
@@ -16,6 +16,44 @@
 # Patches follow
 
 
+commit 5eaf13a569f7b0e7884fc083cbf7e62ddcec6a8f
+Author: Kristian Høgsberg <krh at redhat.com>
+Date:   Fri Feb 13 18:22:53 2009 -0500
+
+    [i915] Bring PLL limits in sync with DDX values.
+    
+    Signed-off-by: Kristian Høgsberg <krh at redhat.com>
+
+commit b02c4adfa7c31b6679dcd4da5a66c125bac8aafe
+Author: Kristian Høgsberg <krh at redhat.com>
+Date:   Fri Feb 13 17:51:11 2009 -0500
+
+    [i915] Collapse identical i8xx_clock() and i9xx_clock().
+    
+    They used to be different.  Now they're identical.
+    
+    Signed-off-by: Kristian Høgsberg <krh at redhat.com>
+
+commit 3435521fd84cf373c02b8e0fb9e59a75285636a4
+Author: Kristian Høgsberg <krh at redhat.com>
+Date:   Fri Feb 13 17:44:12 2009 -0500
+
+    [i915] Use spread spectrum when the bios tells us it's ok.
+    
+    Lifted from the DDX modesetting.
+    
+    Signed-off-by: Kristian Høgsberg <krh at redhat.com>
+
+commit 5e15374a3900c941bbeb5d5cedddad07aa821184
+Author: Kristian Høgsberg <krh at redhat.com>
+Date:   Fri Feb 13 15:41:59 2009 -0500
+
+    [i915] Add missing locking around gem operations.
+    
+    Pinning and setting the domains requires taking the struct mutex.
+    
+    Signed-off-by: Kristian Høgsberg <krh at redhat.com>
+
 commit 6c7aefedd9ebaf1146581dec54f74b29486dae56
 Author: Jesse Barnes <jbarnes at virtuousgeek.org>
 Date:   Wed Feb 4 14:27:01 2009 -0800
@@ -349,6 +387,19 @@
  }
  
  /**
+diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
+index 7325363..135a08f 100644
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -184,6 +184,8 @@ typedef struct drm_i915_private {
+ 	unsigned int lvds_dither:1;
+ 	unsigned int lvds_vbt:1;
+ 	unsigned int int_crt_support:1;
++	unsigned int lvds_use_ssc:1;
++	int lvds_ssc_freq;
+ 
+ 	struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
+ 	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
 index 8185766..ff0d94d 100644
 --- a/drivers/gpu/drm/i915/i915_gem.c
@@ -440,11 +491,153 @@
  
  	return 0;
  }
+diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
+index 4ca82a0..65be30d 100644
+--- a/drivers/gpu/drm/i915/intel_bios.c
++++ b/drivers/gpu/drm/i915/intel_bios.c
+@@ -135,6 +135,14 @@ parse_general_features(struct drm_i915_private *dev_priv,
+ 	if (general) {
+ 		dev_priv->int_tv_support = general->int_tv_support;
+ 		dev_priv->int_crt_support = general->int_crt_support;
++		dev_priv->lvds_use_ssc = general->enable_ssc;
++
++		if (dev_priv->lvds_use_ssc) {
++		  if (IS_I855(dev_priv->dev))
++		    dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
++		  else
++		    dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
++		}
+ 	}
+ }
+ 
 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
-index bbdd729..0c66952 100644
+index bbdd729..2daf989 100644
 --- a/drivers/gpu/drm/i915/intel_display.c
 +++ b/drivers/gpu/drm/i915/intel_display.c
-@@ -782,6 +782,9 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
+@@ -90,12 +90,12 @@ typedef struct {
+ #define I9XX_DOT_MAX		 400000
+ #define I9XX_VCO_MIN		1400000
+ #define I9XX_VCO_MAX		2800000
+-#define I9XX_N_MIN		      3
+-#define I9XX_N_MAX		      8
++#define I9XX_N_MIN		      1
++#define I9XX_N_MAX		      6
+ #define I9XX_M_MIN		     70
+ #define I9XX_M_MAX		    120
+ #define I9XX_M1_MIN		     10
+-#define I9XX_M1_MAX		     20
++#define I9XX_M1_MAX		     22
+ #define I9XX_M2_MIN		      5
+ #define I9XX_M2_MAX		      9
+ #define I9XX_P_SDVO_DAC_MIN	      5
+@@ -189,19 +189,7 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
+ 	return limit;
+ }
+ 
+-/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
+-
+-static void i8xx_clock(int refclk, intel_clock_t *clock)
+-{
+-	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
+-	clock->p = clock->p1 * clock->p2;
+-	clock->vco = refclk * clock->m / (clock->n + 2);
+-	clock->dot = clock->vco / clock->p;
+-}
+-
+-/** Derive the pixel clock for the given refclk and divisors for 9xx chips. */
+-
+-static void i9xx_clock(int refclk, intel_clock_t *clock)
++static void intel_clock(int refclk, intel_clock_t *clock)
+ {
+ 	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
+ 	clock->p = clock->p1 * clock->p2;
+@@ -209,15 +197,6 @@ static void i9xx_clock(int refclk, intel_clock_t *clock)
+ 	clock->dot = clock->vco / clock->p;
+ }
+ 
+-static void intel_clock(struct drm_device *dev, int refclk,
+-			intel_clock_t *clock)
+-{
+-	if (IS_I9XX(dev))
+-		i9xx_clock (refclk, clock);
+-	else
+-		i8xx_clock (refclk, clock);
+-}
+-
+ /**
+  * Returns whether any output on the specified pipe is of the specified type
+  */
+@@ -238,7 +217,7 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
+     return false;
+ }
+ 
+-#define INTELPllInvalid(s)   { /* ErrorF (s) */; return false; }
++#define INTELPllInvalid(s)   do { DRM_DEBUG(s); return false; } while (0)
+ /**
+  * Returns whether the given set of divisors are valid for a given refclk with
+  * the given connectors.
+@@ -318,7 +297,7 @@ static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
+ 				     clock.p1 <= limit->p1.max; clock.p1++) {
+ 					int this_err;
+ 
+-					intel_clock(dev, refclk, &clock);
++					intel_clock(refclk, &clock);
+ 
+ 					if (!intel_PLL_is_valid(crtc, &clock))
+ 						continue;
+@@ -390,10 +369,14 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
+ 		BUG();
+ 	}
+ 
+-	if (i915_gem_object_pin(intel_fb->obj, alignment))
++	mutex_lock(&dev->struct_mutex);
++	if (i915_gem_object_pin(intel_fb->obj, alignment)) {
++		mutex_unlock(&dev->struct_mutex);
+ 		return;
++	}
+ 
+ 	i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1);
++	mutex_unlock(&dev->struct_mutex);
+ 
+ 	Start = obj_priv->gtt_offset;
+ 	Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
+@@ -437,8 +420,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
+ 	intel_wait_for_vblank(dev);
+ 
+ 	if (old_fb) {
++		mutex_lock(&dev->struct_mutex);
+ 		intel_fb = to_intel_framebuffer(old_fb);
+ 		i915_gem_object_unpin(intel_fb->obj);
++		mutex_unlock(&dev->struct_mutex);
+ 	}
+ 
+ 	if (!dev->primary->master)
+@@ -732,7 +717,7 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
+ 	int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
+ 	int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
+ 	int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
+-	int refclk;
++	int refclk, num_outputs = 0;
+ 	intel_clock_t clock;
+ 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;
+ 	bool ok, is_sdvo = false, is_dvo = false;
+@@ -768,9 +753,14 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
+ 			is_crt = true;
+ 			break;
+ 		}
++
++		num_outputs++;
+ 	}
+ 
+-	if (IS_I9XX(dev)) {
++	if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
++		refclk = dev_priv->lvds_ssc_freq * 1000;
++		DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
++	} else if (IS_I9XX(dev)) {
+ 		refclk = 96000;
+ 	} else {
+ 		refclk = 48000;
+@@ -782,6 +772,9 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
  		return;
  	}
  
@@ -454,6 +647,96 @@
  	fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  
  	dpll = DPLL_VGA_MODE_DIS;
+@@ -829,11 +822,14 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
+ 		}
+ 	}
+ 
+-	if (is_tv) {
++	if (is_sdvo && is_tv)
++		dpll |= PLL_REF_INPUT_TVCLKINBC;
++	else if (is_tv)
+ 		/* XXX: just matching BIOS for now */
+-/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
++		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
+ 		dpll |= 3;
+-	}
++	else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
++		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
+ 	else
+ 		dpll |= PLL_REF_INPUT_DREFCLK;
+ 
+@@ -1023,18 +1019,19 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
+ 	}
+ 
+ 	/* we only need to pin inside GTT if cursor is non-phy */
++	mutex_lock(&dev->struct_mutex);
+ 	if (!dev_priv->cursor_needs_physical) {
+ 		ret = i915_gem_object_pin(bo, PAGE_SIZE);
+ 		if (ret) {
+ 			DRM_ERROR("failed to pin cursor bo\n");
+-			goto fail;
++			goto fail_locked;
+ 		}
+ 		addr = obj_priv->gtt_offset;
+ 	} else {
+ 		ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
+ 		if (ret) {
+ 			DRM_ERROR("failed to attach phys object\n");
+-			goto fail;
++			goto fail_locked;
+ 		}
+ 		addr = obj_priv->phys_obj->handle->busaddr;
+ 	}
+@@ -1054,10 +1051,9 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
+ 				i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
+ 		} else
+ 			i915_gem_object_unpin(intel_crtc->cursor_bo);
+-		mutex_lock(&dev->struct_mutex);
+ 		drm_gem_object_unreference(intel_crtc->cursor_bo);
+-		mutex_unlock(&dev->struct_mutex);
+ 	}
++	mutex_unlock(&dev->struct_mutex);
+ 
+ 	intel_crtc->cursor_addr = addr;
+ 	intel_crtc->cursor_bo = bo;
+@@ -1065,6 +1061,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
+ 	return 0;
+ fail:
+ 	mutex_lock(&dev->struct_mutex);
++fail_locked:
+ 	drm_gem_object_unreference(bo);
+ 	mutex_unlock(&dev->struct_mutex);
+ 	return ret;
+@@ -1292,7 +1289,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
+ 		}
+ 
+ 		/* XXX: Handle the 100Mhz refclk */
+-		i9xx_clock(96000, &clock);
++		intel_clock(96000, &clock);
+ 	} else {
+ 		bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
+ 
+@@ -1304,9 +1301,9 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
+ 			if ((dpll & PLL_REF_INPUT_MASK) ==
+ 			    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
+ 				/* XXX: might not be 66MHz */
+-				i8xx_clock(66000, &clock);
++				intel_clock(66000, &clock);
+ 			} else
+-				i8xx_clock(48000, &clock);
++				intel_clock(48000, &clock);
+ 		} else {
+ 			if (dpll & PLL_P1_DIVIDE_BY_TWO)
+ 				clock.p1 = 2;
+@@ -1319,7 +1316,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
+ 			else
+ 				clock.p2 = 2;
+ 
+-			i8xx_clock(48000, &clock);
++			intel_clock(48000, &clock);
+ 		}
+ 	}
+ 
 diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
 index afd1217..0fd76d4 100644
 --- a/drivers/gpu/drm/i915/intel_fb.c


Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.1295
retrieving revision 1.1296
diff -u -r1.1295 -r1.1296
--- kernel.spec	13 Feb 2009 23:24:23 -0000	1.1295
+++ kernel.spec	13 Feb 2009 23:44:29 -0000	1.1296
@@ -1748,6 +1748,9 @@
 %kernel_variant_files -k vmlinux %{with_kdump} kdump
 
 %changelog
+* Fri Feb 13 2009 Kristian Høgsberg <krh at redhat.com>
+- Update drm-intel-next patch with more modesetting fixes.
+
 * Fri Feb 13 2009 David Woodhouse <David.Woodhouse at intel.com>
 - Apply IOMMU write-buffer quirk. (#479996)