rpms/mesa/devel mesa-7.1-nukeglthread-debug.patch, 1.2, 1.3 mesa.spec, 1.224, 1.225 radeon-rewrite.patch, 1.2, 1.3 mesa-7.3-dri-drivers-master.patch, 1.3, NONE

Fri Feb 27 09:42:27 UTC 2009

Author: airlied

Update of /cvs/pkgs/rpms/mesa/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv28605

Modified Files:
	mesa-7.1-nukeglthread-debug.patch mesa.spec 
	radeon-rewrite.patch 
Removed Files:
	mesa-7.3-dri-drivers-master.patch 
Log Message:
* Fri Feb 27 2009 Dave Airlie <airlied at redhat.com> 7.3-8
- reset whole place back to 7.3-6 - bad plan


mesa-7.1-nukeglthread-debug.patch:

Index: mesa-7.1-nukeglthread-debug.patch
===================================================================
RCS file: /cvs/pkgs/rpms/mesa/devel/mesa-7.1-nukeglthread-debug.patch,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -r1.2 -r1.3

--- mesa-7.1-nukeglthread-debug.patch	27 Feb 2009 08:24:31 -0000	1.2
+++ mesa-7.1-nukeglthread-debug.patch	27 Feb 2009 09:41:56 -0000	1.3
@@ -1,8 +1,7 @@
-diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
-index 787c290..be81b65 100644
---- a/src/mesa/drivers/dri/intel/intel_fbo.c
-+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
-@@ -573,11 +573,6 @@ intel_render_texture(GLcontext * ctx,
+diff -up Mesa-7.1/src/mesa/drivers/dri/intel/intel_fbo.c.intel-glthread Mesa-7.1/src/mesa/drivers/dri/intel/intel_fbo.c
+--- Mesa-7.1/src/mesa/drivers/dri/intel/intel_fbo.c.intel-glthread	2008-08-25 10:49:40.000000000 -0400
++++ Mesa-7.1/src/mesa/drivers/dri/intel/intel_fbo.c	2008-08-28 14:26:17.000000000 -0400
+@@ -633,11 +633,6 @@ intel_render_texture(GLcontext * ctx,
         return;
     }
  
@@ -14,3 +13,12 @@
     /* point the renderbufer's region to the texture image region */
     intel_image = intel_texture_image(newImage);
     if (irb->region != intel_image->mt->region) {
+@@ -674,8 +669,6 @@ intel_finish_render_texture(GLcontext * 
+ {
+    struct intel_renderbuffer *irb = intel_renderbuffer(att->Renderbuffer);
+ 
+-   DBG("End render texture (tid %x) tex %u\n", _glthread_GetID(), att->Texture->Name);
+-
+    if (irb) {
+       /* just release the region */
+       intel_region_release(&irb->region);


Index: mesa.spec
===================================================================
RCS file: /cvs/pkgs/rpms/mesa/devel/mesa.spec,v
retrieving revision 1.224
retrieving revision 1.225
diff -u -r1.224 -r1.225
--- mesa.spec	27 Feb 2009 08:24:32 -0000	1.224
+++ mesa.spec	27 Feb 2009 09:41:56 -0000	1.225
@@ -37,7 +37,6 @@
 Source5: http://www.x.org/pub/individual/app/%{xdriinfo}.tar.bz2
 
 Patch0: mesa-7.1-osmesa-version.patch
-Patch1: mesa-7.3-dri-drivers-master.patch
 Patch2: mesa-7.1-nukeglthread-debug.patch
 Patch3: mesa-no-mach64.patch
 
@@ -47,6 +46,7 @@
 Patch9: intel-revert-vbl.patch
 
 Patch12: mesa-7.1-disable-intel-classic-warn.patch
+Patch13: mesa-7.3-965-texture-size.patch
 
 BuildRequires: pkgconfig autoconf automake
 %if %{with_dri}
@@ -168,13 +168,13 @@
 %setup -q -n Mesa-%{version}%{?snapshot} -b0 -b1 -b2 -b5
 #%setup -q -n mesa-%{gitdate} -b2 -b5
 %patch0 -p1 -b .osmesa
-%patch1 -p1 -b .mesa-dri-master
 %patch2 -p1 -b .intel-glthread
 %patch3 -p0 -b .no-mach64
 %patch5 -p1 -b .radeon-rewrite
 %patch7 -p1 -b .dricore
 %patch9 -p1 -b .intel-vbl
 %patch12 -p1 -b .intel-nowarn
+%patch13 -p1 -b .965-texture
 
 # Hack the demos to use installed data files
 sed -i 's,../images,%{_libdir}/mesa-demos-data,' progs/demos/*.c
@@ -424,10 +424,7 @@
 
 %changelog
 * Fri Feb 27 2009 Dave Airlie <airlied at redhat.com> 7.3-8
-- mesa-7.3-dri-drivers-master.patch - pull in DRI drivers from master
-
-* Fri Feb 27 2009 Dave Airlie <airlied at redhat.com> 7.3-7
-- radeon-dri2-fixes.patch: add some fixes to radeon code
+- reset whole place back to 7.3-6 - bad plan
 
 * Tue Feb 24 2009 Adam Jackson <ajax at redhat.com> 7.3-6
 - Fix text relocations in OSMesa build. (#475146)

radeon-rewrite.patch:

View full diff with command:
/usr/bin/cvs -f diff  -kk -u -N -r 1.2 -r 1.3 radeon-rewrite.patch
Index: radeon-rewrite.patch
===================================================================
RCS file: /cvs/pkgs/rpms/mesa/devel/radeon-rewrite.patch,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -r1.2 -r1.3
--- radeon-rewrite.patch	27 Feb 2009 08:24:32 -0000	1.2
+++ radeon-rewrite.patch	27 Feb 2009 09:41:56 -0000	1.3
@@ -1,5 +1,5 @@
 diff --git a/configs/autoconf.in b/configs/autoconf.in
-index e034431..98e39bb 100644
+index b352974..d786029 100644
 --- a/configs/autoconf.in
 +++ b/configs/autoconf.in
 @@ -20,6 +20,8 @@ CXXFLAGS = @CPPFLAGS@ @CXXFLAGS@ \
@@ -12,20 +12,10 @@
  # Assembler
  MESA_ASM_SOURCES = @MESA_ASM_SOURCES@
 diff --git a/configure.ac b/configure.ac
-index 2f3f0be..3554982 100644
+index a9a8d5a..ea2992d 100644
 --- a/configure.ac
 +++ b/configure.ac
-@@ -410,6 +410,9 @@ AC_SUBST([GLU_DIRS])
- AC_SUBST([DRIVER_DIRS])
- AC_SUBST([WINDOW_SYSTEM])
- 
-+AC_SUBST([RADEON_CFLAGS])
-+AC_SUBST([RADEON_LDFLAGS])
-+
- dnl
- dnl User supplied program configuration
- dnl
-@@ -583,6 +585,13 @@ dri)
+@@ -573,6 +575,13 @@ dri)
      GL_PC_REQ_PRIV="libdrm >= $LIBDRM_REQUIRED dri2proto >= $DRI2PROTO_REQUIRED"
      DRI_PC_REQ_PRIV="libdrm >= $LIBDRM_REQUIRED"
  
@@ -39,6 +29,15 @@
      # find the DRI deps for libGL
      if test "$x11_pkgconfig" = yes; then
          # add xcb modules if necessary
+@@ -578,6 +585,8 @@ AC_SUBST([GL_PC_REQ_PRIV])
+ AC_SUBST([GL_PC_LIB_PRIV])
+ AC_SUBST([GL_PC_CFLAGS])
+ AC_SUBST([DRI_PC_REQ_PRIV])
++AC_SUBST([RADEON_CFLAGS])
++AC_SUBST([RADEON_LDFLAGS])
+ 
+ dnl
+ dnl More X11 setup
 diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile
 index e9144ac..e593ed9 100644
 --- a/src/mesa/drivers/dri/r200/Makefile
@@ -739,23 +738,17 @@
 index c067515..a744469 100644
 --- a/src/mesa/drivers/dri/r200/r200_context.c
 +++ b/src/mesa/drivers/dri/r200/r200_context.c
-@@ -54,7 +54,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+@@ -52,9 +52,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DE
+ #include "drivers/common/driverfuncs.h"
+ 
  #include "r200_context.h"
++#include "radeon_span.h"
  #include "r200_ioctl.h"
  #include "r200_state.h"
 -#include "r200_span.h"
  #include "r200_pixel.h"
  #include "r200_tex.h"
  #include "r200_swtcl.h"
-@@ -62,6 +61,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- #include "r200_maos.h"
- #include "r200_vertprog.h"
- 
-+#include "radeon_span.h"
-+
- #define need_GL_ARB_vertex_program
- #define need_GL_ATI_fragment_shader
- #define need_GL_EXT_blend_minmax
 @@ -78,9 +79,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  #include "vblank.h"
  #include "utils.h"
@@ -4962,7 +4955,7 @@
  
  extern void r200LightingSpaceChange( GLcontext *ctx );
 diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
-index 9e4677e..b40690e 100644
+index 9e4677e..013064d 100644
 --- a/src/mesa/drivers/dri/r200/r200_state_init.c
 +++ b/src/mesa/drivers/dri/r200/r200_state_init.c
 @@ -43,6 +43,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -5127,7 +5120,7 @@
     return h.i;
  }
  
-@@ -127,96 +243,388 @@ static int cmdscl2( int offset, int stride, int count )
+@@ -127,71 +243,353 @@ static int cmdscl2( int offset, int stride, int count )
  }
  
  #define CHECK( NM, FLAG )				\
@@ -5254,7 +5247,6 @@
 +   BATCH_LOCALS(&r200->radeon);
 +   uint32_t dwords = atom->cmd_size;
 +
-+   dwords += 6;
 +   BEGIN_BATCH_NO_AUTOSTATE(dwords);
 +   OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
 +   OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
@@ -5267,7 +5259,6 @@
 +   BATCH_LOCALS(&r200->radeon);
 +   uint32_t dwords = atom->cmd_size;
 +
-+   dwords += 8;
 +   BEGIN_BATCH_NO_AUTOSTATE(dwords);
 +   OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
 +   OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
@@ -5280,7 +5271,6 @@
 +   BATCH_LOCALS(&r200->radeon);
 +   uint32_t dwords = atom->cmd_size;
 +
-+   dwords += 8;
 +   BEGIN_BATCH_NO_AUTOSTATE(dwords);
 +   OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
 +   OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
@@ -5293,7 +5283,6 @@
 +   BATCH_LOCALS(&r200->radeon);
 +   uint32_t dwords = atom->cmd_size;
 +
-+   dwords += 4;
 +   BEGIN_BATCH_NO_AUTOSTATE(dwords);
 +   OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
 +   END_BATCH();
@@ -5305,7 +5294,6 @@
 +   BATCH_LOCALS(&r200->radeon);
 +   uint32_t dwords = atom->cmd_size;
 +
-+   dwords += 2;
 +   BEGIN_BATCH_NO_AUTOSTATE(dwords);
 +   OUT_SCL(atom->cmd[0], atom->cmd+1);
 +   END_BATCH();
@@ -5318,7 +5306,6 @@
 +   BATCH_LOCALS(&r200->radeon);
 +   uint32_t dwords = atom->cmd_size;
 +
-+   dwords += 4;
 +   BEGIN_BATCH_NO_AUTOSTATE(dwords);
 +   OUT_VEC(atom->cmd[0], atom->cmd+1);
 +   END_BATCH();
@@ -5330,47 +5317,36 @@
 +   BATCH_LOCALS(&r200->radeon);
 +   struct radeon_renderbuffer *rrb;
 +   uint32_t cbpitch;
-+   uint32_t zbpitch, depth_fmt;
++   uint32_t zbpitch;
 +   uint32_t dwords = atom->cmd_size;
++   GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate;
 +
 +   /* output the first 7 bytes of context */
 +   BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2);
 +   OUT_BATCH_TABLE(atom->cmd, 5);
 +
-+   rrb = radeon_get_depthbuffer(&r200->radeon);
++   rrb = r200->radeon.state.depth.rrb;
 +   if (!rrb) {
 +     OUT_BATCH(0);
 +     OUT_BATCH(0);
 +   } else {
 +     zbpitch = (rrb->pitch / rrb->cpp);
-+     if (r200->using_hyperz)
-+       zbpitch |= RADEON_DEPTH_HYPERZ;
 +     OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 +     OUT_BATCH(zbpitch);
-+     if (rrb->cpp == 4) 
-+       depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 
-+     else 
-+       depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 
-+     atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; 
-+     atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; 
 +   }
 +     
 +   OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
 +   OUT_BATCH(atom->cmd[CTX_CMD_1]);
 +   OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
++   OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
 +
-+   rrb = radeon_get_colorbuffer(&r200->radeon);
++   rrb = r200->radeon.state.color.rrb;
++   if (r200->radeon.radeonScreen->driScreen->dri2.enabled) {
++      rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
++   }
 +   if (!rrb || !rrb->bo) {
-+     OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
 +     OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
 +   } else {
-+     atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); 
-+     if (rrb->cpp == 4) 
-+       atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; 
-+     else 
-+       atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; 
-+ 
[...2632 lines suppressed...]
        fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
-@@ -190,37 +555,37 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -190,37 +534,44 @@ void radeonInitState( radeonContextPtr rmesa )
     }
  
     /* Only have hw stencil when depth buffer is 24 bits deep */
@@ -30628,10 +30423,15 @@
 -   if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
 -      drawOffset = rmesa->radeonScreen->backOffset;
 -      drawPitch  = rmesa->radeonScreen->backPitch;
--   } else {
++   if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) {
++      drawOffset = rmesa->radeon.radeonScreen->backOffset;
++      drawPitch  = rmesa->radeon.radeonScreen->backPitch;
+    } else {
 -      drawOffset = rmesa->radeonScreen->frontOffset;
 -      drawPitch  = rmesa->radeonScreen->frontPitch;
--   }
++      drawOffset = rmesa->radeon.radeonScreen->frontOffset;
++      drawPitch  = rmesa->radeon.radeonScreen->frontPitch;
+    }
  
 -   rmesa->hw.max_state_size = 0;
 +   rmesa->radeon.hw.max_state_size = 0;
@@ -30670,7 +30470,7 @@
     ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
     ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
     ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
-@@ -233,20 +598,25 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -233,20 +584,25 @@ void radeonInitState( radeonContextPtr rmesa )
     ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 );
     ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 );
     ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
@@ -30706,7 +30506,7 @@
     }
     ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
     ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
-@@ -268,43 +638,43 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -268,43 +624,43 @@ void radeonInitState( radeonContextPtr rmesa )
     ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
     ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
     ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
@@ -30781,51 +30581,20 @@
     rmesa->hw.grd.cmd[GRD_CMD_0] = 
        cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
     rmesa->hw.fog.cmd[FOG_CMD_0] = 
-@@ -331,6 +701,22 @@ void radeonInitState( radeonContextPtr rmesa )
- 	 cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
-    }
- 
-+   if (rmesa->radeon.radeonScreen->kernel_mm) {
-+      rmesa->hw.grd.emit = scl_emit;
-+      rmesa->hw.fog.emit = vec_emit;
-+      rmesa->hw.glt.emit = vec_emit;
-+      rmesa->hw.eye.emit = vec_emit;
-+      
-+      for (i = 0; i <= 6; i++)
-+	 rmesa->hw.mat[i].emit = vec_emit;
-+
-+      for (i = 0; i < 8; i++)
-+	 rmesa->hw.lit[i].emit = lit_emit;
-+
-+      for (i = 0; i < 6; i++)
-+	 rmesa->hw.ucp[i].emit = vec_emit;
-+   }
-+
-    rmesa->last_ReallyEnabled = -1;
- 
-    /* Initial Harware state:
-@@ -352,19 +738,7 @@ void radeonInitState( radeonContextPtr rmesa )
- 					    RADEON_SRC_BLEND_GL_ONE |
+@@ -353,10 +709,10 @@ void radeonInitState( radeonContextPtr rmesa )
  					    RADEON_DST_BLEND_GL_ZERO );
  
--   rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
+    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
 -      rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation;
--
--   rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = 
++      rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
+ 
+    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = 
 -      ((rmesa->radeonScreen->depthPitch &
--	RADEON_DEPTHPITCH_MASK) |
--       RADEON_DEPTH_ENDIAN_NO_SWAP);
--       
--   if (rmesa->using_hyperz)
--       rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ;
--
--   rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
--					       RADEON_Z_TEST_LESS |
-+   rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS |
- 					       RADEON_STENCIL_TEST_ALWAYS |
- 					       RADEON_STENCIL_FAIL_KEEP |
- 					       RADEON_STENCIL_ZPASS_KEEP |
-@@ -374,7 +748,7 @@ void radeonInitState( radeonContextPtr rmesa )
++      ((rmesa->radeon.radeonScreen->depthPitch &
+ 	RADEON_DEPTHPITCH_MASK) |
+        RADEON_DEPTH_ENDIAN_NO_SWAP);
+        
+@@ -374,7 +730,7 @@ void radeonInitState( radeonContextPtr rmesa )
     if (rmesa->using_hyperz) {
         rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
  						   RADEON_Z_DECOMPRESSION_ENABLE;
@@ -30834,11 +30603,8 @@
  	 /* works for q3, but slight rendering errors with glxgears ? */
  /*	 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
  	 /* need this otherwise get lots of lockups with q3 ??? */
-@@ -386,10 +760,9 @@ void radeonInitState( radeonContextPtr rmesa )
- 				     RADEON_ANTI_ALIAS_NONE);
- 
-    rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
--				       color_fmt |
+@@ -389,7 +745,7 @@ void radeonInitState( radeonContextPtr rmesa )
+ 				       color_fmt |
  				       RADEON_ZBLOCK16);
  
 -   switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) {
@@ -30846,7 +30612,7 @@
     case DRI_CONF_DITHER_XERRORDIFFRESET:
        rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
        break;
-@@ -397,30 +770,17 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -397,19 +753,19 @@ void radeonInitState( radeonContextPtr rmesa )
        rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
        break;
     }
@@ -30866,23 +30632,22 @@
 -      rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
 +      rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
  
--   rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset +
+    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset +
 -					       rmesa->radeonScreen->fbLocation)
--					      & RADEON_COLOROFFSET_MASK);
--
--   rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch &
--					      RADEON_COLORPITCH_MASK) |
--					     RADEON_COLOR_ENDIAN_NO_SWAP);
--
--
--   /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
++					       rmesa->radeon.radeonScreen->fbLocation)
+ 					      & RADEON_COLOROFFSET_MASK);
+ 
+    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch &
+@@ -418,7 +774,7 @@ void radeonInitState( radeonContextPtr rmesa )
+ 
+ 
+    /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
 -   if (rmesa->sarea->tiling_enabled) {
--      rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
--   }
++   if (rmesa->radeon.sarea->tiling_enabled) {
+       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
+    }
  
-    rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
- 				     RADEON_BFACE_SOLID |
-@@ -444,7 +804,7 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -444,7 +800,7 @@ void radeonInitState( radeonContextPtr rmesa )
    					    RADEON_VC_NO_SWAP;
  #endif
  
@@ -30891,7 +30656,7 @@
       rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
     }
  
-@@ -491,8 +851,8 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -491,8 +847,8 @@ void radeonInitState( radeonContextPtr rmesa )
  	   (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
  
        /* Initialize the texture offset to the start of the card texture heap */
@@ -30902,7 +30667,7 @@
  
        rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
        rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =  
-@@ -513,15 +873,15 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -513,15 +869,15 @@ void radeonInitState( radeonContextPtr rmesa )
  
        rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
        rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
@@ -30923,7 +30688,7 @@
     }
  
     /* Can only add ST1 at the time of doing some multitex but can keep
-@@ -613,5 +973,7 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -613,5 +969,7 @@ void radeonInitState( radeonContextPtr rmesa )
     rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
     rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
     
@@ -32658,7 +32423,7 @@
 -   return 0;
 -}
 diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
-index b165205..2b0ebbc 100644
+index 1e2f654..6a34f1e 100644
 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
 +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
 @@ -43,6 +43,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.


--- mesa-7.3-dri-drivers-master.patch DELETED ---


