Sat Jul 4 11:46:52 UTC 2009

Author: chitlesh

Update of /cvs/pkgs/rpms/alliance/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv17590/devel

Modified Files:
	.cvsignore alliance.spec import.log sources 
Added Files:
	alliance-examples-adm2901.patch 
	alliance-examples-go-all-clean.sh alliance-examples-go-all.sh 
	alliance-examples-mipsR3000.patch 
	alliance-tutorials-amd2901.patch 
	alliance-tutorials-go-all-clean.sh 
	alliance-tutorials-go-all.sh 
	alliance-tutorials-place_n_route.patch 
	alliance-tutorials-simulation.patch 
	alliance-tutorials-start.patch 
	alliance-tutorials-synthesis.patch 
Log Message:
fixed documentation and broken examples

alliance-examples-adm2901.patch:

--- NEW FILE alliance-examples-adm2901.patch ---
diff -Naur alliance-5.0/documentation/alliance-examples/amd2901/amd2901_chip.c test-64/alliance-examples/amd2901/amd2901_chip.c
--- alliance-5.0/documentation/alliance-examples/amd2901/amd2901_chip.c	2004-05-23 20:55:16.000000000 +0200
+++ test-64/alliance-examples/amd2901/amd2901_chip.c	2009-06-14 02:35:45.000000000 +0200
@@ -1,5 +1,5 @@
 #include <genlib.h>
-#define POWER "vdde","vdd","vsse","vss",0
+#define POWER "vdde","vdd","vsse","vss",NULL
 
 int main ()
  {
@@ -78,7 +78,7 @@
 
 	"vdd => vdd",
 	"vss => vss",
-	0);
+	NULL);
 
   GENLIB_LOINS("pck_sp","p_ck","ck","cki", POWER);
 
@@ -119,13 +119,13 @@
   GENLIB_LOINS ("piot_sp","p_r3",
 	"ram_o_up","sh_left","ram_i_up","r3","cki", POWER );
 
-  GENLIB_LOINS("pvddick_sp","p_vddick0","ckc","cki","vdde","vdd","vsse","vss",0);
-  GENLIB_LOINS("pvssick_sp","p_vssick0","ckc","cki","vdde","vdd","vsse","vss",0);
+  GENLIB_LOINS("pvddick_sp","p_vddick0","ckc","cki","vdde","vdd","vsse","vss",NULL);
+  GENLIB_LOINS("pvssick_sp","p_vssick0","ckc","cki","vdde","vdd","vsse","vss",NULL);
 
-  GENLIB_LOINS("pvddeck_sp","p_vddeck0","ckc","cki","vdde","vdd","vsse","vss",0);
-  GENLIB_LOINS("pvddeck_sp","p_vddeck1","ckc","cki","vdde","vdd","vsse","vss",0);
-  GENLIB_LOINS("pvsseck_sp","p_vsseck0","ckc","cki","vdde","vdd","vsse","vss",0);
-  GENLIB_LOINS("pvsseck_sp","p_vsseck1","ckc","cki","vdde","vdd","vsse","vss",0);
+  GENLIB_LOINS("pvddeck_sp","p_vddeck0","ckc","cki","vdde","vdd","vsse","vss",NULL);
+  GENLIB_LOINS("pvddeck_sp","p_vddeck1","ckc","cki","vdde","vdd","vsse","vss",NULL);
+  GENLIB_LOINS("pvsseck_sp","p_vsseck0","ckc","cki","vdde","vdd","vsse","vss",NULL);
+  GENLIB_LOINS("pvsseck_sp","p_vsseck1","ckc","cki","vdde","vdd","vsse","vss",NULL);
 
   GENLIB_SAVE_LOFIG();
 
diff -Naur alliance-5.0/documentation/alliance-examples/amd2901/amd2901_core.c test-64/alliance-examples/amd2901/amd2901_core.c
--- alliance-5.0/documentation/alliance-examples/amd2901/amd2901_core.c	2004-05-23 20:55:16.000000000 +0200
+++ test-64/alliance-examples/amd2901/amd2901_core.c	2009-06-14 02:36:07.000000000 +0200
@@ -109,7 +109,7 @@
        "out_x[3:0] =>     y[3:0]",
 
        "vdd => vdd",
-       "vss => vss", 0);
+       "vss => vss", NULL);
 
 
   /* ***************** Control Instanciation ****************** */
@@ -161,7 +161,7 @@
        "oe => oe",
 
        "vdd => vdd",
-       "vss => vss", 0);
+       "vss => vss", NULL);
 
   GENLIB_PLACE ("amd2901_dpt", "amd2901_dpt", NOSYM, 0, 0);
   GENLIB_DEF_AB (0, 0, 0, 100);


--- NEW FILE alliance-examples-go-all-clean.sh ---
#!/bin/sh

for B in addaccu16 adder4 amd2901 amd2901-vasy digi divcas4 \
    multi16b-reg multi4b multi8 multi8b pgcd sqrt32 sqrt8 \
    mipsR3000 hadamard
do
  if [ -d $B ]
  then echo "----- BENCH $B ----- "
       (cd $B && make clean)
  fi
done


--- NEW FILE alliance-examples-go-all.sh ---
#!/bin/sh

for B in addaccu16 adder4 amd2901 amd2901-vasy digi divcas4 \
    multi16b-reg multi4b multi8 multi8b pgcd sqrt32 sqrt8 \
    mipsR3000 hadamard
do
  if [ -d $B ]
  then echo "----- BENCH $B ----- "
       (cd $B && make clean && make)
  fi
done

alliance-examples-mipsR3000.patch:

--- NEW FILE alliance-examples-mipsR3000.patch ---
diff -Naur alliance-5.0/documentation/alliance-examples/mipsR3000/sce/Makefile test-64/alliance-examples/mipsR3000/sce/Makefile
--- alliance-5.0/documentation/alliance-examples/mipsR3000/sce/Makefile	2004-07-30 02:40:09.000000000 +0200
+++ test-64/alliance-examples/mipsR3000/sce/Makefile	2009-06-14 03:12:56.000000000 +0200
@@ -119,7 +119,7 @@
       LVX = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/lvx
     PROOF = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/proof
      RING = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ring
-    DPGEN = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/genlib
+    DPGEN = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/genlib --keep-exec --verbose
     OCP   = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ocp -v -gnuplot
     OCR   = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ocr
     NERO  = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/nero -V

alliance-tutorials-amd2901.patch:

--- NEW FILE alliance-tutorials-amd2901.patch ---
diff -Naur documentation/tutorials/synthesis/src/amd2901/Makefile tutorials/synthesis/src/amd2901/Makefile
--- documentation/tutorials/synthesis/src/amd2901/Makefile	2002-07-25 14:50:18.000000000 +0200
+++ tutorials/synthesis/src/amd2901/Makefile	2007-07-18 19:34:53.000000000 +0200
@@ -2,17 +2,17 @@
 all: EXAMPLE VAR  CATAL02 res.pat
 
 
-VAR: 
+VAR:
 	MBK_IN_LO=vst;export MBK_IN_LO ;\
-	MBK_CATA_LIB=/asim/alliance/cells/sxlib;export MBK_CATA_LIB
+	MBK_CATA_LIB=$ALLIANCE_TOP/cells/sxlib;export MBK_CATA_LIB
 
 CATAL01:
-	echo amd2901_ctl C >CATAL  
+	echo amd2901_ctl C >CATAL
 	echo amd2901_dpt C >>CATAL
 
 CATAL02:
 	echo amd2901_dpt C >CATAL
-	
+
 EXAMPLE:
 	genlib circuit
 
@@ -38,7 +38,7 @@
 
 res2.pat: amd2901_chip.vst pattern.pat amd2901_core.vst CATAL
 	asimut amd2901_chip pattern res2
-	touch amd2901_chip.vst 
+	touch amd2901_chip.vst
 
 clean :
 	rm -f Makefile-*                 \



--- NEW FILE alliance-tutorials-go-all-clean.sh ---
#!/bin/sh

for B in place_and_route simulation synthesis
do
  if [ -d $B/src ]
  then echo "--- BENCH $B ----"
       (cd $B/src && make clean)
  fi
done


--- NEW FILE alliance-tutorials-go-all.sh ---
#!/bin/sh

for B in place_and_route simulation synthesis
do
  if [ -d $B/src ]
  then echo "--- BENCH $B ----"
       (cd $B/src && make clean && make)
  fi
done

alliance-tutorials-place_n_route.patch:

--- NEW FILE alliance-tutorials-place_n_route.patch ---
diff -Naur alliance-5.0/documentation/tutorials/place_and_route/src/amd2901/amd2901_chip.c test-64/tutorials/place_and_route/src/amd2901/amd2901_chip.c
--- alliance-5.0/documentation/tutorials/place_and_route/src/amd2901/amd2901_chip.c	2002-07-25 14:50:19.000000000 +0200
+++ test-64/tutorials/place_and_route/src/amd2901/amd2901_chip.c	2009-06-14 02:27:03.000000000 +0200
@@ -1,5 +1,5 @@
 #include <genlib.h>
-#define POWER "vdde","vdd","vsse","vss",0
+#define POWER "vdde","vdd","vsse","vss",NULL
 
 int main ()
  {
@@ -78,7 +78,7 @@
 
 	"vdd => vdd",
 	"vss => vss",
-	0);
+	NULL);
 
   GENLIB_LOINS("pck_sp","p_ck","ck","cki", POWER);
 
@@ -119,13 +119,13 @@
   GENLIB_LOINS ("piot_sp","p_r3",
 	"ram_o_up","sh_left","ram_i_up","r3","cki", POWER );
 
-  GENLIB_LOINS("pvddick_sp","p_vddick0","ckc","cki","vdde","vdd","vsse","vss",0);
-  GENLIB_LOINS("pvssick_sp","p_vssick0","ckc","cki","vdde","vdd","vsse","vss",0);
+  GENLIB_LOINS("pvddick_sp","p_vddick0","ckc","cki","vdde","vdd","vsse","vss",NULL);
+  GENLIB_LOINS("pvssick_sp","p_vssick0","ckc","cki","vdde","vdd","vsse","vss",NULL);
 
-  GENLIB_LOINS("pvddeck_sp","p_vddeck0","ckc","cki","vdde","vdd","vsse","vss",0);
-  GENLIB_LOINS("pvddeck_sp","p_vddeck1","ckc","cki","vdde","vdd","vsse","vss",0);
-  GENLIB_LOINS("pvsseck_sp","p_vsseck0","ckc","cki","vdde","vdd","vsse","vss",0);
-  GENLIB_LOINS("pvsseck_sp","p_vsseck1","ckc","cki","vdde","vdd","vsse","vss",0);
+  GENLIB_LOINS("pvddeck_sp","p_vddeck0","ckc","cki","vdde","vdd","vsse","vss",NULL);
+  GENLIB_LOINS("pvddeck_sp","p_vddeck1","ckc","cki","vdde","vdd","vsse","vss",NULL);
+  GENLIB_LOINS("pvsseck_sp","p_vsseck0","ckc","cki","vdde","vdd","vsse","vss",NULL);
+  GENLIB_LOINS("pvsseck_sp","p_vsseck1","ckc","cki","vdde","vdd","vsse","vss",NULL);
 
   GENLIB_SAVE_LOFIG();
 
diff -Naur alliance-5.0/documentation/tutorials/place_and_route/tex/place_and_route.tex test-64/tutorials/place_and_route/tex/place_and_route.tex
--- alliance-5.0/documentation/tutorials/place_and_route/tex/place_and_route.tex	2004-10-16 14:51:56.000000000 +0200
+++ test-64/tutorials/place_and_route/tex/place_and_route.tex	2009-07-04 12:02:23.689711020 +0200
@@ -1,26 +1,17 @@
-%%%%%%%%%%%%%%%%
-% $Id: place_and_route.tex,v 1.5 2004/10/16 12:51:56 fred Exp $
-% $Log: place_and_route.tex,v $
-% Revision 1.5  2004/10/16 12:51:56  fred
-% Erasing the psfig include from the file, changed the font to 10 pt
-% instead of 12 (sparing trees and not being payed by the thickness of
-% my production) and changing font to charter since I got tired of
-% Palatino, sorry Herman!
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\documentclass{article}
+\documentclass[10pt]{article}
 \usepackage[dvips]{graphics}
 \usepackage[english]{babel}
-\usepackage{doublespace}
+\usepackage{setspace}
 \usepackage{epsf}
 \usepackage{fancybox}
-\usepackage{fancyheadings}
+\usepackage{fancyhdr}
 \usepackage{float}
 \usepackage{graphicx}
-\usepackage{here}
-\usepackage{isolatin1}
-\usepackage{charter}
+%\usepackage{here}
+%\usepackage{isolatin1}
+\usepackage{palatino}
 \usepackage{picinpar}
+%\usepackage{psfig}
 \usepackage{rotate}
 \usepackage{subfigure}
 \usepackage{sverb}
@@ -37,7 +28,7 @@
 \setlength{\columnsep}{0.125in}
 \setlength{\columnseprule}{0.5pt}
 \setlength{\footskip}{1cm}
-\setstretch{1.2}
+%\setstretch{1.2}
 
 
 %--------------------------------- styles
@@ -67,7 +58,7 @@
 %--------------------------------- page style --------------------------------
 \pagestyle{fancy} \rhead{Place and route}
 \lhead{PART 3} \rfoot{\thepage} \lfoot{ALLIANCE TUTORIAL} \cfoot{}
-\setlength{\footrulewidth}{0.6pt}
+
 %
 %\begin{figure}[H]\centering
 % \includegraphics[width=8cm,height=8cm]{.eps}

alliance-tutorials-simulation.patch:

--- NEW FILE alliance-tutorials-simulation.patch ---
diff -Naur alliance-5.0/documentation/tutorials/simulation/tex/simulation.tex test-64/tutorials/simulation/tex/simulation.tex
--- alliance-5.0/documentation/tutorials/simulation/tex/simulation.tex	2004-10-16 14:52:05.000000000 +0200
+++ test-64/tutorials/simulation/tex/simulation.tex	2009-07-04 12:18:54.867711418 +0200
@@ -1,27 +1,18 @@
-%%%%%%%%%%%%%%%%
-% $Id: simulation.tex,v 1.5 2004/10/16 12:52:05 fred Exp $
-% $Log: simulation.tex,v $
-% Revision 1.5  2004/10/16 12:52:05  fred
-% Erasing the psfig include from the file, changed the font to 10 pt
-% instead of 12 (sparing trees and not being payed by the thickness of
-% my production) and changing font to charter since I got tired of
-% Palatino, sorry Herman!
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 %--------------------------------- page style --------------------------------
-\documentclass{article}
+\documentclass[10pt]{article}
 \usepackage[dvips]{graphics}
 \usepackage[english]{babel}
-\usepackage{doublespace}
+\usepackage{setspace}
+\usepackage{epsf}
 \usepackage{fancybox}
-\usepackage{fancyheadings}
+\usepackage{fancyhdr}
 \usepackage{float}
 \usepackage{graphicx}
-\usepackage{here}
-\usepackage{isolatin1}
-\usepackage{charter}
+\usepackage[latin1]{inputenc}
+\usepackage{palatino}
 \usepackage{picinpar}
+%\usepackage{psfig}
 \usepackage{rotate}
 \usepackage{subfigure}
 \usepackage{sverb}
@@ -38,7 +29,7 @@
 \setlength{\columnsep}{0.125in}
 \setlength{\columnseprule}{0.5pt}
 \setlength{\footskip}{1cm}
-\setstretch{1}
+%\setstretch{1}
 
 %--------------------------------- styles--------------------------------
 %
@@ -66,7 +57,7 @@
 \rfoot{\thepage}
 \lfoot{ALLIANCE TUTORIAL}
 \cfoot{}
-\setlength{\footrulewidth}{0.6pt}
+%\setlength{\footrulewidth}{0.6pt}
 
 %--------------------------------- page style --------------------------------
 \pagestyle{fancy}
@@ -75,7 +66,7 @@
 \rfoot{\thepage}
 \lfoot{ALLIANCE TUTORIAL}
 \cfoot{}
-\setlength{\footrulewidth}{0.6pt}
+%\setlength{\footrulewidth}{0.6pt}
 
 %---------------------------------- document ---------------------------------
 
@@ -171,7 +162,7 @@
         }
 
 All the files used in this part are located in the \\ 
-\texttt{/tutorial/simulation/src} directory.\\
+\texttt{/usr/share/doc/alliance-doc-5.0//tutorial/simulation/src} directory.\\
 This directory contains two subdirectories and one Makefile : 
 \begin{itemize}
 \item The Makefile allows you to validate automatically the entire simulation part
@@ -626,13 +617,13 @@
 \bf SXLIB }. For the functionality of the various cells and their
 interface, the sxlib man is available. The behavioral
 description of each cell is present in \\
-{\bf /alliance/cells/sxlib }.
+{\bf \$ALLIANCE\_TOP/cells/sxlib }.
 
 You must set the environment variable { \bf MBK\_CATA\_LIB }
 to be able to reach these cells.
 
 \begin{commandline}
- > MBK_CATA_LIB=/alliance/cells/sxlib
+ > MBK_CATA_LIB=\$ALLIANCE\_TOP/cells/sxlib
  > export MBK_CATA_LIB
 \end{commandline}
 

alliance-tutorials-start.patch:

--- NEW FILE alliance-tutorials-start.patch ---
diff -Naur alliance-5.0/documentation/tutorials/start/start.tex test-64/tutorials/start/start.tex
--- alliance-5.0/documentation/tutorials/start/start.tex	2004-10-16 14:52:13.000000000 +0200
+++ test-64/tutorials/start/start.tex	2009-07-04 12:17:35.389714653 +0200
@@ -5,16 +5,16 @@
 % Version for Alliance releases 2.0 and up by Frederic Petrot
 % Modified by czo for Alliance release 4.0 (01/2000)
 % TODO : no fully working, needs some adjustements
-% $Id: start.tex,v 1.5 2004/10/16 12:52:13 fred Exp $
+% $Id: start.tex,v 1.4 2004/07/15 21:40:02 ludo Exp $
 %
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \documentclass{article}
-\usepackage{charter,doublespace,here,fancybox}
+\usepackage{palatino,setspace,fancybox}
 \textwidth 15cm
 \textheight 23cm
 \oddsidemargin  +0.75cm
 \evensidemargin -0.75cm
-\setstretch{1.2}
+%\setstretch{1.2}
 %%%%%%%%%%%%%%%
 % Setting the width of the verbatim parts according to 80 tt chars
 % Since it is tt, any char is fine
@@ -116,13 +116,13 @@
 try to run the following command :
 
 \begin{phraseverbatim}
-~alp/addaccu %-) source /alliance/etc/alc_env.csh
+~alp/addaccu %-) source /etc/profile.d/alc_env.csh
 \end{phraseverbatim}
 
 Otherwise, if you run a \texttt{sh-like} shell, try to run the following 
 command :
 \begin{phraseverbatim}
-~alp/addaccu %-) source /alliance/alc_env.sh
+~alp/addaccu %-) source /etc/profile.d/alc_env.sh
 \end{phraseverbatim}
 \\
 Before we proceed to the tutorial, you must make sure that the
@@ -151,13 +151,13 @@
 MBK_CATAL_NAME=CATAL
 MBK_SCALE_X=100
 MBK_VSS=vss
-MBK_CATA_LIB=.:/alliance/cells/sxlib:/alliance/cells/padlib
+MBK_CATA_LIB=.:\$ALLIANCE\_TOP/cells/sxlib:\$ALLIANCE\_TOP/cells/padlib
 MBK_WORK_LIB=.
 MBK_VDD=vdd
 MBK_C4_LIB=./cellsC4
 MBK_IN_LO=vst
 MBK_IN_PH=ap
-MBK_TARGET_LIB=/alliance/cells/sxlib
+MBK_TARGET_LIB=\$ALLIANCE\_TOP/cells/sxlib
 MBK_OUT_LO=vst
 \end{framedverbatim}
 \caption{\label{mbk} \texttt{MBK} environment variables.}

alliance-tutorials-synthesis.patch:

--- NEW FILE alliance-tutorials-synthesis.patch ---
diff -Naur alliance-5.0/documentation/tutorials/synthesis/src/amd2901/amd2901_chip.c test-64/tutorials/synthesis/src/amd2901/amd2901_chip.c
--- alliance-5.0/documentation/tutorials/synthesis/src/amd2901/amd2901_chip.c	2002-07-25 14:50:18.000000000 +0200
+++ test-64/tutorials/synthesis/src/amd2901/amd2901_chip.c	2009-06-14 00:31:18.000000000 +0200
@@ -78,7 +78,7 @@
 
 	"vdd => vdd",
 	"vss => vss",
-	0);
+	NULL);
 
   GENLIB_LOINS("pck_sp","p_ck","ck","cki", POWER);
 
@@ -119,13 +119,13 @@
   GENLIB_LOINS ("piot_sp","p_r3",
 	"ram_o_up","sh_left","ram_i_up","r3","cki", POWER );
 
-  GENLIB_LOINS("pvddick_sp","p_vddick0","ckc","cki","vdde","vdd","vsse","vss",0);
-  GENLIB_LOINS("pvssick_sp","p_vssick0","ckc","cki","vdde","vdd","vsse","vss",0);
+  GENLIB_LOINS("pvddick_sp","p_vddick0","ckc","cki","vdde","vdd","vsse","vss",NULL);
+  GENLIB_LOINS("pvssick_sp","p_vssick0","ckc","cki","vdde","vdd","vsse","vss",NULL);
 
-  GENLIB_LOINS("pvddeck_sp","p_vddeck0","ckc","cki","vdde","vdd","vsse","vss",0);
-  GENLIB_LOINS("pvddeck_sp","p_vddeck1","ckc","cki","vdde","vdd","vsse","vss",0);
-  GENLIB_LOINS("pvsseck_sp","p_vsseck0","ckc","cki","vdde","vdd","vsse","vss",0);
-  GENLIB_LOINS("pvsseck_sp","p_vsseck1","ckc","cki","vdde","vdd","vsse","vss",0);
+  GENLIB_LOINS("pvddeck_sp","p_vddeck0","ckc","cki","vdde","vdd","vsse","vss",NULL);
+  GENLIB_LOINS("pvddeck_sp","p_vddeck1","ckc","cki","vdde","vdd","vsse","vss",NULL);
+  GENLIB_LOINS("pvsseck_sp","p_vsseck0","ckc","cki","vdde","vdd","vsse","vss",NULL);
+  GENLIB_LOINS("pvsseck_sp","p_vsseck1","ckc","cki","vdde","vdd","vsse","vss",NULL);
 
   GENLIB_SAVE_LOFIG();
 
diff -Naur alliance-5.0/documentation/tutorials/synthesis/src/digicode/log test-64/tutorials/synthesis/src/digicode/log
--- alliance-5.0/documentation/tutorials/synthesis/src/digicode/log	1970-01-01 01:00:00.000000000 +0100
+++ test-64/tutorials/synthesis/src/digicode/log	2009-06-14 12:57:45.000000000 +0200
@@ -0,0 +1,91 @@
+==32653== Memcheck, a memory error detector.
+==32653== Copyright (C) 2002-2006, and GNU GPL'd, by Julian Seward et al.
+==32653== Using LibVEX rev 1658, a library for dynamic binary translation.
+==32653== Copyright (C) 2004-2006, and GNU GPL'd, by OpenWorks LLP.
+==32653== Using valgrind-3.2.1, a dynamic binary instrumentation framework.
+==32653== Copyright (C) 2000-2006, and GNU GPL'd, by Julian Seward et al.
+==32653== For more details, rerun with: -v
+==32653== 
+Mapping Warning: Cell 'halfadder_x4' isn't supported
+Mapping Warning: Cell 'halfadder_x2' isn't supported
+Mapping Warning: Cell 'fulladder_x4' isn't supported
+Mapping Warning: Cell 'fulladder_x2' isn't supported
+
+                  @@@@@@@                             @@@@ @  
+                    @@   @@                         @@    @@  
+                    @@    @@                       @@      @  
+                    @@    @@     @@@       @@@    @@          
+                    @@   @@    @@   @@   @@   @@  @@          
+                    @@@@@@    @@     @@ @@     @@ @@     @@@@@
+                    @@    @@  @@     @@ @@     @@ @@     @ @@ 
+                    @@     @@ @@     @@ @@     @@ @@    @  @@ 
+                    @@     @@ @@     @@ @@     @@  @@      @@ 
+                    @@    @@   @@   @@   @@   @@    @@    @@  
+                  @@@@@@@@       @@@       @@@        @@@@    
+
+                         Binding and Optimizing On Gates
+
+                 Alliance CAD System 5.0, boog 5.0 [2003/01/09]
+                 Copyright (c) 2000-2009,        ASIM/LIP6/UPMC
+                 Author(s):                     François Donnet
+                 E-mail        :    alliance-users at asim.lip6.fr
+
+        MBK_VDD        : vdd
+        MBK_VSS        : vss
+        MBK_IN_LO      : vst
+        MBK_OUT_LO     : vst
+        MBK_WORK_LIB   : .
+        MBK_TARGET_LIB : /users/cao/ludo/chaos/alliance/distrib-64/cells/sxlib
+
+Reading default parameter...
+50% area - 50% delay optimization
+Reading file 'digicoder_b.vbe'...
+Controlling file 'digicoder_b.vbe'...
+Reading lib '/users/cao/ludo/chaos/alliance/distrib-64/cells/sxlib'...
+Controlling lib '/users/cao/ludo/chaos/alliance/distrib-64/cells/sxlib'...
+Preparing file 'digicoder_b.vbe'...
+Capacitances on file 'digicoder_b.vbe'...
+Unflattening file 'digicoder_b.vbe'...
+Mapping file 'digicoder_b.vbe'...
+Saving file 'digicoder_b.vst'...
+Quick estimated critical path (no warranty)...1866 ps from 'i 3' to 'digicode_ep 2'
+Quick estimated area (with over-cell routing)...93500 lambda²
+Details...
+	inv_x2: 12
+	a2_x2: 7
+	na2_x1: 7
+	o2_x2: 6
+	na3_x1: 5
+	no2_x1: 5
+	on12_x1: 4
+	sff1_x4: 3
+	an12_x1: 3
+	nao22_x1: 3
+	no4_x1: 3
+	noa22_x1: 2
+	no3_x1: 2
+	a3_x2: 2
+	o3_x2: 2
+	zero_x0: 1
+	buf_x2: 1
+	oa22_x2: 1
+	xr2_x1: 1
+	a4_x2: 1
+	Total: 71
+Saving critical path in xsch color file 'digicoder_b.xsc'...
+End of boog...
+
+==32653== 
+==32653== ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 5 from 1)
+==32653== malloc/free: in use at exit: 9,263,779 bytes in 17,753 blocks.
+==32653== malloc/free: 18,632 allocs, 879 frees, 9,622,816 bytes allocated.
+==32653== For counts of detected errors, rerun with: -v
+==32653== searching for pointers to 17,753 not-freed blocks.
+==32653== checked 4,796,752 bytes.
+==32653== 
+==32653== LEAK SUMMARY:
+==32653==    definitely lost: 230,722 bytes in 5,658 blocks.
+==32653==      possibly lost: 329,120 bytes in 18 blocks.
+==32653==    still reachable: 8,703,937 bytes in 12,077 blocks.
+==32653==         suppressed: 0 bytes in 0 blocks.
+==32653== Use --leak-check=full to see details of leaked memory.
diff -Naur alliance-5.0/documentation/tutorials/synthesis/tex/synthesis.tex test-64/tutorials/synthesis/tex/synthesis.tex
--- alliance-5.0/documentation/tutorials/synthesis/tex/synthesis.tex	2004-10-16 14:52:17.000000000 +0200
+++ test-64/tutorials/synthesis/tex/synthesis.tex	2009-07-04 12:26:03.345711622 +0200
@@ -1,25 +1,16 @@
-%%%%%%%%%%%%%%%%
-% $Id: synthesis.tex,v 1.4 2004/10/16 12:52:17 fred Exp $
-% $Log: synthesis.tex,v $
-% Revision 1.4  2004/10/16 12:52:17  fred
-% Erasing the psfig include from the file, changed the font to 10 pt
-% instead of 12 (sparing trees and not being payed by the thickness of
-% my production) and changing font to charter since I got tired of
-% Palatino, sorry Herman!
-%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\documentclass{article}
+\documentclass[10pt]{article}
 \usepackage[dvips]{graphics}
 \usepackage[english]{babel}
-\usepackage{doublespace}
+\usepackage{setspace}
+\usepackage{epsf}
 \usepackage{fancybox}
-\usepackage{fancyheadings}
+\usepackage{fancyhdr}
 \usepackage{float}
 \usepackage{graphicx}
-\usepackage{here}
-\usepackage{isolatin1}
-\usepackage{charter}
+\usepackage[latin1]{inputenc}
+\usepackage{palatino}
 \usepackage{picinpar}
+%\usepackage{psfig}
 \usepackage{rotate}
 \usepackage{subfigure}
 \usepackage{sverb}
@@ -36,7 +27,7 @@
 \setlength{\columnsep}{0.125in}
 \setlength{\columnseprule}{0.5pt}
 \setlength{\footskip}{1cm}
-\setstretch{1}
+%\setstretch{1}
 
 
 %--------------------------------- styles
@@ -69,7 +60,7 @@
 \rfoot{\thepage}
 \lfoot{ALLIANCE TUTORIAL}
 \cfoot{}
-\setlength{\footrulewidth}{0.6pt}
+%\setlength{\footrulewidth}{0.6pt}
 
 %---------------------------------- document ---------------------------------
 \begin{document}
@@ -220,7 +211,7 @@
         }
 
 All the files used in this part are located under \\
-\texttt{/tutorial/synthesis/src} directory.\\
+\texttt{/usr/share/doc/alliance-doc-5.0/tutorials/synthesis/src} directory.\\
 This directory contents four subdirectories and one Makefile :
 \begin{itemize}\itemsep=-.8ex
 
@@ -802,9 +793,8 @@
 
 We break up Amd2901 into 2 blocks: %la partie cont\^ole qui regroupe la ``glu'' logique et la partie op\'erative (chemin de donn\'ees).%
 \begin{figure}[H]\center
-\leavevmode
-\includegraphics[width=10cm]{bloc}
-\caption{Amd2901 Organization  \label{bloc}}
+\leavevmode \epsfxsize=10cm \epsffile{bloc.eps} \caption{Amd2901
+Organization  \label{bloc}}
 \end{figure}
 
 
@@ -819,7 +809,8 @@
 We will use the following hierarchical description:
 \begin{figure}[H]\center
 \leavevmode
-\includegraphics[width=10cm]{hier}
+\epsfxsize=10cm
+\epsffile{hier.eps}
 \caption{Hierarchy \label{hier}}
 \end{figure}
 
@@ -862,7 +853,8 @@
 
 \begin{figure}[H]\center
 \leavevmode
-\includegraphics[width=10cm]{exemple1}
+\epsfxsize=10cm
+\epsffile{exemple1.eps}
 \end{figure}
 
 The equivalent { \bf genlib } file is as follows:
@@ -998,12 +990,13 @@
 
 \begin{figure}[H]\center
 \leavevmode
-\includegraphics[width=10cm]{exemple2}
+\epsfxsize=10cm
+\epsffile{exemple2.eps}
 \end{figure}
 
 Here the corresponding data-path structure :
-\begin{figure}[H]\center \leavevmode
-\includegraphics[width=10cm]{datap}
+\begin{figure}[H]\center \leavevmode \epsfxsize=10cm
+\epsffile{datap.eps}
 \end{figure}
 
 Each gate occupies a column, a column making it possible to treat
@@ -1232,39 +1225,47 @@
 
 \begin{figure}[H]\center
 \leavevmode
-\includegraphics[width=12cm]{ctl-mrs-1}
+\epsfxsize=12cm
+\epsffile{ctl-mrs-1.eps}
 \end{figure}
 \begin{figure}[H]\center
 \leavevmode
-\includegraphics[width=12cm]{ctl-alu-1}
+\epsfxsize=12cm
+\epsffile{ctl-alu-1.eps}
 \end{figure}
 \begin{figure}[H]\center
 \leavevmode
-\includegraphics[width=12cm]{ctl-wen-1}
+\epsfxsize=12cm
+\epsffile{ctl-wen-1.eps}
 \end{figure}
 \begin{figure}[H]\center
 \leavevmode
-\includegraphics[width=10cm]{dpt-all-1}
+\epsfxsize=10cm
+\epsffile{dpt-all-1.eps}
 \end{figure}
 
 \begin{figure}[H]\center
 \leavevmode
-\includegraphics[width=12cm]{dpt-alu-1}
+\epsfxsize=12cm
+\epsffile{dpt-alu-1.eps}
 \end{figure}
 
 \begin{figure}[H]\center
 \leavevmode
-\includegraphics[width=12cm]{ctldecode}
+\epsfxsize=12cm
+\epsffile{ctldecode.eps}
 \end{figure}
 
 \begin{figure}[H]\center
 \leavevmode
-\includegraphics[width=12cm]{ctldecodebw}
+\epsfxsize=12cm
+\epsffile{ctldecodebw.eps}
 \end{figure}
 
 \begin{figure}[H]\center
 \leavevmode
-\includegraphics[width=12cm]{dptbanc}
+\epsfxsize=12cm
+\epsffile{dptbanc.eps}
 \end{figure}
 
 \end{document}


Index: .cvsignore
===================================================================
RCS file: /cvs/pkgs/rpms/alliance/devel/.cvsignore,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -p -r1.3 -r1.4
--- .cvsignore	21 Mar 2008 17:11:17 -0000	1.3
+++ .cvsignore	4 Jul 2009 11:46:51 -0000	1.4
@@ -1,2 +1 @@
 alliance-5.0-20070718.tar.gz
-alliance-5.0-tutorials.tar.bz2


Index: alliance.spec
===================================================================
RCS file: /cvs/pkgs/rpms/alliance/devel/alliance.spec,v
retrieving revision 1.21
retrieving revision 1.22
diff -u -p -r1.21 -r1.22
--- alliance.spec	24 Feb 2009 21:02:21 -0000	1.21
+++ alliance.spec	4 Jul 2009 11:46:52 -0000	1.22
@@ -4,8 +4,8 @@
 
 Name:          alliance
 Version:       5.0
-Release:       26.%{snapshot}snap%{?dist}
-Summary:       VLSI EDA System
+Release:       27.%{snapshot}snap%{?dist}
+Summary:       EDA platform for ASIC design
 
 License:       GPLv2
 Group:         Applications/Engineering
@@ -14,12 +14,23 @@ Source:        http://www-asim.lip6.fr/p
 URL:           http://www-asim.lip6.fr/recherche/alliance/
 
 Patch0:        alliance-env.patch
-Patch1:        alliance-examples.patch
 Patch2:        alliance-run.patch
 Patch3:        alliance-perms.patch
 Patch4:        alliance-gcc43.patch
 Patch5:        alliance-generic.patch
 
+# Improving autogeneration of documentation
+Patch6:        alliance-tutorials-place_n_route.patch
+Patch7:        alliance-tutorials-simulation.patch
+Patch8:        alliance-tutorials-start.patch
+Patch9:        alliance-tutorials-synthesis.patch
+
+# Improving robustness of the examples
+Patch10:       alliance-tutorials-amd2901.patch
+Patch11:       alliance-examples.patch
+Patch12:       alliance-examples-adm2901.patch
+Patch13:       alliance-examples-mipsR3000.patch
+
 Source1:       xsch.desktop
 Source2:       dreal.desktop
 Source3:       xpat.desktop
@@ -37,7 +48,10 @@ Source11:      xfsm.png
 Source12:      xpat.png
 Source13:      xsch.png
 
-Source14:      %{name}-5.0-tutorials.tar.bz2
+Source14:      alliance-tutorials-go-all.sh
+Source15:      alliance-tutorials-go-all-clean.sh
+Source16:      alliance-examples-go-all.sh
+Source17:      alliance-examples-go-all-clean.sh
 
 BuildRoot:     %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n)
 BuildRequires: lesstif-devel libXt-devel byacc desktop-file-utils bison
@@ -98,7 +112,9 @@ Architecture dependent files for the All
 Summary:      Alliance VLSI CAD Sytem - Documentations
 Group:        Applications/Engineering
 Requires:     %{name} = %{version}-%{release}
-Requires:     gnuplot
+Requires:     gnuplot 
+BuildRequires:tetex-latex
+
 
 
 %description doc
@@ -116,19 +132,46 @@ sed -i "s|ALLIANCE_TOP|%{prefix}|" *.des
 # removing useless copyrighted (by Cadence) lines from the examples
 # and even in alliance-run
 # https://www-asim.lip6.fr/wws/arc/alliance-users/2007-07/msg00006.html
-%patch1 -p0 -b .examples
+
 %patch2 -p0 -b .run
 # fixing permissions
 %patch3 -p0 -b .perms
 
+%patch4 -p1 -b .include
+%patch5 -p0 -b .generic
 
-### 2008 March: TexLive introduction to Rawhide
+# ------------------------------------------------------------------------------
+# Description : 2008 March : TexLive introduction to Rawhide
 sed -i "s|tutorials||" documentation/Makefile.in
-tar -xvf %{SOURCE14}
-
+%patch6  -p1 -b .doc
+%patch7  -p1 -b .doc
+%patch8  -p1 -b .doc
+%patch9  -p1 -b .doc
+%patch10 -p0 -b .doc
+pushd documentation/tutorials
+    # clean unneccessary files
+    %{__rm} *.pdf
+    # build documentation
+    for folder in place_and_route/tex start simulation/tex synthesis/tex; do
+        pushd $folder
+            %{__make}
+        popd
+        # remove useless directories before %%doc
+        %{__rm} -rf $folder
+    done
+    # Add automated scripts to tutorials
+    %{__install} -pm 755 %{SOURCE14} go-all.sh
+    %{__install} -pm 755 %{SOURCE15} go-all-clean.sh
+    # FEL self test for alliance
+    ./go-all.sh 2>&1 | tee self-test-tutorials.log
+    # clean temporary files
+    ./go-all-clean.sh
+popd
+# ------------------------------------------------------------------------------
 
-%patch4 -p1 -b .include
-%patch5 -p0 -b .generic
+%patch11 -p0 -b .examples
+%patch12 -p1 -b .examples
+%patch13 -p1 -b .examples
 
 # make sure the man pages are UTF-8...
 for nonUTF8 in distrib/doc/alc_origin.1 alcban/man1/alcbanner.1 \
@@ -189,6 +232,17 @@ popd
 %{__rm} -rf %{buildroot}%{prefix}/doc/
 %{__rm} -rf %{buildroot}%{prefix}/examples/
 
+# Add automated scripts to examples
+%{__install} -pm 755 %{SOURCE16} alliance-examples/go-all.sh
+%{__install} -pm 755 %{SOURCE17} alliance-examples/go-all-clean.sh
+
+pushd alliance-examples/
+    # FEL self test for alliance
+    ./go-all.sh 2>&1 | tee self-test-examples.log
+    # clean temporary files
+    ./go-all-clean.sh
+popd
+
 # correcting minor documentation details
 sed -i "s|/bin/zsh|/bin/sh|" doc/alliance-run/bench.zsh
 
@@ -296,10 +350,14 @@ touch --no-create %{_datadir}/icons/hico
 
 
 %changelog
+* Sat Jul 4 2009 Chitlesh Goorah <chitlesh [AT] fedoraproject DOT org> - 5.0-27.20070718snap
+- improved autogeneration of documentation and fixed the examples
+
 * Tue Feb 24 2009 Chitlesh Goorah <chitlesh [AT] fedoraproject DOT org> - 5.0-26.20070718snap
 - fixed build due to new releases of flex and bison
 
-* Mon Feb 23 2009 Fedora Release Engineering <rel-eng at lists.fedoraproject.org> - 5.0-25.20070718snap - Rebuilt for https://fedoraproject.org/wiki/Fedora_11_Mass_Rebuild
+* Mon Feb 23 2009 Fedora Release Engineering <rel-eng at lists.fedoraproject.org> - 5.0-25.20070718snap
+ - Rebuilt for https://fedoraproject.org/wiki/Fedora_11_Mass_Rebuild
 
 * Sun Feb 01 2009 Chitlesh Goorah <chitlesh [AT] fedoraproject DOT org> - 5.0-24.20070718snap
 - Improved VHDL generic implementation


Index: import.log
===================================================================
RCS file: /cvs/pkgs/rpms/alliance/devel/import.log,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -p -r1.3 -r1.4
--- import.log	24 Feb 2009 21:02:21 -0000	1.3
+++ import.log	4 Jul 2009 11:46:52 -0000	1.4
@@ -1,3 +1,4 @@
 alliance-5_0-21_20070718snap_fc9:HEAD:alliance-5.0-21.20070718snap.fc9.src.rpm:1221496180
 alliance-5_0-24_20070718snap_fc10:HEAD:alliance-5.0-24.20070718snap.fc10.src.rpm:1233516213
 alliance-5_0-26_20070718snap_fc10:HEAD:alliance-5.0-26.20070718snap.fc10.src.rpm:1235508896
+alliance-5_0-27_20070718snap_fc11:HEAD:alliance-5.0-27.20070718snap.fc11.src.rpm:1246707806


Index: sources
===================================================================
RCS file: /cvs/pkgs/rpms/alliance/devel/sources,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -p -r1.3 -r1.4
--- sources	21 Mar 2008 17:11:17 -0000	1.3
+++ sources	4 Jul 2009 11:46:52 -0000	1.4
@@ -1,2 +1 @@
 917f4493c09f6f5c49d5a606a5e9bbd8  alliance-5.0-20070718.tar.gz
-32cac3116f85713aec2e1e18379811eb  alliance-5.0-tutorials.tar.bz2


