rpms/mesa/devel mesa.spec, 1.242, 1.243 radeon-rewrite.patch, 1.18, 1.19 sources, 1.34, 1.35

Adam Jackson ajax at fedoraproject.org
Thu Jun 11 17:17:54 UTC 2009 

Author: ajax

Update of /cvs/pkgs/rpms/mesa/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv617

Modified Files:
	mesa.spec radeon-rewrite.patch sources 
Log Message:
* Thu May 21 2009 Adam Jackson <ajax at redhat.com> 7.5-0.15
- mesa-7.5-r300-batch-accounting.patch: Fix cmdbuf sizing (#501312)



Index: mesa.spec
===================================================================
RCS file: /cvs/pkgs/rpms/mesa/devel/mesa.spec,v
retrieving revision 1.242
retrieving revision 1.243
diff -u -p -r1.242 -r1.243
--- mesa.spec	15 Apr 2009 15:14:58 -0000	1.242
+++ mesa.spec	11 Jun 2009 17:17:22 -0000	1.243
@@ -14,13 +14,13 @@
 
 %define manpages gl-manpages-1.0.1
 %define xdriinfo xdriinfo-1.0.2
-%define gitdate 20090322
+%define gitdate 20090428
 #% define snapshot 
 
 Summary: Mesa graphics libraries
 Name: mesa
 Version: 7.5
-Release: 0.10%{?dist}
+Release: 0.15%{?dist}
 License: MIT
 Group: System Environment/Libraries
 URL: http://www.mesa3d.org
@@ -48,7 +48,8 @@ Patch9: intel-revert-vbl.patch
 Patch12: mesa-7.1-disable-intel-classic-warn.patch
 Patch13: mesa-7.5-sparc64.patch
 
-Patch20: mesa-7.5-get-driver-name.patch
+Patch15: radeon-rewrite-emit1clip.patch
+Patch16: mesa-7.5-r300-batch-accounting.patch
 
 BuildRequires: pkgconfig autoconf automake
 %if %{with_dri}
@@ -177,7 +178,8 @@ This package provides some demo applicat
 %patch9 -p1 -b .intel-vbl
 %patch12 -p1 -b .intel-nowarn
 %patch13 -p1 -b .sparc64
-%patch20 -p1 -b .get-driver-name
+%patch15 -p1 -b .fix-clip
+%patch16 -p1 -b .r300-accounting
 
 # Hack the demos to use installed data files
 sed -i 's,../images,%{_libdir}/mesa-demos-data,' progs/demos/*.c
@@ -384,9 +386,11 @@ rm -rf $RPM_BUILD_ROOT
 %{_bindir}/clearspd
 %{_bindir}/copypix
 %{_bindir}/cubemap
+%{_bindir}/dinoshade
 %{_bindir}/drawpix
 %{_bindir}/engine
 %{_bindir}/fbo_firecube
+%{_bindir}/fbotexture
 %{_bindir}/fire
 %{_bindir}/fogcoord
 %{_bindir}/fplight
@@ -397,9 +401,7 @@ rm -rf $RPM_BUILD_ROOT
 %{_bindir}/geartrain
 %{_bindir}/glinfo
 %{_bindir}/gloss
-%{_bindir}/glslnoise
 %{_bindir}/gltestperf
-%{_bindir}/glutfx
 %{_bindir}/ipers
 %{_bindir}/isosurf
 %{_bindir}/lodbias
@@ -407,6 +409,7 @@ rm -rf $RPM_BUILD_ROOT
 %{_bindir}/multiarb
 %{_bindir}/paltex
 %{_bindir}/pointblast
+%{_bindir}/projtex
 %{_bindir}/mesa-rain
 %{_bindir}/ray
 %{_bindir}/readpix
@@ -417,14 +420,11 @@ rm -rf $RPM_BUILD_ROOT
 %{_bindir}/spectex
 %{_bindir}/spriteblast
 %{_bindir}/stex3d
-%{_bindir}/streaming_rect
 %{_bindir}/teapot
 %{_bindir}/terrain
 %{_bindir}/tessdemo
 %{_bindir}/texcyl
-%{_bindir}/texdown
 %{_bindir}/texenv
-%{_bindir}/texobj
 %{_bindir}/textures
 %{_bindir}/trispd
 %{_bindir}/tunnel
@@ -434,6 +434,21 @@ rm -rf $RPM_BUILD_ROOT
 %{_libdir}/mesa-demos-data
 
 %changelog
+* Thu May 21 2009 Adam Jackson <ajax at redhat.com> 7.5-0.15
+- mesa-7.5-r300-batch-accounting.patch: Fix cmdbuf sizing (#501312)
+
+* Tue May 05 2009 Dave Airlie <airlied at redhat.com> 7.5-0.14
+- radeon-rewrite.patch: fixes from upstream for rs690 + r200
+
+* Tue Apr 28 2009 Dave Airlie <airlied at redhat.com> 7.5-0.13
+- radeon fix clip emits
+
+* Tue Apr 28 2009 Dave Airlie <airlied at redhat.com> 7.5-0.12
+- rebase to upstream snapshot + radeon-rewrite
+
+* Thu Apr 16 2009 Dave Airlie <airlied at redhat.com> 7.5-0.11
+- radeon-rewrite-fixes.patch: fix context crash in compiz + r200 fixes
+
 * Tue Apr 14 2009 Adam Jackson <ajax at redhat.com> 7.5-0.10
 - mesa-7.5-get-driver-name.patch: Fix glXGetScreenDriver for DRI2 (#495342)
 

radeon-rewrite.patch:

View full diff with command:
/usr/bin/cvs -f diff  -kk -u -p -N -r 1.18 -r 1.19 radeon-rewrite.patch
Index: radeon-rewrite.patch
===================================================================
RCS file: /cvs/pkgs/rpms/mesa/devel/radeon-rewrite.patch,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -p -r1.18 -r1.19
--- radeon-rewrite.patch	7 Apr 2009 08:57:01 -0000	1.18
+++ radeon-rewrite.patch	11 Jun 2009 17:17:22 -0000	1.19
@@ -12,10 +12,10 @@ index b61d7f3..0f9306d 100644
  # Assembler
  MESA_ASM_SOURCES = @MESA_ASM_SOURCES@
 diff --git a/configure.ac b/configure.ac
-index 46070fd..4164d37 100644
+index 8412cdc..231b7e9 100644
 --- a/configure.ac
 +++ b/configure.ac
-@@ -456,6 +456,8 @@ AC_SUBST([GALLIUM_WINSYS_DRM_DIRS])
+@@ -446,6 +446,8 @@ AC_SUBST([GALLIUM_WINSYS_DRM_DIRS])
  AC_SUBST([GALLIUM_DRIVERS_DIRS])
  AC_SUBST([GALLIUM_AUXILIARY_DIRS])
  AC_SUBST([GALLIUM_STATE_TRACKERS_DIRS])
@@ -24,7 +24,7 @@ index 46070fd..4164d37 100644
  
  dnl
  dnl User supplied program configuration
-@@ -583,6 +585,13 @@ dri)
+@@ -573,6 +575,13 @@ dri)
      GL_PC_REQ_PRIV="libdrm >= $LIBDRM_REQUIRED dri2proto >= $DRI2PROTO_REQUIRED"
      DRI_PC_REQ_PRIV="libdrm >= $LIBDRM_REQUIRED"
  
@@ -38,6 +38,96 @@ index 46070fd..4164d37 100644
      # find the DRI deps for libGL
      if test "$x11_pkgconfig" = yes; then
          # add xcb modules if necessary
+diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c
+index e112720..ae0e61e 100644
+--- a/src/mesa/drivers/dri/common/dri_util.c
++++ b/src/mesa/drivers/dri/common/dri_util.c
+@@ -37,6 +37,9 @@
+ typedef GLboolean ( * PFNGLXGETMSCRATEOMLPROC) (__DRIdrawable *drawable, int32_t *numerator, int32_t *denominator);
+ #endif
+ 
++static void dri_get_drawable(__DRIdrawable *pdp);
++static void dri_put_drawable(__DRIdrawable *pdp);
++
+ /**
+  * This is just a token extension used to signal that the driver
+  * supports setting a read drawable.
+@@ -127,7 +130,7 @@ static int driUnbindContext(__DRIcontext *pcp)
+ 	return GL_FALSE;
+     }
+ 
+-    pdp->refcount--;
++    dri_put_drawable(pdp);
+ 
+     if (prp != pdp) {
+         if (prp->refcount == 0) {
+@@ -135,7 +138,7 @@ static int driUnbindContext(__DRIcontext *pcp)
+ 	    return GL_FALSE;
+ 	}
+ 
+-	prp->refcount--;
++    	dri_put_drawable(prp);
+     }
+ 
+ 
+@@ -170,10 +173,10 @@ static int driBindContext(__DRIcontext *pcp,
+ 	pcp->driReadablePriv = prp;
+ 	if (pdp) {
+ 	    pdp->driContextPriv = pcp;
+-	    pdp->refcount++;
++    	    dri_get_drawable(pdp);
+ 	}
+ 	if ( prp && pdp != prp ) {
+-	    prp->refcount++;
++    	    dri_get_drawable(prp);
+ 	}
+     }
+ 
+@@ -430,7 +433,7 @@ driCreateNewDrawable(__DRIscreen *psp, const __DRIconfig *config,
+ 
+     pdp->loaderPrivate = data;
+     pdp->hHWDrawable = hwDrawable;
+-    pdp->refcount = 0;
++    pdp->refcount = 1;
+     pdp->pStamp = NULL;
+     pdp->lastStamp = 0;
+     pdp->index = 0;
+@@ -483,12 +486,19 @@ dri2CreateNewDrawable(__DRIscreen *screen,
+     return pdraw;
+ }
+ 
+-
+-static void
+-driDestroyDrawable(__DRIdrawable *pdp)
++static void dri_get_drawable(__DRIdrawable *pdp)
++{
++    pdp->refcount++;
++}
++	
++static void dri_put_drawable(__DRIdrawable *pdp)
+ {
+     __DRIscreenPrivate *psp;
+ 
++    pdp->refcount--;
++    if (pdp->refcount)
++	return;
++
+     if (pdp) {
+ 	psp = pdp->driScreenPriv;
+         (*psp->DriverAPI.DestroyBuffer)(pdp);
+@@ -504,6 +514,12 @@ driDestroyDrawable(__DRIdrawable *pdp)
+     }
+ }
+ 
++static void
++driDestroyDrawable(__DRIdrawable *pdp)
++{
++    dri_put_drawable(pdp);
++}
++
+ /*@}*/
+ 
+ 
 diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile
 index e9144ac..6a246ed 100644
 --- a/src/mesa/drivers/dri/r200/Makefile
@@ -125,7 +215,7 @@ index e9144ac..6a246ed 100644
  ##### TARGETS #####
  
 diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
-index e163377..3a11a44 100644
+index e163377..e34ea96 100644
 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c
 +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
 @@ -38,6 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -422,21 +512,21 @@ index e163377..3a11a44 100644
 +   rmesa->radeon.dma.flush = NULL;
 +
 +   elt_used = (elt_used + 2) & ~2;
++
++   nr = elt_used / 2;
  
 -   assert( rmesa->dma.flush == r200FlushElts );
 -   rmesa->dma.flush = NULL;
-+   nr = elt_used / 2;
++   radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
  
 -   /* Cope with odd number of elts:
 -    */
 -   rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2;
 -   dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4;
-+   radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
++   r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
  
 -   cmd[1] |= (dwords - 3) << 16;
 -   cmd[2] |= nr << R200_VF_VERTEX_NUMBER_SHIFT;
-+   r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
-+
 +   radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
 +   rmesa->radeon.tcl.elt_dma_bo = NULL;
  
@@ -455,7 +545,7 @@ index e163377..3a11a44 100644
     GLushort *retval;
  
     if (R200_DEBUG & DEBUG_IOCTL)
-@@ -269,30 +201,25 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
+@@ -269,30 +201,30 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
  
     assert((primitive & R200_VF_PRIM_WALK_IND));
     
@@ -476,6 +566,11 @@ index e163377..3a11a44 100644
 +					  RADEON_GEM_DOMAIN_GTT, 0);
 +   rmesa->radeon.tcl.elt_dma_offset = 0;
 +   rmesa->tcl.elt_used = min_nr * 2;
++
++   radeon_validate_bo(&rmesa->radeon, rmesa->radeon.tcl.elt_dma_bo,
++                      RADEON_GEM_DOMAIN_GTT, 0);
++   if (radeon_revalidate_bos(rmesa->radeon.glCtx) == GL_FALSE)
++      fprintf(stderr,"failure to revalidate BOs - badness\n");
  
 +   radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1);
 +   retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
@@ -500,7 +595,7 @@ index e163377..3a11a44 100644
  
     return retval;
  }
-@@ -300,129 +227,119 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
+@@ -300,129 +232,119 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
  
  
  void r200EmitVertexAOS( r200ContextPtr rmesa,
@@ -4354,7 +4449,7 @@ index bae5644..0000000
 -
 -#endif
 diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c
-index 0eaaaf6..1b9724d 100644
+index 2fcc87c..ebf389e 100644
 --- a/src/mesa/drivers/dri/r200/r200_state.c
 +++ b/src/mesa/drivers/dri/r200/r200_state.c
[...5854 lines suppressed...]
++   OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
++   if (rrb) {
++       OUT_BATCH(((rrb->width - 1) << RADEON_RE_WIDTH_SHIFT) |
++                 ((rrb->height - 1) << RADEON_RE_HEIGHT_SHIFT));
++   } else {
++       OUT_BATCH(0);
++   }
++   END_BATCH();
 +}
 +
 +static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
@@ -33030,7 +36102,7 @@ index 57dc380..174a7e1 100644
     ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
     ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
     ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
-@@ -233,20 +626,29 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -233,20 +637,29 @@ void radeonInitState( radeonContextPtr rmesa )
     ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 );
     ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 );
     ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
@@ -33070,7 +36142,7 @@ index 57dc380..174a7e1 100644
     }
     ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
     ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
-@@ -268,43 +670,43 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -268,43 +681,43 @@ void radeonInitState( radeonContextPtr rmesa )
     ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
     ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
     ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
@@ -33145,7 +36217,7 @@ index 57dc380..174a7e1 100644
     rmesa->hw.grd.cmd[GRD_CMD_0] = 
        cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
     rmesa->hw.fog.cmd[FOG_CMD_0] = 
-@@ -331,6 +733,22 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -331,6 +744,22 @@ void radeonInitState( radeonContextPtr rmesa )
  	 cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
     }
  
@@ -33168,7 +36240,7 @@ index 57dc380..174a7e1 100644
     rmesa->last_ReallyEnabled = -1;
  
     /* Initial Harware state:
-@@ -352,19 +770,7 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -352,19 +781,7 @@ void radeonInitState( radeonContextPtr rmesa )
  					    RADEON_SRC_BLEND_GL_ONE |
  					    RADEON_DST_BLEND_GL_ZERO );
  
@@ -33189,7 +36261,7 @@ index 57dc380..174a7e1 100644
  					       RADEON_STENCIL_TEST_ALWAYS |
  					       RADEON_STENCIL_FAIL_KEEP |
  					       RADEON_STENCIL_ZPASS_KEEP |
-@@ -374,7 +780,7 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -374,7 +791,7 @@ void radeonInitState( radeonContextPtr rmesa )
     if (rmesa->using_hyperz) {
         rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
  						   RADEON_Z_DECOMPRESSION_ENABLE;
@@ -33198,7 +36270,7 @@ index 57dc380..174a7e1 100644
  	 /* works for q3, but slight rendering errors with glxgears ? */
  /*	 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
  	 /* need this otherwise get lots of lockups with q3 ??? */
-@@ -386,10 +792,9 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -386,10 +803,9 @@ void radeonInitState( radeonContextPtr rmesa )
  				     RADEON_ANTI_ALIAS_NONE);
  
     rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
@@ -33210,7 +36282,7 @@ index 57dc380..174a7e1 100644
     case DRI_CONF_DITHER_XERRORDIFFRESET:
        rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
        break;
-@@ -397,31 +802,18 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -397,31 +813,18 @@ void radeonInitState( radeonContextPtr rmesa )
        rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
        break;
     }
@@ -33247,7 +36319,7 @@ index 57dc380..174a7e1 100644
     rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
  				     RADEON_BFACE_SOLID |
  				     RADEON_FFACE_SOLID |
-@@ -444,7 +836,7 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -444,7 +847,7 @@ void radeonInitState( radeonContextPtr rmesa )
    					    RADEON_VC_NO_SWAP;
  #endif
  
@@ -33256,7 +36328,7 @@ index 57dc380..174a7e1 100644
       rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
     }
  
-@@ -491,8 +883,8 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -491,8 +894,8 @@ void radeonInitState( radeonContextPtr rmesa )
  	   (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
  
        /* Initialize the texture offset to the start of the card texture heap */
@@ -33267,7 +36339,7 @@ index 57dc380..174a7e1 100644
  
        rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
        rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =  
-@@ -513,15 +905,15 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -513,15 +916,15 @@ void radeonInitState( radeonContextPtr rmesa )
  
        rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
        rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
@@ -33288,7 +36360,7 @@ index 57dc380..174a7e1 100644
     }
  
     /* Can only add ST1 at the time of doing some multitex but can keep
-@@ -613,5 +1005,7 @@ void radeonInitState( radeonContextPtr rmesa )
+@@ -613,5 +1016,7 @@ void radeonInitState( radeonContextPtr rmesa )
     rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
     rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
     
@@ -33972,7 +37044,7 @@ index 779e9ae..df6708f 100644
  	 if (RADEON_DEBUG & DEBUG_FALLBACKS) 
  	    fprintf(stderr, "Radeon end tcl fallback %s\n",
 diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c
-index b0aec21..21509c6 100644
+index f2b6deb..2549d5c 100644
 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c
 +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c
 @@ -44,6 +44,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -33998,7 +37070,7 @@ index b0aec21..21509c6 100644
        switch ( minf ) {
        case GL_NEAREST:
        case GL_NEAREST_MIPMAP_NEAREST:
-@@ -244,433 +248,13 @@ static void radeonSetTexBorderColor( radeonTexObjPtr t, GLubyte c[4] )
+@@ -249,433 +253,13 @@ static void radeonSetTexBorderColor( radeonTexObjPtr t, const GLfloat color[4] )
     t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
  }
  
@@ -34034,7 +37106,7 @@ index b0aec21..21509c6 100644
 -      radeonSetTexWrap( t, texObj->WrapS, texObj->WrapT );
 -      radeonSetTexMaxAnisotropy( t, texObj->MaxAnisotropy );
 -      radeonSetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
--      radeonSetTexBorderColor( t, texObj->_BorderChan );
+-      radeonSetTexBorderColor( t, texObj->BorderColor );
 -   }
 -
 -   return t;
@@ -34433,7 +37505,7 @@ index b0aec21..21509c6 100644
     GLuint unit = ctx->Texture.CurrentUnit;
     struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
  
-@@ -701,7 +285,7 @@ static void radeonTexEnv( GLcontext *ctx, GLenum target,
+@@ -706,7 +290,7 @@ static void radeonTexEnv( GLcontext *ctx, GLenum target,
         * functions, one mapping [-1.0,0.0] to [-128,0] and one mapping
         * [0.0,4.0] to [0,127].
         */
@@ -34442,7 +37514,7 @@ index b0aec21..21509c6 100644
  	  0.0 : -1.0;
        bias = CLAMP( *param, min, 4.0 );
        if ( bias == 0 ) {
-@@ -734,7 +318,7 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target,
+@@ -739,7 +323,7 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target,
  				struct gl_texture_object *texObj,
  				GLenum pname, const GLfloat *params )
  {
@@ -34451,7 +37523,7 @@ index b0aec21..21509c6 100644
  
     if ( RADEON_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) {
        fprintf( stderr, "%s( %s )\n", __FUNCTION__,
-@@ -762,57 +346,51 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target,
+@@ -767,57 +351,51 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target,
     case GL_TEXTURE_MAX_LEVEL:
     case GL_TEXTURE_MIN_LOD:
     case GL_TEXTURE_MAX_LOD:
@@ -34531,7 +37603,7 @@ index b0aec21..21509c6 100644
     /* Free mipmap images and the texture object itself */
     _mesa_delete_texture_object(ctx, texObj);
  }
-@@ -832,7 +410,7 @@ static void radeonTexGen( GLcontext *ctx,
+@@ -837,7 +415,7 @@ static void radeonTexGen( GLcontext *ctx,
  			  GLenum pname,
  			  const GLfloat *params )
  {
@@ -34540,7 +37612,7 @@ index b0aec21..21509c6 100644
     GLuint unit = ctx->Texture.CurrentUnit;
     rmesa->recheck_texgen[unit] = GL_TRUE;
  }
-@@ -846,29 +424,40 @@ static void radeonTexGen( GLcontext *ctx,
+@@ -851,29 +429,40 @@ static void radeonTexGen( GLcontext *ctx,
  static struct gl_texture_object *
  radeonNewTextureObject( GLcontext *ctx, GLuint name, GLenum target )
  {
@@ -34567,7 +37639,7 @@ index b0aec21..21509c6 100644
 +   radeonSetTexWrap( t, t->base.WrapS, t->base.WrapT );
 +   radeonSetTexMaxAnisotropy( t, t->base.MaxAnisotropy );
 +   radeonSetTexFilter( t, t->base.MinFilter, t->base.MagFilter );
-+   radeonSetTexBorderColor( t, t->base._BorderChan );
++   radeonSetTexBorderColor( t, t->base.BorderColor );
 +   return &t->base;
  }
  
@@ -34592,7 +37664,7 @@ index b0aec21..21509c6 100644
  
     functions->TexEnv			= radeonTexEnv;
     functions->TexParameter		= radeonTexParameter;
-@@ -877,5 +466,12 @@ void radeonInitTextureFuncs( struct dd_function_table *functions )
+@@ -882,5 +471,12 @@ void radeonInitTextureFuncs( struct dd_function_table *functions )
     functions->CompressedTexImage2D	= radeonCompressedTexImage2D;
     functions->CompressedTexSubImage2D	= radeonCompressedTexSubImage2D;
  


Index: sources
===================================================================
RCS file: /cvs/pkgs/rpms/mesa/devel/sources,v
retrieving revision 1.34
retrieving revision 1.35
diff -u -p -r1.34 -r1.35
--- sources	22 Mar 2009 02:20:16 -0000	1.34
+++ sources	11 Jun 2009 17:17:23 -0000	1.35
@@ -1,3 +1,3 @@
 6ae05158e678f4594343f32c2ca50515  gl-manpages-1.0.1.tar.bz2
 a5ec51ed9f0a55dc3462d90d52ff899c  xdriinfo-1.0.2.tar.bz2
-2469ad7640d26d1aed61452cfe62fd49  mesa-20090322.tar.bz2
+d7ff7c44fe42f2639845a2975804792d  mesa-20090428.tar.bz2

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