rpms/xorg-x11-drv-ati/devel radeon-6.11.0-git.patch, 1.2, 1.3 radeon-modeset.patch, 1.35, 1.36 xorg-x11-drv-ati.spec, 1.153, 1.154
Dave Airlie
airlied at fedoraproject.org
Fri Mar 6 23:50:37 UTC 2009
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Author: airlied
Update of /cvs/pkgs/rpms/xorg-x11-drv-ati/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv14532
Modified Files:
radeon-6.11.0-git.patch radeon-modeset.patch
xorg-x11-drv-ati.spec
Log Message:
* Sat Mar 07 2009 Dave Airlie <airlied at redhat.com> 6.11.0-5
- pull in more fixes from master
radeon-6.11.0-git.patch:
Index: radeon-6.11.0-git.patch
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/radeon-6.11.0-git.patch,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -r1.2 -r1.3
--- radeon-6.11.0-git.patch 2 Mar 2009 23:42:19 -0000 1.2
+++ radeon-6.11.0-git.patch 6 Mar 2009 23:50:06 -0000 1.3
@@ -49,6 +49,160 @@
#define PCI_VENDOR_ATI 0x1002
#define PCI_VENDOR_IBM 0x1014
#define PCI_VENDOR_AMD 0x1022
+diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
+index 5c26ef8..bf207bf 100644
+--- a/src/atombios_crtc.c
++++ b/src/atombios_crtc.c
+@@ -186,7 +186,7 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_
+ conv_param.ucOverscanRight = crtc_param->ucOverscanRight;
+ conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft;
+ conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom;
+- conv_param.ucOverscanTop = crtc_param->ucOverscanTop;
++ conv_param.ucOverscanTop = crtc_param->ucOverscanTop;
+ conv_param.ucReserved = crtc_param->ucReserved;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
+@@ -203,7 +203,7 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_
+ }
+
+ void
+-atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags)
++atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
+ {
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+@@ -219,6 +219,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags)
+ xf86OutputPtr output;
+ RADEONOutputPrivatePtr radeon_output = NULL;
+ radeon_encoder_ptr radeon_encoder = NULL;
++ int pll_flags = 0;
+
+ void *ptr;
+ AtomBiosArgRec data;
+@@ -350,7 +351,6 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
+ int i, ret;
+ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
+ Bool tilingChanged = FALSE;
+- int pll_flags = 0;
+ memset(&crtc_timing, 0, sizeof(crtc_timing));
+
+ if (info->allowColorTiling) {
+@@ -373,9 +373,6 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
+ need_tv_timings = 2;
+
+ }
+-
+- if (radeon_output->MonType == MT_LCD)
+- pll_flags |= RADEON_PLL_USE_REF_DIV;
+ }
+ }
+
+@@ -484,7 +481,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
+ 0);
+ }
+
+- atombios_crtc_set_pll(crtc, adjusted_mode, pll_flags);
++ atombios_crtc_set_pll(crtc, adjusted_mode);
+
+ atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
+
+diff --git a/src/atombios_output.c b/src/atombios_output.c
+index c4baa13..613f729 100644
+--- a/src/atombios_output.c
++++ b/src/atombios_output.c
+@@ -430,7 +430,10 @@ atombios_get_encoder_mode(xf86OutputPtr output)
+ return ATOM_ENCODER_MODE_LVDS;
+ break;
+ case CONNECTOR_DISPLAY_PORT:
+- return ATOM_ENCODER_MODE_DP;
++ if (radeon_output->MonType == MT_DP)
++ return ATOM_ENCODER_MODE_DP;
++ else
++ return atombios_maybe_hdmi_mode(output);
+ break;
+ case CONNECTOR_DVI_A:
+ case CONNECTOR_VGA:
+@@ -995,6 +998,61 @@ atombios_output_yuv_setup(xf86OutputPtr output, Bool enable)
+ }
+
+ static int
++atombios_output_overscan_setup(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode)
++{
++ RADEONOutputPrivatePtr radeon_output = output->driver_private;
++ RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
++ RADEONInfoPtr info = RADEONPTR(output->scrn);
++ SET_CRTC_OVERSCAN_PS_ALLOCATION overscan_param;
++ AtomBiosArgRec data;
++ unsigned char *space;
++ memset(&overscan_param, 0, sizeof(overscan_param));
++
++ overscan_param.usOverscanRight = 0;
++ overscan_param.usOverscanLeft = 0;
++ overscan_param.usOverscanBottom = 0;
++ overscan_param.usOverscanTop = 0;
++ overscan_param.ucCRTC = radeon_crtc->crtc_id;
++
++ if (radeon_output->Flags & RADEON_USE_RMX) {
++ if (radeon_output->rmx_type == RMX_FULL) {
++ overscan_param.usOverscanRight = 0;
++ overscan_param.usOverscanLeft = 0;
++ overscan_param.usOverscanBottom = 0;
++ overscan_param.usOverscanTop = 0;
++ } else if (radeon_output->rmx_type == RMX_CENTER) {
++ overscan_param.usOverscanTop = (adjusted_mode->CrtcVDisplay - mode->CrtcVDisplay) / 2;
++ overscan_param.usOverscanBottom = (adjusted_mode->CrtcVDisplay - mode->CrtcVDisplay) / 2;
++ overscan_param.usOverscanLeft = (adjusted_mode->CrtcHDisplay - mode->CrtcHDisplay) / 2;
++ overscan_param.usOverscanRight = (adjusted_mode->CrtcHDisplay - mode->CrtcHDisplay) / 2;
++ } else if (radeon_output->rmx_type == RMX_ASPECT) {
++ int a1 = mode->CrtcVDisplay * adjusted_mode->CrtcHDisplay;
++ int a2 = adjusted_mode->CrtcVDisplay * mode->CrtcHDisplay;
++
++ if (a1 > a2) {
++ overscan_param.usOverscanLeft = (adjusted_mode->CrtcHDisplay - (a2 / mode->CrtcVDisplay)) / 2;
++ overscan_param.usOverscanRight = (adjusted_mode->CrtcHDisplay - (a2 / mode->CrtcVDisplay)) / 2;
++ } else if (a2 > a1) {
++ overscan_param.usOverscanLeft = (adjusted_mode->CrtcVDisplay - (a1 / mode->CrtcHDisplay)) / 2;
++ overscan_param.usOverscanRight = (adjusted_mode->CrtcVDisplay - (a1 / mode->CrtcHDisplay)) / 2;
++ }
++ }
++ }
++
++ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
++ data.exec.dataSpace = (void *)&space;
++ data.exec.pspace = &overscan_param;
++
++ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
++ ErrorF("Set CRTC %d Overscan success\n", radeon_crtc->crtc_id);
++ return ATOM_SUCCESS ;
++ }
++
++ ErrorF("Set CRTC %d Overscan failed\n", radeon_crtc->crtc_id);
++ return ATOM_NOT_IMPLEMENTED;
++}
++
++static int
+ atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode)
+ {
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+@@ -1051,6 +1109,8 @@ atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode)
+ disp_data.ucEnable = ATOM_SCALER_EXPANSION;
+ else if (radeon_output->rmx_type == RMX_CENTER)
+ disp_data.ucEnable = ATOM_SCALER_CENTER;
++ else if (radeon_output->rmx_type == RMX_ASPECT)
++ disp_data.ucEnable = ATOM_SCALER_EXPANSION;
+ } else {
+ ErrorF("Not using RMX\n");
+ disp_data.ucEnable = ATOM_SCALER_DISABLE;
+@@ -1423,7 +1483,8 @@ atombios_output_mode_set(xf86OutputPtr output,
+ if (radeon_encoder == NULL)
+ return;
+
+- atombios_output_scaler_setup(output, mode);
++ atombios_output_overscan_setup(output, mode, adjusted_mode);
++ atombios_output_scaler_setup(output, adjusted_mode);
+ atombios_set_output_crtc_source(output);
+ if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
+ atombios_output_yuv_setup(output, TRUE);
diff --git a/src/r600_exa.c b/src/r600_exa.c
new file mode 100644
index 0000000..3a4dc8d
@@ -10793,10 +10947,34 @@
}
}
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
-index 5a7c730..60140d6 100644
+index 5a7c730..a87e99b 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
-@@ -587,8 +587,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
+@@ -410,6 +410,14 @@ radeon_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
+ int align = 4096, size;
+ int cpp = pScrn->bitsPerPixel / 8;
+
++ /* No rotation without accel */
++ if (((info->ChipFamily >= CHIP_FAMILY_R600) && !info->directRenderingEnabled) ||
++ xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
++ "Acceleration required for rotation\n");
++ return NULL;
++ }
++
+ rotate_pitch = pScrn->displayWidth * cpp;
+ size = rotate_pitch * height;
+
+@@ -424,7 +432,7 @@ radeon_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
+
+ return info->FB + rotate_offset;
+ }
+-
++
+ /**
+ * Creates a pixmap for this CRTC's rotated shadow framebuffer.
+ */
+@@ -587,8 +595,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -10807,7 +10985,7 @@
radeon_crtc_funcs.shadow_allocate = radeon_crtc_shadow_allocate;
radeon_crtc_funcs.shadow_destroy = radeon_crtc_shadow_destroy;
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
-index 59d9a83..45f79ed 100644
+index 59d9a83..2b7540c 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -45,11 +45,14 @@
@@ -10834,7 +11012,7 @@
typedef struct {
unsigned int hostbridgeVendor;
unsigned int hostbridgeDevice;
-@@ -737,48 +740,55 @@ typedef struct {
+@@ -737,48 +740,57 @@ typedef struct {
static radeon_agpmode_quirk radeon_agpmode_quirk_list[] = {
/* Intel E7505 Memory Controller Hub / RV350 AR [Radeon 9600XT] Needs AGPMode 4 (deb #515326) */
@@ -10847,6 +11025,8 @@
/* Intel 82855PM Processor to I/O Controller / Mobility M6 LY Needs AGPMode 1 (deb #467235) */
- { PCI_VENDOR_INTEL,0x3340, PCI_VENDOR_ATI,0x4c59, 0x1014,0x052f, 1 },
+ { PCI_VENDOR_INTEL,0x3340, PCI_VENDOR_ATI,0x4c59, PCI_VENDOR_IBM,0x052f, 1 },
++ /* Intel 82855PM host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #195051) */
++ { PCI_VENDOR_INTEL,0x3340, PCI_VENDOR_ATI,0x4e50, PCI_VENDOR_IBM,0x0550, 1 },
+ /* Intel 82855PM host bridge / Mobility M9+ / VaioPCG-V505DX Needs AGPMode 2 (fdo #17928) */
+ { PCI_VENDOR_INTEL,0x3340, PCI_VENDOR_ATI,0x5c61, PCI_VENDOR_SONY,0x816b, 2 },
/* Intel 82855PM Processor to I/O Controller / Mobility M9+ Needs AGPMode 8 (phoronix forum) */
@@ -10914,7 +11094,7 @@
{ 0, 0, 0, 0, 0, 0, 0 },
};
-@@ -790,92 +800,96 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -790,92 +802,96 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
unsigned long mode = drmAgpGetMode(info->dri->drmFD); /* Default mode */
unsigned int vendor = drmAgpVendorId(info->dri->drmFD);
unsigned int device = drmAgpDeviceId(info->dri->drmFD);
@@ -11089,7 +11269,7 @@
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x; Card 0x%04x/0x%04x 0x%04x/0x%04x]\n",
-@@ -910,6 +924,9 @@ static void RADEONSetAgpBase(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -910,6 +926,9 @@ static void RADEONSetAgpBase(RADEONInfoPtr info, ScreenPtr pScreen)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
unsigned char *RADEONMMIO = info->MMIO;
@@ -11099,7 +11279,7 @@
/* drm already does this, so we can probably remove this.
* agp_base_2 ?
*/
-@@ -1183,13 +1200,14 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1183,13 +1202,14 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
drm_radeon_init_t drmInfo;
memset(&drmInfo, 0, sizeof(drm_radeon_init_t));
@@ -11120,7 +11300,7 @@
drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
drmInfo.is_pci = (info->cardType!=CARD_AGP);
-@@ -1223,7 +1241,8 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1223,7 +1243,8 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
* registers back to their default values, so we need to restore
* those engine register here.
*/
@@ -11130,7 +11310,7 @@
return TRUE;
}
-@@ -1299,14 +1318,16 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1299,14 +1320,16 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[drm] falling back to irq-free operation\n");
info->dri->irq = 0;
} else {
@@ -11155,7 +11335,7 @@
}
}
-@@ -1840,7 +1861,8 @@ void RADEONDRIResume(ScreenPtr pScreen)
+@@ -1840,7 +1863,8 @@ void RADEONDRIResume(ScreenPtr pScreen)
/* FIXME: return? */
}
@@ -11166,7 +11346,7 @@
RADEONDRICPInit(pScrn);
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
-index 32cb307..7cac321 100644
+index 32cb307..0842164 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -578,7 +578,7 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr)
@@ -11432,19 +11612,32 @@
return FALSE;
}
}
-@@ -2336,7 +2345,10 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
- xf86DrvMsg(pScrn->scrnIndex, from, "Page Flipping %sabled%s\n",
- info->dri->allowPageFlip ? "en" : "dis", reason);
+@@ -2952,6 +2961,24 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+ goto fail;
+ }
+
++ /* fix up cloning on rn50 cards
++ * since they only have one crtc sometimes the xserver doesn't assign
++ * a crtc to one of the outputs even though both outputs have common modes
++ * which results in only one monitor being enabled. Assign a crtc here so
++ * that both outputs light up.
++ */
++ if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
++ int i;
++
++ for (i = 0; i < xf86_config->num_output; i++) {
++ xf86OutputPtr output = xf86_config->output[i];
++
++ /* XXX: double check crtc mode */
++ if ((output->probed_modes != NULL) && (output->crtc == NULL))
++ output->crtc = xf86_config->crtc[0];
++ }
++ }
++
+ ErrorF("after xf86InitialConfiguration\n");
-- info->DMAForXv = TRUE;
-+ if (info->ChipFamily >= CHIP_FAMILY_R600)
-+ info->DMAForXv = FALSE;
-+ else
-+ info->DMAForXv = TRUE;
- from = xf86GetOptValBool(info->Options, OPTION_XV_DMA, &info->DMAForXv)
- ? X_CONFIG : X_INFO;
- xf86DrvMsg(pScrn->scrnIndex, from,
-@@ -3644,11 +3656,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+ RADEONSetPitch(pScrn);
+@@ -3644,11 +3671,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
RADEONDGAInit(pScreen);
/* Init Xv */
@@ -11459,7 +11652,7 @@
if (info->r600_shadow_fb == TRUE) {
if (!shadowSetup(pScreen)) {
-@@ -3771,9 +3781,10 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
+@@ -3771,9 +3796,10 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
} else {
OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000);
}
@@ -11472,7 +11665,7 @@
}
} else {
-@@ -3958,7 +3969,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
+@@ -3958,7 +3984,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
}
#ifdef USE_EXA
@@ -11481,7 +11674,7 @@
{
drm_radeon_getparam_t gp;
int gart_base;
-@@ -4419,15 +4430,40 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
+@@ -4419,15 +4445,40 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->aux_cntl2[j] = INREG(i + 0x040);
state->aux_cntl3[j] = INREG(i + 0x400);
state->aux_cntl4[j] = INREG(i + 0x440);
@@ -11526,7 +11719,7 @@
}
j = 0;
/* save PHY,LINK regs */
-@@ -4770,15 +4806,40 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
+@@ -4770,15 +4821,40 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG((i + 0x040), state->aux_cntl2[j]);
OUTREG((i + 0x400), state->aux_cntl3[j]);
OUTREG((i + 0x440), state->aux_cntl4[j]);
@@ -11571,7 +11764,7 @@
}
j = 0;
/* save PHY,LINK regs */
-@@ -5046,8 +5107,10 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
+@@ -5046,8 +5122,10 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
"RADEONRestore\n");
#if X_BYTE_ORDER == X_BIG_ENDIAN
@@ -11584,7 +11777,7 @@
#endif
RADEONBlank(pScrn);
-@@ -5220,7 +5283,8 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5220,7 +5298,8 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
if (info->accelOn) {
RADEON_SYNC(info, pScrn);
@@ -11594,7 +11787,7 @@
}
#ifdef XF86DRI
-@@ -5424,6 +5488,10 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
+@@ -5424,6 +5503,10 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
xf86OutputPtr output = config->output[config->compat_output];
xf86CrtcPtr crtc = output->crtc;
@@ -11605,7 +11798,7 @@
#ifdef XF86DRI
if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0);
#endif
-@@ -5536,9 +5604,12 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
+@@ -5536,9 +5619,12 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
if (info->adaptor)
RADEONResetVideo(pScrn);
@@ -11764,7 +11957,7 @@
ExaOffscreenArea *area = mem_struct;
diff --git a/src/radeon_modes.c b/src/radeon_modes.c
-index e06f8dd..0a8fa00 100644
+index e06f8dd..ec60cc9 100644
--- a/src/radeon_modes.c
+++ b/src/radeon_modes.c
@@ -65,15 +65,19 @@ void RADEONSetPitch (ScrnInfoPtr pScrn)
@@ -11796,11 +11989,113 @@
dummy = (pScrn->virtualX + pitch_mask) & ~pitch_mask;
pScrn->displayWidth = dummy;
info->CurrentLayout.displayWidth = pScrn->displayWidth;
+@@ -411,6 +415,56 @@ RADEONUpdatePanelSize(xf86OutputPtr output)
+ }
+ }
+
++static void
++radeon_add_common_modes(xf86OutputPtr output, DisplayModePtr modes)
++{
++ RADEONOutputPrivatePtr radeon_output = output->driver_private;
++ radeon_native_mode_ptr native_mode = &radeon_output->native_mode;
++ DisplayModePtr last = NULL;
++ DisplayModePtr new = NULL;
++ DisplayModePtr first = NULL;
++ int i;
++ /* Add some common sizes */
++ int widths[15] = {640, 800, 1024, 1152, 1280, 1280, 1280, 1280, 1280, 1440, 1400, 1680, 1600, 1920, 1920};
++ int heights[15] = {480, 600, 768, 768, 720, 800, 854, 960, 1024, 900, 1050, 1050, 1200, 1080, 1200};
++
++ for (i = 0; i < 15; i++) {
++ if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
++ /* already added the native mode */
++ if (widths[i] == native_mode->PanelXRes && heights[i] == native_mode->PanelYRes)
++ continue;
++
++ /* Note: We allow all non-standard modes as long as they do not
++ * exceed the native resolution of the panel. Since these modes
++ * need the internal RMX unit in the video chips (and there is
++ * only one per card), this will only apply to the primary head.
++ */
++ if (widths[i] < 320 || widths[i] > native_mode->PanelXRes ||
++ heights[i] < 200 || heights[i] > native_mode->PanelYRes)
++ continue;
++ }
++
++ new = xf86CVTMode(widths[i], heights[i], 60.0, FALSE, FALSE);
++
++ new->type = M_T_DRIVER;
++
++ new->next = NULL;
++ new->prev = last;
++
++ if (last) last->next = new;
++ last = new;
++ if (!first) first = new;
++ }
++
++ if (last) {
++ last->next = NULL; //first;
++ first->prev = NULL; //last;
++ }
++
++ xf86ModesAdd(modes, first);
++
++}
++
+ DisplayModePtr
+ RADEONProbeOutputModes(xf86OutputPtr output)
+ {
+@@ -459,12 +513,16 @@ RADEONProbeOutputModes(xf86OutputPtr output)
+ if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT))
+ modes = RADEONFPNativeMode(output);
+ /* add the screen modes */
+- RADEONAddScreenModes(output, &modes);
++ if (modes == NULL)
++ RADEONAddScreenModes(output, &modes);
+ }
+ }
+ }
+ }
+
++ if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT))
++ radeon_add_common_modes(output, modes);
++
+ return modes;
+ }
+
diff --git a/src/radeon_output.c b/src/radeon_output.c
-index 352519f..897c6a2 100644
+index 352519f..fcf22ef 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
-@@ -1147,7 +1147,7 @@ radeon_create_resources(xf86OutputPtr output)
+@@ -255,7 +255,11 @@ radeon_ddc_connected(xf86OutputPtr output)
+ MonType = MT_DFP;
+ break;
+ case CONNECTOR_DISPLAY_PORT:
+- MonType = MT_DP;
++ /*
++ * XXX wrong. need to infer based on whether we got DDC from I2C
++ * or AUXCH.
++ */
++ MonType = MT_DFP;
+ case CONNECTOR_DVI_I:
+ if (MonInfo->rawData[0x14] & 0x80) /* if it's digital and DVI */
+ MonType = MT_DFP;
+@@ -399,6 +403,13 @@ radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
+ }
+ }
+
++ if (radeon_output->ConnectorType == CONNECTOR_DISPLAY_PORT &&
++ radeon_output->MonType == MT_DFP) {
++ /* DP to DVI converter, single-link only */
++ if (pMode->Clock > 165000)
++ return MODE_CLOCK_HIGH;
++ }
++
+ if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
+ if (radeon_output->rmx_type == RMX_OFF) {
+ if (pMode->HDisplay != native_mode->PanelXRes ||
+@@ -1147,7 +1158,7 @@ radeon_create_resources(xf86OutputPtr output)
}
#endif
@@ -11809,11 +12104,150 @@
load_detection_atom = MAKE_ATOM("load_detection");
range[0] = 0; /* off */
+@@ -1465,6 +1476,11 @@ radeon_set_property(xf86OutputPtr output, Atom property,
+ radeon_output->rmx_type = RMX_FULL;
+ } else if (value->size == strlen("center") && !strncmp("center", s, strlen("center"))) {
+ radeon_output->rmx_type = RMX_CENTER;
++ } else if (value->size == strlen("aspect") && !strncmp("aspect", s, strlen("aspect"))) {
++ if (IS_AVIVO_VARIANT)
++ radeon_output->rmx_type = RMX_ASPECT;
++ else
++ return FALSE;
+ } else if (value->size == strlen("off") && !strncmp("off", s, strlen("off"))) {
+ radeon_output->rmx_type = RMX_OFF;
+ } else
+@@ -2500,6 +2516,14 @@ radeon_output_clones (ScrnInfoPtr pScrn, xf86OutputPtr output)
+ return index_mask;
+ }
+
++static xf86OutputPtr
++RADEONOutputCreate(ScrnInfoPtr pScrn, const char *name, int i)
++{
++ char buf[32];
++ sprintf(buf, name, i);
++ return xf86OutputCreate(pScrn, &radeon_output_funcs, buf);
++}
++
+ /*
+ * initialise the static data sos we don't have to re-do at randr change */
+ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
+@@ -2512,6 +2536,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
+ int num_vga = 0;
+ int num_dvi = 0;
+ int num_hdmi = 0;
++ int num_dp = 0;
+
+ /* We first get the information about all connectors from BIOS.
+ * This is how the card is phyiscally wired up.
+@@ -2648,15 +2673,18 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
+
+ for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
+ if (info->BiosConnector[i].valid) {
+- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) ||
+- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I) ||
+- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) {
++ RADEONConnectorType conntype = info->BiosConnector[i].ConnectorType;
++ if ((conntype == CONNECTOR_DVI_D) ||
++ (conntype == CONNECTOR_DVI_I) ||
++ (conntype == CONNECTOR_DVI_A)) {
+ num_dvi++;
+- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) {
++ } else if (conntype == CONNECTOR_VGA) {
+ num_vga++;
+- } else if ((info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_A) ||
+- (info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_B)) {
++ } else if ((conntype == CONNECTOR_HDMI_TYPE_A) ||
++ (conntype == CONNECTOR_HDMI_TYPE_B)) {
+ num_hdmi++;
++ } else if (conntype == CONNECTOR_DISPLAY_PORT) {
++ num_dp++;
+ }
+ }
+ }
+@@ -2664,8 +2692,9 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
+ for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
+ if (info->BiosConnector[i].valid) {
+ RADEONOutputPrivatePtr radeon_output;
++ RADEONConnectorType conntype = info->BiosConnector[i].ConnectorType;
+
+- if (info->BiosConnector[i].ConnectorType == CONNECTOR_NONE)
++ if (conntype == CONNECTOR_NONE)
+ continue;
+
+ radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1);
+@@ -2673,7 +2702,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
+ return FALSE;
+ }
+ radeon_output->MonType = MT_UNKNOWN;
+- radeon_output->ConnectorType = info->BiosConnector[i].ConnectorType;
++ radeon_output->ConnectorType = conntype;
+ radeon_output->devices = info->BiosConnector[i].devices;
+ radeon_output->ddc_i2c = info->BiosConnector[i].ddc_i2c;
+ radeon_output->igp_lane_info = info->BiosConnector[i].igp_lane_info;
+@@ -2682,33 +2711,21 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
+ radeon_output->linkb = info->BiosConnector[i].linkb;
+ radeon_output->connector_id = info->BiosConnector[i].connector_object;
+
+- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) ||
+- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I) ||
+- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) {
+- if (num_dvi > 1) {
+- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-1");
+- num_dvi--;
+- } else {
+- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-0");
+- }
+- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) {
+- if (num_vga > 1) {
+- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-1");
+- num_vga--;
+- } else {
+- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-0");
+- }
+- } else if ((info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_A) ||
+- (info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_B)) {
+- if (num_hdmi > 1) {
+- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "HDMI-1");
+- num_hdmi--;
+- } else {
+- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "HDMI-0");
+- }
+- } else
+- output = xf86OutputCreate(pScrn, &radeon_output_funcs,
+- ConnectorTypeName[radeon_output->ConnectorType]);
++ if ((conntype == CONNECTOR_DVI_D) ||
++ (conntype == CONNECTOR_DVI_I) ||
++ (conntype == CONNECTOR_DVI_A)) {
++ output = RADEONOutputCreate(pScrn, "DVI-%d", --num_dvi);
++ } else if (conntype == CONNECTOR_VGA) {
++ output = RADEONOutputCreate(pScrn, "VGA-%d", --num_vga);
++ } else if ((conntype == CONNECTOR_HDMI_TYPE_A) ||
++ (conntype == CONNECTOR_HDMI_TYPE_B)) {
++ output = RADEONOutputCreate(pScrn, "HDMI-%d", --num_hdmi);
++ } else if (conntype == CONNECTOR_DISPLAY_PORT) {
++ output = RADEONOutputCreate(pScrn, "DisplayPort-%d", --num_dp);
++ } else {
++ output = RADEONOutputCreate(pScrn,
++ ConnectorTypeName[conntype], 0);
++ }
+
+ if (!output) {
+ return FALSE;
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
-index 447ef57..f072b9c 100644
+index 447ef57..afc8e21 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
-@@ -373,7 +373,7 @@ struct avivo_state
+@@ -101,7 +101,8 @@ typedef enum
+ {
+ RMX_OFF,
+ RMX_FULL,
+- RMX_CENTER
++ RMX_CENTER,
++ RMX_ASPECT
+ } RADEONRMXType;
+
+ typedef struct {
+@@ -373,7 +374,7 @@ struct avivo_state
/* dvoa */
uint32_t dvoa[16];
@@ -11822,7 +12256,7 @@
uint32_t fmt1[18];
uint32_t fmt2[18];
uint32_t dig1[19];
-@@ -384,9 +384,15 @@ struct avivo_state
+@@ -384,9 +385,15 @@ struct avivo_state
uint32_t aux_cntl2[14];
uint32_t aux_cntl3[14];
uint32_t aux_cntl4[14];
@@ -11938,7 +12372,7 @@
+
#endif
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
-index 7712344..cbedb7e 100644
+index 7712344..2df299f 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -36,6 +36,7 @@
@@ -11974,16 +12408,16 @@
static Bool
RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix)
{
-@@ -146,6 +159,56 @@ static __inline__ uint32_t F_TO_24(float val)
+@@ -146,6 +159,132 @@ static __inline__ uint32_t F_TO_24(float val)
#endif /* XF86DRI */
+static void
-+R600CopyPlanar(ScrnInfoPtr pScrn,
-+ unsigned char *y_src, unsigned char *u_src, unsigned char *v_src,
-+ uint32_t dst_mc_addr,
-+ int srcPitch, int srcPitch2, int dstPitch,
-+ int w, int h)
++R600CopyPlanarHW(ScrnInfoPtr pScrn,
++ unsigned char *y_src, unsigned char *u_src, unsigned char *v_src,
++ uint32_t dst_mc_addr,
++ int srcPitch, int srcPitch2, int dstPitch,
++ int w, int h)
+{
+ int dstPitch2 = dstPitch >> 1;
+ int h2 = h >> 1;
@@ -12014,10 +12448,10 @@
+}
+
+static void
-+R600CopyPacked(ScrnInfoPtr pScrn,
-+ unsigned char *src, uint32_t dst_mc_addr,
-+ int srcPitch, int dstPitch,
-+ int w, int h)
++R600CopyPackedHW(ScrnInfoPtr pScrn,
++ unsigned char *src, uint32_t dst_mc_addr,
++ int srcPitch, int dstPitch,
++ int w, int h)
+{
+
+ /* YUV */
@@ -12028,10 +12462,86 @@
+
+}
+
++static void
++R600CopyPlanarSW(ScrnInfoPtr pScrn,
++ unsigned char *y_src, unsigned char *u_src, unsigned char *v_src,
++ unsigned char *dst,
++ int srcPitch, int srcPitch2, int dstPitch,
++ int w, int h)
++{
++ int i;
++ int dstPitch2 = dstPitch >> 1;
++ int h2 = h >> 1;
++
++ /* Y */
++ if (srcPitch == dstPitch) {
++ memcpy(dst, y_src, srcPitch * h);
++ dst += (dstPitch * h);
++ } else {
++ for (i = 0; i < h; i++) {
++ memcpy(dst, y_src, srcPitch);
++ y_src += srcPitch;
++ dst += dstPitch;
++ }
++ }
++
++ /* tex base need 256B alignment */
++ if (h & 1)
++ dst += dstPitch;
++
++ /* V */
++ if (srcPitch2 == dstPitch2) {
++ memcpy(dst, v_src, srcPitch2 * h2);
++ dst += (dstPitch2 * h2);
++ } else {
++ for (i = 0; i < h2; i++) {
++ memcpy(dst, v_src, srcPitch2);
++ v_src += srcPitch2;
++ dst += dstPitch2;
++ }
++ }
++
++ /* tex base need 256B alignment */
++ if (h2 & 1)
++ dst += dstPitch2;
++
++ /* U */
++ if (srcPitch2 == dstPitch2) {
++ memcpy(dst, u_src, srcPitch2 * h2);
++ dst += (dstPitch2 * h2);
++ } else {
++ for (i = 0; i < h2; i++) {
++ memcpy(dst, u_src, srcPitch2);
++ u_src += srcPitch2;
++ dst += dstPitch2;
++ }
++ }
++}
++
++static void
++R600CopyPackedSW(ScrnInfoPtr pScrn,
++ unsigned char *src, unsigned char *dst,
++ int srcPitch, int dstPitch,
++ int w, int h)
++{
++ int i;
++
++ if (srcPitch == dstPitch) {
++ memcpy(dst, src, srcPitch * h);
++ dst += (dstPitch * h);
++ } else {
++ for (i = 0; i < h; i++) {
++ memcpy(dst, src, srcPitch);
++ src += srcPitch;
++ dst += dstPitch;
++ }
++ }
++}
++
static int
RADEONPutImageTextured(ScrnInfoPtr pScrn,
short src_x, short src_y,
-@@ -214,7 +277,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+@@ -214,7 +353,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
break;
}
@@ -12043,7 +12553,7 @@
if (pPriv->video_memory != NULL && size != pPriv->size) {
radeon_legacy_free_memory(pScrn, pPriv->video_memory);
-@@ -222,16 +288,21 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+@@ -222,16 +364,21 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
}
if (pPriv->video_memory == NULL) {
@@ -12069,7 +12579,7 @@
pPriv->bicubic_enabled = FALSE;
if (pPriv->bicubic_enabled && (pPriv->bicubic_state == BICUBIC_AUTO)) {
/*
-@@ -280,7 +351,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+@@ -280,7 +427,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left;
pPriv->src_offset = pPriv->video_offset + info->fbLocation + pScrn->fbOffset;
@@ -12081,7 +12591,7 @@
pPriv->src_pitch = dstPitch;
pPriv->size = size;
pPriv->pDraw = pDraw;
-@@ -294,29 +368,51 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+@@ -294,35 +444,77 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
switch(id) {
case FOURCC_YV12:
case FOURCC_I420:
@@ -12101,17 +12611,29 @@
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ s2offset = srcPitch * height;
+ s3offset = (srcPitch2 * (height >> 1)) + s2offset;
-+ if (id == FOURCC_YV12)
-+ R600CopyPlanar(pScrn, buf, buf + s3offset, buf + s2offset,
-+ pPriv->src_offset,
-+ srcPitch, srcPitch2, pPriv->src_pitch,
-+ width, height);
-+ else
-+ R600CopyPlanar(pScrn, buf, buf + s2offset, buf + s3offset,
-+ pPriv->src_offset,
-+ srcPitch, srcPitch2, pPriv->src_pitch,
-+ width, height);
-+
++ if (info->DMAForXv) {
++ if (id == FOURCC_YV12)
++ R600CopyPlanarHW(pScrn, buf, buf + s3offset, buf + s2offset,
++ pPriv->src_offset,
++ srcPitch, srcPitch2, pPriv->src_pitch,
++ width, height);
++ else
++ R600CopyPlanarHW(pScrn, buf, buf + s2offset, buf + s3offset,
++ pPriv->src_offset,
++ srcPitch, srcPitch2, pPriv->src_pitch,
++ width, height);
++ } else {
++ if (id == FOURCC_YV12)
++ R600CopyPlanarSW(pScrn, buf, buf + s3offset, buf + s2offset,
++ pPriv->src_addr,
++ srcPitch, srcPitch2, pPriv->src_pitch,
++ width, height);
++ else
++ R600CopyPlanarSW(pScrn, buf, buf + s2offset, buf + s3offset,
++ pPriv->src_addr,
++ srcPitch, srcPitch2, pPriv->src_pitch,
++ width, height);
++ }
+ } else {
+ top &= ~1;
+ nlines = ((((y2 + 0xffff) >> 16) + 1) & ~1) - top;
@@ -12141,9 +12663,14 @@
- nlines = ((y2 + 0xffff) >> 16) - top;
- RADEONCopyData(pScrn, buf, pPriv->src_addr, srcPitch, dstPitch, nlines, npixels, 2);
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
-+ R600CopyPacked(pScrn, buf, pPriv->src_offset,
-+ 2 * width, pPriv->src_pitch,
-+ width, height);
++ if (info->DMAForXv)
++ R600CopyPackedHW(pScrn, buf, pPriv->src_offset,
++ 2 * width, pPriv->src_pitch,
++ width, height);
++ else
++ R600CopyPackedSW(pScrn, buf, pPriv->src_addr,
++ 2 * width, pPriv->src_pitch,
++ width, height);
+ } else {
+ nlines = ((y2 + 0xffff) >> 16) - top;
+ RADEONCopyData(pScrn, buf, pPriv->src_addr, srcPitch, dstPitch, nlines, npixels, 2);
@@ -12151,7 +12678,18 @@
break;
}
-@@ -340,7 +436,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+ /* Upload bicubic filter tex */
+- if (pPriv->bicubic_enabled)
+- RADEONCopyData(pScrn, (uint8_t *)bicubic_tex_512, (uint8_t *)(info->FB + pPriv->bicubic_offset), 1024, 1024, 1, 512, 2);
++ if (pPriv->bicubic_enabled) {
++ if (info->ChipFamily < CHIP_FAMILY_R600)
++ RADEONCopyData(pScrn, (uint8_t *)bicubic_tex_512,
++ (uint8_t *)(info->FB + pPriv->bicubic_offset), 1024, 1024, 1, 512, 2);
++ }
+
+ /* update cliplist */
+ if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) {
+@@ -340,7 +532,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
pPriv->h = height;
#ifdef XF86DRI
@@ -12162,7 +12700,7 @@
RADEONDisplayTexturedVideoCP(pScrn, pPriv);
else
#endif
-@@ -370,6 +468,16 @@ static XF86VideoEncodingRec DummyEncodingR500[1] =
+@@ -370,6 +564,16 @@ static XF86VideoEncodingRec DummyEncodingR500[1] =
}
};
@@ -12179,7 +12717,7 @@
#define NUM_FORMATS 3
static XF86VideoFormatRec Formats[NUM_FORMATS] =
-@@ -471,7 +579,9 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
+@@ -471,7 +675,9 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
adapt->flags = 0;
adapt->name = "Radeon Textured Video";
adapt->nEncodings = 1;
@@ -12190,15 +12728,6 @@
adapt->pEncodings = DummyEncodingR500;
else
adapt->pEncodings = DummyEncoding;
-@@ -483,7 +593,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
- pPortPriv =
- (RADEONPortPrivPtr)(&adapt->pPortPrivates[num_texture_ports]);
-
-- if (IS_R300_3D || IS_R500_3D) {
-+ if (IS_R300_3D || IS_R500_3D || IS_R600_3D) {
- adapt->pAttributes = Attributes_r300;
- adapt->nAttributes = NUM_ATTRIBUTES_R300;
- } else {
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index c6ed472..f55ae12 100644
--- a/src/radeon_textured_videofuncs.c
@@ -12230,3 +12759,16 @@
/*
* Rendering of the actual polygon is done in two different
+diff --git a/src/radeon_video.c b/src/radeon_video.c
+index 2fb5fcc..92d1a71 100644
+--- a/src/radeon_video.c
++++ b/src/radeon_video.c
+@@ -310,7 +310,7 @@ void RADEONInitVideo(ScreenPtr pScreen)
+ } else
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n");
+ } else
+- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video requires CP on R5xx/IGP\n");
++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video requires CP on R5xx/R6xx/R7xx/IGP\n");
+ } else
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video disabled on RV250 due to HW bug\n");
+
radeon-modeset.patch:
Index: radeon-modeset.patch
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/radeon-modeset.patch,v
retrieving revision 1.35
retrieving revision 1.36
diff -u -r1.35 -r1.36
--- radeon-modeset.patch 5 Mar 2009 07:28:48 -0000 1.35
+++ radeon-modeset.patch 6 Mar 2009 23:50:06 -0000 1.36
@@ -1,904 +1,3 @@
-commit e66aba3c88e6bbd8abe0f481da28872fa17a4f57
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Mar 5 16:05:41 2009 +1000
-
- radeon: add support for relocatable CRTC inside VLINE
-
- We cannot let userspace decide which CRTC it wants because its userspace
- and might not own the crtc, so we need to provide a way to relocate it
-
-commit 00c0032dac820986b84effdb37c5cc1884eabcaf
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Mar 3 15:30:21 2009 +1000
-
- radeon: initial framebuffer resize support
-
- This relies on the kernel pinning everything which the latest
- rawhide kernel should do fine
-
-commit 354303071be3e40e5cffb97e61d1ec6475ea4685
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Mar 3 09:20:30 2009 +1000
-
- radeon: do get sarea until we know we aren't DRI2
-
-commit 908f5308463b69b89d8b7ff34b2f534fddf0fd77
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Mar 3 09:12:30 2009 +1000
-
- radeon: no need to do any of this for DRI2
-
-commit 0b144608c88ce2dfc265873cd55608f5fbd179bd
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Feb 27 12:00:29 2009 +1000
-
- fixup issues post rebase
-
-commit d6801eeb38720a7aec7c6392136382a006561a15
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Feb 26 10:47:42 2009 +1000
-
- radeon: don't init 3d engine in Xv path for drm mm
-
-commit f49b3d2a3b523cfc0ea3ec10ee1bdfdea0da9423
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Feb 17 19:14:27 2009 +1000
-
- radeon: fix vt switch for legacy paths
-
-commit cd0fd2b14d6b732e2852bf93cd4bd4cce79936bf
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Feb 17 19:13:05 2009 +1000
-
- radeon: only init gart heap for non-kms
-
-commit 6d5fc6d6ca642ceda1351b941955614a792fc5ec
-Author: Dave Airlie <airlied at redhat.com>
-Date: Sun Jan 11 09:29:44 2009 +1000
-
- radeon: drop CS1
-
-commit c1a806452b802f5284a113908109cf810d3b33be
-Author: Jerome Glisse <glisse at freedesktop.org>
-Date: Wed Nov 12 14:36:52 2008 +0100
-
- radeon: enable dri2 only if memory manager is present
- (cherry picked from commit fd4bb9b7b639befd63e7acd37254011b9e46732d)
-
-commit 48c2d0902416bfed8a5d768ea1e923b5d34c6320
-Author: Jerome Glisse <glisse at freedesktop.org>
-Date: Mon Nov 10 22:16:57 2008 +0100
-
- radeon: flush command stream in block handler and in dri2 copy callback
- (cherry picked from commit 13fa5ab73a707af52e71af400ea186073022f8b7)
-
-commit 2ea27ca1bf6fa9e96703932981e57b11e653d6a3
-Author: Jerome Glisse <glisse at freedesktop.org>
-Date: Fri Nov 14 12:44:29 2008 +0100
-
- radeon: bufmgr exa doesn't exist
- (cherry picked from commit 8a00de47a186db1707b82a5977da8cbf2e8e0c80)
-
-commit 68b3becc0620c4357872ca034fc6ae5b41432591
-Author: Jerome Glisse <glisse at freedesktop.org>
-Date: Thu Nov 6 00:25:18 2008 +0100
-
- radeon: initial dri2 support
-
-commit 1190226af0c2685557fe90cb0a5fd3446f31c672
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Dec 1 19:15:41 2008 +1000
-
- radeno: fixup unpinned buffers
- (cherry picked from commit d9759ca976cad48e6c8fd3c7d17ce38588522c34)
-
-commit eb09bc9aaee774acff6d07cae0018d020ad3ec44
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Dec 22 16:16:16 2008 +1000
-
- radeon: fix for 1.6 server
-
-commit 068107ac540d8e7bd1781799fb2b3268f3d9fe34
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Dec 19 12:37:01 2008 +1100
-
- radeon: only do mappings if direct rendering is enabled
-
-commit fa8b8dc164393bc43c6f6273aeed50924bc1d6c1
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Dec 9 13:29:18 2008 +1000
-
- radeon: upstream fix for Init3D vs switch to/from 2d/3d
-
-commit 77034ccc327b54f2f6c643e3baa9f42477fa221c
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Dec 8 14:19:47 2008 +1000
-
- radeon: only update dri buffers if DRI enabled
-
-commit 400bc21d00dfe433c3341f8c3be87f15c1b52fae
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Dec 1 15:31:08 2008 +1100
-
- radeon: don't have 2D and 3D in one CS buffer
-
-commit c25a72d143129b4cd4c8a6c16c27d13b9b173e74
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Nov 26 16:09:29 2008 +1100
-
- radeon: set touched flag on pinned buffers
-
-commit 1d2a6732029a80e8c47fc1420186941eb8f210dc
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Nov 26 16:04:35 2008 +1100
-
- radeon: fix up some of the touched by gpu handling and force gtt handling
-
- this fixes DFS on the rs690
-
-commit 434c9f580cb7350510997070b191f3202e88d24b
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Nov 26 12:52:24 2008 +1100
-
- radeon: brutal attempt to fix RS4xx and RS6xx by flushing more often
-
- this might take more CPU but hopefully leads to stabler GPU
-
-commit e6b95cd6c312e3ea785956f1d26f65724f66af46
-Author: Dave Airlie <airlied at redhat.com>
-Date: Sun Nov 23 17:56:02 2008 +1000
-
- radeon: wait for rendering before doing UTS
-
-commit a80b03a333c17334400abe0ad65c8eacf203e4e7
-Author: Dave Airlie <airlied at redhat.com>
-Date: Sun Nov 23 17:54:27 2008 +1000
-
- radeon: stop this_op_read from going negative
-
-commit d802c2d18b877b4f45057d550bf8e72136ca6143
-Author: Dave Airlie <airlied at redhat.com>
-Date: Sun Nov 23 17:52:42 2008 +1000
-
- radeon: return flush for conflicting domains
-
-commit c96555c16890ccdb148fb3b84c7544786418a599
-Author: Dave Airlie <airlied at redhat.com>
-Date: Sun Nov 23 17:50:47 2008 +1000
-
- radeon: only reset state2d before emitting cache flush
-
-commit 1c00a7c0b71cbf0161c21f3eab01670717b6fd81
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Nov 20 16:48:33 2008 +1000
-
- flush on UTS if any references
-
-commit 77cb0c5b5a1c0c4bcffbcfc0a0c55facdc0aa451
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Nov 20 16:44:40 2008 +1000
-
- radeon: add gart vs vram writes
-
-commit cdc160b2aa809f7c6cb6dd47083ea4ca0857eeac
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Nov 20 16:37:07 2008 +1000
-
- radeon: improve DFS performance for non-vram objects
-
-commit 2ff1aa8bdd2f54b46291ce8b3b9683e01f959c7d
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Nov 19 14:49:44 2008 +1000
-
- radeon: scrap state on LeaveVT not EnterVT
-
-commit a6023c6f60cb49db2479c9bd9ae1b09cfb5edf0d
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Nov 19 11:08:34 2008 +1000
-
- radeon: even more typos
-
-commit 754d9743cafbae194e2060e1b119c3b78d0f66e5
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Nov 19 07:51:03 2008 +1000
-
- radeon: oops bad typo
-
-commit fb033bc3e6fe02dc98209efef3e5d21c7b885f89
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Nov 18 16:09:10 2008 +1000
-
- radeon: even if kernels fails, struggle onwards
-
- try and keep the session going even if visual glitches happen
-
-commit 5a444b214dc743e6e9eeceb30394a97ed2580cbc
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Nov 18 15:46:46 2008 +1000
-
- radeon_bufmgr: much more complete size check functionality
-
-commit b64bca1a42abeff57e565f14fbf904329da9ebb5
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Nov 18 14:33:44 2008 +1000
-
- radeon: I fail at uint32_t division
-
-commit 551600d7f262f8e6b28d44f8682f2c20e856bc3f
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Nov 18 12:06:02 2008 +1000
-
- radeon: workaround O(wtf) logic in post_submit bufmgr
-
-commit 960d79a125e983bc547fb308cc200246b20ffeb9
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Nov 17 19:19:43 2008 +1000
-
- radeon: set emit limit to 90% VRAM
-
-commit 0906e781b9cdbe6b6aac9e1331c10b258c495768
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Nov 17 16:16:51 2008 +1000
-
- radeon: use get/set master ioctls
-
-commit 10dfd9b73060daff0d5a63d108b3bb636d706e50
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Nov 14 15:56:16 2008 +1000
-
- radeon: make space accounting a lot smarter
-
-commit 4ea0d643a90c9ad6b9dfc52c3633101c0c1404be
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Nov 14 15:55:12 2008 +1000
-
- radeon: retry on CS2 EAGAIN
-
-commit 156750c19cbebfde006c6025cee834021b0d591f
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Nov 14 15:20:59 2008 +1000
-
- radeon: add src/mask/dest to fallbacks
-
-commit fa717f5f9c30af039eb5f6b47f26f63c0942156b
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Nov 14 15:20:37 2008 +1000
-
- radeon_memory: align all allocations
-
-commit 24f17583021515c6d81d4009f84539a90a491195
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Nov 14 11:03:34 2008 +1000
-
- radeon: force gtt for mmap after fallbacks
-
-commit ed019780b9ef897f32d834b12c183d6734d4ecf7
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Nov 10 14:18:17 2008 +1000
-
- radeon: add more buffer info + fix read objects too big fallback
-
-commit 76154a56db2c4f86e61bf4310d6ea9bdb0f21ff0
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Nov 10 11:47:02 2008 +1000
-
- radeon: remove old exa bufmgr not used anymore code
-
-commit 140f511b2183ead469b61d3ffa71284fdc71b713
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Nov 10 11:18:27 2008 +1000
-
- radeon: fix crtc dpms
-
- need to find a better way to switch displays off
-
-commit 836e48ae2d8a53293d9d687724c0a25c9c5d50b5
-Author: Dave Airlie <airlied at redhat.com>
-Date: Sat Nov 8 14:48:29 2008 +1000
-
- radeon: add DPMS support for connectors
-
-commit 2ffbd858a1f8d9906836ff5c5cdb922910e5c522
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Nov 7 16:20:09 2008 +1000
-
- radeon: fix rotation of right-of heads
-
-commit 66e6d3d4f16b10c1b1a1301874a95eefa0a95cbf
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Nov 3 14:51:43 2008 +1000
-
- radeon: respect fb tex percent + trust kernel values
-
-commit bb967f80e260d5ba84b700cbebdfe83c882e4074
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Oct 31 15:05:14 2008 +1000
-
- radeon: remove workaround hack since kernel is hopefully fixed
-
-commit f2ea624ac7f8e397ebb8c2164edf77b90b14f583
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Oct 31 15:04:31 2008 +1000
-
- radeon: workaround use after free
-
-commit c39f256cb3f55b8856ff7a0cbbf425340694982f
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Oct 30 13:53:02 2008 +1000
-
- radeon: setup accel dfs for PCIE cards only if drm_mm
-
-commit 55c6ca51207871f1a713f890b1d9eca0950699ca
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Oct 30 10:00:10 2008 +1000
-
- radeon: fixup name handling for bufmgr
-
-commit a53e9ae9fdba42ee6d4ea8a8868fe94da5839ed0
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Oct 30 09:59:11 2008 +1000
-
- radeon: fix memory leak in CS2 code
-
-commit ffdb167bc74b6fdf1775e04c524d927bd248cac0
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Oct 28 20:35:19 2008 +1000
-
- return on empty IBs, flush happen in the kernel
-
-commit da8f605d63de37e7469d25afd3fa3a9f8d1f54b8
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Oct 28 10:16:09 2008 +1000
-
- radeon: remove some debugging
-
-commit c98d54139e40bcbe077be5096ef5cc8a9dbf03e7
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Oct 28 06:40:31 2008 +1000
-
- radeon: enable gem wait rendering.
-
-commit 3ae5a806eb8e7c4bcc08e214d3fdbdf4386304b6
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Oct 27 16:51:00 2008 +1000
-
- radeon: add new CS submission scheme
-
-commit 728361aa97b7fa6c7ca7f6ded9c9bb0b02d2782c
-Author: Dave Airlie <airlied at dhcp-1-203.bne.redhat.com>
-Date: Thu Oct 23 17:05:12 2008 +1000
-
- radeon: really rough effort at vram limit setting
-
-commit 03a1797d90ce550a2d5195dcd3a58abff8c7aebb
-Author: Dave Airlie <airlied at dhcp-1-203.bne.redhat.com>
-Date: Thu Oct 23 17:04:51 2008 +1000
-
- radeon: this shouldn't fail but it did once while debugging so patch up
-
-commit a0e577f5ab128b310ae00f0cabf072fc067d62b5
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Oct 23 10:43:09 2008 +1000
-
- radeon: fixup some memory allocation issues
-
- hopefully since the alignment got fixed this doesn't break anything
-
-commit e21dcdbeacf60bfebfc82c4119f2ad62e6b94c2f
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Oct 21 15:50:17 2008 +1000
-
- radeon: cleanup reserved space calcs
-
-commit 37a44646ee3fca050fec56ee6cb6ccd7c3181673
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Oct 21 15:49:48 2008 +1000
-
- radeon: fixup Owen's optimisation - this fixes corruption
-
- I haven't a good explaination why mapping the buffer twice in a row
- seems to cause this failure. but I probably don't have time to track
- it down before release.
-
-commit e04c58e4f1b5fece2601603dd5d14fdfe92727d2
-Author: Dave Airlie <airlied at redhat.com>
-Date: Sun Oct 19 18:27:53 2008 +1000
-
- radeon: fixup tex offset for no modeset
-
-commit 20521bd438fa3bbc00cc7c131ad143353c922d3d
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Oct 15 17:01:34 2008 +1000
-
- radeon: add DFS support for CS
-
-commit a72197efa5acb5086ef1aad5596276addefe08ba
-Author: airlied <airlied at unused-12-220.bne.redhat.com>
-Date: Wed Oct 15 23:55:13 2008 +1000
-
- radeon: add r100/r200 support for EXA render
-
-commit b0afa63afc461fb61fc9a545ad7b31c4bdca28a5
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Oct 13 16:59:02 2008 +1000
-
- radeon: fix switch mode path so nexuiz starts
-
-commit 70ef5d335475b1bbab524a842a202b9776051921
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Oct 10 15:29:24 2008 +1000
-
- remove gem buf caching useless on radeon
-
-commit a433033f8c6d6d0b9a34689c0387e3043067535f
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Oct 10 15:18:41 2008 +1000
-
- radeon: drmmode make names same as for non-kms drivers
-
-commit 4b8c3d5cedb4fc1f9872d35ab0b2fc462488e6a3
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Oct 10 15:10:28 2008 +1000
-
- radeon: fix rotation under kms
-
-commit 8f68fe2151503466e0e27b1d84c22f445952313e
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Oct 10 14:44:39 2008 +1000
-
- radeon: remove testing fallback
-
-commit b656b31ac14003b1925656ab4941baff850b37dd
-Author: Kristian Høgsberg <krh at redhat.com>
-Date: Fri Oct 10 10:57:47 2008 +1100
-
- radeon: add copy fb contents patch
-
-commit 5b30500df1595ac9fd4a4ebc555536a3736dc2a0
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Oct 10 10:57:20 2008 +1100
-
- bufmgr: turn off debug
-
-commit 15ebeac41bdf7a24389634db16284a0f0e0ff537
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Oct 10 10:38:38 2008 +1100
-
- radeon: fixup modesetting code after rebasing to master
-
-commit 8cad0abd7717e4d24201a19dd9921f8a28f8176d
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Oct 9 16:34:52 2008 +1100
-
- radeon: misc cleanups in exa
-
-commit 4da0198297cd08d7c723a23c7c13beeccbb4d07f
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Oct 9 16:34:23 2008 +1100
-
- radeon: fix UTS for non-modesetting
-
-commit 4d713860077916e547cec30441766aedd0ec54e5
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Oct 9 16:33:59 2008 +1100
-
- radeon: fix exa limits problem - shouldn't have been resetting scissor
-
-commit f4dcb33ab67d884a6cd2e6ad08e7a25870ff4b3a
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Oct 1 11:21:53 2008 +1000
-
- radeon: fixup for latest libdrm changes
-
-commit 08139fafdc537de8d83054c7e63767b161016f5d
-Author: Owen Taylor <otaylor at localhost.localdomain>
-Date: Fri Sep 26 16:17:49 2008 -0400
-
- Don't flush when mapping a newly created pixmap into system ram If we have a pixmap that has never been mapped into vram (and thus never written to by the GPU), there is no need to flush the graphics pipeline and wait for idle before starting to write to it.
-
-commit c05eddc144ebc7187417ffa30927f9f1b116b2eb
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Sep 29 16:32:51 2008 +1000
-
- radeon: hopefully fix textured xv
-
-commit 308d3c763e3e805fc06e4f83aaf6115c4c547b09
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Sep 26 11:38:36 2008 +1000
-
- radeon: fix the offset checks for command submission
-
- since we are relocating in the kernel we don't need these
-
-commit 5b6c1015fbe516d2581a2337e07e0e9b8412746b
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Sep 26 10:46:20 2008 +1000
-
- radeon: fixup after mertge
-
-commit 5192b6bed534056d160341684b53cec6880eedf5
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Sep 26 10:34:41 2008 +1000
-
- radeon: fix issues with emitting DST PIPE on cards that don't use it
-
-commit 7741152ce929278f5768cbafcd3eeb22be84d36d
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Sep 24 17:12:19 2008 +1000
-
- modesetting: fixup bits of drmmode_display.c
-
-commit 519250b04b5eccd42ac977052f16d29477b6fe45
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Sep 24 15:42:01 2008 +1000
-
- r600: fixup for kms
-
-commit a50fc6c938ec6774ce5eb901f957304b792456a4
-Author: Dave Airlie <airlied at redhat.com>
-Date: Sun Sep 7 08:01:56 2008 +1000
-
- modeset: fix AddFB for current tree
-
-commit 1acfa20073823b399d72ab58d69f32b4d4ec2297
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Aug 14 10:52:52 2008 +1000
-
- radeon: disable overlay for modesetting for now
-
-commit c981de57577f6ea57ba455a414fc7eb015acfcbf
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Aug 14 10:52:42 2008 +1000
-
- radeon: no need for this anymore
-
-commit 773fd7a81cd7404c4adcf0f549e710fcc03fca9f
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Sep 5 16:32:01 2008 +1000
-
- radeon: fix up for suspend/resume - uses new API
-
-commit bbb87f49273cc12f366506ba52d976eefd4690f5
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Aug 27 13:09:55 2008 +1000
-
- radeon: update to proper domain
-
- this should fix 3d again for now at least
-
-commit 0dd982c1e3263a8e39c5ea9a6fe254275217725c
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Aug 26 18:29:23 2008 +1000
-
- ddx: move to using new gem interface
-
- add a GEM bufmgr backend along the lines of Intels one.
-
- The buffer reuse is disabled and I'll probably rip it out for radeon
- as we can't just re-use buffers that might have ended up in VRAM etc.
-
- Probably need some sort of in-kernel re-use.
-
-commit 0cc73177663be1897fbdaab57d6903dae7f6df1b
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Aug 25 11:37:48 2008 +1000
-
- radeon: add an initial GEM bufmgr
-
-commit 5fef64ad52b7e91ea0e416b9d4e6d2c829ae8f07
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Aug 25 11:37:20 2008 +1000
-
- radeon: implement simple UTS
-
-commit 55565e480631ce30e1abfaf6e3220001006383fb
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Aug 22 15:34:58 2008 +1000
-
- radeon: add read/write domains properly
-
-commit 5d318501c57643513a95622a6e795f0e305d7b48
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Aug 15 11:25:31 2008 +1000
-
- radeon: fix some rotate bugs
-
-commit 6671103f8e609d608c882c27de26b2f803c8edc2
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Aug 15 11:16:18 2008 +1000
-
- radeon: when create fake bos, they are already mapped
-
-commit 77b2173406ed875e8196fb734c2d1cdce582af1c
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Aug 15 11:15:58 2008 +1000
-
- exa: remove wrong assert
-
-commit 750aca4cdc9f2d324a5d23c350a217261d3f5d84
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Aug 12 19:27:44 2008 +1000
-
- radeon: start to work on rotate pixmap support
-
-commit 927b541d3ef8c01887677dda54689ea2c38872bd
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Aug 12 18:28:23 2008 +1000
-
- radeon: port simple exa bufmgr
-
- exa pixmaps work now but they are slow
-
-commit 09472769aa55bda09be76afd0fda1b1eb713a95c
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Aug 7 17:52:04 2008 +1000
-
- further pixmaps on EXA
-
-commit 0c2079cc5c3ecdbd9a2b77103546540b22ad581e
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Aug 7 11:22:46 2008 +1000
-
- initial exa on gem hackx
-
- Conflicts:
-
- src/radeon_exa.c
- src/radeon_memory.c
-
-commit 77d86019b6881ac49c2a3397aaf6ff13ceae8f3d
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Aug 12 15:31:03 2008 +1000
-
- radeon: initial rotate pixmap
-
- This doesn't work, we really need EXA pixmaps for this stuff
-
-commit aa89d1e78d34f4d9f86442135ebaa8b1b353b000
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Aug 12 14:40:18 2008 +1000
-
- radeon: use buffer names
-
-commit 47b650b53ca9cbf1298717ea49849a98f75ada55
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Aug 12 14:38:56 2008 +1000
-
- ati: fix do adjust mode
-
-commit 9aa2c37674e7e92a590f55f671aebf969b5a2653
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Aug 12 09:38:48 2008 +1000
-
- FEDORA: update offsets in DRI private
-
-commit 4a803ac551df2c84174faeaf45d9fcb35215dc95
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Aug 12 09:10:18 2008 +1000
-
- radeon: add vt bind flag
-
-commit 2dc1897cf0cf90ea7eea39ee70f10b0fccfef0a2
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Aug 6 13:30:54 2008 +1000
-
- radeon: warning cleanups
-
-commit f25d18044a08ecd451585162fe8d51129cbd65c8
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Aug 6 13:18:52 2008 +1000
-
- radeon: remove debugging
-
-commit 963d1a62cf51b834183dab1d3312ef20262c2ec4
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Aug 6 13:17:31 2008 +1000
-
- radeon: add code to set memory map and not futz with mappings
-
-commit 03c3c7aeff5108917a2d4283c1715f03c3f3b41d
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Aug 6 13:16:56 2008 +1000
-
- drm: don't futz with framebuffer when no drm_mm
-
-commit 3b5773862110a7513801d1cd8929f5c33cb44208
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Aug 5 16:47:21 2008 +1000
-
- radeon: undef OUT_RELOC
-
-commit 55b5e2297b40ad4b296d91ce7d8520ec19cedbea
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Aug 5 16:37:52 2008 +1000
-
- radeon: add stdint/lib to check for modesetting
-
-commit 0b515d8f217583ce432715b5d3abc8468597f60c
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Aug 5 16:07:31 2008 +1000
-
- fix whitespace
-
-commit 6b492d113905257a1b12586eafb93a1c21649dfd
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Aug 5 16:07:07 2008 +1000
-
- radeon: fix build issue
-
-commit c9ff3947e40716847fe1ce0187c83c073ba4d9c8
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Aug 4 16:27:55 2008 +1000
-
- radeon: free all pinned memory on server shutdown
-
-commit 8872b1bdc623eaccb746862d4e2d881afb1c3923
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Aug 4 16:11:30 2008 +1000
-
- radeon: get textured video working on the memory manager
-
-commit bf51c8f1d2023eec5ce9b621c3c2caf6ffc11cc8
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Aug 4 16:11:18 2008 +1000
-
- radeon: convert bus addr to void pointer
-
-commit e616681225088fdb6784c1df4cbbfa63b4d3bc1d
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Aug 4 15:11:13 2008 +1000
-
- radeon: avoid z cache flushes if not needed
-
-commit efec614d5a5cab051968810a10f5dc1620a42146
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Jul 30 17:04:22 2008 +1000
-
- radeon: update DRI support, so mappings get added
-
- We only add fake frontbuffer mapping as DRI clients expect one.
-
-commit 23c37b78d7af1874e5a63251eb44231e91b8300c
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Jul 29 16:50:03 2008 +1000
-
- radeon: exa through the handle relocation function
-
-commit d0527a52ee83562b442b006a59eb03f41c4889a5
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Jul 29 14:58:22 2008 +1000
-
- radeon: keep track of 2D state
-
- This lets the kernel use the 2D blit engine in theory
-
-commit 0d9dcbc26f04a606c498b47d1c0228a6906b9518
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Jul 28 17:48:59 2008 +1000
-
- new command submission attempt
-
-commit 69ce5d53c186bbd3dce93909e94f12855e6b296e
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Jul 28 17:48:08 2008 +1000
-
- radeon: fixup over fluishing problem
-
-commit d92685f8f9bb7e240822bbdd1a1d2424542b7d50
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Jul 28 17:44:51 2008 +1000
-
- hack for now: divide texture size by 2
-
-commit 2c0ce08b8e2e32e4cbaf6f4271ab95369da73954
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Jul 25 17:07:20 2008 +1000
-
- radeon: fix dri message
-
-commit 769fdab086f42d64cacf73fc07175a6811d6e3dd
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Jul 25 15:11:58 2008 +1000
-
- radeon: fix pool which caused memory corruption
-
-commit 79ae58c84558ef4ad3c021f842b16c8621eb7d20
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Jul 25 14:59:07 2008 +1000
-
- radeon: get DRI to attempt to start up
-
-commit 80fae5b9af8b8d7a4907fae2d607668170de8d85
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Jul 25 14:58:23 2008 +1000
-
- radeon: call the right sync function
-
-commit 50497f43feb52ffc0cfa1420a6509e15b0bd2a82
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Jul 25 14:57:21 2008 +1000
-
- radeon: unmap memory from objects
-
-commit 02e4a3ab2f955415ca1b52f0c860d54edb60d99e
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Jul 23 10:59:16 2008 +1000
-
- use CP for 3D engine with modeset
-
-commit b7c23b09e1ced1b36cafeb150c58605a4c7699c4
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Jul 23 10:59:04 2008 +1000
-
- radeon: fix DFS
-
-commit e3a5ff240714ea5871e95f2a8ba74c3419cf6bb7
-Author: Dave Airlie <airlied at redhat.com>
-Date: Wed Jul 23 10:48:45 2008 +1000
-
- radeon: get the fb location right
-
-commit 2cb38725c09f6c80cdf7ef0db95e065f74a57cf4
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Jul 22 18:08:25 2008 +1000
-
- radeon: make at least the EXA stipple work..
-
-commit bcf36a6c8360fcec90d2430d58b6ac8e282b57f8
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Jul 22 18:07:15 2008 +1000
-
- radeon: disable debugging for now
-
-commit 2598b49272cffc937bb2c449868d2e0dd2c4d719
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Jul 21 18:40:14 2008 +1000
-
- radeon: initial indirect buffer use.
-
- Move EXA and front allocation into one big buffer to workaround
- EXA issues - need to move to driver pixmap hooks.
-
- Add new indirect GEM to take indirect buffers.
-
- doesn't work think the offsets are all wrong.
-
-commit 4a91206107a218747bea080f721dce253638eac4
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Jul 18 13:46:41 2008 +1000
-
- modesetting step 1: have X and a cursor
-
-commit 9a7fbdd2ccb4073f7cbcc48e8d65d430cbb08b3a
-Author: Dave Airlie <airlied at redhat.com>
-Date: Thu Jul 17 09:59:19 2008 +1000
-
- radeon: add radeon_memory.c
-
-commit e516b7612d2fcfe115306f8de049feebe463a0fd
-Author: Dave Airlie <airlied at redhat.com>
-Date: Tue Jul 8 16:55:27 2008 +1000
-
- remove mappings of some buffers.
-
- use drm gart code if available
-
-commit 2e0da77a17f9c6767a602e09ed60a5de91f3e5cb
-Author: Dave Airlie <airlied at redhat.com>
-Date: Mon Jul 7 16:54:35 2008 +1000
-
- add initial support for a kernel memory manager
-
- This just pins all the current allocations via the kernel memory manager
- instead of trying to do them all in userspace.
-
- useful steps towards getting kernel modesetting
-
-commit a4a1143fbfd783a9278c8b9aa7997011c9f4852f
-Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Jul 4 10:39:34 2008 +1000
-
- port to using drm header files
diff --git a/configure.ac b/configure.ac
index b094a50..29a19e3 100644
--- a/configure.ac
@@ -3506,7 +2605,7 @@
xf86CrtcPtr crtc = xf86_config->crtc[c];
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
-index 45f79ed..318ebc0 100644
+index 2b7540c..6a24ae2 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -40,6 +40,8 @@
@@ -3750,7 +2849,7 @@
}
/* AGP Mode Quirk List - Certain hostbridge/gfx-card combos don't work with
-@@ -988,6 +1144,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -990,6 +1146,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[agp] ring handle = 0x%08x\n",
(unsigned int)info->dri->ringHandle);
@@ -3759,7 +2858,7 @@
if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
&info->dri->ring) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n");
-@@ -996,9 +1154,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -998,9 +1156,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Ring mapped at 0x%08lx\n",
(unsigned long)info->dri->ring);
@@ -3771,7 +2870,7 @@
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not add ring read ptr mapping\n");
return FALSE;
-@@ -1007,6 +1166,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1009,6 +1168,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[agp] ring read ptr handle = 0x%08x\n",
(unsigned int)info->dri->ringReadPtrHandle);
@@ -3780,7 +2879,7 @@
if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize,
&info->dri->ringReadPtr) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
-@@ -1016,6 +1177,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1018,6 +1179,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Ring read ptr mapped at 0x%08lx\n",
(unsigned long)info->dri->ringReadPtr);
@@ -3788,7 +2887,7 @@
if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize,
DRM_AGP, 0, &info->dri->bufHandle) < 0) {
-@@ -1093,6 +1255,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1095,6 +1257,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[pci] ring handle = 0x%08x\n",
(unsigned int)info->dri->ringHandle);
@@ -3796,7 +2895,7 @@
if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
&info->dri->ring) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n");
-@@ -1104,6 +1267,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1106,6 +1269,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring contents 0x%08lx\n",
*(unsigned long *)(pointer)info->dri->ring);
@@ -3804,7 +2903,7 @@
if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize,
DRM_SCATTER_GATHER, flags, &info->dri->ringReadPtrHandle) < 0) {
-@@ -1115,8 +1279,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1117,8 +1281,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[pci] ring read ptr handle = 0x%08x\n",
(unsigned int)info->dri->ringReadPtrHandle);
@@ -3815,7 +2914,7 @@
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not map ring read ptr\n");
return FALSE;
-@@ -1127,6 +1293,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1129,6 +1295,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring read ptr contents 0x%08lx\n",
*(unsigned long *)(pointer)info->dri->ringReadPtr);
@@ -3823,7 +2922,7 @@
if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize,
DRM_SCATTER_GATHER, 0, &info->dri->bufHandle) < 0) {
-@@ -1179,6 +1346,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1181,6 +1348,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
*/
static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
@@ -3833,7 +2932,7 @@
/* Map registers */
info->dri->registerSize = info->MMIOSize;
if (drmAddMap(info->dri->drmFD, info->MMIOAddr, info->dri->registerSize,
-@@ -1219,20 +1389,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1221,20 +1391,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
drmInfo.fb_bpp = info->CurrentLayout.pixel_code;
drmInfo.depth_bpp = (info->dri->depthBits - 8) * 2;
@@ -3871,7 +2970,7 @@
if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT,
&drmInfo, sizeof(drm_radeon_init_t)) < 0)
return FALSE;
-@@ -1241,8 +1414,9 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1243,8 +1416,9 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
* registers back to their default values, so we need to restore
* those engine register here.
*/
@@ -3883,7 +2982,7 @@
return TRUE;
}
-@@ -1440,12 +1614,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
+@@ -1442,12 +1616,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
/* Get DRM version & close DRM */
info->dri->pKernelDRMVersion = drmGetVersion(fd);
@@ -3897,7 +2996,7 @@
}
/* Now check if we qualify */
-@@ -1479,10 +1652,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
+@@ -1481,10 +1654,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
req_patch);
drmFreeVersion(info->dri->pKernelDRMVersion);
info->dri->pKernelDRMVersion = NULL;
@@ -3928,7 +3027,7 @@
}
Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
-@@ -1491,6 +1683,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
+@@ -1493,6 +1685,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int value = 0;
@@ -3938,7 +3037,7 @@
if (!info->want_vblank_interrupts)
on = FALSE;
-@@ -1510,6 +1705,52 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
+@@ -1512,6 +1707,52 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
return TRUE;
}
@@ -3991,7 +3090,7 @@
/* Initialize the screen-specific data structures for the DRI and the
* Radeon. This is the main entry point to the device-specific
-@@ -1573,10 +1814,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+@@ -1575,10 +1816,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4;
pDRIInfo->ddxDriverMinorVersion = 3;
pDRIInfo->ddxDriverPatchVersion = 0;
@@ -4018,7 +3117,7 @@
pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES;
pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES
< RADEON_MAX_DRAWABLES
-@@ -1629,9 +1882,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+@@ -1631,9 +1884,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d;
pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d;
pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d;
@@ -4029,7 +3128,7 @@
pDRIInfo->ClipNotify = RADEONDRIClipNotify;
#endif
-@@ -1663,57 +1914,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+@@ -1665,57 +1916,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo = NULL;
return FALSE;
}
@@ -4134,7 +3233,7 @@
static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
-@@ -1755,17 +2009,21 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
+@@ -1757,17 +2011,21 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
return FALSE;
}
@@ -4164,7 +3263,7 @@
/* Initialize and start the CP if required */
RADEONDRICPInit(pScrn);
-@@ -1774,6 +2032,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
+@@ -1776,6 +2034,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
pSAREAPriv = (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScreen);
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
@@ -4175,7 +3274,7 @@
pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate;
pRADEONDRI->deviceID = info->Chipset;
-@@ -1931,6 +2193,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
+@@ -1933,6 +2195,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
drmUnmap(info->dri->buf, info->dri->bufMapSize);
info->dri->buf = NULL;
}
@@ -4184,7 +3283,7 @@
if (info->dri->ringReadPtr) {
drmUnmap(info->dri->ringReadPtr, info->dri->ringReadMapSize);
info->dri->ringReadPtr = NULL;
-@@ -1939,6 +2203,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
+@@ -1941,6 +2205,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
drmUnmap(info->dri->ring, info->dri->ringMapSize);
info->dri->ring = NULL;
}
@@ -4192,7 +3291,7 @@
if (info->dri->agpMemHandle != DRM_AGP_NO_HANDLE) {
drmAgpUnbind(info->dri->drmFD, info->dri->agpMemHandle);
drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle);
-@@ -2344,3 +2609,11 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
+@@ -2346,3 +2611,11 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
&radeonsetparam, sizeof(drm_radeon_setparam_t));
return ret;
}
@@ -4963,7 +4062,7 @@
+
+#endif
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
-index 7cac321..b65bb51 100644
+index 0842164..c61a722 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -67,7 +67,7 @@
@@ -5175,7 +4274,7 @@
info->cp->CPInUse = FALSE;
info->cp->CPStarted = FALSE;
info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
-@@ -2704,6 +2735,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = {
+@@ -2701,6 +2732,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = {
RADEONCRTCResize
};
@@ -5213,7 +4312,7 @@
Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
{
xf86CrtcConfigPtr xf86_config;
-@@ -2724,6 +2786,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2721,6 +2783,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
info = RADEONPTR(pScrn);
info->MMIO = NULL;
@@ -5222,7 +4321,7 @@
info->IsSecondary = FALSE;
info->IsPrimary = FALSE;
-@@ -2758,62 +2822,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2755,62 +2819,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
}
info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
@@ -5333,7 +4432,7 @@
if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive))
goto fail;
-@@ -2823,10 +2888,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2820,10 +2885,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR;
pScrn->monitor = pScrn->confScreen->monitor;
@@ -5350,7 +4449,7 @@
if (!RADEONPreInitVisual(pScrn))
goto fail;
-@@ -2840,136 +2907,198 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2837,154 +2904,216 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions));
xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
@@ -5577,21 +4676,49 @@
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n");
+ goto fail;
+ }
-+
-+ ErrorF("after xf86InitialConfiguration\n");
- ErrorF("before xf86InitialConfiguration\n");
-+ } else {
-+#ifdef XF86DRM_MODE
-+ char *bus_id;
-+ if (!radeon_alloc_dri(pScrn))
-+ return FALSE;
++ /* fix up cloning on rn50 cards
++ * since they only have one crtc sometimes the xserver doesn't assign
++ * a crtc to one of the outputs even though both outputs have common modes
++ * which results in only one monitor being enabled. Assign a crtc here so
++ * that both outputs light up.
++ */
++ if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
++ int i;
++
++ for (i = 0; i < xf86_config->num_output; i++) {
++ xf86OutputPtr output = xf86_config->output[i];
++
++ /* XXX: double check crtc mode */
++ if ((output->probed_modes != NULL) && (output->crtc == NULL))
++ output->crtc = xf86_config->crtc[0];
++ }
++ }
- if (!xf86InitialConfiguration (pScrn, FALSE))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n");
- goto fail;
- }
++ ErrorF("after xf86InitialConfiguration\n");
+
+- /* fix up cloning on rn50 cards
+- * since they only have one crtc sometimes the xserver doesn't assign
+- * a crtc to one of the outputs even though both outputs have common modes
+- * which results in only one monitor being enabled. Assign a crtc here so
+- * that both outputs light up.
+- */
+- if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
+- int i;
++ } else {
++#ifdef XF86DRM_MODE
++ char *bus_id;
++ if (!radeon_alloc_dri(pScrn))
++ return FALSE;
+
+- for (i = 0; i < xf86_config->num_output; i++) {
+- xf86OutputPtr output = xf86_config->output[i];
+ bus_id = DRICreatePCIBusID(info->PciInfo);
+ if (drmmode_pre_init(pScrn, &info->drmmode, bus_id, "radeon", pScrn->bitsPerPixel / 8) == FALSE) {
+ xfree(bus_id);
@@ -5599,7 +4726,9 @@
+ goto fail;
+ }
-- ErrorF("after xf86InitialConfiguration\n");
+- /* XXX: double check crtc mode */
+- if ((output->probed_modes != NULL) && (output->crtc == NULL))
+- output->crtc = xf86_config->crtc[0];
+ info->dri->drmFD = info->drmmode.fd;
+ info->dri2.drm_fd = info->drmmode.fd;
+ info->dri2.enabled = FALSE;
@@ -5638,13 +4767,15 @@
+ if (info->ChipFamily < CHIP_FAMILY_R600) {
+ info->useEXA = TRUE;
+ info->directRenderingEnabled = TRUE;
-+ }
+ }
+ info->new_cs = TRUE;
+ info->drm_mm = TRUE;
+ // info->directRenderingDisabled = FALSE;
+#endif
-+ }
+ }
+- ErrorF("after xf86InitialConfiguration\n");
+-
RADEONSetPitch(pScrn);
- /* Set display resolution */
@@ -5654,7 +4785,7 @@
/* Get ScreenInit function */
if (!xf86LoadSubModule(pScrn, "fb")) return FALSE;
-@@ -2984,10 +3113,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2999,10 +3128,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
if (!RADEONPreInitXv(pScrn)) goto fail;
}
@@ -5671,7 +4802,7 @@
}
if (pScrn->modes == NULL) {
-@@ -3140,6 +3271,9 @@ static void RADEONBlockHandler(int i, pointer blockData,
+@@ -3155,6 +3286,9 @@ static void RADEONBlockHandler(int i, pointer blockData,
#ifdef USE_EXA
info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
@@ -5681,7 +4812,7 @@
#endif
}
-@@ -3228,7 +3362,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3243,7 +3377,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
int subPixelOrder = SubPixelUnknown;
char* s;
#endif
@@ -5690,7 +4821,7 @@
info->accelOn = FALSE;
#ifdef USE_XAA
-@@ -3248,58 +3382,61 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3263,58 +3397,61 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
"RADEONScreenInit %lx %ld\n",
pScrn->memPhysBase, pScrn->fbOffset);
#endif
@@ -5791,7 +4922,7 @@
/* Visual setup */
miClearVisualTypes();
if (!miSetVisualTypes(pScrn->depth,
-@@ -3333,19 +3470,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3348,19 +3485,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
hasDRI = info->directRenderingEnabled;
#endif /* XF86DRI */
@@ -5825,7 +4956,7 @@
}
}
-@@ -3382,7 +3521,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3397,7 +3536,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#ifdef XF86DRI
if (hasDRI) {
info->accelDFS = xf86ReturnOptValBool(info->Options, OPTION_ACCEL_DFS,
@@ -5837,7 +4968,7 @@
/* Reserve approx. half of offscreen memory for local textures by
* default, can be overridden with Option "FBTexPercent".
-@@ -3408,7 +3550,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3423,7 +3565,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#endif
#if defined(XF86DRI) && defined(USE_XAA)
@@ -5846,7 +4977,7 @@
info->dri->textureSize = -1;
if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT,
&(info->dri->textureSize))) {
-@@ -3426,7 +3568,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3441,7 +3583,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#endif
#ifdef USE_XAA
@@ -5855,7 +4986,7 @@
return FALSE;
#endif
-@@ -3447,7 +3589,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3462,7 +3604,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
info->CurrentLayout.pixel_bytes);
int maxy = info->FbMapSize / width_bytes;
@@ -5864,7 +4995,7 @@
xf86DrvMsg(scrnIndex, X_ERROR,
"Static buffer allocation failed. Disabling DRI.\n");
xf86DrvMsg(scrnIndex, X_ERROR,
-@@ -3457,19 +3599,54 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3472,19 +3614,54 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024);
info->directRenderingEnabled = FALSE;
} else {
@@ -5923,7 +5054,7 @@
#endif
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Initializing fb layer\n");
-@@ -3493,7 +3670,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3508,7 +3685,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (info->r600_shadow_fb == FALSE) {
/* Init fb layer */
@@ -5932,7 +5063,7 @@
pScrn->virtualX, pScrn->virtualY,
pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
pScrn->bitsPerPixel))
-@@ -3535,8 +3712,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3550,8 +3727,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* restore the memory map here otherwise we may get a hang when
* initializing the drm below
*/
@@ -5945,7 +5076,7 @@
/* Backing store setup */
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-@@ -3546,7 +3725,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3561,7 +3740,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* DRI finalisation */
#ifdef XF86DRI
@@ -5954,7 +5085,7 @@
info->dri->pKernelDRMVersion->version_minor >= 19)
{
if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0)
-@@ -3562,14 +3741,24 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3577,14 +3756,24 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (info->directRenderingEnabled) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"DRI Finishing init !\n");
@@ -5980,7 +5111,7 @@
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
-@@ -3665,10 +3854,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3680,10 +3869,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
return FALSE;
}
}
@@ -5998,7 +5129,7 @@
/* Provide SaveScreen & wrap BlockHandler and CloseScreen */
/* Wrap CloseScreen */
-@@ -5245,7 +5440,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5260,7 +5455,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
#ifdef XF86DRI
Bool CPStarted = info->cp->CPStarted;
@@ -6007,7 +5138,7 @@
DRILock(pScrn->pScreen, 0);
RADEONCP_STOP(pScrn, info);
}
-@@ -5268,8 +5463,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5283,8 +5478,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
#endif
}
@@ -6020,7 +5151,7 @@
ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0);
-@@ -5281,16 +5478,19 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5296,16 +5493,19 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
/* xf86SetRootClip would do, but can't access that here */
}
@@ -6048,7 +5179,7 @@
}
#endif
-@@ -5488,6 +5688,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
+@@ -5503,6 +5703,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
xf86OutputPtr output = config->output[config->compat_output];
xf86CrtcPtr crtc = output->crtc;
@@ -6060,7 +5191,7 @@
/* not handled */
if (IS_AVIVO_VARIANT)
return;
-@@ -5527,76 +5732,103 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
+@@ -5542,76 +5747,103 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONEnterVT\n");
@@ -6213,7 +5344,7 @@
}
#endif
/* this will get XVideo going again, but only if XVideo was initialised
-@@ -5611,7 +5843,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
+@@ -5626,7 +5858,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
info->accel_state->XInited3D = FALSE;
#ifdef XF86DRI
@@ -6222,7 +5353,7 @@
RADEONCP_START(pScrn, info);
DRIUnlock(pScrn->pScreen);
}
-@@ -5634,26 +5866,28 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+@@ -5649,26 +5881,28 @@ void RADEONLeaveVT(int scrnIndex, int flags)
"RADEONLeaveVT\n");
#ifdef XF86DRI
if (RADEONPTR(pScrn)->directRenderingInited) {
@@ -6266,7 +5397,7 @@
/* Make sure 3D clients will re-upload textures to video RAM */
if (info->dri->textureSize) {
-@@ -5669,6 +5903,11 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+@@ -5684,6 +5918,11 @@ void RADEONLeaveVT(int scrnIndex, int flags)
i = list[i].next;
} while (i != 0);
}
@@ -6278,7 +5409,7 @@
}
#endif
-@@ -5695,10 +5934,18 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+@@ -5710,10 +5949,18 @@ void RADEONLeaveVT(int scrnIndex, int flags)
xf86_hide_cursors (pScrn);
@@ -6300,7 +5431,7 @@
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Ok, leaving now...\n");
-@@ -5752,7 +5999,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
+@@ -5767,7 +6014,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
#endif /* USE_XAA */
if (pScrn->vtSema) {
@@ -6310,7 +5441,7 @@
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-@@ -5787,6 +6035,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
+@@ -5802,6 +6050,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
info->DGAModes = NULL;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Unmapping memory\n");
@@ -8834,10 +7965,10 @@
+}
+
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
-index f072b9c..6d31e39 100644
+index afc8e21..6138f36 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
-@@ -145,6 +145,27 @@ typedef struct
+@@ -146,6 +146,27 @@ typedef struct
Bool hw_capable;
} RADEONI2CBusRec, *RADEONI2CBusPtr;
@@ -8865,7 +7996,7 @@
typedef struct _RADEONCrtcPrivateRec {
void *crtc_rotate_mem;
void *cursor_mem;
-@@ -158,6 +179,8 @@ typedef struct _RADEONCrtcPrivateRec {
+@@ -159,6 +180,8 @@ typedef struct _RADEONCrtcPrivateRec {
int can_tile;
Bool enabled;
Bool initialized;
@@ -8875,7 +8006,7 @@
typedef struct _radeon_encoder {
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
-index cbedb7e..da60494 100644
+index 2df299f..72d60e2 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -40,6 +40,7 @@
@@ -8910,7 +8041,7 @@
#include "radeon_textured_videofuncs.c"
-@@ -298,6 +302,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+@@ -374,6 +378,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
size * 2, 64);
if (pPriv->video_offset == 0)
return BadAlloc;
@@ -8920,7 +8051,7 @@
}
/* Bicubic filter setup */
-@@ -321,6 +328,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+@@ -397,6 +404,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
pPriv->bicubic_src_offset = pPriv->bicubic_offset + info->fbLocation + pScrn->fbOffset;
if (pPriv->bicubic_offset == 0)
pPriv->bicubic_enabled = FALSE;
@@ -8930,7 +8061,7 @@
}
if (pDraw->type == DRAWABLE_WINDOW)
-@@ -350,11 +360,22 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+@@ -426,11 +436,22 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
left = (x1 >> 16) & ~1;
npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left;
@@ -8958,13 +8089,15 @@
pPriv->src_pitch = dstPitch;
pPriv->size = size;
pPriv->pDraw = pDraw;
-@@ -417,8 +438,24 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+@@ -510,10 +531,23 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
}
/* Upload bicubic filter tex */
-- if (pPriv->bicubic_enabled)
-- RADEONCopyData(pScrn, (uint8_t *)bicubic_tex_512, (uint8_t *)(info->FB + pPriv->bicubic_offset), 1024, 1024, 1, 512, 2);
-+ if (pPriv->bicubic_enabled) {
+- if (pPriv->bicubic_enabled) {
+- if (info->ChipFamily < CHIP_FAMILY_R600)
+- RADEONCopyData(pScrn, (uint8_t *)bicubic_tex_512,
+- (uint8_t *)(info->FB + pPriv->bicubic_offset), 1024, 1024, 1, 512, 2);
++ if (pPriv->bicubic_enabled && info->ChipFamily < CHIP_FAMILY_R600) {
+ uint8_t *bicubic_addr;
+ int ret;
+
@@ -8981,11 +8114,10 @@
+
+ if (info->new_cs)
+ dri_bo_unmap(pPriv->bicubic_bo);
-+ }
+ }
/* update cliplist */
- if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) {
-@@ -435,10 +472,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+@@ -531,10 +565,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
pPriv->w = width;
pPriv->h = height;
@@ -9183,7 +8315,7 @@
RADEON_COLOR_ARG_A_ZERO |
RADEON_COLOR_ARG_B_ZERO |
diff --git a/src/radeon_video.c b/src/radeon_video.c
-index 2fb5fcc..33a4fd6 100644
+index 92d1a71..c953618 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -287,7 +287,7 @@ void RADEONInitVideo(ScreenPtr pScreen)
Index: xorg-x11-drv-ati.spec
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/xorg-x11-drv-ati.spec,v
retrieving revision 1.153
retrieving revision 1.154
diff -u -r1.153 -r1.154
--- xorg-x11-drv-ati.spec 5 Mar 2009 07:28:50 -0000 1.153
+++ xorg-x11-drv-ati.spec 6 Mar 2009 23:50:06 -0000 1.154
@@ -5,7 +5,7 @@
Summary: Xorg X11 ati video driver
Name: xorg-x11-drv-ati
Version: 6.11.0
-Release: 4%{?dist}
+Release: 5%{?dist}
URL: http://www.x.org
License: MIT
Group: User Interface/X Hardware Support
@@ -76,6 +76,9 @@
%{_mandir}/man4/radeon.4*
%changelog
+* Sat Mar 07 2009 Dave Airlie <airlied at redhat.com> 6.11.0-5
+- pull in more fixes from master
+
* Thu Mar 05 2009 Dave Airlie <airlied at redhat.com> 6.11.0-4
- modeset: fixup radeon Xv with latest kernel
- Previous message (by thread): rpms/rosegarden4/devel .cvsignore, 1.6, 1.7 rosegarden4.spec, 1.10, 1.11 sources, 1.6, 1.7 rosegarden-1.5.1-desktop-file.patch, 1.1, NONE rosegarden-1.6.0-fix-cmake-optflags.patch, 1.1, NONE rosegarden-1.6.1-gcc43.patch, 1.1, NONE
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