rpms/kernel/devel drm-nouveau.patch, 1.18, 1.19 kernel.spec, 1.1395, 1.1396
Ben Skeggs
bskeggs at fedoraproject.org
Mon Mar 9 04:32:26 UTC 2009
Author: bskeggs
Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv2442
Modified Files:
drm-nouveau.patch kernel.spec
Log Message:
* Mon Mar 09 2009 Ben Skeggs <bskeggs at gmail.com>
- drm-nouveau.patch: nv50 and kms fixes
drm-nouveau.patch:
Index: drm-nouveau.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-nouveau.patch,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -r1.18 -r1.19
--- drm-nouveau.patch 5 Mar 2009 05:52:05 -0000 1.18
+++ drm-nouveau.patch 9 Mar 2009 04:32:25 -0000 1.19
@@ -22,7 +22,7 @@
+ userspaces with this enabled will cause pain.
+
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
-index 03ceb3e..3df55d7 100644
+index d6788df..97aa0c8 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -27,4 +27,5 @@ obj-$(CONFIG_DRM_I915) += i915/
@@ -32,7 +32,7 @@
+obj-$(CONFIG_DRM_NOUVEAU) +=nouveau/
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
-index 325b4aa..05e928f 100644
+index 4d2161f..ac503e2 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -51,38 +51,24 @@ resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resour
@@ -103,10 +103,10 @@
if (mask & ~fence->type) {
DRM_ERROR("Wait trying to extend fence type"
diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
-index 7e277c7..e5efd4a 100644
+index 5d45cbf..e3b0a76 100644
--- a/drivers/gpu/drm/drm_stub.c
+++ b/drivers/gpu/drm/drm_stub.c
-@@ -414,14 +414,14 @@ int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
+@@ -406,14 +406,14 @@ int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
if (dev->driver->load) {
ret = dev->driver->load(dev, ent->driver_data);
if (ret)
@@ -123,7 +123,7 @@
}
list_add_tail(&dev->driver_item, &driver->device_list);
-@@ -432,8 +432,11 @@ int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
+@@ -424,8 +424,11 @@ int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
return 0;
@@ -136,7 +136,7 @@
err_g2:
pci_disable_device(pdev);
err_g1:
-@@ -515,11 +518,11 @@ void drm_put_dev(struct drm_device *dev)
+@@ -507,11 +510,11 @@ void drm_put_dev(struct drm_device *dev)
dev->agp = NULL;
}
@@ -2524,10 +2524,10 @@
+MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
new file mode 100644
-index 0000000..adb7fdb
+index 0000000..06e3f9e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
-@@ -0,0 +1,737 @@
+@@ -0,0 +1,741 @@
+/*
+ * Copyright 2005 Stephane Marchesin.
+ * All Rights Reserved.
@@ -2773,6 +2773,8 @@
+ int (*init)(struct drm_device *);
+ void (*takedown)(struct drm_device *);
+
++ void (*fifo_access)(struct drm_device *, bool);
++
+ int (*create_context)(struct nouveau_channel *);
+ void (*destroy_context)(struct nouveau_channel *);
+ int (*load_context)(struct nouveau_channel *);
@@ -3120,6 +3122,7 @@
+extern void nouveau_nv04_context_switch(struct drm_device *);
+extern int nv04_graph_init(struct drm_device *);
+extern void nv04_graph_takedown(struct drm_device *);
++extern void nv04_graph_fifo_access(struct drm_device *, bool);
+extern int nv04_graph_create_context(struct nouveau_channel *);
+extern void nv04_graph_destroy_context(struct nouveau_channel *);
+extern int nv04_graph_load_context(struct nouveau_channel *);
@@ -3154,6 +3157,7 @@
+/* nv50_graph.c */
+extern int nv50_graph_init(struct drm_device *);
+extern void nv50_graph_takedown(struct drm_device *);
++extern void nv50_graph_fifo_access(struct drm_device *, bool);
+extern int nv50_graph_create_context(struct nouveau_channel *);
+extern void nv50_graph_destroy_context(struct nouveau_channel *);
+extern int nv50_graph_load_context(struct nouveau_channel *);
@@ -4505,10 +4509,10 @@
+};
diff --git a/drivers/gpu/drm/nouveau/nouveau_fifo.c b/drivers/gpu/drm/nouveau/nouveau_fifo.c
new file mode 100644
-index 0000000..b31a000
+index 0000000..469fdf3
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_fifo.c
-@@ -0,0 +1,673 @@
+@@ -0,0 +1,676 @@
+/*
+ * Copyright 2005-2006 Stephane Marchesin
+ * All Rights Reserved.
@@ -4855,6 +4859,7 @@
+ return ret;
+ }
+
++ engine->graph.fifo_access(dev, false);
+ nouveau_wait_for_idle(dev);
+
+ /* disable the fifo caches */
@@ -4910,6 +4915,8 @@
+ /* reenable the fifo caches */
+ nv_wr32(NV03_PFIFO_CACHES, 1);
+
++ engine->graph.fifo_access(dev, true);
++
+ if (dev_priv->mm_enabled) {
+ ret = nouveau_dma_channel_setup(chan);
+ if (ret) {
@@ -5184,10 +5191,10 @@
+int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
new file mode 100644
-index 0000000..7abee4c
+index 0000000..94a2dab
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
-@@ -0,0 +1,714 @@
+@@ -0,0 +1,716 @@
+/*
+ * Copyright (C) 2008 Ben Skeggs.
+ * All Rights Reserved.
@@ -5265,6 +5272,8 @@
+ flags = DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE;
+ flags |= DRM_BO_FLAG_MAPPABLE;
+ flags |= DRM_BO_FLAG_MEM_LOCAL;
++ if (dev_priv->gart_info.type != NOUVEAU_GART_AGP)
++ flags |= DRM_BO_FLAG_CACHED;
+
+ size = (size + (PAGE_SIZE-1)) & ~(PAGE_SIZE-1);
+ if (dev_priv->card_type == NV_50) {
@@ -7857,10 +7866,10 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
new file mode 100644
-index 0000000..48ff77e
+index 0000000..068797b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
-@@ -0,0 +1,1229 @@
+@@ -0,0 +1,1237 @@
+/*
+ * Copyright (C) 2006 Ben Skeggs.
+ *
@@ -8212,6 +8221,7 @@
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_engine *engine = &dev_priv->engine;
+ struct nouveau_gpuobj *gpuobj;
++ int i;
+
+ DRM_DEBUG("gpuobj %p\n", pgpuobj ? *pgpuobj : NULL);
+
@@ -8224,6 +8234,13 @@
+ return -EINVAL;
+ }
+
++ if (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE) {
++ engine->instmem.prepare_access(dev, true);
++ for (i = 0; i < gpuobj->im_pramin->size; i += 4)
++ INSTANCE_WR(gpuobj, i/4, 0);
++ engine->instmem.finish_access(dev);
++ }
++
+ if (gpuobj->dtor)
+ gpuobj->dtor(dev, gpuobj);
+
@@ -9092,7 +9109,7 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
new file mode 100644
-index 0000000..510b528
+index 0000000..44337e6
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -0,0 +1,835 @@
@@ -9902,7 +9919,7 @@
+# define NV50_PDISPLAY_DAC_REGS_CLK_CTRL1_CONNECTED__SHIFT 9
+
+# define NV50_PDISPLAY_SOR_REGS 0x0061c000
-+# define NV50_PDISPLAY_SOR_REGS__LEN 0x2
++# define NV50_PDISPLAY_SOR_REGS__LEN 0x3
+# define NV50_PDISPLAY_SOR_REGS__ESIZE 0x800
+# define NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(i) (0x0061c004+(i)*0x800)
+# define NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON (1<<0)
@@ -10301,10 +10318,10 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
new file mode 100644
-index 0000000..6b7fed1
+index 0000000..52036d5
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
-@@ -0,0 +1,942 @@
+@@ -0,0 +1,948 @@
+/*
+ * Copyright 2005 Stephane Marchesin
+ * Copyright 2008 Stuart Bennett
@@ -10367,6 +10384,7 @@
+ engine->fb.takedown = nv04_fb_takedown;
+ engine->graph.init = nv04_graph_init;
+ engine->graph.takedown = nv04_graph_takedown;
++ engine->graph.fifo_access = nv04_graph_fifo_access;
+ engine->graph.create_context = nv04_graph_create_context;
+ engine->graph.destroy_context = nv04_graph_destroy_context;
+ engine->graph.load_context = nv04_graph_load_context;
@@ -10400,6 +10418,7 @@
+ engine->graph.takedown = nv10_graph_takedown;
+ engine->graph.create_context = nv10_graph_create_context;
+ engine->graph.destroy_context = nv10_graph_destroy_context;
++ engine->graph.fifo_access = nv04_graph_fifo_access;
+ engine->graph.load_context = nv10_graph_load_context;
+ engine->graph.save_context = nv10_graph_save_context;
+ engine->fifo.channels = 32;
@@ -10431,6 +10450,7 @@
+ engine->graph.takedown = nv20_graph_takedown;
+ engine->graph.create_context = nv20_graph_create_context;
+ engine->graph.destroy_context = nv20_graph_destroy_context;
++ engine->graph.fifo_access = nv04_graph_fifo_access;
+ engine->graph.load_context = nv20_graph_load_context;
+ engine->graph.save_context = nv20_graph_save_context;
+ engine->fifo.channels = 32;
@@ -10460,6 +10480,7 @@
+ engine->fb.takedown = nv10_fb_takedown;
+ engine->graph.init = nv30_graph_init;
+ engine->graph.takedown = nv20_graph_takedown;
++ engine->graph.fifo_access = nv04_graph_fifo_access;
+ engine->graph.create_context = nv20_graph_create_context;
+ engine->graph.destroy_context = nv20_graph_destroy_context;
+ engine->graph.load_context = nv20_graph_load_context;
@@ -10492,6 +10513,7 @@
+ engine->fb.takedown = nv40_fb_takedown;
+ engine->graph.init = nv40_graph_init;
+ engine->graph.takedown = nv40_graph_takedown;
++ engine->graph.fifo_access = nv04_graph_fifo_access;
+ engine->graph.create_context = nv40_graph_create_context;
+ engine->graph.destroy_context = nv40_graph_destroy_context;
+ engine->graph.load_context = nv40_graph_load_context;
@@ -10526,6 +10548,7 @@
+ engine->fb.takedown = nouveau_stub_takedown;
+ engine->graph.init = nv50_graph_init;
+ engine->graph.takedown = nv50_graph_takedown;
++ engine->graph.fifo_access = nv50_graph_fifo_access;
+ engine->graph.create_context = nv50_graph_create_context;
+ engine->graph.destroy_context = nv50_graph_destroy_context;
+ engine->graph.load_context = nv50_graph_load_context;
@@ -11667,10 +11690,10 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nv04_graph.c b/drivers/gpu/drm/nouveau/nv04_graph.c
new file mode 100644
-index 0000000..62ef1cf
+index 0000000..5f923ef
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv04_graph.c
-@@ -0,0 +1,516 @@
+@@ -0,0 +1,527 @@
+/*
+ * Copyright 2007 Stephane Marchesin
+ * All Rights Reserved.
@@ -12175,7 +12198,6 @@
+
+ nv_wr32(NV04_PGRAPH_STATE , 0xFFFFFFFF);
+ nv_wr32(NV04_PGRAPH_CTX_CONTROL , 0x10010100);
-+ nv_wr32(NV04_PGRAPH_FIFO , 0x00000001);
+
+ /* These don't belong here, they're part of a per-channel context */
+ nv_wr32(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
@@ -12187,6 +12209,18 @@
+void nv04_graph_takedown(struct drm_device *dev)
+{
+}
++
++void
++nv04_graph_fifo_access(struct drm_device *dev, bool enabled)
++{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
++
++ if (enabled)
++ nv_wr32(NV04_PGRAPH_FIFO, nv_rd32(NV04_PGRAPH_FIFO) | 1);
++ else
++ nv_wr32(NV04_PGRAPH_FIFO, nv_rd32(NV04_PGRAPH_FIFO) & ~1);
++}
++
diff --git a/drivers/gpu/drm/nouveau/nv04_instmem.c b/drivers/gpu/drm/nouveau/nv04_instmem.c
new file mode 100644
index 0000000..a83d271
@@ -12686,10 +12720,10 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c
new file mode 100644
-index 0000000..791e08b
+index 0000000..6a8c270
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv10_graph.c
-@@ -0,0 +1,914 @@
+@@ -0,0 +1,913 @@
+/*
+ * Copyright 2007 Matthieu CASTET <castet.matthieu at free.fr>
+ * All Rights Reserved.
@@ -13596,7 +13630,6 @@
+ nv_wr32(NV10_PGRAPH_CTX_SWITCH4, 0x00000000);
+ nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
+ nv_wr32(NV10_PGRAPH_STATE , 0xFFFFFFFF);
-+ nv_wr32(NV04_PGRAPH_FIFO , 0x00000001);
+
+ return 0;
+}
@@ -13606,10 +13639,10 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nv20_graph.c b/drivers/gpu/drm/nouveau/nv20_graph.c
new file mode 100644
-index 0000000..b8e138e
+index 0000000..adbd389
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv20_graph.c
-@@ -0,0 +1,917 @@
+@@ -0,0 +1,915 @@
+#include "drmP.h"
+#include "drm.h"
+#include "nouveau_drv.h"
@@ -14380,7 +14413,6 @@
+
+ nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x10000100);
+ nv_wr32(NV10_PGRAPH_STATE , 0xFFFFFFFF);
-+ nv_wr32(NV04_PGRAPH_FIFO , 0x00000001);
+
+ tmp = nv_rd32(NV10_PGRAPH_SURFACE) & 0x0007ff00;
+ nv_wr32(NV10_PGRAPH_SURFACE, tmp);
@@ -14491,7 +14523,6 @@
+ nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x10000100);
+ nv_wr32(NV10_PGRAPH_STATE , 0xFFFFFFFF);
+ nv_wr32(0x0040075c , 0x00000001);
-+ nv_wr32(NV04_PGRAPH_FIFO , 0x00000001);
+
+ /* begin RAM config */
+// vramsz = drm_get_resource_len(dev, 0) - 1;
@@ -14821,10 +14852,10 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
new file mode 100644
-index 0000000..31147ef
+index 0000000..710a9a9
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
-@@ -0,0 +1,2192 @@
+@@ -0,0 +1,2191 @@
+/*
+ * Copyright (C) 2007 Ben Skeggs.
+ * All Rights Reserved.
@@ -16839,7 +16870,6 @@
+
+ nv_wr32(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
+ nv_wr32(NV10_PGRAPH_STATE , 0xFFFFFFFF);
-+ nv_wr32(NV04_PGRAPH_FIFO , 0x00000001);
+
+ j = nv_rd32(0x1540) & 0xff;
+ if (j) {
@@ -17661,10 +17691,10 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
new file mode 100644
-index 0000000..5e6be22
+index 0000000..340e772
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
-@@ -0,0 +1,776 @@
+@@ -0,0 +1,775 @@
+/*
+ * Copyright (C) 2008 Maarten Maathuis.
+ * All Rights Reserved.
@@ -17739,7 +17769,6 @@
+ }
+ break;
+ default:
-+ DRM_INFO("load 24bpp\n");
+ /* R8G8B8 */
+ for (i = 0; i < 256; i++) {
+ writew(crtc->lut.r[i] >> 2, lut + 8*i + 0);
@@ -18987,10 +19016,10 @@
+
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
new file mode 100644
-index 0000000..5bd41ef
+index 0000000..0e9fd37
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
-@@ -0,0 +1,441 @@
+@@ -0,0 +1,442 @@
+/*
+ * Copyright (C) 2008 Maarten Maathuis.
+ * All Rights Reserved.
@@ -19052,6 +19081,7 @@
+ /* SOR */
+ nv_wr32(0x006101e0 + 0 * 0x4, nv_rd32(0x0061c000 + 0 * 0x800));
+ nv_wr32(0x006101e0 + 1 * 0x4, nv_rd32(0x0061c000 + 1 * 0x800));
++ nv_wr32(0x006101e0 + 2 * 0x4, nv_rd32(0x0061c000 + 2 * 0x800));
+ /* Something not yet in use, tv-out maybe. */
+ nv_wr32(0x006101f0 + 0 * 0x4, nv_rd32(0x0061e000 + 0 * 0x800));
+ nv_wr32(0x006101f0 + 1 * 0x4, nv_rd32(0x0061e000 + 1 * 0x800));
@@ -19196,7 +19226,7 @@
+ }
+#endif
+
-+ for (i = 0; i < 2; i++) {
++ for (i = 0; i < NV50_PDISPLAY_SOR_REGS__LEN; i++) {
+ if (!nv_wait(NV50_PDISPLAY_SOR_REGS_DPMS_STATE(i),
+ NV50_PDISPLAY_SOR_REGS_DPMS_STATE_WAIT, 0)) {
+ DRM_ERROR("timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
@@ -20267,10 +20297,10 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
new file mode 100644
-index 0000000..b892830
+index 0000000..30246c2
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
-@@ -0,0 +1,333 @@
+@@ -0,0 +1,345 @@
+/*
+ * Copyright (C) 2007 Ben Skeggs.
+ * All Rights Reserved.
@@ -20344,7 +20374,7 @@
+ nv_wr32(0x400108, 0xffffffff);
+
+ nv_wr32(0x400824, 0x00004000);
-+ nv_wr32(0x400500, 0x00010001);
++ nv_wr32(0x400500, 0x00000000);
+}
+
+static void
@@ -20417,9 +20447,9 @@
+ DRM_DEBUG("\n");
+
+ nv50_graph_init_reset(dev);
-+ nv50_graph_init_intr(dev);
+ nv50_graph_init_regs__nv(dev);
+ nv50_graph_init_regs(dev);
++ nv50_graph_init_intr(dev);
+
+ ret = nv50_graph_init_ctxctl(dev);
+ if (ret)
@@ -20434,6 +20464,18 @@
+ DRM_DEBUG("\n");
+}
+
++void
++nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
++{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
++ const uint32_t mask = 0x00010001;
++
++ if (enabled)
++ nv_wr32(0x400500, nv_rd32(0x400500) | mask);
++ else
++ nv_wr32(0x400500, nv_rd32(0x400500) & ~mask);
++}
++
+int
+nv50_graph_create_context(struct nouveau_channel *chan)
+{
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.1395
retrieving revision 1.1396
diff -u -r1.1395 -r1.1396
--- kernel.spec 9 Mar 2009 03:11:27 -0000 1.1395
+++ kernel.spec 9 Mar 2009 04:32:25 -0000 1.1396
@@ -1810,6 +1810,9 @@
# and build.
%changelog
+* Mon Mar 09 2009 Ben Skeggs <bskeggs at gmail.com>
+- drm-nouveau.patch: nv50 and kms fixes
+
* Mon Mar 09 2009 Dave Airlie <airlied at redhat.com>
- drm-next.patch: fixes from upstream queue for r600 support
- drm-modesetting-radeon.patch: make 2D/3D on PCIE faster
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