rpms/mesa/devel mesa.spec,1.227,1.228 radeon-rewrite.patch,1.7,1.8
Dave Airlie
airlied at fedoraproject.org
Mon Mar 9 05:40:18 UTC 2009
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Author: airlied
Update of /cvs/pkgs/rpms/mesa/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv19323
Modified Files:
mesa.spec radeon-rewrite.patch
Log Message:
* Mon Mar 09 2009 Dave Airlie <airlied at redhat.com> 7.3-11
- radeon-rewrite.patch: update with swtcl and r100 bugfixes
Index: mesa.spec
===================================================================
RCS file: /cvs/pkgs/rpms/mesa/devel/mesa.spec,v
retrieving revision 1.227
retrieving revision 1.228
diff -u -r1.227 -r1.228
--- mesa.spec 5 Mar 2009 08:19:34 -0000 1.227
+++ mesa.spec 9 Mar 2009 05:39:46 -0000 1.228
@@ -427,6 +427,9 @@
%{_libdir}/mesa-demos-data
%changelog
+* Mon Mar 09 2009 Dave Airlie <airlied at redhat.com> 7.3-11
+- radeon-rewrite.patch: update with swtcl and r100 bugfixes
+
* Thu Mar 05 2009 Dave Airlie <airlied at redhat.com> 7.3-10
- radeon-rewrite.patch: fixup link against libdrm_radeon
radeon-rewrite.patch:
View full diff with command:
/usr/bin/cvs -f diff -kk -u -N -r 1.7 -r 1.8 radeon-rewrite.patch
Index: radeon-rewrite.patch
===================================================================
RCS file: /cvs/pkgs/rpms/mesa/devel/radeon-rewrite.patch,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -r1.7 -r1.8
--- radeon-rewrite.patch 6 Mar 2009 00:07:16 -0000 1.7
+++ radeon-rewrite.patch 9 Mar 2009 05:39:46 -0000 1.8
@@ -1,3 +1,15 @@
+commit 6c28708e141d047fc44369eac08cfb9a47f22c87
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Mar 9 13:51:39 2009 +1000
+
+ radeon/r200/r300: update from latest radeon-rewrite branch
+
+commit 38262b6fc16f627a66e1475b729047ffe8258803
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Mar 9 13:46:44 2009 +1000
+
+ r300: remove some links
+
commit 263b887d85e3eac9a32673c8ed3004c3129ce997
Author: Dave Airlie <airlied at redhat.com>
Date: Sun Feb 15 17:03:47 2009 +1000
@@ -812,7 +824,7 @@
- cmd[0].wait.flags = flags;
-}
diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
-index 5531e0a..a744469 100644
+index 5531e0a..10a6362 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -54,7 +54,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -924,9 +936,9 @@
+{
+ radeon->vtbl.get_lock = r200_get_lock;
+ radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset;
-+ radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer;
+ radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header;
+ radeon->vtbl.swtcl_flush = r200_swtcl_flush;
++ radeon->vtbl.fallback = r200Fallback;
+}
+
@@ -1989,7 +2001,7 @@
}
}
diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c
-index 0741e57..c08968f 100644
+index 0741e57..1ab5a82 100644
--- a/src/mesa/drivers/dri/r200/r200_ioctl.c
+++ b/src/mesa/drivers/dri/r200/r200_ioctl.c
@@ -41,6 +41,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -2001,7 +2013,7 @@
#include "r200_context.h"
#include "r200_state.h"
#include "r200_ioctl.h"
-@@ -54,635 +56,28 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+@@ -54,635 +56,45 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define R200_TIMEOUT 512
#define R200_IDLE_RETRY 16
@@ -2478,10 +2490,9 @@
- assert(dPriv);
- assert(dPriv->driContextPriv);
- assert(dPriv->driContextPriv->driverPrivate);
-+ if (flags & (RADEON_FRONT | RADEON_BACK)) {
-
+-
- rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate;
-
+-
- if ( R200_DEBUG & DEBUG_IOCTL ) {
- fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__,
- rmesa->sarea->pfCurrentPage);
@@ -2494,10 +2505,8 @@
- UNLOCK_HARDWARE( rmesa );
- usleep( 10000 ); /* throttle invisible client 10ms */
- return;
- }
-+
-+ if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
-+ && (flags & RADEON_CLEAR_FASTZ)) {
+- }
++ GLuint mask = 0;
- /* Need to do this for the perf box placement:
- */
@@ -2507,7 +2516,9 @@
- b[0] = box[0];
- rmesa->sarea->nbox = 1;
- }
--
++ if (flags & RADEON_FRONT)
++ mask |= BUFFER_BIT_FRONT_LEFT;
+
- /* Throttle the frame rate -- only allow a few pending swap buffers
- * request at a time.
- */
@@ -2517,21 +2528,31 @@
- if ( missed_target ) {
- rmesa->swap_missed_count++;
- (void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust );
- }
+- }
- LOCK_HARDWARE( rmesa );
++ if (flags & RADEON_BACK)
++ mask |= BUFFER_BIT_BACK_LEFT;
- ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP );
--
++ if (flags & RADEON_DEPTH)
++ mask |= BUFFER_BIT_DEPTH;
+
- UNLOCK_HARDWARE( rmesa );
--
++ if (flags & RADEON_STENCIL)
++ mask |= BUFFER_BIT_STENCIL;
+
- if ( ret ) {
- fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret );
- exit( 1 );
- }
--
++#if 1
++ _swrast_Clear(ctx, mask);
++#else
++ if (flags & (RADEON_FRONT | RADEON_BACK)) {
+
- rmesa->swap_count++;
- (void) (*psp->systemTime->getUST)( & rmesa->swap_ust );
--
+
-#if 000
- if ( rmesa->sarea->pfCurrentPage == 1 ) {
- rmesa->state.color.drawOffset = rmesa->r200Screen->frontOffset;
@@ -2539,15 +2560,18 @@
- } else {
- rmesa->state.color.drawOffset = rmesa->r200Screen->backOffset;
- rmesa->state.color.drawPitch = rmesa->r200Screen->backPitch;
-- }
--
+ }
++
++ if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
++ && (flags & RADEON_CLEAR_FASTZ)) {
+
- R200_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset
- + rmesa->r200Screen->fbLocation;
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
- if (rmesa->sarea->tiling_enabled) {
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
-- }
+ }
-#else
- /* Get ready for drawing next frame. Update the renderbuffers'
- * flippedOffset/Pitch fields so we draw into the right place.
@@ -2557,7 +2581,7 @@
-
-
- r200UpdateDrawBuffer(rmesa->glCtx);
--#endif
+ #endif
}
-
@@ -2573,10 +2597,7 @@
- GLuint color_mask = 0;
- GLint ret, i;
- GLint cx, cy, cw, ch;
-+ __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
-+ GLint cx, cy, cw, ch, ret;
-+ GLuint i;
-
+-
- if ( R200_DEBUG & DEBUG_IOCTL ) {
- fprintf( stderr, "r200Clear\n");
- }
@@ -2606,7 +2627,10 @@
- flags |= RADEON_DEPTH;
- mask &= ~BUFFER_BIT_DEPTH;
- }
--
++ __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
++ GLint cx, cy, cw, ch, ret;
++ GLuint i;
+
- if ( (mask & BUFFER_BIT_STENCIL) && rmesa->state.stencil.hwBuffer ) {
- flags |= RADEON_STENCIL;
- mask &= ~BUFFER_BIT_STENCIL;
@@ -2647,7 +2671,7 @@
/* Throttle the number of clear ioctls we do.
*/
-@@ -693,7 +88,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
+@@ -693,7 +105,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
gp.param = RADEON_PARAM_LAST_CLEAR;
gp.value = (int *)&clear;
[...5783 lines suppressed...]
++ rb->bo = NULL;
++ }
++ rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
++ if (rb && rb->bo) {
++ radeon_bo_unref(rb->bo);
++ rb->bo = NULL;
++ }
++ rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
++ if (rb->bo == NULL) {
++ /* Failed to BO for the buffer */
++ return;
++ }
++
++ _mesa_lock_texture(radeon->glCtx, texObj);
++ if (t->bo) {
++ radeon_bo_unref(t->bo);
++ t->bo = NULL;
++ }
++ if (rImage->bo) {
++ radeon_bo_unref(rImage->bo);
++ rImage->bo = NULL;
++ }
++ if (t->mt) {
++ radeon_miptree_unreference(t->mt);
++ t->mt = NULL;
++ }
++ if (rImage->mt) {
++ radeon_miptree_unreference(rImage->mt);
++ rImage->mt = NULL;
++ }
++ fprintf(stderr,"settexbuf %d %dx%d@%d\n", rb->pitch, rb->width, rb->height, rb->cpp);
++ _mesa_init_teximage_fields(radeon->glCtx, target, texImage,
++ rb->width, rb->height, 1, 0, rb->cpp);
++ texImage->TexFormat = &_mesa_texformat_rgba8888_rev;
++ rImage->bo = rb->bo;
++ radeon_bo_ref(rImage->bo);
++ t->bo = rb->bo;
++ radeon_bo_ref(t->bo);
++ t->tile_bits = 0;
++ t->image_override = GL_TRUE;
++ t->override_offset = 0;
++ t->pp_txpitch &= (1 << 13) -1;
++ pitch_val = rb->pitch;
++ switch (rb->cpp) {
++ case 4:
++ t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format;
++ t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter;
++ break;
++ case 3:
++ default:
++ t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format;
++ t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter;
++ break;
++ case 2:
++ t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format;
++ t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter;
++ break;
++ }
++ t->pp_txsize = ((rb->width - 1) << RADEON_TEX_USIZE_SHIFT)
++ | ((rb->height - 1) << RADEON_TEX_VSIZE_SHIFT);
++ t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
++ t->pp_txpitch = pitch_val;
++ t->pp_txpitch -= 32;
++
++ t->validated = GL_TRUE;
++ _mesa_unlock_texture(radeon->glCtx, texObj);
++ return;
++}
++
+ #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
+ RADEON_MIN_FILTER_MASK | \
+ RADEON_MAG_FILTER_MASK | \
+@@ -901,12 +760,58 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
RADEON_TXFORMAT_NON_POWER2)
@@ -33713,7 +34844,7 @@
GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
RADEON_STATECHANGE( rmesa, tex[unit] );
-@@ -915,10 +716,9 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
+@@ -915,10 +820,9 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK;
cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK;
cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK;
@@ -33725,7 +34856,7 @@
GLuint *txr_cmd = RADEON_DB_STATE( txr[unit] );
txr_cmd[TXR_PP_TEX_SIZE] = texobj->pp_txsize; /* NPOT only! */
txr_cmd[TXR_PP_TEX_PITCH] = texobj->pp_txpitch; /* NPOT only! */
-@@ -928,22 +728,12 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
+@@ -928,22 +832,12 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
else {
se_coord_fmt &= ~(RADEON_VTX_ST0_NONPARAMETRIC << unit);
@@ -33751,7 +34882,7 @@
}
}
-@@ -952,13 +742,11 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
+@@ -952,13 +846,11 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
}
@@ -33767,7 +34898,7 @@
GLuint unit,
const GLfloat *s_plane,
const GLfloat *t_plane,
-@@ -986,14 +774,14 @@ static void set_texgen_matrix( radeonContextPtr rmesa,
+@@ -986,14 +878,14 @@ static void set_texgen_matrix( radeonContextPtr rmesa,
rmesa->TexGenMatrix[unit].m[15] = q_plane[3];
rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE << unit;
@@ -33784,7 +34915,7 @@
struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
GLuint tmp = rmesa->TexGenEnabled;
-@@ -1094,283 +882,185 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit )
+@@ -1094,283 +986,189 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit )
}
if (tmp != rmesa->TexGenEnabled) {
@@ -33893,16 +35024,18 @@
- struct gl_texture_object *tObj = texUnit->_Current;
- radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
- GLuint face;
--
++ const struct gl_texture_image *firstImage;
++ GLint log2Width, log2Height, log2Depth, texelBytes;
+
- /* Need to load the 2d images associated with this unit.
- */
- if (t->pp_txformat & RADEON_TXFORMAT_NON_POWER2) {
- t->pp_txformat &= ~RADEON_TXFORMAT_NON_POWER2;
- for (face = 0; face < 6; face++)
- t->base.dirty_images[face] = ~0;
-- }
-+ const struct gl_texture_image *firstImage;
-+ GLint log2Width, log2Height, log2Depth, texelBytes;
++ if ( t->bo ) {
++ return GL_TRUE;
+ }
- ASSERT(tObj->Target == GL_TEXTURE_CUBE_MAP);
+ firstImage = t->base.Image[0][t->mt->firstLevel];
@@ -33980,16 +35113,16 @@
- return GL_TRUE;
-}
-+ t->pp_txsize = (((firstImage->Width - 1) << RADEON_TEX_USIZE_SHIFT)
-+ | ((firstImage->Height - 1) << RADEON_TEX_VSIZE_SHIFT));
-
+-
-static GLboolean enable_tex_rect( GLcontext *ctx, int unit )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
- struct gl_texture_object *tObj = texUnit->_Current;
- radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
--
++ t->pp_txsize = (((firstImage->Width - 1) << RADEON_TEX_USIZE_SHIFT)
++ | ((firstImage->Height - 1) << RADEON_TEX_VSIZE_SHIFT));
+
- if (!(t->pp_txformat & RADEON_TXFORMAT_NON_POWER2)) {
- t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
- t->base.dirty_images[0] = ~0;
@@ -34059,27 +35192,27 @@
- rmesa->state.texture.unit[unit].texobj->base.bound &=
- ~(1UL << unit);
- }
-+ RADEON_STATECHANGE( rmesa, ctx );
-+ rmesa->hw.ctx.cmd[CTX_PP_CNTL] |=
-+ (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit;
-
+-
- rmesa->state.texture.unit[unit].texobj = t;
- t->base.bound |= (1UL << unit);
- t->dirty_state |= 1<<unit;
- driUpdateTextureLRU( (driTextureObject *) t ); /* XXX: should be locked! */
- }
++ RADEON_STATECHANGE( rmesa, ctx );
++ rmesa->hw.ctx.cmd[CTX_PP_CNTL] |=
++ (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit;
+
+ RADEON_STATECHANGE( rmesa, tcl );
+ rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit);
-+ rmesa->recheck_texgen[unit] = GL_TRUE;
-
- /* Newly enabled?
- */
- if ( !(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (RADEON_TEX_0_ENABLE<<unit))) {
- RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] |=
- (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit;
--
++ rmesa->recheck_texgen[unit] = GL_TRUE;
+
- RADEON_STATECHANGE( rmesa, tcl );
-
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit);
- Previous message (by thread): rpms/ghc-paths/devel dead.package, NONE, 1.1 .cvsignore, 1.2, NONE Makefile, 1.1, NONE ghc-paths.spec, 1.3, NONE import.log, 1.1, NONE sources, 1.2, NONE
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