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Re: memtest86+ ECC oddity - EDAC in kernel 2.6.16 (ie FC5)

Bruno Wolff III wrote:
On Fri, May 05, 2006 at 08:13:05 +1000,
  David Timms <dtimms bigpond net au> wrote:
I think the error correcting code is at the chipset level (the ECC ram just provides the extra storage bit per byte that is needed to implement the ECC code). Perhaps what is happening is the chipset detects and

It's more than one bit. One bit only allows you to detect single bit errors.
Typically, ECC memory allows you to correct 1 bit errors and detect 2 bit
But I'd still contend that ECC memory is only another bit per byte of
storage (or 9 chips instead of 8), and the memory itself knows not what
it is being used for.

Isn't it the ECC chipset that is using the extra storage to calculate
errors and corrections ? I remember reading along the lines that for
8x8=64 bits, the extra 8x1=8 bits are enough for the chipset to perform
the ECC algorithm.

I was also thinking about my experiments with turning ECC off in the
BIOS. After re-analyzing, I am thinking that even though I can turn the
ECC to disabled in my BIOS, it may only be the notification or logging
of errors that is being turned off. The chipset will still correct
errors. This would mean that the memtest results with ECC not being On
would make sense - the chipset is correcting the errors before memtest
sees the result of it's tests. Does this add up ?


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