Request for testing : Icarus Verilog v0.9.2 pre-release

[Chitlesh GOORAH]

Hello Verilog users,

A test snapshot of the next v0.9.2 iverilog release was pushed to
updates-testing repository. It is upstream's last test snapshot before
the v0.9.2 release.

We would like you to test it against
 * your large structural designs (upstream's wish)
 * your FPGA specific designs - post synthesis [1] and post place and route

The test plan is detailed here along with some known bugs
https://fedorahosted.org/fedora-electronic-lab/wiki/Testing/iverilog

This release is a huge enhancement over the one in Fedora stable
repositories. It is more compliant too with IEEE Standard 1364-2005
[2]. Runtime has also been improved.

We would appreciate if you can give some feedbacks such as :
 * estimated gate count
 * estimated time of execution
 * architecture: i686 or x86_84
 * rpm -q iverilog

Kind regards,
Chitlesh

[1] : http://chitlesh.wordpress.com/2009/05/18/xilinx-icarus-verilog-post-synthesis-simulation/
[2] : https://fedorahosted.org/fedora-electronic-lab/wiki/Digital/iverilog

-- 
Chitlesh GOORAH
Fedora Electronic Lab
http://spins.fedoraproject.org/fel