[Bug 478365] New: Review Request: perl-Verilog-CodeGen - Verilog code generator

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Summary: Review Request: perl-Verilog-CodeGen - Verilog code generator

https://bugzilla.redhat.com/show_bug.cgi?id=478365

           Summary: Review Request: perl-Verilog-CodeGen - Verilog code
                    generator
           Product: Fedora
           Version: rawhide
          Platform: All
        OS/Version: Linux
            Status: NEW
          Severity: medium
          Priority: medium
         Component: Package Review
        AssignedTo: nobody at fedoraproject.org
        ReportedBy: cgoorah at yahoo.com.au
         QAContact: extras-qa at fedoraproject.org
                CC: notting at redhat.com, fedora-package-review at redhat.com
   Estimated Hours: 0.0
    Classification: Fedora


Spec URL: http://chitlesh.fedorapeople.org/RPMS/perl-Verilog-CodeGen.spec
SRPM URL:
http://chitlesh.fedorapeople.org/RPMS/perl-Verilog-CodeGen-0.9.4-1.fc10.src.rpm
Description:
Provides an object-oriented environment to generate Verilog code for
modules and testbenches. The Verilog::CodeGen module provides two
functions, one to create a code template and another to create a Perl
module which contains the device library. This module ,
DeviceLibs::YourDesign, provides the class methods and contains the objects
for every Verilog module; the objects are created based on a fixed
template. The purpose of this module is to allow the generation of
customized Verilog modules. A Verilog module can have a large number of
parameters like input and output bus width, buffer depth, signal delay etc.
The code generator allows to create an object that will generate the
Verilog module code for arbitraty values of the parameters.

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