[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #7 from Chitlesh GOORAH <cgoorah at yahoo.com.au>  2008-11-19 17:03:44 EDT ---
#001  You can replace
%setup -q -n %{name}-%{version} by
%setup -q

#002 add %{?_smp_mflags}
SYSTEMPERL=%{_datadir}/verilator/perl-systemc %{__make} %{?_smp_mflags}

#003: use fedora optflags:
add the following after configure
%{__sed} -i "s|CPPFLAGSNOWALL +=|CPPFLAGSNOWALL +=%{optflags}|" \
{src,test_c,test_regress,test_sc,test_sp,test_verilated}/Makefile_obj

#004: Are these useful ?
/usr/share/verilator/bin
/usr/share/verilator/bin/verilator_includer

#005: move BUIDROOT/usr/share/verilator/examples to examples/
then %doc examples/

#006: Are these important:
chitlesh(SPECS)[1]$rpm -ql verilator | grep -v examples | grep .cpp
/usr/share/verilator/include/verilated.cpp
/usr/share/verilator/perl-systemc/src/SpTraceVcdC.cpp

#007 can you give me quick case study of how to use verilator ? It might be
helpful for those who don't know, but want to do the review.

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