[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516


Lane <dirjud at gmail.com> changed:

           What    |Removed                     |Added
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               Flag|                            |fedora-cvs-




--- Comment #46 from Lane <dirjud at gmail.com>  2009-07-22 12:13:09 EDT ---
New Package CVS Request
=======================
Package Name: verilator
Short Description: A fast simulator of synthesizable Verilog HDL
Owners: dirjud chitlesh
Branches: F-10 F-11 EL-5
InitialCC:

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