[libvirt] [PATCH] Allow PCI virtio on ARM "virt" machine

Pavel Fedin p.fedin at samsung.com
Tue May 26 07:19:02 UTC 2015


> I think you'll need to add a new qemu capabilities flag
> like QEMU_CAPS_AARCH64_VIRT_PCI that's enabled for qemu 2.3.0 or later... if
> it's available, then we default to PCI.

 How could i check for this ? Actually qemu already has PCI for both 32 and 64-bit virt
board for quite some time. But the only way to check this is to run qemu. It does not
expose any additional options for that. Or do you suggest just to check version number ?

> >  "virt-" prefix is intentionally ignored in third chunk because it is a temporary
> > and qemu developers agreed to use "gic version" option, for which there is already
> > in libvirt.
> >
> I don't follow this, can you expand a bit? Maybe Michal can explain too since
> he did the libvirt gic patches

 Sorry, ignore this because i was telling crap :)
 I suggested that it was added just in case, because we are working on qemu mailing list
on implementing GICv3 support, and my current solution is to add a new "virt-v3" machine.
I tried an option but there are some technical difficulties about it. So perhaps it will
stay "virt-v3" or "virt-gicv3" or something like that.
 But i found this commit in libvirt history, and it is explained that it's actually for
distro maintainers who might want to add their own virt-something machines.

> Another thing is we probably need to extend the XML parser to add a
> <controller type='pci'> automatically like we do for x86.
> I can help with some of this if you want, just let me know.

 Yes, please, would be nice because i'm not much into that XML stuff... I've seen
notations like address type='pci' and then it's necessary to specify the location. But
this requires some extra magic, like i need to specify that the machine has a controller
(otherwise libvirt complains that i don't have a free slot), and i'm not sure that all
these problems make sense for qemu, since qemu (AFAIK) does not allow to explicitly pin
down devices on the PCI bus.

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia

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