[libvirt] [PATCH v5 8/8] perf: add more perf events support
John Ferlan
jferlan at redhat.com
Wed Aug 3 22:30:55 UTC 2016
From: Qiaowei Ren <qiaowei.ren at intel.com>
With current perf framework, this patch adds support and documentation
for more perf events, including cache misses, cache references, cpu cycles,
and instructions.
Signed-off-by: Qiaowei Ren <qiaowei.ren at intel.com>
Signed-off-by: John Ferlan <jferlan at redhat.com>
---
docs/formatdomain.html.in | 24 ++++++++++++++++++
docs/schemas/domaincommon.rng | 4 +++
include/libvirt/libvirt-domain.h | 39 +++++++++++++++++++++++++++++
src/libvirt-domain.c | 9 +++++++
src/qemu/qemu_driver.c | 4 +++
src/util/virperf.c | 16 +++++++++++-
src/util/virperf.h | 5 ++++
tests/genericxml2xmlindata/generic-perf.xml | 4 +++
tools/virsh.pod | 13 ++++++++++
9 files changed, 117 insertions(+), 1 deletion(-)
diff --git a/docs/formatdomain.html.in b/docs/formatdomain.html.in
index fa88839..f7c5d3b 100644
--- a/docs/formatdomain.html.in
+++ b/docs/formatdomain.html.in
@@ -1867,6 +1867,10 @@
<event name='cmt' enabled='yes'/>
<event name='mbmt' enabled='no'/>
<event name='mbml' enabled='yes'/>
+ <event name='cpu_cycles' enabled='no'/>
+ <event name='instructions' enabled='yes'/>
+ <event name='cache_references' enabled='no'/>
+ <event name='cache_misses' enabled='no'/>
</perf>
...
</pre>
@@ -1892,6 +1896,26 @@
<td>bandwidth of memory traffic for a memory controller</td>
<td><code>perf.mbml</code></td>
</tr>
+ <tr>
+ <td><code>cpu_cycles</code></td>
+ <td>the number of cpu cycles one instruction needs</td>
+ <td><code>perf.cpu_cycles</code></td>
+ </tr>
+ <tr>
+ <td><code>instructions</code></td>
+ <td>the count of instructions by applications running on the platform</td>
+ <td><code>perf.instructions</code></td>
+ </tr>
+ <tr>
+ <td><code>cache_references</code></td>
+ <td>the count of cache hits by applications running on the platform</td>
+ <td><code>perf.cache_references</code></td>
+ </tr>
+ <tr>
+ <td><code>cache_misses</code></td>
+ <td>the count of cache misses by applications running on the platform</td>
+ <td><code>perf.cache_misses</code></td>
+ </tr>
</table>
<h3><a name="elementsDevices">Devices</a></h3>
diff --git a/docs/schemas/domaincommon.rng b/docs/schemas/domaincommon.rng
index cb9f134..715ccc5 100644
--- a/docs/schemas/domaincommon.rng
+++ b/docs/schemas/domaincommon.rng
@@ -414,6 +414,10 @@
<value>cmt</value>
<value>mbmt</value>
<value>mbml</value>
+ <value>cpu_cycles</value>
+ <value>instructions</value>
+ <value>cache_references</value>
+ <value>cache_misses</value>
</choice>
</attribute>
<attribute name="enabled">
diff --git a/include/libvirt/libvirt-domain.h b/include/libvirt/libvirt-domain.h
index 42a2bea..6e0e7fb 100644
--- a/include/libvirt/libvirt-domain.h
+++ b/include/libvirt/libvirt-domain.h
@@ -1972,6 +1972,45 @@ void virDomainStatsRecordListFree(virDomainStatsRecordPtr *stats);
*/
# define VIR_PERF_PARAM_MBML "mbml"
+/**
+ * VIR_PERF_PARAM_CACHE_MISSES:
+ *
+ * Macro for typed parameter name that represents cache_misses perf
+ * event which can be used to measure the count of cache misses by
+ * applications running on the platform. It corresponds to the
+ * "perf.cache_misses" field in the *Stats APIs.
+ */
+# define VIR_PERF_PARAM_CACHE_MISSES "cache_misses"
+
+/**
+ * VIR_PERF_PARAM_CACHE_REFERENCES:
+ *
+ * Macro for typed parameter name that represents cache_references
+ * perf event which can be used to measure the count of cache hits
+ * by applications running on the platform. It corresponds to the
+ * "perf.cache_references" field in the *Stats APIs.
+ */
+# define VIR_PERF_PARAM_CACHE_REFERENCES "cache_references"
+
+/**
+ * VIR_PERF_PARAM_INSTRUCTIONS:
+ *
+ * Macro for typed parameter name that represents instructions perf
+ * event which can be used to measure the count of instructions
+ * by applications running on the platform. It corresponds to the
+ * "perf.instructions" field in the *Stats APIs.
+ */
+# define VIR_PERF_PARAM_INSTRUCTIONS "instructions"
+
+/**
+ * VIR_PERF_PARAM_CPU_CYCLES:
+ *
+ * Macro for typed parameter name that represents cpu_cycles perf event
+ * which can be used to measure how many cpu cycles one instruction needs.
+ * It corresponds to the "perf.cpu_cycles" field in the *Stats APIs.
+ */
+# define VIR_PERF_PARAM_CPU_CYCLES "cpu_cycles"
+
int virDomainGetPerfEvents(virDomainPtr dom,
virTypedParameterPtr *params,
int *nparams,
diff --git a/src/libvirt-domain.c b/src/libvirt-domain.c
index 4f08349..46f0318 100644
--- a/src/libvirt-domain.c
+++ b/src/libvirt-domain.c
@@ -11457,6 +11457,15 @@ virConnectGetDomainCapabilities(virConnectPtr conn,
* "perf.mbml" - the amount of data (bytes/s) sent through the memory controller
* on the socket as unsigned long long. It is produced by mbml
* perf event.
+ * "perf.cache_misses" - the count of cache misses as unsigned long long.
+ * It is produced by cache_misses perf event.
+ * "perf.cache_references" - the count of cache hits as unsigned long long.
+ * It is produced by cache_references perf event.
+ * "perf.instructions" - The count of instructions as unsigned long long.
+ * It is produced by instructions perf event.
+ * "perf.cpu_cycles" - The number of cpu cycles one instruction needs as
+ * unsigned long long. It is produced by cpu_cycles
+ * perf event.
*
* Note that entire stats groups or individual stat fields may be missing from
* the output in case they are not supported by the given hypervisor, are not
diff --git a/src/qemu/qemu_driver.c b/src/qemu/qemu_driver.c
index b41eaa3..b81745d 100644
--- a/src/qemu/qemu_driver.c
+++ b/src/qemu/qemu_driver.c
@@ -9637,6 +9637,10 @@ qemuDomainSetPerfEvents(virDomainPtr dom,
VIR_PERF_PARAM_CMT, VIR_TYPED_PARAM_BOOLEAN,
VIR_PERF_PARAM_MBMT, VIR_TYPED_PARAM_BOOLEAN,
VIR_PERF_PARAM_MBML, VIR_TYPED_PARAM_BOOLEAN,
+ VIR_PERF_PARAM_CPU_CYCLES, VIR_TYPED_PARAM_BOOLEAN,
+ VIR_PERF_PARAM_INSTRUCTIONS, VIR_TYPED_PARAM_BOOLEAN,
+ VIR_PERF_PARAM_CACHE_REFERENCES, VIR_TYPED_PARAM_BOOLEAN,
+ VIR_PERF_PARAM_CACHE_MISSES, VIR_TYPED_PARAM_BOOLEAN,
NULL) < 0)
return -1;
diff --git a/src/util/virperf.c b/src/util/virperf.c
index 018000a..cd66b05 100644
--- a/src/util/virperf.c
+++ b/src/util/virperf.c
@@ -38,7 +38,9 @@ VIR_LOG_INIT("util.perf");
#define VIR_FROM_THIS VIR_FROM_PERF
VIR_ENUM_IMPL(virPerfEvent, VIR_PERF_EVENT_LAST,
- "cmt", "mbmt", "mbml");
+ "cmt", "mbmt", "mbml",
+ "cpu_cycles", "instructions",
+ "cache_references", "cache_misses");
struct virPerfEvent {
int type;
@@ -71,6 +73,18 @@ static struct virPerfEventAttr attrs[] = {
{.type = VIR_PERF_EVENT_CMT, .attrType = 0, .attrConfig = 1},
{.type = VIR_PERF_EVENT_MBMT, .attrType = 0, .attrConfig = 2},
{.type = VIR_PERF_EVENT_MBML, .attrType = 0, .attrConfig = 3},
+ {.type = VIR_PERF_EVENT_CPU_CYCLES,
+ .attrType = PERF_TYPE_HARDWARE,
+ .attrConfig = PERF_COUNT_HW_CPU_CYCLES},
+ {.type = VIR_PERF_EVENT_INSTRUCTIONS,
+ .attrType = PERF_TYPE_HARDWARE,
+ .attrConfig = PERF_COUNT_HW_INSTRUCTIONS},
+ {.type = VIR_PERF_EVENT_CACHE_REFERENCES,
+ .attrType = PERF_TYPE_HARDWARE,
+ .attrConfig = PERF_COUNT_HW_CACHE_REFERENCES},
+ {.type = VIR_PERF_EVENT_CACHE_MISSES,
+ .attrType = PERF_TYPE_HARDWARE,
+ .attrConfig = PERF_COUNT_HW_CACHE_MISSES},
};
typedef struct virPerfEventAttr *virPerfEventAttrPtr;
diff --git a/src/util/virperf.h b/src/util/virperf.h
index bdafe03..41be878 100644
--- a/src/util/virperf.h
+++ b/src/util/virperf.h
@@ -32,6 +32,11 @@ typedef enum {
VIR_PERF_EVENT_MBMT, /* Memory Bandwidth Monitoring Total */
VIR_PERF_EVENT_MBML, /* Memory Bandwidth Monitor Limit for controller */
+ VIR_PERF_EVENT_CPU_CYCLES, /* CPU Cycles per instruction */
+ VIR_PERF_EVENT_INSTRUCTIONS, /* Count of instructions for application */
+ VIR_PERF_EVENT_CACHE_REFERENCES, /* Cache hits by applications */
+ VIR_PERF_EVENT_CACHE_MISSES, /* Cache misses by applications */
+
VIR_PERF_EVENT_LAST
} virPerfEventType;
diff --git a/tests/genericxml2xmlindata/generic-perf.xml b/tests/genericxml2xmlindata/generic-perf.xml
index 394d2a6..a914133 100644
--- a/tests/genericxml2xmlindata/generic-perf.xml
+++ b/tests/genericxml2xmlindata/generic-perf.xml
@@ -16,6 +16,10 @@
<event name='cmt' enabled='yes'/>
<event name='mbmt' enabled='no'/>
<event name='mbml' enabled='yes'/>
+ <event name='cpu_cycles' enabled='no'/>
+ <event name='instructions' enabled='yes'/>
+ <event name='cache_references' enabled='no'/>
+ <event name='cache_misses' enabled='no'/>
</perf>
<devices>
</devices>
diff --git a/tools/virsh.pod b/tools/virsh.pod
index 7ce498b..0a77978 100644
--- a/tools/virsh.pod
+++ b/tools/virsh.pod
@@ -934,6 +934,10 @@ I<--perf> returns the statistics of all enabled perf events:
"perf.cmt" - the cache usage in Byte currently used
"perf.mbmt" - total system bandwidth from one level of cache
"perf.mbml" - bandwidth of memory traffic for a memory controller
+"perf.cpu_cycles" - the number of cpu cycles one instruction needs
+"perf.instructions" - the count of instructions
+"perf.cache_references" - the count of cache hits
+"perf.cache_misses" - the count of caches misses
See the B<perf> command for more details about each event.
@@ -2237,6 +2241,15 @@ B<Valid perf event names>
mbml - Provides a way to limit the amount of data
(bytes/s) send through the memory controller
on the socket.
+ cache_misses - Provides the count of cache misses by
+ applications running on the platform.
+ cache_references - Provides the count of cache hits by
+ applications running on th e platform.
+ instructions - Provides the count of instructions executed
+ by applications running on the platform.
+ cpu_cycles - Provides the number of cpu_cycles for one
+ instruction. May be used with instructions
+ in order to get a cycles per instruction.
B<Note>: The statistics can be retrieved using the B<domstats> command using
the I<--perf> flag.
--
2.7.4
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