[libvirt PATCH v3 0/2] Add script to sync from QEMU i386 cpu models

[Tim Wiederhake]

This hopefully makes synchronization with QEMU faster and less
error prone.

Patch #2 showcases the changes to the cpu models the script
suggests for qemu 8d90bfc5c31ad60f6049dd39be636b06bc00b652.

V1: https://www.redhat.com/archives/libvir-list/2020-October/msg01008.html
V2: https://www.redhat.com/archives/libvir-list/2020-October/msg01051.html

Changes since last version:
* Fix issues found by flake8

Tim Wiederhake (2):
  cpu_map: Add script to sync from QEMU i386 cpu models
  [DONTMERGE] Sample output of new sync script

 src/cpu_map/sync_qemu_i386.py                 | 369 ++++++++++++++++++
 src/cpu_map/x86_486.xml                       |   8 +
 src/cpu_map/x86_Broadwell-IBRS.xml            |  19 +-
 src/cpu_map/x86_Broadwell-noTSX-IBRS.xml      |  19 +-
 src/cpu_map/x86_Broadwell-noTSX.xml           |  19 +-
 src/cpu_map/x86_Broadwell.xml                 |  18 +-
 src/cpu_map/x86_Cascadelake-Server-noTSX.xml  |  20 +-
 src/cpu_map/x86_Cascadelake-Server.xml        |  17 +-
 src/cpu_map/x86_Conroe.xml                    |  10 +-
 src/cpu_map/x86_Cooperlake.xml                |   8 +-
 src/cpu_map/x86_Denverton.xml                 |  74 ++++
 src/cpu_map/x86_Dhyana.xml                    |  12 +-
 src/cpu_map/x86_EPYC-IBPB.xml                 |  19 +-
 src/cpu_map/x86_EPYC-Rome.xml                 |   9 +
 src/cpu_map/x86_EPYC.xml                      |  14 +-
 src/cpu_map/x86_Haswell-IBRS.xml              |  20 +-
 src/cpu_map/x86_Haswell-noTSX-IBRS.xml        |  20 +-
 src/cpu_map/x86_Haswell-noTSX.xml             |  20 +-
 src/cpu_map/x86_Haswell.xml                   |  18 +-
 src/cpu_map/x86_Icelake-Client-noTSX.xml      |  14 +-
 src/cpu_map/x86_Icelake-Client.xml            |  11 +-
 src/cpu_map/x86_Icelake-Server-noTSX.xml      |  29 +-
 src/cpu_map/x86_Icelake-Server.xml            |  11 +-
 src/cpu_map/x86_IvyBridge-IBRS.xml            |  13 +-
 src/cpu_map/x86_IvyBridge.xml                 |  12 +-
 src/cpu_map/x86_KnightsMill.xml               |  77 ++++
 src/cpu_map/x86_Nehalem-IBRS.xml              |  14 +-
 src/cpu_map/x86_Nehalem.xml                   |  13 +-
 src/cpu_map/x86_Opteron_G1.xml                |   9 +-
 src/cpu_map/x86_Opteron_G2.xml                |  10 +-
 src/cpu_map/x86_Opteron_G3.xml                |  10 +-
 src/cpu_map/x86_Opteron_G4.xml                |  11 +-
 src/cpu_map/x86_Opteron_G5.xml                |  11 +-
 src/cpu_map/x86_Penryn.xml                    |  10 +-
 src/cpu_map/x86_SandyBridge-IBRS.xml          |  14 +-
 src/cpu_map/x86_SandyBridge.xml               |  13 +-
 src/cpu_map/x86_Skylake-Client-IBRS.xml       |  16 +-
 src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml |  18 +-
 src/cpu_map/x86_Skylake-Client.xml            |  15 +-
 src/cpu_map/x86_Skylake-Server-IBRS.xml       |  12 +-
 src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml |  15 +-
 src/cpu_map/x86_Skylake-Server.xml            |  12 +-
 src/cpu_map/x86_Snowridge.xml                 |  79 ++++
 src/cpu_map/x86_Westmere-IBRS.xml             |  13 +-
 src/cpu_map/x86_Westmere.xml                  |  14 +-
 src/cpu_map/x86_athlon.xml                    |   8 +
 src/cpu_map/x86_core2duo.xml                  |  12 +-
 src/cpu_map/x86_coreduo.xml                   |  10 +-
 src/cpu_map/x86_kvm32.xml                     |   9 +
 src/cpu_map/x86_kvm64.xml                     |   9 +
 src/cpu_map/x86_n270.xml                      |  12 +-
 src/cpu_map/x86_pentium.xml                   |   9 +
 src/cpu_map/x86_pentium2.xml                  |   9 +
 src/cpu_map/x86_pentium3.xml                  |   9 +
 src/cpu_map/x86_phenom.xml                    |  17 +-
 src/cpu_map/x86_qemu32.xml                    |   8 +
 src/cpu_map/x86_qemu64.xml                    |  17 +-
 57 files changed, 1188 insertions(+), 130 deletions(-)
 create mode 100755 src/cpu_map/sync_qemu_i386.py
 create mode 100644 src/cpu_map/x86_Denverton.xml
 create mode 100644 src/cpu_map/x86_KnightsMill.xml
 create mode 100644 src/cpu_map/x86_Snowridge.xml

-- 
2.26.2