[PULL 05/66] target/mips/mips-defs: Reorder CPU_MIPS5 definition
Philippe Mathieu-Daudé
f4bug at amsat.org
Thu Jan 7 22:21:52 UTC 2021
Move CPU_MIPS5 after CPU_MIPS4 :)
Reviewed-by: Jiaxun Yang <jiaxun.yang at flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson at linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug at amsat.org>
Message-Id: <20210104221154.3127610-3-f4bug at amsat.org>
---
target/mips/mips-defs.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 555e165fb01..48544ba73b4 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -65,13 +65,12 @@
#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
+#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
-#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
-
/* MIPS Technologies "Release 1" */
#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
--
2.26.2
More information about the libvir-list
mailing list