[edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 09/15] MdeModulePkg/PciBusDxe: Enable RelaxedOrdering feature
Javeed, Ashraf
ashraf.javeed at intel.com
Sun May 10 16:14:06 UTC 2020
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Program phase feature init routine for RelaxedOrdering
PCIe feature.
Signed-off-by: Ashraf Javeed <ashraf.javeed at intel.com>
Signed-off-by: Ray Ni <ray.ni at intel.com>
Cc: Jian J Wang <jian.j.wang at intel.com>
Cc: Hao A Wu <hao.a.wu at intel.com>
Cc: Ray Ni <ray.ni at intel.com>
Cc: Ashraf Javeed <ashraf.javeed at intel.com>
---
MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 3 +++
MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 7 +++++++
3 files changed, 59 insertions(+)
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
index e1f739e..9948e17 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
@@ -56,6 +56,8 @@ PCIE_FEATURE_ENTRY mPcieFeatures[] = {
TRUE, { TRUE, TRUE }, { MaxPayloadSizeScan, MaxPayloadSizeProgram } },
{ OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, MaxReadRequestSize),
TRUE, { TRUE, TRUE }, { NULL, MaxReadRequestSizeProgram } },
+ { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, RelaxedOrdering),
+ TRUE, { TRUE, TRUE }, { NULL, RelaxedOrderingProgram } },
};
/**
@@ -230,6 +232,7 @@ PcieNotifyDeviceState (
PcieDeviceState.MaxPayloadSize = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.MaxPayloadSize;
PcieDeviceState.MaxReadRequestSize = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.MaxReadRequestSize;
+ PcieDeviceState.RelaxedOrdering = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.RelaxedOrdering;
return mPciePlatformProtocol->NotifyDeviceState (
mPciePlatformProtocol,
PciIoDevice->Handle,
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
index a7591e6..5216dac 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
@@ -167,3 +167,52 @@ MaxReadRequestSizeProgram (
return EFI_SUCCESS;
}
+
+/**
+ Program the PCIe Device Control register Relaxed Ordering field per platform policy.
+
+ @param PciDevice A pointer to the PCI_IO_DEVICE instance.
+ @param Level The level of the PCI device in the heirarchy.
+ Level of root ports is 0.
+ @param Context Pointer to feature specific context.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI device.
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
+ valid for the PCI configuration header of the PCI controller.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
+**/
+EFI_STATUS
+RelaxedOrderingProgram (
+ IN PCI_IO_DEVICE *PciDevice,
+ IN UINTN Level,
+ IN VOID **Context
+ )
+{
+ ASSERT (*Context == NULL);
+
+ if (PciDevice->DeviceState.RelaxedOrdering == EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE ||
+ PciDevice->DeviceState.RelaxedOrdering == EFI_PCI_EXPRESS_DEVICE_POLICY_AUTO) {
+ return EFI_SUCCESS;
+ }
+
+ if (PciDevice->PciExpressCapability.DeviceControl.Bits.RelaxedOrdering != PciDevice->DeviceState.RelaxedOrdering) {
+ DEBUG ((
+ DEBUG_INFO, " %a [%02d|%02d|%02d]: %x -> %x\n",
+ __FUNCTION__, PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber,
+ PciDevice->PciExpressCapability.DeviceControl.Bits.RelaxedOrdering,
+ PciDevice->DeviceState.RelaxedOrdering
+ ));
+ PciDevice->PciExpressCapability.DeviceControl.Bits.RelaxedOrdering = PciDevice->DeviceState.RelaxedOrdering;
+
+ return PciDevice->PciIo.Pci.Write (
+ &PciDevice->PciIo,
+ EfiPciIoWidthUint16,
+ PciDevice->PciExpressCapabilityOffset
+ + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl),
+ 1,
+ &PciDevice->PciExpressCapability.DeviceControl.Uint16
+ );
+ }
+ return EFI_SUCCESS;
+}
+
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
index 40e28b8..7d70f06 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
@@ -31,4 +31,11 @@ MaxReadRequestSizeProgram (
IN VOID **Context
);
+EFI_STATUS
+RelaxedOrderingProgram (
+ IN PCI_IO_DEVICE *PciDevice,
+ IN UINTN Level,
+ IN VOID **Context
+ );
+
#endif
--
2.21.0.windows.1
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