[edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/15] MdeModulePkg/PciBusDxe: Enable MaxReadRequestSize feature
Ni, Ray
ray.ni at intel.com
Wed May 13 06:49:09 UTC 2020
Reviewed-by: Ray Ni <ray.ni at intel.com>
> -----Original Message-----
> From: Javeed, Ashraf <ashraf.javeed at intel.com>
> Sent: Monday, May 11, 2020 12:14 AM
> To: devel at edk2.groups.io
> Cc: Ni, Ray <ray.ni at intel.com>; Wang, Jian J <jian.j.wang at intel.com>; Wu, Hao A <hao.a.wu at intel.com>
> Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/15] MdeModulePkg/PciBusDxe: Enable MaxReadRequestSize
> feature
>
> REF:
> https://bugzilla.tianocore.org/show_bug.cgi?id=1954
> https://bugzilla.tianocore.org/show_bug.cgi?id=2194
> https://bugzilla.tianocore.org/show_bug.cgi?id=2313
> https://bugzilla.tianocore.org/show_bug.cgi?id=2499
> https://bugzilla.tianocore.org/show_bug.cgi?id=2500
>
> Add the Program phase feature init routine for MaxReadRequestSize
> PCIe feature.
>
> Signed-off-by: Ashraf Javeed <ashraf.javeed at intel.com>
> Signed-off-by: Ray Ni <ray.ni at intel.com>
> Cc: Jian J Wang <jian.j.wang at intel.com>
> Cc: Hao A Wu <hao.a.wu at intel.com>
> Cc: Ray Ni <ray.ni at intel.com>
> Cc: Ashraf Javeed <ashraf.javeed at intel.com>
> ---
> MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 3 +++
> MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
> MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 6 ++++++
> 3 files changed, 59 insertions(+)
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
> index 634e26b..e1f739e 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
> @@ -54,6 +54,8 @@ PCIE_FEATURE_ENTRY mPcieFeatures[] = {
> //
> { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, MaxPayloadSize),
> TRUE, { TRUE, TRUE }, { MaxPayloadSizeScan, MaxPayloadSizeProgram } },
> + { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, MaxReadRequestSize),
> + TRUE, { TRUE, TRUE }, { NULL, MaxReadRequestSizeProgram } },
> };
>
> /**
> @@ -227,6 +229,7 @@ PcieNotifyDeviceState (
> CopyMem (&PcieDeviceState, &PciIoDevice->DeviceState, sizeof (PciIoDevice->DeviceState));
>
> PcieDeviceState.MaxPayloadSize = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.MaxPayloadSize;
> + PcieDeviceState.MaxReadRequestSize = (UINT8)PciIoDevice-
> >PciExpressCapability.DeviceControl.Bits.MaxReadRequestSize;
> return mPciePlatformProtocol->NotifyDeviceState (
> mPciePlatformProtocol,
> PciIoDevice->Handle,
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
> index d1a78f7..a7591e6 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
> @@ -117,3 +117,53 @@ MaxPayloadSizeProgram (
> return EFI_SUCCESS;
> }
>
> +/**
> + Program the PCIe Device Control register Max. Read Request Size field per platform policy.
> +
> + @param PciDevice A pointer to the PCI_IO_DEVICE instance.
> + @param Level The level of the PCI device in the heirarchy.
> + Level of root ports is 0.
> + @param Context Pointer to feature specific context.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PCI device.
> + @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
> + valid for the PCI configuration header of the PCI controller.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
> +**/
> +EFI_STATUS
> +MaxReadRequestSizeProgram (
> + IN PCI_IO_DEVICE *PciDevice,
> + IN UINTN Level,
> + IN VOID **Context
> + )
> +{
> + ASSERT (*Context == NULL);
> +
> + if (PciDevice->DeviceState.MaxReadRequestSize == EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE) {
> + return EFI_SUCCESS;
> + }
> + if (PciDevice->DeviceState.MaxReadRequestSize == EFI_PCI_EXPRESS_DEVICE_POLICY_AUTO) {
> + PciDevice->DeviceState.MaxReadRequestSize = (UINT8) PciDevice-
> >PciExpressCapability.DeviceControl.Bits.MaxPayloadSize;
> + }
> +
> + if (PciDevice->PciExpressCapability.DeviceControl.Bits.MaxReadRequestSize != PciDevice-
> >DeviceState.MaxReadRequestSize) {
> + DEBUG ((
> + DEBUG_INFO, " %a [%02d|%02d|%02d]: %x -> %x\n",
> + __FUNCTION__, PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber,
> + PciDevice->PciExpressCapability.DeviceControl.Bits.MaxReadRequestSize,
> + PciDevice->DeviceState.MaxReadRequestSize
> + ));
> + PciDevice->PciExpressCapability.DeviceControl.Bits.MaxReadRequestSize = PciDevice->DeviceState.MaxReadRequestSize;
> +
> + return PciDevice->PciIo.Pci.Write (
> + &PciDevice->PciIo,
> + EfiPciIoWidthUint16,
> + PciDevice->PciExpressCapabilityOffset
> + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl),
> + 1,
> + &PciDevice->PciExpressCapability.DeviceControl.Uint16
> + );
> + }
> + return EFI_SUCCESS;
> +}
> +
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
> index 7b820e8..40e28b8 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
> @@ -24,5 +24,11 @@ MaxPayloadSizeProgram (
> IN VOID **Context
> );
>
> +EFI_STATUS
> +MaxReadRequestSizeProgram (
> + IN PCI_IO_DEVICE *PciDevice,
> + IN UINTN Level,
> + IN VOID **Context
> + );
>
> #endif
> --
> 2.21.0.windows.1
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