[edk2-devel][edk2-platforms][PATCH V1 2/9] WhitleySiliconPkg: Add definitions used in ACPI subsystem
Oram, Isaac W
isaac.w.oram at intel.com
Thu Mar 10 22:41:07 UTC 2022
Needed to convert FvLateOpenBoard ACPI binary drivers to open source.
Cc: Nate DeSimone <nathaniel.l.desimone at intel.com>
Cc: Chasel Chiu <chasel.chiu at intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram at intel.com>
---
Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 3 +
Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStruct.h | 7 +
Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuConfigLib.h | 82 ++++
Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h | 3 +
Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h | 301 ++++++++++++
Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h | 2 +
Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h | 74 ++-
Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib.h | 494 ++++++++++++++++++++
Silicon/Intel/WhitleySiliconPkg/Include/Library/SpdAccessLib.h | 32 ++
Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h | 7 +
Silicon/Intel/WhitleySiliconPkg/Include/Platform.h | 7 +
Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h | 2 +-
Silicon/Intel/WhitleySiliconPkg/Include/Protocol/AcpiPlatformProtocol.h | 51 ++
Silicon/Intel/WhitleySiliconPkg/Include/Protocol/CpuCsrAccess.h | 254 ++++++++++
Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol.h | 43 +-
Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol2.h | 255 ++++++++++
Silicon/Intel/WhitleySiliconPkg/Include/Protocol/NfitTableUpdateProtocol.h | 27 ++
Silicon/Intel/WhitleySiliconPkg/Include/Protocol/SmbiosMemInfo.h | 87 ++++
Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h | 2 +
Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h | 25 +
Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h | 34 +-
Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/MemDefaults.h | 7 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchInfoHob.h | 50 ++
Silicon/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec | 1 +
24 files changed, 1783 insertions(+), 67 deletions(-)
diff --git a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
index 902abd30f8..2ccdbffa35 100644
--- a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
@@ -82,6 +82,9 @@
gRcSimBiosIdFileGuid = { 0xf0c51ad5, 0x44f0, 0x4622, { 0x95, 0x15, 0xe2, 0x7, 0x71, 0xf0, 0xe0, 0xf2 }}
gSystemTopologyGuid = { 0x743e5992, 0xf2a0, 0x4c9f, { 0xa5, 0xf5, 0x3b, 0x24, 0xad, 0xe8, 0x7f, 0x4d }}
+[Protocols]
+ gEfiCpuCsrAccessGuid = { 0x0067835f, 0x9a50, 0x433a, { 0x8c, 0xbb, 0x85, 0x20, 0x78, 0x19, 0x78, 0x14 }}
+
[PPIs]
## Include/Ppi/MemorySetupPolicyPpi.h
gMemoryPolicyPpiGuid = { 0x731b6dbc, 0x18ac, 0x4cc3, { 0x9e, 0xe2, 0x9e, 0x5f, 0x33, 0x39, 0x68, 0x81 }}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStruct.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStruct.h
index aaabf032f9..e1416a0d1c 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStruct.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStruct.h
@@ -24,4 +24,11 @@
//
#define CONFIG_TDP_TOTAL_LEVEL 5
+typedef struct {
+ UINT32 RegEax;
+ UINT32 RegEbx;
+ UINT32 RegEcx;
+ UINT32 RegEdx;
+} EFI_CPUID_REGISTER;
+
#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuConfigLib.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuConfigLib.h
index 298fe08624..805f2ac6c8 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuConfigLib.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuConfigLib.h
@@ -19,6 +19,88 @@
#define C0_ENABLE 0x00
#define C6_ENABLE 0x03
+//
+// Structure for collected CPUID data.
+//
+typedef struct {
+ EFI_CPUID_REGISTER *CpuIdLeaf;
+ UINTN NumberOfBasicCpuidLeafs;
+ UINTN NumberOfExtendedCpuidLeafs;
+ UINTN NumberOfCacheAndTlbCpuidLeafs;
+ UINTN NumberOfDeterministicCacheParametersCpuidLeafs;
+ UINTN NumberOfExtendedTopologyEnumerationLeafs;
+} CPU_CPUID_DATA;
+
+typedef struct {
+ UINTN Ratio;
+ UINTN Vid;
+ UINTN Power;
+ UINTN TransitionLatency;
+ UINTN BusMasterLatency;
+} FVID_ENTRY;
+
+typedef struct {
+ VOID *MicrocodeData;
+ UINTN MicrocodeSize;
+ UINT32 ProcessorId;
+} MICROCODE_INFO;
+
+//
+// Miscellaneous processor data
+//
+typedef struct {
+ //
+ // Local Apic Data
+ //
+ UINT32 InitialApicID; ///< Initial APIC ID
+ UINT32 ApicID; ///< Current APIC ID
+ EFI_PHYSICAL_ADDRESS ApicBase;
+ UINT32 ApicVersion;
+ //
+ // Frequency data
+ //
+ UINTN IntendedFsbFrequency;
+ UINTN ActualFsbFrequency;
+ UINTN MaxCoreToBusRatio;
+ UINTN MinCoreToBusRatio;
+ UINTN MaxTurboRatio;
+ UINTN PackageTdp;
+ UINTN NumberOfPStates;
+ FVID_ENTRY *FvidTable;
+ UINTN GreaterNumberOfPStates; // Greater Than 16 p-state support
+ FVID_ENTRY *GreaterFvidTable; // Greater Than 16 p-state support
+ //
+ // Other data
+ //
+ UINT32 MicrocodeRevision;
+ UINT64 EnabledThreadCountMsr;
+ MICROCODE_INFO MicrocodeInfo;
+ UINT64 MiscEnablesMsr;
+} CPU_MISC_DATA;
+
+//
+// Structure for all collected processor data
+//
+typedef struct {
+ CPU_CPUID_DATA CpuidData;
+ EFI_CPU_PHYSICAL_LOCATION ProcessorLocation;
+ CPU_MISC_DATA CpuMiscData;
+ UINT8 PackageIdBitOffset;
+ BOOLEAN PackageBsp;
+} CPU_COLLECTED_DATA;
+
+//
+// Definition of Processor Configuration Context Buffer
+//
+typedef struct {
+ UINTN NumberOfProcessors;
+ UINTN BspNumber;
+ CPU_COLLECTED_DATA *CollectedDataBuffer;
+ CPU_REGISTER_TABLE *PreSmmInitRegisterTable;
+ CPU_REGISTER_TABLE *RegisterTable;
+ BOOLEAN RegisterTableSaved;
+} CPU_CONFIG_CONTEXT_BUFFER;
+
//
// Structure conveying socket ID configuration information.
//
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h b/Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h
index 0e9fbde11f..88d7e02dcf 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h
@@ -12,6 +12,9 @@
#define R_ACPI_LV2 0x14
+#define R_IOPORT_CMOS_STANDARD_INDEX 0x70
+#define R_IOPORT_CMOS_STANDARD_DATA 0x71
+
#define R_IOPORT_CMOS_UPPER_INDEX 0x72
#define R_IOPORT_CMOS_UPPER_DATA 0x73
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h b/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h
new file mode 100644
index 0000000000..0b80015c65
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h
@@ -0,0 +1,301 @@
+/** @file
+
+ @copyright
+ Copyright 2006 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _bdat_h
+#define _bdat_h
+
+//
+// Memory location that don't care was set to 0xFF
+//
+#define DO_NOT_CARE 0xFF
+
+#pragma pack(1)
+
+typedef struct bdatSchemaHeader {
+ EFI_GUID SchemaId;
+ UINT32 DataSize;
+ UINT16 Crc16;
+} BDAT_SCHEMA_HEADER_STRUCTURE;
+
+//
+// SPD data schema related definition
+//
+
+//
+// Memory SPD Data Header
+//
+typedef struct {
+ EFI_GUID MemSpdGuid; // GUID that uniquely identifies the memory SPD data revision
+ UINT32 Size; // Total size in bytes including the header and all SPD data
+ UINT32 Crc; // 32-bit CRC generated over the whole size minus this crc field
+ // Note: UEFI 32-bit CRC implementation (CalculateCrc32)
+ // Consumers can ignore CRC check if not needed.
+ UINT32 Reserved; // Reserved for future use, must be initialized to 0
+} MEM_SPD_RAW_DATA_HEADER;
+
+//
+// Memory SPD Raw Data
+//
+typedef struct {
+ MEM_SPD_RAW_DATA_HEADER Header;
+
+ //
+ // This is a dynamic region, where SPD data entries are filled out.
+ //
+} MEM_SPD_DATA_STRUCTURE;
+
+typedef struct {
+ BDAT_SCHEMA_HEADER_STRUCTURE SchemaHeader;
+ MEM_SPD_DATA_STRUCTURE SpdData;
+} BDAT_MEM_SPD_STRUCTURE;
+
+//
+// List of all entry types supported by this revision of memory SPD data structure
+//
+typedef enum {
+ MemSpdDataType0 = 0,
+
+ MemSpdDataTypeMax,
+ MemSpdDataTypeDelim = MAX_INT32
+} MEM_SPD_DATA_TYPE;
+
+//
+// Generic entry header for all memory SPD raw data entries
+//
+typedef struct {
+ MEM_SPD_DATA_TYPE Type;
+ UINT16 Size; // Entries will be packed by byte in contiguous space. Size of the entry includes the header.
+} MEM_SPD_DATA_ENTRY_HEADER;
+
+//
+// Structure to specify SPD dimm memory location
+//
+typedef struct {
+ UINT8 Socket;
+ UINT8 Channel;
+ UINT8 Dimm;
+} MEM_SPD_DATA_ENTRY_MEMORY_LOCATION;
+
+//
+// Type 0: SPD RDIMM/LRDIMM DDR4
+// The NumberOfBytes are 512 for DDR4.
+//
+typedef struct {
+ MEM_SPD_DATA_ENTRY_HEADER Header;
+ MEM_SPD_DATA_ENTRY_MEMORY_LOCATION MemoryLocation;
+ UINT16 NumberOfBytes;
+ //
+ // This is a dynamic region, where SPD data are filled out.
+ // The total number of bytes of the SPD data must match NumberOfBytes
+ //
+} MEM_SPD_ENTRY_TYPE0;
+
+//
+// Memory training data schema related definition
+//
+
+//
+// Memory training Data Header
+//
+typedef struct {
+ EFI_GUID MemDataGuid; // GUID that uniquely identifies the memory training data revision
+ UINT32 Size; // Total size in bytes including the header and all memory training data
+ UINT32 Crc; // 32-bit CRC generated over the whole size minus this crc field
+ // Note: UEFI 32-bit CRC implementation (CalculateCrc32)
+ // Consumers can ignore CRC check if not needed.
+ UINT32 Reserved; // Reserved for future use, must be initialized to 0
+} MEM_TRAINING_DATA_HEADER;
+
+//
+// Memory SPD Raw Data
+//
+typedef struct {
+ MEM_TRAINING_DATA_HEADER Header;
+
+ //
+ // This is a dynamic region, where memory training data entries are filled out.
+ //
+} MEM_TRAINING_DATA_STRUCTURE;
+
+typedef struct {
+ BDAT_SCHEMA_HEADER_STRUCTURE SchemaHeader;
+ MEM_TRAINING_DATA_STRUCTURE Data;
+} BDAT_MEM_TRAINING_STRUCTURE;
+
+//
+// List of all entry types supported by this revision of memory training data structure
+//
+typedef enum {
+ MemTrainingDataCapability = 0,
+ MemTrainingDataIoGroup = 1,
+ MemTrainingDataDram = 2,
+ MemTrainingDataRcd = 3,
+ MemTrainingDataIoSignal = 4,
+ MemTrainingDataIoLatency = 5,
+
+ MemTrainingDataTypeMax,
+ MemTrainingDataTypeDelim = MAX_INT32
+} MEM_TRAINING_DATA_TYPE;
+
+//
+// Generic entry header for all memory training data entries
+//
+typedef struct {
+ MEM_TRAINING_DATA_TYPE Type;
+ UINT16 Size; // Entries will be packed by byte in contiguous space. Size of the entry includes the header.
+} MEM_TRAINING_DATA_ENTRY_HEADER;
+
+//
+// Structure to specify memory training data location
+//
+typedef struct {
+ UINT8 Socket;
+ UINT8 Channel;
+ UINT8 SubChannel;
+ UINT8 Dimm; // 0xFF = n/a
+ UINT8 Rank; // 0xFF = n/a
+} MEM_TRAINING_DATA_ENTRY_MEMORY_LOCATION;
+
+//
+// List of memory training data scope
+//
+typedef enum {
+ PerBitMemTrainData = 0,
+ PerStrobeMemTrainData = 1,
+ PerRankMemTrainData = 2,
+ PerSubChannelMemTrainData = 3,
+ PerChannelMemTrainData = 4,
+
+ MemTrainDataScopeMax,
+ MemTrainDataScopDelim = MAX_INT32
+} MEM_TRAINING_DATA_SCOPE;
+
+//
+// Type 0: Define the capability. This info can be helpful for
+// the code to display the training data.
+//
+
+typedef struct {
+ MEM_TRAINING_DATA_ENTRY_HEADER Header;
+ UINT8 EccEnable;
+ UINT8 MaxSocket;
+ UINT8 MaxChannel;
+ UINT8 MaxSubChannel; // It is 1 if there is no sub-channel
+ UINT8 MaxDimm;
+ UINT8 MaxRank;
+ UINT8 MaxStrobePerSubChannel; // It is the MaxStrobe of the chanenl if there is no sub-channel
+ UINT8 MaxBitsPerSubChannel; // It is the MaxBits of the chanenl if there is no sub-channel
+} MEM_TRAINING_DATA_ENTRY_TYPE0;
+
+//
+// Type 1: General training data that commonly accessed by GetSet API via Group
+//
+
+typedef struct {
+ MEM_TRAINING_DATA_ENTRY_HEADER Header;
+ MEM_TRAINING_DATA_ENTRY_MEMORY_LOCATION MemoryLocation;
+ MRC_LT Level;
+ MRC_GT Group;
+ MEM_TRAINING_DATA_SCOPE Scope; // If Scope is PerSubChannelMemTrainData or PerChannelMemTrainData, the training
+ // is applicable to whole SubChannel or Channel regardless the Dimm or Rank.
+ // The MemoryLoaction.Dimm and MemoryLoaction.Rank should be ignored.
+ UINT8 NumberOfElements;
+ UINT8 SizeOfElement; // Number of bytes of each training data element.
+ // 1: UINT8
+ // 2: UINT16
+ // 4: UINT32
+ //
+ // This is a dynamic region, where training data are filled out.
+ // The total number of bytes of the training data must be equal to
+ // NumberOfElements * SizeOfElement
+ //
+} MEM_TRAINING_DATA_ENTRY_TYPE1;
+
+//
+// Type 2: DRAM mode register data
+//
+
+typedef struct {
+ MEM_TRAINING_DATA_ENTRY_HEADER Header;
+ MEM_TRAINING_DATA_ENTRY_MEMORY_LOCATION MemoryLocation;
+ UINT8 NumberOfModeRegisters;
+ UINT8 NumberOfDrams;
+
+ //
+ // This is a dynamic region, where DRAM mode register data are filled out.
+ // Each mode register data is one byte. The total number of bytes of the data must be equal to
+ // NumberOfModeRegisters * NumberOfDrams. The data is indexed as [ModeRegister][Dram]
+ //
+} MEM_TRAINING_DATA_ENTRY_TYPE2;
+
+//
+// Type 3: RCD data
+//
+
+typedef struct {
+ MEM_TRAINING_DATA_ENTRY_HEADER Header;
+ MEM_TRAINING_DATA_ENTRY_MEMORY_LOCATION MemoryLocation;
+ UINT8 NumberOfRegisters;
+
+ //
+ // This is a dynamic region, where RCD RW register data are filled out.
+ // Each RW register data is one byte. The total number of bytes of the data must be equal to
+ // NumberOfRegisters.
+ //
+} MEM_TRAINING_DATA_ENTRY_TYPE3;
+
+//
+// Type 4: IO Signal training data
+//
+typedef struct {
+ MRC_GT Signal;
+ INT16 Value;
+} SIGNAL_DATA;
+
+typedef struct {
+ MEM_TRAINING_DATA_ENTRY_HEADER Header;
+ MEM_TRAINING_DATA_ENTRY_MEMORY_LOCATION MemoryLocation;
+ MRC_LT Level;
+ MEM_TRAINING_DATA_SCOPE Scope; // If Scope is PerSubChannelMemTrainData or PerChannelMemTrainData, the training
+ // is applicable to whole SubChannel or Channel regardless the Dimm or Rank.
+ // The MemoryLoaction.Dimm and MemoryLoaction.Rank should be ignored.
+ UINT8 NumberOfSignals; // Number of SIGNAL_DATA struct
+ //
+ // This is a dynamic region, where signal training data are filled out.
+ // Each signal training data element is defined by a SIGNAL_DATA struct.
+ // The total number of bytes of the training data must be equal to
+ // NumberOfSignals * sizeof (SIGNAL_DATA)
+ //
+} MEM_TRAINING_DATA_ENTRY_TYPE4;
+
+//
+// Type 5: IO latency, Round trip and IO Comp training data
+//
+
+typedef struct {
+ MEM_TRAINING_DATA_ENTRY_HEADER Header;
+ MEM_TRAINING_DATA_ENTRY_MEMORY_LOCATION MemoryLocation;
+ MEM_TRAINING_DATA_SCOPE Scope; // If Scope is PerSubChannelMemTrainData or PerChannelMemTrainData, the training
+ // is applicable to whole SubChannel or Channel regardless the Dimm or Rank.
+ // The MemoryLoaction.Dimm and MemoryLoaction.Rank should be ignored.
+ UINT8 IoLatency;
+ UINT8 RoundTrip;
+ UINT8 IoComp;
+} MEM_TRAINING_DATA_ENTRY_TYPE5;
+
+//
+// Memory training data HOB header
+// This header contains the actual size of the training data in the HOB. The HOB data size is
+// always mutiples of 8.
+//
+typedef struct {
+ UINT32 Size;
+} MEM_TRAINING_DATA_HOB_HEADER;
+
+#pragma pack()
+#endif // _bdat_h
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
index 1512b90881..73f303594a 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
@@ -13,6 +13,8 @@
#include "SysHost.h"
#include "PartialMirrorGuid.h"
+#define MEM_IMCCH_TO_SKTCH(Imc, Ch) ((Imc) * MAX_MC_CH + (Ch))
+
#define RESERVED_2 2
#define RESERVED_4 4
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
index 98f759be81..37a1e627da 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
@@ -124,32 +124,54 @@
//-----------------------------------------------------------------------------------
// Port Index definition for ICX-SP
//------------------------------------------------------------------------------------
+#define PCIE_PORT_0_DEV_0 0x03
+#define PCIE_PORT_0_FUNC_0 0x00
-// IOU0
-#define PORT_1A_INDEX_1 1
-#define PORT_1B_INDEX_1 2
-#define PORT_1C_INDEX_1 3
-#define PORT_1D_INDEX_1 4
-// IOU1
-#define PORT_2A_INDEX_2 5
-#define PORT_2B_INDEX_2 6
-#define PORT_2C_INDEX_2 7
-#define PORT_2D_INDEX_2 8
-// IOU2
-#define PORT_3A_INDEX_3 9
-#define PORT_3B_INDEX_3 10
-#define PORT_3C_INDEX_3 11
-#define PORT_3D_INDEX_3 12
-// IOU3
-#define PORT_4A_INDEX_4 13
-#define PORT_4B_INDEX_4 14
-#define PORT_4C_INDEX_4 15
-#define PORT_4D_INDEX_4 16
-// IOU4
-#define PORT_5A_INDEX_5 17
-#define PORT_5B_INDEX_5 18
-#define PORT_5C_INDEX_5 19
-#define PORT_5D_INDEX_5 20
+#define PCIE_PORT_1A_DEV_1 0x02
+#define PCIE_PORT_1A_FUNC_1 0x00
+#define PCIE_PORT_1B_DEV_1 0x03
+#define PCIE_PORT_1C_DEV_1 0x04
+#define PCIE_PORT_1D_DEV_1 0x05
+#define PCIE_PORT_1A_FUNC_1 0x00
+#define PCIE_PORT_1B_FUNC_1 0x00
+#define PCIE_PORT_1C_FUNC_1 0x00
+#define PCIE_PORT_1D_FUNC_1 0x00
+
+#define PCIE_PORT_2A_DEV_2 0x02
+#define PCIE_PORT_2B_DEV_2 0x03
+#define PCIE_PORT_2C_DEV_2 0x04
+#define PCIE_PORT_2D_DEV_2 0x05
+#define PCIE_PORT_2A_FUNC_2 0x00
+#define PCIE_PORT_2B_FUNC_2 0x00
+#define PCIE_PORT_2C_FUNC_2 0x00
+#define PCIE_PORT_2D_FUNC_2 0x00
+
+#define PCIE_PORT_3A_DEV_3 0x02
+#define PCIE_PORT_3B_DEV_3 0x03
+#define PCIE_PORT_3C_DEV_3 0x04
+#define PCIE_PORT_3D_DEV_3 0x05
+#define PCIE_PORT_3A_FUNC_3 0x00
+#define PCIE_PORT_3B_FUNC_3 0x00
+#define PCIE_PORT_3C_FUNC_3 0x00
+#define PCIE_PORT_3D_FUNC_3 0x00
+
+#define PCIE_PORT_4A_DEV_4 0x02
+#define PCIE_PORT_4B_DEV_4 0x03
+#define PCIE_PORT_4C_DEV_4 0x04
+#define PCIE_PORT_4D_DEV_4 0x05
+#define PCIE_PORT_4A_FUNC_4 0x00
+#define PCIE_PORT_4B_FUNC_4 0x00
+#define PCIE_PORT_4C_FUNC_4 0x00
+#define PCIE_PORT_4D_FUNC_4 0x00
+
+#define PCIE_PORT_5A_DEV_5 0x02
+#define PCIE_PORT_5B_DEV_5 0x03
+#define PCIE_PORT_5C_DEV_5 0x04
+#define PCIE_PORT_5D_DEV_5 0x05
+#define PCIE_PORT_5A_FUNC_5 0x00
+#define PCIE_PORT_5B_FUNC_5 0x00
+#define PCIE_PORT_5C_FUNC_5 0x00
+#define PCIE_PORT_5D_FUNC_5 0x00
//
// Port Config Mode
@@ -158,6 +180,8 @@
#define VMD_OWNERSHIP 3
#define PCIEAIC_OCL_OWNERSHIP 4
+#define DMI_BUS_NUM 0
+
#define NUMBER_TRACE_HUB_PER_SOCKET 1
//
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib.h
new file mode 100644
index 0000000000..211dc48c86
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib.h
@@ -0,0 +1,494 @@
+/** @file
+ Interface header file for the Enhanced warning log library class.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ENHANCED_WARNING_LOG_LIB_
+#define _ENHANCED_WARNING_LOG_LIB_
+
+#include <Uefi.h>
+#include <MrcCommonTypes.h>
+
+#pragma pack(1)
+
+///
+/// Enhanced Warning Log Identification GUID
+/// This GUID is used for HOB, UEFI variables, or UEFI Configuration Table as needed by platform implementations
+/// {D8E05800-005E-4462-AA3D-9C6B4704920B}
+///
+#define EWL_ID_GUID { 0xd8e05800, 0x5e, 0x4462, { 0xaa, 0x3d, 0x9c, 0x6b, 0x47, 0x4, 0x92, 0xb } };
+
+///
+/// Enhanced Warning Log Revision GUID
+/// Rev 1: {75713370-3805-46B0-9FED-60F282486CFC}
+///
+#define EWL_REVISION1_GUID { 0x75713370, 0x3805, 0x46b0, { 0x9f, 0xed, 0x60, 0xf2, 0x82, 0x48, 0x6c, 0xfc } };
+
+///
+/// Enhanced Warning Log Header
+///
+typedef struct {
+ EFI_GUID EwlGuid; /// GUID that uniquely identifies the EWL revision
+ UINT32 Size; /// Total size in bytes including the header and buffer
+ UINT32 FreeOffset; /// Offset of the beginning of the free space from byte 0
+ /// of the buffer immediately following this structure
+ /// Can be used to determine if buffer has sufficient space for next entry
+ UINT32 Crc; /// 32-bit CRC generated over the whole size minus this crc field
+ /// Note: UEFI 32-bit CRC implementation (CalculateCrc32) (References [7])
+ /// Consumers can ignore CRC check if not needed.
+ UINT32 Reserved; /// Reserved for future use, must be initialized to 0
+} EWL_HEADER;
+
+///
+/// List of all entry types supported by this revision of EWL
+///
+typedef enum {
+ EwlType0 = 0,
+ EwlType1 = 1,
+ EwlType2 = 2,
+ EwlType3 = 3,
+ EwlType4 = 4,
+ EwlType5 = 5,
+ EwlType6 = 6,
+ EwlType7 = 7,
+ EwlType8 = 8,
+ EwlType9 = 9,
+ EwlType10 = 10,
+ EwlType11 = 11,
+ EwlType12 = 12,
+ EwlType13 = 13,
+ EwlType14 = 14,
+ EwlType15 = 15,
+ EwlType16 = 16,
+ EwlType17 = 17,
+ EwlType18 = 18,
+ EwlType19 = 19,
+ EwlType20 = 20,
+ EwlType21 = 21,
+ EwlType22 = 22,
+ EwlType23 = 23,
+ EwlType24 = 24,
+ EwlType25 = 25,
+ EwlType26 = 26,
+ EwlType27 = 27,
+ EwlType28 = 28,
+ EwlType29 = 29,
+ EwlTypeMax,
+ EwlTypeOem = 0x8000,
+ EwlTypeDelim = MAX_INT32
+ } EWL_TYPE;
+
+///
+/// EWL severities
+///
+typedef enum {
+ EwlSeverityInfo,
+ EwlSeverityWarning,
+ EwlSeverityFatal,
+ EwlSeverityMax,
+ EwlSeverityDelim = MAX_INT32
+ } EWL_SEVERITY;
+
+///
+/// EWL Size\Type Structure for error checking
+///
+typedef struct {
+ EWL_TYPE Type;
+ UINT16 Size;
+} EWL_SIZE_CHECK;
+
+///
+/// Generic entry header for parsing the log
+///
+typedef struct {
+ EWL_TYPE Type;
+ UINT16 Size; /// Entries will be packed by byte in contiguous space
+ EWL_SEVERITY Severity; /// Warning, error, informational, this may be extended in the future
+} EWL_ENTRY_HEADER;
+
+///
+/// Legacy content provides context of the warning
+///
+typedef struct {
+ UINT8 MajorCheckpoint; // EWL Spec - Appendix B
+ UINT8 MinorCheckpoint;
+ UINT8 MajorWarningCode; // EWL Spec - Appendix A
+ UINT8 MinorWarningCode;
+} EWL_ENTRY_CONTEXT;
+
+///
+/// Legacy content to specify memory location
+///
+typedef struct {
+ UINT8 Socket; /// 0xFF = n/a
+ UINT8 Channel; /// 0xFF = n/a
+ UINT8 Dimm; /// 0xFF = n/a
+ UINT8 Rank; /// 0xFF = n/a
+} EWL_ENTRY_MEMORY_LOCATION;
+
+///
+/// Type 1 = Legacy memory warning log content plus checkpoint
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+} EWL_ENTRY_TYPE1;
+
+///
+/// Type 2 = Enhanced type for data IO errors per device, per bit.
+/// Primarily associated with MRC training failures. Checkpoint information provides additional
+/// details to identify associated training step.
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+ UINT8 Strobe; /// 0xFF = n/a; include mapping of Dqs to Dq bits
+ UINT8 Bit; /// 0xFF = n/a; Dq bit# within strobe group
+ MRC_LT Level; /// MrcGtDelim = n/a; Check BIOS SSA spec (References [1])
+ MRC_GT Group; /// MrcGtDelim = n/a; Check BIOS SSA spec (References [1])
+ UINT8 EyeSize; /// 0xFF = n/a
+} EWL_ENTRY_TYPE2;
+
+///
+/// Type 3 = Enhanced type for command, control IO errors
+/// Primarily associated with MRC training failures. Checkpoint information provides additional
+/// details to identify associated training step.
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+ MRC_LT Level; /// MrcGtDelim = n/a; Check BIOS SSA spec (References [1])
+ MRC_GT Group; /// MrcGtDelim = n/a; Check BIOS SSA spec (References [1])
+ GSM_CSN Signal; /// GsmCsnDelim = n/a
+ UINT8 EyeSize; /// 0xFF = n/a
+} EWL_ENTRY_TYPE3;
+
+///
+/// Requisite definitions for Type 4
+///
+/// Advanced Memtest Types
+///
+typedef enum {
+ AdvMtMax = 20,
+ AdvMtDelim = MAX_INT32
+ } ADV_MT_TYPE;
+
+///
+/// Advanced Memtest Error log structure based on processor specific CSR definitions
+///
+typedef struct {
+ UINT32 Dat0S;
+ UINT32 Dat1S;
+ UINT32 Dat2S;
+ UINT32 Dat3S;
+ UINT32 EccS;
+ UINT32 Chunk;
+ UINT32 Column;
+ UINT32 ColumnExt;
+ UINT32 Row;
+ UINT32 RowExt;
+ UINT32 Bank;
+ UINT32 Rank;
+ UINT32 Subrank;
+} EWL_ADV_MT_STATUS;
+
+///
+/// Type 4 = Enhanced type for DRAM Advanced Memtest errors
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+ ADV_MT_TYPE MemtestType;
+ EWL_ADV_MT_STATUS AdvMemtestErrorInfo;
+ UINT32 Count;
+} EWL_ENTRY_TYPE4;
+
+///
+/// Type 5 = Legacy Memtest accumulated DQ errors
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+ UINT8 SubRank;
+ UINT8 BankAddress;
+ UINT8 DqBytes[9]; /// Byte 0 = DQ[7:0], byte 1 = DQ[15:8], etc.
+} EWL_ENTRY_TYPE5;
+
+///
+/// Type 6 = Legacy UPI/KTIRC warning log content plus checkpoint
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ UINT8 SocketMask; /// Bitmask of CPU Sockets affected; 0xFF = SystemWide
+ UINT8 SocketType; /// 0 = CPU Socket, 1 = FPGA, 0xFF = System Wide Warning
+ UINT8 Port; /// 0xFF = n/a; bitmask of affected port(s)
+} EWL_ENTRY_TYPE6;
+
+///
+/// Type 7 = CPU BIST failures
+///
+typedef struct{
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ UINT8 Socket; /// Socket number, 0 based
+ UINT32 Core; /// Core number, 0 based
+} EWL_ENTRY_TYPE7;
+
+///
+/// IIO Link Error log structure primary based on PCIE Specification 3.0 (References [8])
+///
+typedef struct {
+ UINT8 Socket; /// Socket number, 0 based
+ UINT8 Stack; /// 0-4, 0 = Cstack, 1-3 = Pstack, 4 MCP-stack (Only SKX-F)
+ UINT8 Port; /// 0-3
+ UINT8 LtssmMainState; /// Link state
+ UINT8 LtssmSubState; /// Check Appendix C to review states definitions
+ UINT32 DidVid; /// [31:16] DeviceID, [15:0] VendorID of the device
+ /// attached to the Root Port
+} EWL_IIO_LINK_DESCRIPTION;
+
+///
+/// Type 8 = IIO Link Degraded width
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_IIO_LINK_DESCRIPTION LinkDescription;
+ UINT8 ExpectedLinkWidth; /// Check register "Link Capabilities Register" over
+ UINT8 ActualLinkWidth; /// PCIE Specification 3.0 (References [8])
+} EWL_ENTRY_TYPE8;
+
+///
+/// Type 9 = IIO Link Degraded speed
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_IIO_LINK_DESCRIPTION LinkDescription;
+ UINT8 ExpectedLinkSpeed; /// Check register "Link Capabilities Register" over
+ UINT8 ActualLinkSpeed; /// PCIE Specification 3.0 (References [8])
+} EWL_ENTRY_TYPE9;
+
+///
+/// Type 10 = Dq Swizzle Discovery errors
+/// Error if 0 or greater than 1 bit set in SwizzledDqLanes per strobe
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+ UINT8 SwizzlePattern; /// DQ pattern sent from device
+ UINT8 SwizzledDqLanes; /// DQ pattern received at Host
+ UINT8 LanesPerStrobe; /// 4 or 8
+ UINT8 Strobe; /// DQS number to identify device
+} EWL_ENTRY_TYPE10;
+
+///
+/// Type 13 = NVMDIMM Training Failure
+/// Reported when a training issue is encountered
+/// Includes additional details on the NVMDIMM SPD and FW revisions
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+ UINT16 RevisionNvmdimmFw;
+ UINT8 RevisionNvmdimmSpd;
+} EWL_ENTRY_TYPE13;
+
+///
+/// Type 17 = ME communication failures
+/// Failure to communicate with Manageability Engine
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ UINT32 Revision; /// ME API Revision
+ UINT32 Mefs1; /// ME Firmware Status 1 (HECI-1 HFS)
+ UINT32 Mefs2; /// ME Firmware Status 2 (HECI-1 GS_SHDW)
+ UINT8 HeciDevice; /// HECI device (1, 2, or 3)
+ UINT8 MeAddress; /// HECI address of ME entity
+ UINT8 SendStatus; /// Status of send operation
+ UINT8 ReceiveStatus; /// Status of receive operation
+ UINT64 Request; /// First 8 bytes of request message
+ UINT32 Response; /// First 4 bytes of response message
+} EWL_ENTRY_TYPE17;
+
+///
+/// To get more information about Machine-Check Architecture please check Chapter 15 from Vol. 3B
+/// of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual (References [6]) for a
+/// general review.
+///
+/// Type 20 = CPU Machine Check Errors
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ UINT32 CpuId; /// Refer to CPUID(EAX = 1) instruction to get Type, Family,
+ /// Model, and Stepping ID from (References [6])
+ UINT8 Socket; /// Socket number, 0 based
+ UINT32 Core; /// Core number, 0 based
+ UINT32 McBankNum; /// Please refer to mcBankTable
+ UINT32 McBankStatus; /// Check register IA32_MCi_STATUS MSRs (References [6]&[5])
+ UINT32 McBankAddr; /// Check register IA32_MCi_ADDR MSRs (References [6]&[5])
+ UINT32 McBankMisc; /// Check register IA32_MCi_MISC MSRs (References [6]&[5])
+} EWL_ENTRY_TYPE20;
+
+///
+/// Requisite definitions for Type 21
+///
+/// Reasons for Topology degradation
+///
+typedef enum {
+ Undefined = 0,
+ LinkFail = 1,
+ InvalidTopology = 2,
+ FeatureVsTopology = 3,
+ DegradeReasonMax,
+ DegradeReasonDelim = MAX_INT32
+ } TOPOLOGY_DEGRADE_REASON;
+
+///
+/// Type 21: Warning for tracking changes to KTI/UPI topology
+///
+/// Topology will be represented with a UINT64 bit array
+/// 0 indicates absent or inactive link
+/// 1 indicates active KTI/UPI link
+///
+/// Link Bit array member variables follow this format
+/// Each nibble corresponds to a socket:
+/// Each socket has MAX_FW_KTI_PORTS bits
+/// [(8*MAX_FW_KTI_PORTS - 1):7*MAX_FW_KTI_PORTS] - link bit mask for socket 7
+/// [(7*MAX_FW_KTI_PORTS - 1):6*MAX_FW_KTI_PORTS] - link bit mask for socket 6
+/// ....
+/// [(2*MAX_FW_KTI_PORTS - 1): MAX_FW_KTI_PORTS] - link bit mask for socket 1
+/// [(MAX_FW_KTI_PORTS - 1) : 0] - link bit mask for socket 0
+///
+/// Bit 0 indicates an active link on port socket 0 port 0
+/// Bit 1 indicates an active link on port socket 0 port 1
+/// and so on.
+
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ TOPOLOGY_DEGRADE_REASON Reason;
+ UINT64 DegradedFrom; /// Link Bit Array
+ UINT64 NewTopology; /// Link Bit Array
+} EWL_ENTRY_TYPE21;
+
+///
+/// To get more information about Machine-Check Architecture please check Chapter 15 from Vol. 3B
+/// of the Intel 64 and IA-32 Architectures Software Developer's Manual (References [6]) for a
+/// general review.
+///
+/// Type 22 = CPU Machine Check Errors. 2nd Version.
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ UINT32 CpuId; /// Refer to CPUID(EAX=1) instruction to get Type, Family,
+ /// Model, and Stepping ID from (References [6])
+ UINT8 Socket; /// Socket number, 0 based
+ UINT32 Core; /// Core number, 0 based
+ UINT32 McBankNum; /// Please refer to mcBankTable
+ UINT64 McBankStatus; /// Check register IA32_MCi_STATUS MSRs (References [6]&[5])
+ UINT64 McBankAddr; /// Check register IA32_MCi_ADDR MSRs (References [6]&[5])
+ UINT64 McBankMisc; /// Check register IA32_MCi_MISC MSRs (References [6]&[5])
+} EWL_ENTRY_TYPE22;
+
+//
+// Memory Boot Health check Warning log.
+//
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+ MRC_GT Group; /// MrcGtDelim = n/a;
+ INT16 Offset; /// Signal offset size that caused the error
+} EWL_ENTRY_TYPE25;
+
+//
+// Memory Power Management Errors
+//
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+} EWL_ENTRY_TYPE26;
+
+///
+/// Type 27 = NVMDIMM Media Log
+/// Reported NVMDIMM Media log
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+ UINT64 TimeStamp;
+ UINT64 DPA;
+ UINT64 PDA;
+ UINT8 Range;
+ UINT8 ErrorType;
+ UINT8 ErrorFlag;
+ UINT8 TransacationType;
+ UINT16 SequenceNumber;
+ UINT16 Rsvd;
+} EWL_ENTRY_TYPE27;
+
+///
+/// Type 28 = NVMDIMM Thermal Log
+/// Reported NVMDIMM Thermal log
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+ UINT64 TimeStamp;
+ UINT32 HostReportedTempData;
+ UINT16 SequenceNumber;
+ UINT16 Rsvd;
+} EWL_ENTRY_TYPE28;
+
+//
+// RMT minimum margin check warning log.
+//
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+ MRC_GT Group;
+ INT16 NegativeMargin;
+ INT16 PositiveMargin;
+ INT16 MinimumMargin;
+} EWL_ENTRY_TYPE29;
+
+#pragma pack()
+
+///
+/// Enhanced Warning Log Spec defined data log structure
+///
+typedef struct {
+ EWL_HEADER Header; /// The size will vary by implementation and should not be assumed
+ UINT8 Buffer[4 * 1024]; /// The spec requirement is that the buffer follow the header
+} EWL_PUBLIC_DATA;
+
+///
+/// EWL private data structure. This is going to be implementation dependent
+/// When we separate OEM hooks via a PPI, we can remove this
+///
+typedef struct {
+ UINT32 bufSizeOverflow; // Number of bytes that could not be added to buffer
+ UINT32 numEntries; // Number of entries currently logged
+ EWL_PUBLIC_DATA status; // Spec defined EWL
+} EWL_PRIVATE_DATA;
+
+#endif // #ifndef _ENHANCED_WARNING_LOG_LIB_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/SpdAccessLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/SpdAccessLib.h
new file mode 100644
index 0000000000..4b15795665
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/SpdAccessLib.h
@@ -0,0 +1,32 @@
+/** @file
+ The SPD Access Library API provides the necessary functions to initiate SPD
+ read/write transactions.
+
+ This API is designed to function as an interface between an agent that needs
+ to read/write to a DIMM SPD and a lower level library (such as an SMBus library)
+ which handles the actual transactions. The read/write functions accept DIMM
+ location information as well as the SPD byte offset and should then handle
+ the steps necessary to initiate (for example) a SMBus transaction to do the
+ reading/writing. Functions are also provided to initialize any data/setup
+ steps needed before attempting a read/write transaction and to communicate to
+ the library that DIMM detection is complete providing a way for the library
+ to know that it can check for a DIMM's presence bofore initiating a transaction.
+
+ @copyright
+ Copyright 2018 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SPD_ACCESS_LIB_H_
+#define _SPD_ACCESS_LIB_H_
+
+//
+// DDR Technology supported
+//
+typedef enum {
+ Ddr4Type = 0, // DDR4 Technology support
+ DdrMaxType // Enum limit to check valid value
+} DDR_TECHNOLOGY_TYPE;
+
+#endif // #ifndef _SPD_ACCESS_LIB_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h b/Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h
index 6958b1431b..af9f0b0734 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h
@@ -38,4 +38,11 @@ typedef enum {
TYPE_MAX_MMIO_BAR
} MMIO_BARS;
+//
+// Memory parameters and SPD JEDEC definitions
+//
+#define MAX_SPD_BYTE_DDR4 512 // Number of bytes in Serial EEPROM on DDR4
+
+#define MAX_SPD_BYTE_DDR MAX_SPD_BYTE_DDR4
+
#endif //#ifndef __MEM_COMMON_H__
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Platform.h b/Silicon/Intel/WhitleySiliconPkg/Include/Platform.h
index b8ed188f16..e3cc80acde 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Platform.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Platform.h
@@ -224,6 +224,8 @@
#define PCH_TCO_BASE_ADDRESS PcdGet16 (PcdTcoBaseAddress)
+#define PM_BASE_ADDRESS PCH_ACPI_BASE_ADDRESS
+
#define SIO_GPIO_BASE_ADDRESS 0x0800
//
@@ -240,6 +242,8 @@
#define CMOS_PLATFORM_ID_LO 0x18 // Second bank CMOS location of Platform ID
#define CMOS_PLATFORM_ID_HI 0x19 //
+#define HPET_BLOCK_ADDRESS 0x0FED00000
+
#define PCI_BUS_NUMBER_PCH_HPET 0x0
#define PCI_DEVICE_NUMBER_PCH_HPET 0x1F
@@ -250,6 +254,9 @@
#define PCI_FUNCTION_NUMBER_PCH_IOAPIC 0x0
+#define SW_SMI_OS_REQUEST 0x83 // OS transition request.
+#define MEM_ADDR_SHFT_VAL 26 // For 64 MB granularity
+
//
// AHCI port offset values
//
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
index 6c5ca06bc1..38b90713f7 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
@@ -999,7 +999,7 @@ struct memSetup {
/// @brief
/// Pirnt length of SPD data.<BR>
/// @details
- /// 0 - AUTO(512 for DDR4, 1024 for DDR5).<BR>
+ /// 0 - AUTO(512 for DDR4).<BR>
/// 256.<BR>
/// 512.<BR>
///
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/AcpiPlatformProtocol.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/AcpiPlatformProtocol.h
new file mode 100644
index 0000000000..d7f1adca4d
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/AcpiPlatformProtocol.h
@@ -0,0 +1,51 @@
+/** @file
+ EFI ACPI Platform Protocol
+
+ @copyright
+ Copyright 2018 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_PLATFORM_PROTOCOL_H
+#define _ACPI_PLATFORM_PROTOCOL_H
+
+#include <IndustryStandard/Acpi62.h>
+
+///
+/// ACPI Platform protocol provided for DXE phase
+///
+typedef struct _ACPI_PLATFORM_PROTOCOL ACPI_PLATFORM_PROTOCOL;
+
+typedef EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE ACPI_MEMORY_AFFINITY_DATA;
+#define ACPI_MEMORY_NONVOLATILE EFI_ACPI_6_2_MEMORY_NONVOLATILE
+
+/**
+ Function retrieves selected data of ACPI SRAT Memory Affinity Structures
+ (please note that data will not be available until SRAT table installation)
+
+ @param[out] *MemAffData ACPI Memory Affinity Data
+ @param[out] *MemAffDataLength ACPI Memory Affinity Data Length
+
+ @retval EFI_SUCCESS ACPI Memory Affinity Data retrieved successfully
+ @retval EFI_NOT_FOUND ACPI Memory Affinity Data not found (SRAT ACPI table was not published)
+ @retval EFI_INVALID_PARAMETER One or more of input arguments is NULL
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_ACPI_MEMORY_AFFINITY_DATA) (
+ OUT ACPI_MEMORY_AFFINITY_DATA **MemAffData,
+ OUT UINTN *MemAffDataLength
+ );
+
+
+/**
+ ACPI Platform protocol provided for DXE phase
+**/
+struct _ACPI_PLATFORM_PROTOCOL {
+ GET_ACPI_MEMORY_AFFINITY_DATA GetAcpiMemoryAffinityData;
+};
+
+extern EFI_GUID gAcpiPlatformProtocolGuid;
+
+#endif // _ACPI_PLATFORM_PROTOCOL_H
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/CpuCsrAccess.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/CpuCsrAccess.h
new file mode 100644
index 0000000000..4ace32de62
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/CpuCsrAccess.h
@@ -0,0 +1,254 @@
+/** @file
+ Header file for IOX access APIs.
+
+ @copyright
+ Copyright 2007 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_CSR_ACCESS_H_
+#define _CPU_CSR_ACCESS_H_
+
+extern EFI_GUID gEfiCpuCsrAccessGuid;
+
+/**
+
+ Computes address of CPU Uncore & IIO PCI configuration space using the MMIO mechanism
+
+ @param[in] SocId - CPU Socket Node number
+ @param[in] BoxInst - Box Instance, 0 based
+ @param[in] Offset - Register offset; values come from the auto generated header file
+ @param[in, out] Size - Ptr to register size in bytes (may be updated if pseudo-offset)
+
+ @retval Address
+
+**/
+
+typedef
+UINT64
+(EFIAPI *GET_CPU_CSR_ADDRESS) (
+ IN UINT8 SocId,
+ IN UINT8 BoxInst,
+ IN UINT32 Offset,
+ IN OUT UINT8 *Size
+ );
+
+/**
+
+ Reads CPU Uncore & IIO PCI configuration space using the MMIO mechanism
+
+ @param[in] SocId - CPU Socket Node number
+ @param[in] BoxInst - Box Instance, 0 based
+ @param[in] Offset - Register offset; values come from the auto generated header file
+
+ @retval Register value
+
+**/
+
+typedef
+UINT32
+(EFIAPI *READ_CPU_CSR) (
+ IN UINT8 SocId,
+ IN UINT8 BoxInst,
+ IN UINT32 Offset
+ );
+
+/**
+
+ Writes CPU Uncore & IIO PCI configuration space using the MMIO mechanism
+
+ @param[in] SocId - CPU Socket Node number
+ @param[in] BoxInst - Box Instance, 0 based
+ @param[in] Offset - Register offset; values come from the auto generated header file
+ @param[in] Data - Register data to be written
+
+ @retval None
+
+**/
+
+typedef
+VOID
+(EFIAPI *WRITE_CPU_CSR) (
+ IN UINT8 SocId,
+ IN UINT8 BoxInst,
+ IN UINT32 Offset,
+ IN UINT32 Data
+ );
+
+/**
+
+ Reads CPU Memory Controller configuration space using the MMIO mechanism
+
+ @param[in] SocId - Socket ID
+ @param[in] McId - Memory controller ID
+ @param[in] Offset - Register offset; values come from the auto generated header file
+
+ @retval Register value
+
+**/
+
+typedef
+UINT32
+(EFIAPI *READ_MC_CPU_CSR) (
+ IN UINT8 SocId,
+ IN UINT8 McId,
+ IN UINT32 Offset
+ );
+
+/**
+
+ Writes CPU Memory Controller configuration space using the MMIO mechanism
+
+ @param[in] SocId - Socket ID
+ @param[in] McId - Memory controller ID
+ @param[in] RegOffset - Register offset; values come from the auto generated header file
+ @param[in] Data - Register data to be written
+
+ @retval None
+
+**/
+
+typedef
+VOID
+(EFIAPI *WRITE_MC_CPU_CSR) (
+ IN UINT8 SocId,
+ IN UINT8 McId,
+ IN UINT32 RegOffset,
+ IN UINT32 Data
+ );
+
+/**
+
+ Get CPU Memory Controller configuration space address used by MMIO mechanism
+
+ @param[in] SocId - Socket ID
+ @param[in] McId - Memory controller ID
+ @param[in] Offset - Register offset; values come from the auto generated header file
+
+ @retval MC Register MMCFG address
+
+**/
+
+typedef
+UINTN
+(EFIAPI *GET_MC_CPU_ADDR) (
+ IN UINT8 SocId,
+ IN UINT8 McId,
+ IN UINT32 RegOffset
+ );
+
+/**
+
+ Reads PCI configuration space using the MMIO mechanism
+
+ @param[in] Socket - Socket
+ @param[in] Reg - "Reg" uses the format in the Bus_Dev_Func_CFG.H files
+
+ @retval Value in requested reg
+
+**/
+
+typedef
+UINT32
+(EFIAPI *READ_PCI_CSR) (
+ IN UINT8 Socket,
+ IN UINT32 Reg
+ );
+
+/**
+
+ Writes specified data to PCI configuration space using the MMIO mechanism
+
+ @param[in] Socket - Socket
+ @param[in] Reg - "Reg" uses the format in the Bus_Dev_Func_CFG.H files
+ @param[in] Data - Value to write
+
+ @retval VOID
+
+**/
+
+typedef
+VOID
+(EFIAPI *WRITE_PCI_CSR) (
+ IN UINT8 Socket,
+ IN UINT32 Reg,
+ IN UINT32 Data
+ );
+
+/**
+
+ Get PCI configuration space address used MMIO mechanism
+
+ @param[in] Socket - Socket
+ @param[in] Reg - "Reg" uses the format in the Bus_Dev_Func_CFG.H files
+
+ @retval Address of requested reg
+
+**/
+
+typedef
+UINT32
+(EFIAPI *GET_PCI_CSR_ADDR) (
+ IN UINT8 Socket,
+ IN UINT32 Reg
+ );
+
+/**
+
+ Writes the given command to BIOS to PCU Mailbox Interface CSR register
+
+ @param[in] Socket - CPU Socket number
+ @param[in] Command - Pcu mailbox command to write
+ @param[in] Data - Pcu mailbox data
+
+ @retval error code from the Pcu mailbox (0 = NO ERROR)
+
+**/
+
+typedef
+UINT64
+(EFIAPI *BIOS_2_VCODE_MAILBOX_WRITE) (
+ IN UINT8 Socket,
+ IN UINT32 Command,
+ IN UINT32 Data
+ );
+
+/**
+
+ Writes the checkpoint code to the checkpoint CSR and breaks if match with debug breakpoint
+ @param[in] Socket - Socket to write
+ @param[in] majorCode - Major Checkpoint code to write
+ @param[in] minorCode - Minor Checkpoint code to write
+ @param[in] data - Data specific to the minor checkpoint is written to
+ low word of the checkpoint CSR
+
+ @retval VOID
+
+**/
+
+typedef
+VOID
+(EFIAPI *BREAK_AT_CHECK_POINT) (
+ IN UINT8 Socket,
+ IN UINT8 MajorCode,
+ IN UINT8 MinorCode,
+ IN UINT16 Data
+ );
+
+typedef struct _EFI_CPU_CSR_ACCESS_PROTOCOL {
+ GET_CPU_CSR_ADDRESS GetCpuCsrAddress;
+ READ_CPU_CSR ReadCpuCsr;
+ WRITE_CPU_CSR WriteCpuCsr;
+ BIOS_2_VCODE_MAILBOX_WRITE Bios2VcodeMailBoxWrite;
+ READ_MC_CPU_CSR ReadMcCpuCsr;
+ WRITE_MC_CPU_CSR WriteMcCpuCsr;
+ GET_MC_CPU_ADDR GetMcCpuCsrAddress;
+ READ_PCI_CSR ReadPciCsr;
+ WRITE_PCI_CSR WritePciCsr;
+ GET_PCI_CSR_ADDR GetPciCsrAddress;
+ BREAK_AT_CHECK_POINT BreakAtCheckpoint;
+} EFI_CPU_CSR_ACCESS_PROTOCOL;
+
+#endif // _CPU_CSR_ACCESS_H_
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol.h
index df8317937f..b9531dbf75 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol.h
@@ -1,5 +1,5 @@
/** @file
- Dynamic link silicon library service access Protocol
+ Dynamic link silicon library service access Protocol for earlier boot functions
This protocol abstracts silicon static library accesses via a protocol
@@ -19,6 +19,9 @@
#include <Library/CpuEarlyDataLib.h>
#include <UsraAccessType.h>
#include <IioUniversalData.h>
+#include <Protocol/IioUds.h>
+#include <Protocol/CpuCsrAccess.h>
+#include <GpioConfig.h>
#define DYNAMIC_SI_LIBARY_PROTOCOL_GUID \
{ 0xb235fbed, 0x3b25, 0x4cb3, { 0x98, 0x9c, 0x8c, 0xe7, 0xec, 0x49, 0x8b, 0x7e } }
@@ -30,13 +33,6 @@
// Functions
//
-typedef
-EFI_STATUS
-(EFIAPI *DXE_SET_GPIO_OUTPUT_VALUE) (
- IN UINT32 GPioPad,
- IN UINT32 Value
- );
-
typedef
BOOLEAN
(EFIAPI *DXE_IsCpuAndRevision) (
@@ -79,6 +75,27 @@ VOID
IN UINT32 DidVid
);
+typedef
+EFI_STATUS
+(EFIAPI *DXE_GpioGetInputValue) (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *InputVal
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *DXE_SET_GPIO_OUTPUT_VALUE) (
+ IN UINT32 GPioPad,
+ IN UINT32 Value
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *DXE_GpioSetPadConfig) (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_CONFIG *GpioData
+ );
+
typedef
CHAR8*
(EFIAPI *DXE_PchGetSeriesStr) (
@@ -210,6 +227,13 @@ UINT32
VOID
);
+typedef
+VOID
+(EFIAPI *DXE_WriteScratchpad5) (
+ UINT8 Socket,
+ UINT32 Value
+ );
+
//
// UBA specific silicon abstraction protocol
//
@@ -223,7 +247,9 @@ typedef struct {
DXE_MmPciBase MmPciBase;
DXE_GetSysCpuCsrAccessVar GetSysCpuCsrAccessVar;
DXE_IioPciHookBeforeEnumeration IioPciHookBeforeEnumeration;
+ DXE_GpioGetInputValue GpioGetInputValue;
DXE_SET_GPIO_OUTPUT_VALUE GpioSetOutputValue;
+ DXE_GpioSetPadConfig GpioSetPadConfig;
DXE_PchGetSeriesStr PchGetSeriesStr;
DXE_PchGetSteppingStr PchGetSteppingStr;
DXE_PchGetSkuStr PchGetSkuStr;
@@ -245,6 +271,7 @@ typedef struct {
DXE_ProgramImr2Regs ProgramImr2Regs;
DXE_CheckAndPopulateIedTraceMemory CheckAndPopulateIedTraceMemory;
DXE_ReadScratchpad7 ReadScratchpad7;
+ DXE_WriteScratchpad5 WriteScratchpad5;
} DYNAMIC_SI_LIBARY_PROTOCOL;
extern EFI_GUID gDynamicSiLibraryProtocolGuid;
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol2.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol2.h
new file mode 100644
index 0000000000..5f984aa391
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol2.h
@@ -0,0 +1,255 @@
+/** @file
+ Dynamic link silicon library service access Protocol for later boot functions
+
+ This protocol abstracts silicon static library accesses via a protocol
+
+ @copyright
+ Copyright 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DYNAMIC_SI_LIBARY_PROTOCOL2_H_
+#define _DYNAMIC_SI_LIBARY_PROTOCOL2_H_
+
+#include <Protocol/IioUds.h>
+#include <Protocol/CpuCsrAccess.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/CpuConfigLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define DYNAMIC_SI_LIBARY_PROTOCOL2_GUID { 0x98bdd399, 0x9349, 0x4131, { 0x87, 0x60, 0x90, 0xaf, 0x68, 0x01, 0x21, 0xee } }
+
+#define DYNAMIC_SI_LIBARY_PROTOCOL2_SIGNATURE SIGNATURE_32('D', 'S', 'L', '2')
+#define DYNAMIC_SI_LIBARY_PROTOCOL2_VERSION 0x01
+
+//
+// Functions
+//
+
+typedef
+UINT32
+(EFIAPI *DXE_GetVtdBar) (
+ IN UINT8 SocId,
+ IN UINT8 StackId
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_GetMaxPortPerSocket) (
+ IN UINT8 SocId
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_GetStackPerPort) (
+ IN UINT8 SocId,
+ IN UINT8 PortIndex
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_GetSocketPortBusNum) (
+ IN UINT8 SocId,
+ IN UINT8 PortIndex
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_IioNtbIsEnabled) (
+ IN UINT8 IioIndex,
+ IN UINT8 IioPort,
+ OUT UINT8 *DevNoPtr,
+ OUT UINT8 *FuncNoPtr
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_IioVmdPortIsEnabled) (
+ IN UINT8 IioIndex,
+ IN UINT8 IioPort
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *DXE_IioVmdGetPciLocation) (
+ IN UINT8 IioIndex,
+ IN UINT8 IioStack,
+ OUT UINT8 *PciDevPtr,
+ OUT UINT8 *PciFuncPtr
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_GetCurrentPXPMap) (
+ IN UINT8 SocId,
+ IN UINT8 PortIndex
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_IsSlowBoot) (
+ VOID
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *DXE_UpdatePcatTable) (
+ IN OUT EFI_ACPI_COMMON_HEADER *Table
+ );
+
+#pragma pack(1)
+typedef struct {
+ UINT32 ApicId;
+ UINT32 ThreadIdValue;
+ UINT32 CollocatedChaId;
+ UINT32 SNCProximityDomain;
+} CPU_LOGICAL_THREAD_ID_TABLE;
+#pragma pack()
+
+typedef
+UINT8
+(EFIAPI *DXE_GetNumOfClusterPerSystem) (
+ VOID
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_GetMaxPhysicalAddrBits) (
+ VOID
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_IsMemTypeVolatile) (
+ MEM_TYPE MemType
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_IsMemType2lm) (
+ MEM_TYPE MemType
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_IsMemTypeReserved) (
+ MEM_TYPE MemType
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_IsMemTypeAppDirect) (
+ MEM_TYPE MemType
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_IsMemTypeFpga) (
+ MEM_TYPE MemType
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_GetKtiPortCnt) (
+ VOID
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_GetMaxImc) (
+ VOID
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_GetNumChannelPerMc) (
+ VOID
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_GetAcpiDieCount) (
+ IN UINT8 SocketId
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *DXE_SpdReadByte) (
+ IN UINT8 Socket,
+ IN UINT8 Chan,
+ IN UINT8 Dimm,
+ IN UINT16 ByteOffset,
+ OUT UINT8 *Data
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_DetectHwpFeature) (
+ VOID
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_SocketPresent) (
+ IN UINT32 SocId
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_IfStackPresent) (
+ IN UINT8 SocId,
+ IN UINT8 StackId
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *DXE_PchHpetBaseGet) (
+ OUT UINT32 *HpetBase
+ );
+
+typedef
+UINT32
+(EFIAPI *DXE_PcuGetDesiredCoreSmtDis) (
+ UINT8 Socket
+ );
+
+//
+// UBA specific silicon abstraction protocol
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Version;
+
+ DXE_GetVtdBar GetVtdBar;
+ DXE_GetMaxPortPerSocket GetMaxPortPerSocket;
+ DXE_GetStackPerPort GetStackPerPort;
+ DXE_GetSocketPortBusNum GetSocketPortBusNum;
+ DXE_IioNtbIsEnabled IioNtbIsEnabled;
+ DXE_IioVmdPortIsEnabled IioVmdPortIsEnabled;
+ DXE_IioVmdGetPciLocation IioVmdGetPciLocation;
+ DXE_GetCurrentPXPMap GetCurrentPXPMap;
+ DXE_IsSlowBoot IsSlowBoot;
+ DXE_UpdatePcatTable UpdatePcatTable;
+ DXE_GetNumOfClusterPerSystem GetNumOfClusterPerSystem;
+ DXE_GetMaxPhysicalAddrBits GetMaxPhysicalAddrBits;
+ DXE_IsMemTypeVolatile IsMemTypeVolatile;
+ DXE_IsMemType2lm IsMemType2lm;
+ DXE_IsMemTypeReserved IsMemTypeReserved;
+ DXE_IsMemTypeAppDirect IsMemTypeAppDirect;
+ DXE_IsMemTypeFpga IsMemTypeFpga;
+ DXE_GetKtiPortCnt GetKtiPortCnt;
+ DXE_GetMaxImc GetMaxImc;
+ DXE_GetNumChannelPerMc GetNumChannelPerMc;
+ DXE_GetAcpiDieCount GetAcpiDieCount;
+ DXE_SpdReadByte SpdReadByte;
+ DXE_DetectHwpFeature DetectHwpFeature;
+ DXE_SocketPresent SocketPresent;
+ DXE_IfStackPresent IfStackPresent;
+ DXE_PchHpetBaseGet PchHpetBaseGet;
+ DXE_PcuGetDesiredCoreSmtDis PcuGetDesiredCoreSmtDis;
+} DYNAMIC_SI_LIBARY_PROTOCOL2;
+
+extern EFI_GUID gDynamicSiLibraryProtocol2Guid;
+
+#endif // _DYNAMIC_SI_LIBARY_PROTOCOL2_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/NfitTableUpdateProtocol.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/NfitTableUpdateProtocol.h
new file mode 100644
index 0000000000..bd85f646c9
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/NfitTableUpdateProtocol.h
@@ -0,0 +1,27 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _NFIT_TABLE_UPDATE_PROTOCOL_H_
+#define _NFIT_TABLE_UPDATE_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiNfitTableUpdateProtocolGuid;
+
+typedef
+EFI_STATUS
+(EFIAPI *NFIT_TABLE_UPDATE) (
+ UINT64 *NfitTablePointer
+ );
+
+typedef struct _EFI_NFIT_TABLE_UPDATE_PROTOCOL {
+ NFIT_TABLE_UPDATE UpdateAcpiTable;
+} EFI_NFIT_TABLE_UPDATE_PROTOCOL;
+
+#endif // _NFIT_TABLE_UPDATE_PROTOCOL_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/SmbiosMemInfo.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/SmbiosMemInfo.h
new file mode 100644
index 0000000000..7b398cf1dc
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/SmbiosMemInfo.h
@@ -0,0 +1,87 @@
+/** @file
+ This file publishes protocol that provides additional information
+ for memory related SMBIOS entries.
+ NOTE: Currently only Type17 entries are used, no need for others identified.
+ Only Type17 entries that represent existing DIMMs are listed.
+
+ @copyright
+ Copyright 2017 - 2018 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PROTOCOL_SMBIOSMEMINFO_H_
+#define _PROTOCOL_SMBIOSMEMINFO_H_
+
+#define SMBIOS_MEMINFO_PROT_VERSION 1
+
+//
+// Invalid SMBIOS handle to use if Type17 entry does not exist.
+//
+#define SMBIOS_INVALID_HANDLE 0xFFFF
+
+typedef struct _SMBIOS_MEM_INFO_PROTOCOL_ SMBIOS_MEM_INFO_PROTOCOL;
+
+/**
+ * Localization information for SMBIOS Type17 entries that represent DIMMs.
+ */
+typedef struct _SMBIOS_DIMM_INFO_ {
+ INT8 Socket; ///< Socket index (0 based)
+ INT8 Imc; ///< Intergrated memory controller in the above socket
+ INT8 Channel; ///< Channel in the above IMC
+ INT8 Dimm; ///< DIMM slot index in the above channel
+ EFI_SMBIOS_HANDLE Type17Handle; ///< Type17 handle in SMBIOS table
+ BOOLEAN IsNvDimm; ///< True if it is Non Volatile DIMM
+} SMBIOS_DIMM_INFO;
+
+
+/**
+ This function finds SMBIOS Type17 entry for given SMBIOS handle.
+
+ On input Info->Handle must be set.
+ On output, unless error was returned, the rest of the structure is filled.
+
+ @param[in] This - Pointer to the protocol
+ @param[in,out] Info - Pointer to DIMM info structure
+
+ @return Standard status codes are returned.
+**/
+typedef EFI_STATUS (EFIAPI *SMBIOS_GET_DIMM_BY_HANDLE) (
+ IN SMBIOS_MEM_INFO_PROTOCOL *This,
+ IN OUT SMBIOS_DIMM_INFO *Info
+ );
+
+/**
+ This function finds SMBIOS Type17 entry for given DIMM location.
+
+ On input Info->Socket, Info->Imc, Info->Channel, Info->Dimm must be set.
+ On output, unless error was returned, the rest of the structure is filled.
+
+ @param[in] This - Pointer to the protocol
+ @param[in,out] Info - Pointer to DIMM info structure.
+
+ @return Standard status codes are returned.
+**/
+typedef EFI_STATUS (EFIAPI *SMBIOS_GET_DIMM_BY_LOCATION) (
+ IN SMBIOS_MEM_INFO_PROTOCOL *This,
+ IN OUT SMBIOS_DIMM_INFO *Info
+ );
+
+/**
+ * This protocol provides information about memory related SMBIOS entries.
+ *
+ * NOTE: Currently only Type17 entries are used, no need for others.
+ * Only Type17 entries that represent existing DIMMs are listed.
+ */
+typedef struct _SMBIOS_MEM_INFO_PROTOCOL_ {
+ UINT16 SmbiosMemInfoProtVersion;
+ UINT8 Reserved[2];
+ UINT32 SmbiosDimmNum; ///< Number of DIMM (Type17) handles in SMBIOS
+
+ SMBIOS_GET_DIMM_BY_HANDLE SmbiosGetDimmByHandle;
+ SMBIOS_GET_DIMM_BY_LOCATION SmbiosGetDimmByLocation;
+} SMBIOS_MEM_INFO_PROTOCOL;
+
+extern EFI_GUID gSmbiosMemInfoProtocolGuid;
+
+#endif // _PROTOCOL_SMBIOSMEMINFO_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h
index 3c8abe4dbb..7b2baa3284 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h
@@ -10,6 +10,8 @@
#ifndef _memregs_h
#define _memregs_h
+#define SPD_TYPE_DDR4 0x0C // DDR4 SDRAM
+
//
// NVM DIMM Reg Structs
//
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h
index eba0a14354..a85e10609a 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h
@@ -21,8 +21,33 @@ typedef struct {
UINT32 NumDqLanesPerCh; // Number of active DQ lanes in a data channel (bus width)
} MRC_MSM;
+typedef enum {
+ DdrLevel = 0, ///< Refers to frontside of DIMM
+ LrbufLevel = 1, ///< Refers to data level at backside of LRDIMM or NVMDIMM buffer
+ RegALevel = 2, ///< Refers to cmd level at backside of register, side A
+ RegBLevel = 3, ///< Refers to cmd level at backside of register, side B
+ HbmLevel = 4, ///< Refers to HBM
+ MrcLtMax,
+ MrcLtDelim = MAX_INT32
+ } MRC_LT;
+
+///
+/// Memory training margin group selectors.
+///
+typedef enum {
+ MrcGtMax = 224,
+ MrcGtDelim = MAX_INT32
+ } MRC_GT;
+
typedef enum {
MrcTtDelim = MAX_INT32
} MRC_TT;
+///
+/// External signal names
+///
+typedef enum {
+ gsmCsnDelim = MAX_INT32
+} GSM_CSN;
+
#endif // _MrcCommonTypes_h_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h
index d419edea4a..50aa342994 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h
@@ -27,39 +27,7 @@ typedef struct sysHost SYSHOST, *PSYSHOST;
#include "PlatformHost.h"
#include "MemHost.h"
#include <Ppi/MemoryPolicyPpi.h>
-
-///
-/// Enhanced Warning Log Header
-///
-typedef struct {
- EFI_GUID EwlGuid; /// GUID that uniquely identifies the EWL revision
- UINT32 Size; /// Total size in bytes including the header and buffer
- UINT32 FreeOffset; /// Offset of the beginning of the free space from byte 0
- /// of the buffer immediately following this structure
- /// Can be used to determine if buffer has sufficient space for next entry
- UINT32 Crc; /// 32-bit CRC generated over the whole size minus this crc field
- /// Note: UEFI 32-bit CRC implementation (CalculateCrc32) (References [7])
- /// Consumers can ignore CRC check if not needed.
- UINT32 Reserved; /// Reserved for future use, must be initialized to 0
-} EWL_HEADER;
-
-///
-/// Enhanced Warning Log Spec defined data log structure
-///
-typedef struct {
- EWL_HEADER Header; /// The size will vary by implementation and should not be assumed
- UINT8 Buffer[4 * 1024]; /// The spec requirement is that the buffer follow the header
-} EWL_PUBLIC_DATA;
-
-///
-/// EWL private data structure. This is going to be implementation dependent
-/// When we separate OEM hooks via a PPI, we can remove this
-///
-typedef struct {
- UINT32 bufSizeOverflow; // Number of bytes that could not be added to buffer
- UINT32 numEntries; // Number of entries currently logged
- EWL_PUBLIC_DATA status; // Spec defined EWL
-} EWL_PRIVATE_DATA;
+#include <Library/EnhancedWarningLogLib.h>
#pragma pack(1)
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/MemDefaults.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/MemDefaults.h
index 68c2f447c9..97f1f45290 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/MemDefaults.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/MemDefaults.h
@@ -17,6 +17,13 @@
#define SMB_CLK_700K 2
#define SMB_CLK_1M 3
+//
+// Volatile Memory Mode
+//
+#define VOL_MEM_MODE_1LM 0
+#define VOL_MEM_MODE_2LM 1
+#define VOL_MEM_MODE_MIX_1LM2LM 2
+
#define MAX_PARTIAL_MIRROR 4 //Maximum number of partial mirror regions that can be created
//
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchInfoHob.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchInfoHob.h
new file mode 100644
index 0000000000..0972181531
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchInfoHob.h
@@ -0,0 +1,50 @@
+/** @file
+ This file contains definitions of PCH Info HOB.
+
+ at copyright
+ Copyright 2018 Intel Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_INFO_HOB_H_
+#define _PCH_INFO_HOB_H_
+
+#include <Library/PchPcieRpLib.h>
+
+extern EFI_GUID gPchInfoHobGuid;
+
+#define PCH_INFO_HOB_REVISION 2
+
+#pragma pack (push,1)
+/**
+ This structure is used to provide the information of PCH controller.
+
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Add CridSupport, CridOrgRid, and CridNewRid.
+**/
+typedef struct {
+ /**
+ This member specifies the revision of the PCH Info HOB. This field is used
+ to indicate backwards compatible changes to the protocol. Platform code that
+ consumes this protocol must read the correct revision value to correctly interpret
+ the content of the protocol fields.
+ **/
+ UINT8 Revision;
+
+ /**
+ Publish Hpet BDF and IoApic BDF information for VTD.
+ **/
+ UINT32 HpetBusNum : 8;
+ UINT32 HpetDevNum : 5;
+ UINT32 HpetFuncNum : 3;
+ UINT32 IoApicBusNum : 8;
+ UINT32 IoApicDevNum : 5;
+ UINT32 IoApicFuncNum : 3;
+} PCH_INFO_HOB;
+
+#pragma pack (pop)
+
+#endif // _PCH_INFO_HOB_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec b/Silicon/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec
index ae951e0b14..d50b1d8da3 100644
--- a/Silicon/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec
@@ -37,6 +37,7 @@ PACKAGE_GUID = 6f1ec317-5d04-456a-8908-6290453d57ac
[Protocols]
gDynamicSiLibraryProtocolGuid = { 0xb235fbed, 0x3b25, 0x4cb3, { 0x98, 0x9c, 0x8c, 0xe7, 0xec, 0x49, 0x8b, 0x7e }}
+ gDynamicSiLibraryProtocol2Guid = { 0x98bdd399, 0x9349, 0x4131, { 0x87, 0x60, 0x90, 0xaf, 0x68, 0x01, 0x21, 0xee }}
gDynamicSiLibrarySmmProtocolGuid = { 0x82faf3a3, 0x6226, 0x48be, {0xb0, 0x4e, 0xc2, 0xfb, 0x0f, 0x72, 0xcf, 0x2f }}
[PcdsDynamicEx]
--
2.27.0.windows.1
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