Fwd: AMD x2 chips
Mark Hahn
hahn at physics.mcmaster.ca
Thu Feb 16 16:00:10 UTC 2006
> > the cores on AMD's dual-core chips are most definitely not
> > independent ICs.
>
> So you're saying the ALUs, FPUs, L1 cache, L2 cache, etc... logic is
> merged between the two cores?
no, that's obviously not the case - you can see it from the die photos.
the cores are clearly laid out as separate blocks - that doesn't mean
they're separate ICs, by any normal definition. for instance, the cores
certainly don't have a pad ring and IO drivers, just to connect to the
SRQ (another on-die block within the same IC.)
> I'm talking a self-contained integrated circuit that operates on its
> own (short of any power/pin-out). From my understanding, there's not
> change in what each core is externally, at least logically (and
> fundamentally electrically) from independent dies.
normally, this is simply called a block. most large ICs have lots of
blocks - most caches are multiple blocks, for instance. that doesn't
mean that the cache can sanely be called multiple ICs.
> > the opposite is true: Intel's DC chips are much closer to being
> > separate ICs, since they're attached with even less bridging
> > (present two bus loads, for instance).
>
> Huh? How does interconnect two "front side busses" to a single
> memory controller hub (MCH) without bridging them _before_?
at least the initial Intel DC implementation literally had
the FSB extended on-die to two electrically independent cores.
since they didn't have a "real" internal bus arbiter, the chip
actually presented 2 bus-loads to the system FSB.
> > so they're going to invent a whole new HT addressing scheme
> > just so they can do glueless HT within the chip?
>
> No, quite the opposite! I'm saying the addressing scheme is the
> _exact_same_. I'm not following your logic at all here.
but you don't seem to be getting the fact that the current HT
has an 8-node limit. since you can already buy an 8-socket,
16-core machine (without any sort of HT switching or bridging),
it's clear that each DC socket acts as a single HT node. it simply
can't somehow have additional HT address range on-chip.
that's the topic: AMD's diagrams and Bill's message point out that
within a single AMD DC chip, the memory, HT ports and core(s) are
connected by a non-HT xbar. the cores are not separately HT-addressable
and neither is the dram interface.
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