Fwd: AMD x2 chips

[Bryan J. Smith]

Mark Hahn <hahn at physics.mcmaster.ca> wrote:
> no, that's obviously not the case - you can see it from the die
> photos. the cores are clearly laid out as separate blocks - that
> doesn't mean they're separate ICs, by any normal definition.  for
> instance, the cores certainly don't have a pad ring and IO drivers,
> just to connect to the SRQ (another on-die block within the same
> IC.)

So in other words, you're talking only _packaging_ differences.
I'm talking about _functional_ units here.

> normally, this is simply called a block.  most large ICs have
> lots of blocks - most caches are multiple blocks, for instance.
> that doesn't mean that the cache can sanely be called multiple
> ICs.

If the peripheral or other logic around the core is _separate_ -- it
literally connects through some bus logic or other arbitration that
is timed _differently_ than the core, then yes, I consider it a
_separate_ IC.  It's just on the same die, moving whatever bus or
other arbitration logic inside of the die.

If the peripherals are integrated as part of the core, timing and
lack of other drivers (such as segmentation by a general bus), then
it's the same IC AFAICT.

Today's foundaries are definitely blurring the distinction, but we
can play this game all day.  Packaging is not how I'd differentiate
between an IC and a die -- it makes the two the _exact_same_.

> at least the initial Intel DC implementation literally had 
> the FSB extended on-die to two electrically independent cores.
> since they didn't have a "real" internal bus arbiter, the chip
> actually presented 2 bus-loads to the system FSB.

But it was still bridging.  There is no way (AFAICT) to just connect
both cores directly to the FSB.

> but you don't seem to be getting the fact that the current HT 
> has an 8-node limit.  since you can already buy an 8-socket,
> 16-core machine (without any sort of HT switching or bridging),
> it's clear that each DC socket acts as a single HT node.  it simply
> can't somehow have additional HT address range on-chip.

Then how do you explain more than 16 sockets using the 4 CPU boards
with HyperTransport connectors between?

I do _not_disagree_ with you that each DC socket acts as a single HT
node from the standpoint of the socket.  I'm merely saying that AMD
uses HyperTransport inside of the processor, or at least some sort of
switched EV6.

> that's the topic: AMD's diagrams and Bill's message point out that 
> within a single AMD DC chip, the memory, HT ports and core(s) are 
> connected by a non-HT xbar.  the cores are not separately
> HT-addressable and neither is the dram interface.

Then what is the xbar?
Is it EV6?

I've always wondered if that's what used to connect a single core to
its memory controller and HyperTransport anyway.

In any case, the changes have been _minimal_ for AMD AFAICT.  The
package changes _little_ with the addition of more CPU cores --
however they are switching it on-die.



-- 
Bryan J. Smith     Professional, Technical Annoyance
b.j.smith at ieee.org      http://thebs413.blogspot.com
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*** Speed doesn't kill, difference in speed does ***