[edk2-devel] [edk2-platforms] [PATCH V1 02/17] WhitleySiliconPkg: Add Includes and Libraries
Nate DeSimone
nathaniel.l.desimone at intel.com
Tue Jul 13 00:41:16 UTC 2021
Signed-off-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
Co-authored-by: Isaac Oram <isaac.w.oram at intel.com>
Co-authored-by: Mohamed Abbas <mohamed.abbas at intel.com>
Cc: Chasel Chiu <chasel.chiu at intel.com>
Cc: Michael D Kinney <michael.d.kinney at intel.com>
Cc: Isaac Oram <isaac.w.oram at intel.com>
Cc: Mohamed Abbas <mohamed.abbas at intel.com>
Cc: Liming Gao <gaoliming at byosoft.com.cn>
Cc: Eric Dong <eric.dong at intel.com>
Cc: Michael Kubacki <Michael.Kubacki at microsoft.com>
---
.../Include/BackCompatible.h | 19 +
.../Include/ConfigBlock/TraceHubConfig.h | 65 +
.../Include/ConfigBlock/Usb2PhyConfig.h | 63 +
.../Include/ConfigBlock/UsbConfig.h | 85 +
.../WhitleySiliconPkg/Include/Cpu/CpuIds.h | 18 +
.../Include/CpuAndRevisionDefines.h | 283 +++
.../Include/EmulationConfiguration.h | 22 +
.../Intel/WhitleySiliconPkg/Include/Fpga.h | 17 +
.../WhitleySiliconPkg/Include/GpioConfig.h | 288 +++
.../Include/Guid/EmulationDfxVariable.h | 25 +
.../Include/Guid/FpgaSocketVariable.h | 39 +
.../Include/Guid/MemBootHealthGuid.h | 71 +
.../Include/Guid/MemoryMapData.h | 197 ++
.../Include/Guid/PartialMirrorGuid.h | 61 +
.../Include/Guid/PlatformInfo.h | 150 ++
.../Guid/SiliconPolicyInitLibInterface.h | 78 +
.../Include/Guid/SocketCommonRcVariable.h | 57 +
.../Include/Guid/SocketIioVariable.h | 444 ++++
.../Include/Guid/SocketMemoryVariable.h | 477 ++++
.../Include/Guid/SocketMpLinkVariable.h | 320 +++
.../Include/Guid/SocketPciResourceData.h | 60 +
.../Guid/SocketPowermanagementVariable.h | 300 +++
.../Guid/SocketProcessorCoreVariable.h | 143 ++
.../Include/Guid/SocketVariable.h | 36 +
.../Include/Guid/StatusCodeDataTypeExDebug.h | 50 +
.../WhitleySiliconPkg/Include/IioConfig.h | 398 ++++
.../Include/IioPlatformData.h | 204 ++
.../Intel/WhitleySiliconPkg/Include/IioRegs.h | 179 ++
.../Include/IioSetupDefinitions.h | 60 +
.../Include/IioUniversalData.h | 166 ++
.../WhitleySiliconPkg/Include/ImonVrSvid.h | 26 +
.../Include/KtiSetupDefinitions.h | 22 +
.../Include/Library/CompressedVariableLib.h | 35 +
.../Library/EmulationConfigurationLib.h | 34 +
.../Include/Library/MemTypeLib.h | 32 +
.../Include/Library/MemVrSvidMapLib.h | 66 +
.../Include/Library/PchInfoLib.h | 22 +
.../Include/Library/PlatformHooksLib.h | 17 +
.../Include/Library/SemaphoreLib.h | 326 +++
.../Intel/WhitleySiliconPkg/Include/MaxCore.h | 20 +
.../WhitleySiliconPkg/Include/MaxSocket.h | 20 +
.../WhitleySiliconPkg/Include/MaxThread.h | 20 +
.../WhitleySiliconPkg/Include/MemCommon.h | 41 +
.../Include/Memory/Ddr4SpdRegisters.h | 38 +
.../Include/Memory/ProcSmbChipCommon.h | 28 +
.../WhitleySiliconPkg/Include/Platform.h | 266 +++
.../Include/PlatformInfoTypes.h | 106 +
.../Include/Ppi/DynamicSiLibraryPpi.h | 474 ++++
.../Include/Ppi/MemoryPolicyPpi.h | 2112 +++++++++++++++++
.../Include/Ppi/RasImcS3Data.h | 53 +
.../Include/Ppi/UpiPolicyPpi.h | 39 +
.../Protocol/DynamicSiLibraryProtocol.h | 252 ++
.../Protocol/DynamicSiLibrarySmmProtocol.h | 60 +
.../Include/Protocol/GlobalNvsArea.h | 212 ++
.../Include/Protocol/IioUds.h | 47 +
.../Include/Protocol/PciCallback.h | 85 +
.../WhitleySiliconPkg/Include/RcVersion.h | 23 +
.../Include/ScratchpadList.h | 49 +
.../Include/SiliconUpdUpdate.h | 53 +
.../WhitleySiliconPkg/Include/SystemInfoVar.h | 93 +
.../Include/UncoreCommonIncludes.h | 111 +
.../WhitleySiliconPkg/Include/Upi/KtiDisc.h | 36 +
.../WhitleySiliconPkg/Include/Upi/KtiHost.h | 304 +++
.../WhitleySiliconPkg/Include/Upi/KtiSi.h | 32 +
.../Include/UsraAccessType.h | 291 +++
.../Core/Include/DataTypes.h | 36 +
.../BaseMemoryCoreLib/Core/Include/MemHost.h | 1051 ++++++++
.../Core/Include/MemHostChipCommon.h | 190 ++
.../BaseMemoryCoreLib/Core/Include/MemRegs.h | 25 +
.../Core/Include/MrcCommonTypes.h | 28 +
.../Core/Include/NGNDimmPlatformCfgData.h | 22 +
.../BaseMemoryCoreLib/Core/Include/SysHost.h | 193 ++
.../Core/Include/SysHostChipCommon.h | 101 +
.../BaseMemoryCoreLib/Platform/MemDefaults.h | 28 +
.../BaseMemoryCoreLib/Platform/PlatformHost.h | 35 +
.../FspWrapperPlatformLib.c | 243 ++
.../FspWrapperPlatformLib.inf | 71 +
.../Library/SetupLib/PeiSetupLib.c | 259 ++
.../Library/SetupLib/PeiSetupLib.inf | 55 +
.../Library/SetupLib/SetupLib.c | 253 ++
.../Library/SetupLib/SetupLib.inf | 59 +
.../Library/SetupLib/SetupLibNull.c | 159 ++
.../Library/SetupLib/SetupLibNull.inf | 46 +
.../SiliconPolicyInitLibShim.c | 104 +
.../SiliconPolicyInitLibShim.inf | 38 +
.../SiliconWorkaroundLibNull.c | 38 +
.../SiliconWorkaroundLibNull.inf | 50 +
87 files changed, 12904 insertions(+)
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/TraceHubConfig.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/Usb2PhyConfig.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/UsbConfig.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Cpu/CpuIds.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/CpuAndRevisionDefines.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/EmulationConfiguration.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Fpga.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/GpioConfig.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/EmulationDfxVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/FpgaSocketVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemBootHealthGuid.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/PartialMirrorGuid.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/PlatformInfo.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SiliconPolicyInitLibInterface.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketCommonRcVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMpLinkVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/StatusCodeDataTypeExDebug.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioPlatformData.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioUniversalData.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ImonVrSvid.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/KtiSetupDefinitions.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/CompressedVariableLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/EmulationConfigurationLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/MemTypeLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/MemVrSvidMapLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/PchInfoLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/PlatformHooksLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/SemaphoreLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/MaxCore.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/MaxSocket.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/MaxThread.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Memory/Ddr4SpdRegisters.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Memory/ProcSmbChipCommon.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Platform.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Ppi/DynamicSiLibraryPpi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPpi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibrarySmmProtocol.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/GlobalNvsArea.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/IioUds.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/PciCallback.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/RcVersion.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ScratchpadList.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/SiliconUpdUpdate.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/SystemInfoVar.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiDisc.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiSi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/UsraAccessType.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/NGNDimmPlatformCfgData.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/MemDefaults.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.inf
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h b/Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h
new file mode 100644
index 0000000000..0e9fbde11f
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h
@@ -0,0 +1,19 @@
+/** @file
+ Back Compatiable temp header file
+
+ @copyright
+ Copyright 2007 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __BACK_COMPATIABLE_H__
+#define __BACK_COMPATIABLE_H__
+
+#define R_ACPI_LV2 0x14
+
+#define R_IOPORT_CMOS_UPPER_INDEX 0x72
+#define R_IOPORT_CMOS_UPPER_DATA 0x73
+
+#endif
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/TraceHubConfig.h b/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/TraceHubConfig.h
new file mode 100644
index 0000000000..11b9367e9a
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/TraceHubConfig.h
@@ -0,0 +1,65 @@
+/** @file
+ PCH Trace Hub policy
+
+ at copyright
+ Copyright 2015 - 2021 Intel Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _TRACEHUB_CONFIG_H_
+#define _TRACEHUB_CONFIG_H_
+
+#define CPU_TRACEHUB_PREMEM_CONFIG_REVISION 1
+#define PCH_TRACEHUB_PREMEM_CONFIG_REVISION 1
+
+extern EFI_GUID gPchTraceHubPreMemConfigGuid;
+
+///
+/// The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation
+///
+typedef enum {
+ TraceHubModeDisabled = 0,
+ TraceHubModeTargetDebugger = 1,
+ TraceHubModeHostDebugger = 2,
+ TraceHubModeMax
+} TRACE_HUB_ENABLE_MODE;
+
+///
+/// The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size
+///
+typedef enum {
+ TraceBufferNone = 0,
+ TraceBuffer1M = SIZE_1MB,
+ TraceBuffer8M = SIZE_8MB,
+ TraceBuffer64M = SIZE_64MB,
+ TraceBuffer128M = SIZE_128MB,
+ TraceBuffer256M = SIZE_256MB,
+ TraceBuffer512M = SIZE_512MB
+} TRACE_BUFFER_SIZE;
+
+#pragma pack (push,1)
+
+///
+/// TRACE_HUB_CONFIG block describes TraceHub settings.
+///
+typedef struct {
+ /**
+ Trace hub mode. Default is disabled.
+ Target Debugger mode refers to debug tool running on target device itself and it works as a conventional PCI device;
+ Host Debugger mode refers to SUT debugged via probe on host, configured as ACPI device with PCI configuration sapce hidden.
+ <b>0 = Disable</b>; 1 = Target Debugger mode; 2 = Host Debugger mode
+ Refer to TRACE_HUB_ENABLE_MODE
+ **/
+ UINT32 EnableMode;
+ /**
+ Trace hub memory buffer region size policy.
+ The avaliable memory size options are: <b>0:0MB (none)</b>, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB.
+ Refer to TRACE_BUFFER_SIZE.
+ **/
+ UINT32 MemReg0Size;
+ UINT32 MemReg1Size;
+} TRACE_HUB_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _TRACEHUB_CONFIG_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/Usb2PhyConfig.h b/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/Usb2PhyConfig.h
new file mode 100644
index 0000000000..1db4d54a39
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/Usb2PhyConfig.h
@@ -0,0 +1,63 @@
+/** @file
+ USB2 PHY configuration policy
+
+ at copyright
+ Copyright 2018 - 2021 Intel Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _USB2_PHY_CONFIG_H_
+#define _USB2_PHY_CONFIG_H_
+
+#define USB2_PHY_CONFIG_REVISION 1
+extern EFI_GUID gUsb2PhyConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure configures per USB2 AFE settings.
+ It allows to setup the port electrical parameters.
+**/
+typedef struct {
+/** Per Port HS Preemphasis Bias (PERPORTPETXISET)
+ 000b - 0mV
+ 001b - 11.25mV
+ 010b - 16.9mV
+ 011b - 28.15mV
+ 100b - 28.15mV
+ 101b - 39.35mV
+ 110b - 45mV
+ 111b - 56.3mV
+**/
+ UINT8 Petxiset;
+/** Per Port HS Transmitter Bias (PERPORTTXISET)
+ 000b - 0mV
+ 001b - 11.25mV
+ 010b - 16.9mV
+ 011b - 28.15mV
+ 100b - 28.15mV
+ 101b - 39.35mV
+ 110b - 45mV
+ 111b - 56.3mV
+**/
+ UINT8 Txiset;
+/**
+ Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN)
+ 00b - Emphasis OFF
+ 01b - De-emphasis ON
+ 10b - Pre-emphasis ON
+ 11b - Pre-emphasis & De-emphasis ON
+**/
+ UINT8 Predeemp;
+/**
+ Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF)
+ 1b - half-bit pre-emphasis
+ 0b - full-bit pre-emphasis
+**/
+ UINT8 Pehalfbit;
+} USB2_PHY_PARAMETERS;
+
+#pragma pack (pop)
+
+#endif // _USB2_PHY_CONFIG_H_
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/UsbConfig.h b/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/UsbConfig.h
new file mode 100644
index 0000000000..8bb60137df
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/UsbConfig.h
@@ -0,0 +1,85 @@
+/** @file
+ Common USB policy shared between PCH and CPU
+ Contains general features settings for xHCI and xDCI
+
+ at copyright
+ Copyright 2017 - 2021 Intel Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _USB_CONFIG_H_
+#define _USB_CONFIG_H_
+
+#define USB_CONFIG_REVISION 1
+extern EFI_GUID gUsbConfigGuid;
+
+#define MAX_USB2_PORTS 16
+#define MAX_USB3_PORTS 10
+
+#pragma pack (push,1)
+
+#define PCH_USB_OC_PINS_MAX 8 ///< Maximal possible number of USB Over Current pins
+
+///
+/// Overcurrent pins, the values match the setting of EDS, please refer to EDS for more details
+///
+typedef enum {
+ UsbOverCurrentPin0 = 0,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin2,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPin5,
+ UsbOverCurrentPin6,
+ UsbOverCurrentPin7,
+ UsbOverCurrentPinMax,
+ UsbOverCurrentPinSkip = 0xFF
+} USB_OVERCURRENT_PIN;
+
+/**
+ This structure configures per USB2.0 port settings like enabling and overcurrent protection
+**/
+typedef struct {
+ /**
+ These members describe the specific over current pin number of USB 2.0 Port N.
+ It is SW's responsibility to ensure that a given port's bit map is set only for
+ one OC pin Description. USB2 and USB3 on the same combo Port must use the same
+ OC pin (see: USB_OVERCURRENT_PIN).
+ **/
+ UINT32 OverCurrentPin : 8;
+ UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
+ UINT32 RsvdBits0 : 23; ///< Reserved bits
+} USB2_PORT_CONFIG;
+
+/**
+ This structure configures per USB3.x port settings like enabling and overcurrent protection
+**/
+typedef struct {
+ /**
+ These members describe the specific over current pin number of USB 2.0 Port N.
+ It is SW's responsibility to ensure that a given port's bit map is set only for
+ one OC pin Description. USB2 and USB3 on the same combo Port must use the same
+ OC pin (see: USB_OVERCURRENT_PIN).
+ **/
+ UINT32 OverCurrentPin : 8;
+ UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
+ UINT32 RsvdBits0 : 23; ///< Reserved bits
+} USB3_PORT_CONFIG;
+
+
+/**
+ The XDCI_CONFIG block describes the configurations
+ of the xDCI Usb Device controller.
+**/
+typedef struct {
+ /**
+ This member describes whether or not the xDCI controller should be enabled.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 Enable : 1;
+ UINT32 RsvdBits0 : 31; ///< Reserved bits
+} XDCI_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _USB_CONFIG_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Cpu/CpuIds.h b/Silicon/Intel/WhitleySiliconPkg/Include/Cpu/CpuIds.h
new file mode 100644
index 0000000000..0cb9cb6df5
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Cpu/CpuIds.h
@@ -0,0 +1,18 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPUID_REGS_H_
+#define _CPUID_REGS_H_
+
+#define CPU_FAMILY_SKX 0x5065 // Skylake/CascadeLake CPU
+#define CPU_FAMILY_ICX 0x606A // IceLake CPU
+#define EFI_CACHE_UNCACHEABLE 0
+#define EFI_CACHE_WRITEBACK 6
+
+#define APICID_MASK_BIT14_8 0x7F //current Si support programmable APICID up to 15bits
+#endif //_CPUID_REGS_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/CpuAndRevisionDefines.h b/Silicon/Intel/WhitleySiliconPkg/Include/CpuAndRevisionDefines.h
new file mode 100644
index 0000000000..f94a5b3d68
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/CpuAndRevisionDefines.h
@@ -0,0 +1,283 @@
+/** @file
+ Defines for CPU and Revision library.
+
+ @copyright
+ Copyright 2019 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_AND_REVISION_DEFINES_H_// #ifndef _CPU_AND_REVISION_LIB_H_
+#define _CPU_AND_REVISION_DEFINES_H_
+
+// CPU types
+#define CPU_SKX 0 // Skylake: Mainstream Xeon – 14nm
+#define CPU_CLX 1 // CascadeLake: Mainstream Xeon – 14nm
+#define CPU_CPX 2 // CooperLake: Mainstream Xeon – 14nm
+#define CPU_ICXSP 4 // Icelake-SP: Mainstream Xeon – 10nm Wave 1
+#define CPU_MAX 0xFF // MAX CPU limit
+
+
+// CPU Physical chop types
+#define CPU_CHOP_TYPE_LCC 0
+#define CPU_CHOP_TYPE_MCC 1
+#define CPU_CHOP_TYPE_HCC 2
+#define CPU_CHOP_TYPE_XCC 3
+
+#define MINOR_REV_MASK 0x000F
+#define MINOR_REV_BIT_WIDTH 4
+#define MAJOR_REV_MASK 0xFFF0
+
+#define MAJOR_REV_A (0x01 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_B (0x02 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_C (0x03 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_D (0x04 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_E (0x05 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_F (0x06 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_G (0x07 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_H (0x08 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_I (0x09 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_J (0x0A << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_K (0x0B << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_L (0x0C << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_M (0x0D << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_N (0x0E << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_O (0x0F << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_P (0x10 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_Q (0x11 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_R (0x12 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_S (0x13 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_T (0x14 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_U (0x15 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_V (0x16 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_W (0x17 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_X (0x18 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_Y (0x19 << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_Z (0x1A << (MINOR_REV_BIT_WIDTH))
+#define MAJOR_REV_ALL (0x1F << (MINOR_REV_BIT_WIDTH))
+
+#define MINOR_REV_0 0
+#define MINOR_REV_1 1
+#define MINOR_REV_2 2
+#define MINOR_REV_3 3
+#define MINOR_REV_4 4
+#define MINOR_REV_5 5
+#define MINOR_REV_6 6
+#define MINOR_REV_7 7
+#define MINOR_REV_8 8
+#define MINOR_REV_ALL 0xF
+
+//
+// Revision defines - Generic for all Cpu Types
+// If new revisions are needed, follow same pattern
+//
+#define REV_A0 (MAJOR_REV_A | MINOR_REV_0)
+#define REV_A1 (MAJOR_REV_A | MINOR_REV_1)
+#define REV_A2 (MAJOR_REV_A | MINOR_REV_2)
+#define REV_A3 (MAJOR_REV_A | MINOR_REV_3)
+#define REV_A4 (MAJOR_REV_A | MINOR_REV_4)
+#define REV_A5 (MAJOR_REV_A | MINOR_REV_5)
+#define REV_AX (MAJOR_REV_A | MINOR_REV_ALL)
+
+#define REV_B0 (MAJOR_REV_B | MINOR_REV_0)
+#define REV_B1 (MAJOR_REV_B | MINOR_REV_1)
+#define REV_B2 (MAJOR_REV_B | MINOR_REV_2)
+#define REV_B3 (MAJOR_REV_B | MINOR_REV_3)
+#define REV_B4 (MAJOR_REV_B | MINOR_REV_4)
+#define REV_B5 (MAJOR_REV_B | MINOR_REV_5)
+#define REV_BX (MAJOR_REV_B | MINOR_REV_ALL)
+
+#define REV_C0 (MAJOR_REV_C | MINOR_REV_0)
+#define REV_C1 (MAJOR_REV_C | MINOR_REV_1)
+#define REV_C2 (MAJOR_REV_C | MINOR_REV_2)
+#define REV_C3 (MAJOR_REV_C | MINOR_REV_3)
+#define REV_C4 (MAJOR_REV_C | MINOR_REV_4)
+#define REV_C5 (MAJOR_REV_C | MINOR_REV_5)
+#define REV_CX (MAJOR_REV_C | MINOR_REV_ALL)
+
+#define REV_D0 (MAJOR_REV_D | MINOR_REV_0)
+#define REV_D1 (MAJOR_REV_D | MINOR_REV_1)
+#define REV_D2 (MAJOR_REV_D | MINOR_REV_2)
+#define REV_D3 (MAJOR_REV_D | MINOR_REV_3)
+#define REV_D4 (MAJOR_REV_D | MINOR_REV_4)
+#define REV_D5 (MAJOR_REV_D | MINOR_REV_5)
+#define REV_DX (MAJOR_REV_D | MINOR_REV_ALL)
+
+#define REV_E0 (MAJOR_REV_E | MINOR_REV_0)
+#define REV_E1 (MAJOR_REV_E | MINOR_REV_1)
+#define REV_E2 (MAJOR_REV_E | MINOR_REV_2)
+#define REV_E3 (MAJOR_REV_E | MINOR_REV_3)
+#define REV_E4 (MAJOR_REV_E | MINOR_REV_4)
+#define REV_E5 (MAJOR_REV_E | MINOR_REV_5)
+#define REV_EX (MAJOR_REV_E | MINOR_REV_ALL)
+
+#define REV_F0 (MAJOR_REV_F | MINOR_REV_0)
+#define REV_F1 (MAJOR_REV_F | MINOR_REV_1)
+#define REV_F2 (MAJOR_REV_F | MINOR_REV_2)
+#define REV_F3 (MAJOR_REV_F | MINOR_REV_3)
+#define REV_F4 (MAJOR_REV_F | MINOR_REV_4)
+#define REV_F5 (MAJOR_REV_F | MINOR_REV_5)
+#define REV_FX (MAJOR_REV_F | MINOR_REV_ALL)
+
+#define REV_G0 (MAJOR_REV_G | MINOR_REV_0)
+#define REV_G1 (MAJOR_REV_G | MINOR_REV_1)
+#define REV_G2 (MAJOR_REV_G | MINOR_REV_2)
+#define REV_G3 (MAJOR_REV_G | MINOR_REV_3)
+#define REV_G4 (MAJOR_REV_G | MINOR_REV_4)
+#define REV_G5 (MAJOR_REV_G | MINOR_REV_5)
+#define REV_GX (MAJOR_REV_G | MINOR_REV_ALL)
+
+#define REV_H0 (MAJOR_REV_H | MINOR_REV_0)
+#define REV_H1 (MAJOR_REV_H | MINOR_REV_1)
+#define REV_H2 (MAJOR_REV_H | MINOR_REV_2)
+#define REV_H3 (MAJOR_REV_H | MINOR_REV_3)
+#define REV_H4 (MAJOR_REV_H | MINOR_REV_4)
+#define REV_H5 (MAJOR_REV_H | MINOR_REV_5)
+#define REV_HX (MAJOR_REV_H | MINOR_REV_ALL)
+
+#define REV_I0 (MAJOR_REV_I | MINOR_REV_0)
+#define REV_I1 (MAJOR_REV_I | MINOR_REV_1)
+#define REV_I2 (MAJOR_REV_I | MINOR_REV_2)
+#define REV_I3 (MAJOR_REV_I | MINOR_REV_3)
+#define REV_I4 (MAJOR_REV_I | MINOR_REV_4)
+#define REV_I5 (MAJOR_REV_I | MINOR_REV_5)
+#define REV_IX (MAJOR_REV_I | MINOR_REV_ALL)
+
+#define REV_J0 (MAJOR_REV_J | MINOR_REV_0)
+#define REV_J1 (MAJOR_REV_J | MINOR_REV_1)
+#define REV_J2 (MAJOR_REV_J | MINOR_REV_2)
+#define REV_J3 (MAJOR_REV_J | MINOR_REV_3)
+#define REV_J4 (MAJOR_REV_J | MINOR_REV_4)
+#define REV_J5 (MAJOR_REV_J | MINOR_REV_5)
+#define REV_JX (MAJOR_REV_J | MINOR_REV_ALL)
+
+#define REV_K0 (MAJOR_REV_K | MINOR_REV_0)
+#define REV_K1 (MAJOR_REV_K | MINOR_REV_1)
+#define REV_K2 (MAJOR_REV_K | MINOR_REV_2)
+#define REV_K3 (MAJOR_REV_K | MINOR_REV_3)
+#define REV_K4 (MAJOR_REV_K | MINOR_REV_4)
+#define REV_K5 (MAJOR_REV_K | MINOR_REV_5)
+#define REV_KX (MAJOR_REV_K | MINOR_REV_ALL)
+
+#define REV_L0 (MAJOR_REV_L | MINOR_REV_0)
+#define REV_L1 (MAJOR_REV_L | MINOR_REV_1)
+#define REV_L2 (MAJOR_REV_L | MINOR_REV_2)
+#define REV_L3 (MAJOR_REV_L | MINOR_REV_3)
+#define REV_L4 (MAJOR_REV_L | MINOR_REV_4)
+#define REV_L5 (MAJOR_REV_L | MINOR_REV_5)
+#define REV_LX (MAJOR_REV_L | MINOR_REV_ALL)
+
+#define REV_M0 (MAJOR_REV_M | MINOR_REV_0)
+#define REV_M1 (MAJOR_REV_M | MINOR_REV_1)
+#define REV_M2 (MAJOR_REV_M | MINOR_REV_2)
+#define REV_M3 (MAJOR_REV_M | MINOR_REV_3)
+#define REV_M4 (MAJOR_REV_M | MINOR_REV_4)
+#define REV_M5 (MAJOR_REV_M | MINOR_REV_5)
+#define REV_MX (MAJOR_REV_M | MINOR_REV_ALL)
+
+#define REV_N0 (MAJOR_REV_N | MINOR_REV_0)
+#define REV_N1 (MAJOR_REV_N | MINOR_REV_1)
+#define REV_N2 (MAJOR_REV_N | MINOR_REV_2)
+#define REV_N3 (MAJOR_REV_N | MINOR_REV_3)
+#define REV_N4 (MAJOR_REV_N | MINOR_REV_4)
+#define REV_N5 (MAJOR_REV_N | MINOR_REV_5)
+#define REV_NX (MAJOR_REV_N | MINOR_REV_ALL)
+
+#define REV_O0 (MAJOR_REV_O | MINOR_REV_0)
+#define REV_O1 (MAJOR_REV_O | MINOR_REV_1)
+#define REV_O2 (MAJOR_REV_O | MINOR_REV_2)
+#define REV_O3 (MAJOR_REV_O | MINOR_REV_3)
+#define REV_O4 (MAJOR_REV_O | MINOR_REV_4)
+#define REV_O5 (MAJOR_REV_O | MINOR_REV_5)
+#define REV_OX (MAJOR_REV_O | MINOR_REV_ALL)
+
+#define REV_P0 (MAJOR_REV_P | MINOR_REV_0)
+#define REV_P1 (MAJOR_REV_P | MINOR_REV_1)
+#define REV_P2 (MAJOR_REV_P | MINOR_REV_2)
+#define REV_P3 (MAJOR_REV_P | MINOR_REV_3)
+#define REV_P4 (MAJOR_REV_P | MINOR_REV_4)
+#define REV_P5 (MAJOR_REV_P | MINOR_REV_5)
+#define REV_PX (MAJOR_REV_P | MINOR_REV_ALL)
+
+#define REV_Q0 (MAJOR_REV_Q | MINOR_REV_0)
+#define REV_Q1 (MAJOR_REV_Q | MINOR_REV_1)
+#define REV_Q2 (MAJOR_REV_Q | MINOR_REV_2)
+#define REV_Q3 (MAJOR_REV_Q | MINOR_REV_3)
+#define REV_Q4 (MAJOR_REV_Q | MINOR_REV_4)
+#define REV_Q5 (MAJOR_REV_Q | MINOR_REV_5)
+#define REV_QX (MAJOR_REV_Q | MINOR_REV_ALL)
+
+#define REV_R0 (MAJOR_REV_R | MINOR_REV_0)
+#define REV_R1 (MAJOR_REV_R | MINOR_REV_1)
+#define REV_R2 (MAJOR_REV_R | MINOR_REV_2)
+#define REV_R3 (MAJOR_REV_R | MINOR_REV_3)
+#define REV_R4 (MAJOR_REV_R | MINOR_REV_4)
+#define REV_R5 (MAJOR_REV_R | MINOR_REV_5)
+#define REV_RX (MAJOR_REV_R | MINOR_REV_ALL)
+
+#define REV_S0 (MAJOR_REV_S | MINOR_REV_0)
+#define REV_S1 (MAJOR_REV_S | MINOR_REV_1)
+#define REV_S2 (MAJOR_REV_S | MINOR_REV_2)
+#define REV_S3 (MAJOR_REV_S | MINOR_REV_3)
+#define REV_S4 (MAJOR_REV_S | MINOR_REV_4)
+#define REV_S5 (MAJOR_REV_S | MINOR_REV_5)
+#define REV_SX (MAJOR_REV_S | MINOR_REV_ALL)
+
+#define REV_T0 (MAJOR_REV_T | MINOR_REV_0)
+#define REV_T1 (MAJOR_REV_T | MINOR_REV_1)
+#define REV_T2 (MAJOR_REV_T | MINOR_REV_2)
+#define REV_T3 (MAJOR_REV_T | MINOR_REV_3)
+#define REV_T4 (MAJOR_REV_T | MINOR_REV_4)
+#define REV_T5 (MAJOR_REV_T | MINOR_REV_5)
+#define REV_TX (MAJOR_REV_T | MINOR_REV_ALL)
+
+#define REV_U0 (MAJOR_REV_U | MINOR_REV_0)
+#define REV_U1 (MAJOR_REV_U | MINOR_REV_1)
+#define REV_U2 (MAJOR_REV_U | MINOR_REV_2)
+#define REV_U3 (MAJOR_REV_U | MINOR_REV_3)
+#define REV_U4 (MAJOR_REV_U | MINOR_REV_4)
+#define REV_U5 (MAJOR_REV_U | MINOR_REV_5)
+#define REV_UX (MAJOR_REV_U | MINOR_REV_ALL)
+
+#define REV_V0 (MAJOR_REV_V | MINOR_REV_0)
+#define REV_V1 (MAJOR_REV_V | MINOR_REV_1)
+#define REV_V2 (MAJOR_REV_V | MINOR_REV_2)
+#define REV_V3 (MAJOR_REV_V | MINOR_REV_3)
+#define REV_V4 (MAJOR_REV_V | MINOR_REV_4)
+#define REV_V5 (MAJOR_REV_V | MINOR_REV_5)
+#define REV_VX (MAJOR_REV_V | MINOR_REV_ALL)
+
+#define REV_W0 (MAJOR_REV_W | MINOR_REV_0)
+#define REV_W1 (MAJOR_REV_W | MINOR_REV_1)
+#define REV_W2 (MAJOR_REV_W | MINOR_REV_2)
+#define REV_W3 (MAJOR_REV_W | MINOR_REV_3)
+#define REV_W4 (MAJOR_REV_W | MINOR_REV_4)
+#define REV_W5 (MAJOR_REV_W | MINOR_REV_5)
+#define REV_WX (MAJOR_REV_W | MINOR_REV_ALL)
+
+#define REV_X0 (MAJOR_REV_X | MINOR_REV_0)
+#define REV_X1 (MAJOR_REV_X | MINOR_REV_1)
+#define REV_X2 (MAJOR_REV_X | MINOR_REV_2)
+#define REV_X3 (MAJOR_REV_X | MINOR_REV_3)
+#define REV_X4 (MAJOR_REV_X | MINOR_REV_4)
+#define REV_X5 (MAJOR_REV_X | MINOR_REV_5)
+#define REV_XX (MAJOR_REV_X | MINOR_REV_ALL)
+
+#define REV_Y0 (MAJOR_REV_Y | MINOR_REV_0)
+#define REV_Y1 (MAJOR_REV_Y | MINOR_REV_1)
+#define REV_Y2 (MAJOR_REV_Y | MINOR_REV_2)
+#define REV_Y3 (MAJOR_REV_Y | MINOR_REV_3)
+#define REV_Y4 (MAJOR_REV_Y | MINOR_REV_4)
+#define REV_Y5 (MAJOR_REV_Y | MINOR_REV_5)
+#define REV_YX (MAJOR_REV_Y | MINOR_REV_ALL)
+
+#define REV_Z0 (MAJOR_REV_Z | MINOR_REV_0)
+#define REV_Z1 (MAJOR_REV_Z | MINOR_REV_1)
+#define REV_Z2 (MAJOR_REV_Z | MINOR_REV_2)
+#define REV_Z3 (MAJOR_REV_Z | MINOR_REV_3)
+#define REV_Z4 (MAJOR_REV_Z | MINOR_REV_4)
+#define REV_Z5 (MAJOR_REV_Z | MINOR_REV_5)
+#define REV_ZX (MAJOR_REV_Z | MINOR_REV_ALL)
+
+#define REV_ALL (MAJOR_REV_ALL | MINOR_REV_ALL)
+#endif
\ No newline at end of file
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/EmulationConfiguration.h b/Silicon/Intel/WhitleySiliconPkg/Include/EmulationConfiguration.h
new file mode 100644
index 0000000000..c15ec034ec
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/EmulationConfiguration.h
@@ -0,0 +1,22 @@
+/** @file
+
+ @copyright
+ Copyright 2017 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _EMULATION_CONFIGURATION_H_
+#define _EMULATION_CONFIGURATION_H_
+
+//
+// Emulation Setting Values
+//
+#define EMULATION_AUTO 0
+#define EMULATION_DISABLE 1
+#define EMULATION_ENABLE 2
+
+#endif // _EMULATION_CONFIGURATION_H_
+
+
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Fpga.h b/Silicon/Intel/WhitleySiliconPkg/Include/Fpga.h
new file mode 100644
index 0000000000..758b6f845d
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Fpga.h
@@ -0,0 +1,17 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FPGA_DATA_H_
+#define _FPGA_DATA_H_
+
+// Max Sockets for FPGA's, for all arrays, index loops,...
+// Note: all bit mask arrays are defined as "UINT8", so if this increases
+// Those will have to be refactored to hold the new data.
+#define FPGA_MAX_SOCKET MAX_SOCKET
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/GpioConfig.h b/Silicon/Intel/WhitleySiliconPkg/Include/GpioConfig.h
new file mode 100644
index 0000000000..700e629d3c
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/GpioConfig.h
@@ -0,0 +1,288 @@
+/** @file
+ Header file for GpioConfig structure used by GPIO library.
+
+ @copyright
+ Copyright 2014 - 2021 Intel Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GPIO_CONFIG_H_
+#define _GPIO_CONFIG_H_
+
+#pragma pack(push, 1)
+
+///
+/// For any GpioPad usage in code use GPIO_PAD type
+///
+typedef UINT32 GPIO_PAD;
+
+
+///
+/// For any GpioGroup usage in code use GPIO_GROUP type
+///
+typedef UINT32 GPIO_GROUP;
+
+/**
+ GPIO configuration structure used for pin programming.
+ Structure contains fields that can be used to configure pad.
+**/
+typedef struct {
+ /**
+ Pad Mode
+ Pad can be set as GPIO or one of its native functions.
+ When in native mode setting Direction (except Inversion), OutputState,
+ InterruptConfig and Host Software Pad Ownership are unnecessary.
+ Refer to definition of GPIO_PAD_MODE.
+ Refer to EDS for each native mode according to the pad.
+ **/
+ UINT32 PadMode : 4;
+ /**
+ Host Software Pad Ownership
+ Set pad to ACPI mode or GPIO Driver Mode.
+ Refer to definition of GPIO_HOSTSW_OWN.
+ **/
+ UINT32 HostSoftPadOwn : 2;
+ /**
+ GPIO Direction
+ Can choose between In, In with inversion Out, both In and Out, both In with inversion and out or disabling both.
+ Refer to definition of GPIO_DIRECTION for supported settings.
+ **/
+ UINT32 Direction : 5;
+ /**
+ Output State
+ Set Pad output value.
+ Refer to definition of GPIO_OUTPUT_STATE for supported settings.
+ This setting takes place when output is enabled.
+ **/
+ UINT32 OutputState : 2;
+ /**
+ GPIO Interrupt Configuration
+ Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting is applicable only if GPIO is in input mode.
+ If GPIO is set to cause an SCI then also Gpe is enabled for this pad.
+ Refer to definition of GPIO_INT_CONFIG for supported settings.
+ **/
+ UINT32 InterruptConfig : 8;
+ /**
+ GPIO Power Configuration.
+ This setting controls Pad Reset Configuration.
+ Refer to definition of GPIO_RESET_CONFIG for supported settings.
+ **/
+ UINT32 PowerConfig : 4;
+
+ /**
+ GPIO Electrical Configuration
+ This setting controls pads termination and voltage tolerance.
+ Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
+ **/
+ UINT32 ElectricalConfig : 7;
+
+ /**
+ GPIO Lock Configuration
+ This setting controls pads lock.
+ Refer to definition of GPIO_LOCK_CONFIG for supported settings.
+ **/
+ UINT32 LockConfig : 3;
+ /**
+ Additional GPIO configuration
+ Refer to definition of GPIO_OTHER_CONFIG for supported settings.
+ **/
+ UINT32 OtherSettings : 2;
+ UINT32 RsvdBits : 27; ///< Reserved bits for future extension
+ UINT32 RsvdBits1; ///< Reserved bits for future extension
+} GPIO_CONFIG;
+
+
+typedef enum {
+ GpioHardwareDefault = 0x0
+} GPIO_HARDWARE_DEFAULT;
+
+///
+/// GPIO Pad Mode
+///
+typedef enum {
+ GpioPadModeGpio = 0x1,
+ GpioPadModeNative1 = 0x3,
+ GpioPadModeNative2 = 0x5,
+ GpioPadModeNative3 = 0x7,
+ GpioPadModeNative4 = 0x9
+} GPIO_PAD_MODE;
+
+///
+/// Host Software Pad Ownership modes
+///
+typedef enum {
+ GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
+ GpioHostOwnAcpi = 0x1, ///< Set HOST ownership to ACPI
+ GpioHostOwnGpio = 0x3 ///< Set HOST ownership to GPIO
+} GPIO_HOSTSW_OWN;
+
+///
+/// GPIO Direction
+///
+typedef enum {
+ GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
+ GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
+ GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
+ GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
+ GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
+ GpioDirOut = 0x5, ///< Set pad for output only
+ GpioDirNone = 0x7 ///< Disable both output and input
+} GPIO_DIRECTION;
+
+///
+/// GPIO Output State
+///
+typedef enum {
+ GpioOutDefault = 0x0, ///< Leave output value unmodified
+ GpioOutLow = 0x1, ///< Set output to low
+ GpioOutHigh = 0x3 ///< Set output to high
+} GPIO_OUTPUT_STATE;
+
+///
+/// GPIO interrupt configuration
+/// This setting is applicable only if GPIO is in input mode.
+/// GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
+/// and how it is triggered (edge or level).
+/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdgecan
+/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel
+/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad.
+/// Not all GPIO are capable of generating an SMI or NMI interrupt
+///
+
+typedef enum {
+ GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
+ GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
+ GpioIntNmi = 0x3, ///< Enable NMI interrupt only
+ GpioIntSmi = 0x5, ///< Enable SMI interrupt only
+ GpioIntSci = 0x9, ///< Enable SCI interrupt only
+ GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
+ GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
+ GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
+ GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
+ GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
+} GPIO_INT_CONFIG;
+
+#define GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
+#define GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
+
+/**
+ GPIO Power Configuration
+ GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
+ be used to reset certain GPIO settings.
+ Refer to EDS for settings that are controllable by PadRstCfg.
+**/
+typedef enum {
+
+
+ GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
+ ///
+ /// LBG configuration
+ ///
+ GpioResetPwrGood = 0x09, ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood")
+ GpioResetDeep = 0x0B, ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")
+ GpioResetNormal = 0x0D, ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )
+ GpioResetResume = 0x0F, ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset")
+
+ ///
+ /// New GPIO reset configuration options
+ ///
+ /**
+ Resume Reset (RSMRST)
+ GPP: PadRstCfg = 00b = "Powergood"
+ GPD: PadRstCfg = 11b = "Resume Reset"
+ Pad setting will reset on:
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ **/
+ GpioResumeReset = 0x01,
+ /**
+ Host Deep Reset
+ PadRstCfg = 01b = "Deep GPIO Reset"
+ Pad settings will reset on:
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ **/
+ GpioHostDeepReset = 0x03,
+ /**
+ Platform Reset (PLTRST)
+ PadRstCfg = 10b = "GPIO Reset"
+ Pad settings will reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ **/
+ GpioPlatformReset = 0x05,
+ /**
+ Deep Sleep Well Reset (DSW_PWROK)
+ GPP: not applicable
+ GPD: PadRstCfg = 00b = "Powergood"
+ Pad settings will reset on:
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ **/
+ GpioDswReset = 0x07
+} GPIO_RESET_CONFIG;
+
+
+///
+/// GPIO Electrical Configuration
+/// Set GPIO termination and Pad Tolerance (applicable only for some pads)
+/// Field from GpioTermDefault to GpioTermNative can be OR'ed with GpioTolerance1v8.
+///
+typedef enum {
+ GpioTermDefault = 0x0, ///< Leave termination setting unmodified
+ GpioTermNone = 0x1, ///< none
+ GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
+ GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
+ GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
+ GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
+ GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
+ GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
+ GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
+ GpioTermNative = 0x1F, ///< Native function controls pads termination
+ GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance
+ GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance
+} GPIO_ELECTRICAL_CONFIG;
+
+#define GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
+#define GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting
+
+///
+/// GPIO LockConfiguration
+/// Set GPIO configuration lock and output state lock
+/// GpioLockPadConfig and GpioLockOutputState can be OR'ed
+///
+typedef enum {
+ GpioLockDefault = 0x0, ///< Leave lock setting unmodified
+ GpioPadConfigLock = 0x3, ///< Lock Pad Configuration
+ GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value
+} GPIO_LOCK_CONFIG;
+
+///
+/// Other GPIO Configuration
+/// GPIO_OTHER_CONFIG is used for less often settings and for future extensions
+/// Supported settings:
+/// - RX raw override to '1' - allows to override input value to '1'
+/// This setting is applicable only if in input mode (both in GPIO and native usage).
+/// The override takes place at the internal pad state directly from buffer and before the RXINV.
+///
+typedef enum {
+ GpioRxRaw1Default = 0x0, ///< Use default input override value
+ GpioRxRaw1Dis = 0x1, ///< Don't override input
+ GpioRxRaw1En = 0x3 ///< Override input to '1'
+} GPIO_OTHER_CONFIG;
+
+#pragma pack(pop)
+
+#endif //_GPIO_CONFIG_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/EmulationDfxVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/EmulationDfxVariable.h
new file mode 100644
index 0000000000..2b7d4cc86d
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/EmulationDfxVariable.h
@@ -0,0 +1,25 @@
+/** @file
+ Data format for Emulation
+
+ @copyright
+ Copyright 2017 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __EMULATION_DFX_VARIABLE_H__
+#define __EMULATION_DFX_VARIABLE_H__
+
+#pragma pack(1)
+typedef struct {
+ UINT8 DfxUbiosGeneration;
+ UINT8 DfxHybridSystemLevelEmulation;
+ UINT8 DfxPmMsrTrace;
+} EMULATION_DFX_CONFIGURATION;
+#pragma pack()
+
+extern EFI_GUID gEmulationDfxVariableGuid;
+#define EMULATION_DFX_CONFIGURATION_NAME L"EmulationDfxConfig"
+
+#endif
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/FpgaSocketVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/FpgaSocketVariable.h
new file mode 100644
index 0000000000..96e9f6d428
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/FpgaSocketVariable.h
@@ -0,0 +1,39 @@
+/** @file
+ Data format for Universal Data Structure
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __FPGA_SOCKET_CONFIGURATION_DATA_H__
+#define __FPGA_SOCKET_CONFIGURATION_DATA_H__
+
+#include <Fpga.h>
+
+extern EFI_GUID gFpgaSocketVariableGuid;
+#define FPGA_SOCKET_CONFIGURATION_NAME L"FpgaSocketConfig"
+
+#pragma pack(1)
+
+typedef struct {
+
+ // User Bitmap to enable the FPGA socket.
+ UINT8 FpgaSetupEnabled;
+
+ // for each socket enabled, use this Bit stream GUID Index
+ // Note: variable is Index+ 1 for unused default to be 0
+ UINT8 FpgaSocketGuid[FPGA_MAX_SOCKET];
+ // FPGA Temperature Threshold 1/2: Max value clamped at 100 C;
+ // i.e. if the SW tries to write value greater than 100 C, HW will automatically default to 100 C.
+ UINT8 FpgaThermalTH1[FPGA_MAX_SOCKET];
+ UINT8 FpgaThermalTH2[FPGA_MAX_SOCKET];
+
+ // FPGA reserved data
+ UINT8 FpgaReserved[14];
+} FPGA_SOCKET_CONFIGURATION;
+#pragma pack()
+
+#endif
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemBootHealthGuid.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemBootHealthGuid.h
new file mode 100644
index 0000000000..5b760117f7
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemBootHealthGuid.h
@@ -0,0 +1,71 @@
+/** @file
+ MemBootHealthGuid.h
+
+ Header for using Structured PCD in MemBootHealth
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _MEM_BOOT_HEALTH_GUID_H_
+#define _MEM_BOOT_HEALTH_GUID_H_
+
+// Enable Mem boot health check feature
+#define MEM_BOOT_HEALTH_ENABLE 1
+// Disable Mem boot health check feature
+#define MEM_BOOT_HEALTH_DISABLE 0
+
+// Mem Boot Health check option
+// Option to choose Mem Boot Health configuration type.
+// 00=>Auto (Use defaults)
+#define MEM_BOOT_HEALTH_CONFIG_AUTO 0
+// 01=>Manual(Override defaults with setup option)
+#define MEM_BOOT_HEALTH_CONFIG_MANUAL 1
+// 02=>Disable (Disable feature)
+#define MEM_BOOT_HEALTH_CONFIG_DISABLE 2
+
+#define ENABLE_REBOOT_ON_CRITICAL_FAILURE 1
+#define DISABLE_REBOOT_ON_CRITICAL_FAILURE 0
+
+#pragma pack(1)
+typedef struct {
+
+ //
+ // Memory Boot Health Check
+ //
+ UINT8 MemBootHealthVisible; // 0 => Hide Memory boot health check option, 1 => Enable the option in setup
+
+ UINT8 MemBootHealthCheck; // 0=>Auto, 1=>Manual and 2=>Disabled Memory Boot Health Check
+
+ UINT8 ResetOnCriticalError; // 0 => Dont reboot on critical error, 1 = Reboot on critical error
+ //
+ // Memory Boot Health check parameters
+ //
+ UINT8 WarningTxDqDelayLeftEdge;
+ UINT8 WarningTxDqDelayRightEdge;
+ UINT8 WarningTxVrefLeftEdge;
+ UINT8 WarningTxVrefRightEdge;
+ UINT8 WarningRxDqsDelayLeftEdge;
+ UINT8 WarningRxDqsDelayRightEdge;
+ UINT8 WarningRxVrefLeftEdge;
+ UINT8 WarningRxVrefRightEdge;
+
+ UINT8 CriticalTxDqDelayLeftEdge;
+ UINT8 CriticalTxDqDelayRightEdge;
+ UINT8 CriticalTxVrefLeftEdge;
+ UINT8 CriticalTxVrefRightEdge;
+ UINT8 CriticalRxDqsDelayLeftEdge;
+ UINT8 CriticalRxDqsDelayRightEdge;
+ UINT8 CriticalRxVrefLeftEdge;
+ UINT8 CriticalRxVrefRightEdge;
+} MEM_BOOT_HEALTH_CONFIG;
+#pragma pack()
+
+#define MEM_BOOT_HEALTH_GUID { 0xACD56900, 0xDEFC, 0x4127, { 0xDE, 0x12, 0x32, 0xA0, 0xD2, 0x69, 0x46, 0x2F } }
+
+#define MEM_BOOT_HEALTH_SETUP_STR L"MemBootHealthConfig"
+
+extern EFI_GUID gMemBootHealthGuid;
+#endif // _MEM_BOOT_HEALTH_GUID_H_
\ No newline at end of file
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
new file mode 100644
index 0000000000..1512b90881
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
@@ -0,0 +1,197 @@
+/** @file
+ GUID used for Memory Map Data entries in the HOB list.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _MEMORY_MAP_DATA_H_
+#define _MEMORY_MAP_DATA_H_
+
+#include "SysHost.h"
+#include "PartialMirrorGuid.h"
+
+#define RESERVED_2 2
+#define RESERVED_4 4
+
+//
+// System Memory Map HOB information
+//
+
+#pragma pack(1)
+struct RankDevice {
+ UINT8 enabled; // 0 = disabled, 1 = enabled
+ UINT8 logicalRank; // Logical Rank number (0 - 7)
+ UINT16 rankSize; // Units of 64 MB
+};
+
+struct PersisentDpaMap
+{
+ UINT32 perRegionDPAOffset;
+ UINT32 SPALimit;
+};
+
+typedef struct DimmDevice {
+ UINT8 Present;
+ BOOLEAN Enabled;
+ UINT8 DcpmmPresent; // 1 - This is a DCPMM
+ UINT8 X4Present;
+ UINT8 NumRanks;
+ UINT8 keyByte;
+ UINT8 actKeyByte2; // Actual module type reported by SPD
+ UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width
+ UINT8 dimmTs; // Thermal sensor data.
+ UINT16 VolCap; // Volatile capacity (AEP DIMM only)
+ UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only)
+ UINT16 DimmSize;
+ UINT32 NVmemSize;
+ UINT16 SPDMMfgId; // Module Mfg Id from SPD
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT32 perRegionDPA; // DPA of PMEM that Nfit needs
+ struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map
+ UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
+ UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number
+ UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17
+ struct firmwareRev FirmwareVersion; // Firmware revision
+ struct RankDevice rankList[MAX_RANK_DIMM];
+ UINT16 InterfaceFormatCode;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT16 FisVersion; // Firmware Interface Specification version
+ UINT8 DimmSku; // Dimm SKU info
+ UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM
+ UINT16 manufacturingDate; // Date the NVDIMM was manufactured
+ INT32 commonTck;
+ UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
+ BOOLEAN NvDimmNPresent; ///< JEDEC NVDIMM-N Type Memory Present
+ UINT16 SPDRegVen; ///< Register Vendor ID in SPD
+ UINT8 CidBitMap; // SubRankPer CS for DIMM device
+} MEMMAP_DIMM_DEVICE_INFO_STRUCT;
+
+struct ChannelDevice {
+ UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
+ UINT8 Features; // Bit mask of features to enable or disable
+ UINT8 MaxDimm; // Number of DIMM
+ UINT8 NumRanks; // Number of ranks on this channel
+ UINT8 chFailed;
+ UINT8 ngnChFailed;
+ UINT8 SpareLogicalRank[MAX_SPARE_RANK]; // Logical rank, selected as Spare
+ UINT8 SparePhysicalRank[MAX_SPARE_RANK]; // Physical rank, selected as spare
+ UINT16 SpareRankSize[MAX_SPARE_RANK]; // spare rank size
+ UINT8 EnabledLogicalRanks; // Bitmap of Logical ranks that are enabled
+ MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM];
+};
+
+struct memcontroller {
+ UINT32 MemSize;
+};
+
+typedef struct socket {
+ UINT8 SocketEnabled;
+ UINT16 IioStackBitmap;
+ BOOLEAN Reserved[RESERVED_4];
+ UINT8 imcEnabled[MAX_IMC];
+ UINT8 SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][MC_MAX_NODE]; // SAD interleave list
+ UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU
+ UINT32 SktSkuLimit; // SKU limit value from PCU
+ UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
+ UINT32 SktPmemMapSpa; // Total persistent memory mapped to SPA
+ UINT32 SktMemSize2LM; // Total memory excluded from Limit
+ SAD_TABLE SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; // SAD table
+ struct memcontroller imc[MAX_IMC];
+ struct ChannelDevice ChannelInfo[MAX_CH];
+} MEMMAP_SOCKET;
+
+typedef struct SystemMemoryMapElement {
+ UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
+ UINT8 NodeId; // Node ID of the HA Owning the memory
+ UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
+ UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets
+ UINT8 ImcInterBitmap; // IMC interleave bitmap for this memory
+ UINT8 ChInterBitmap[MAX_IMC];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+ UINT32 BaseAddress; // Base Address of the element in 64MB chunks
+ UINT32 ElementSize; // Size of this memory element in 64MB chunks
+} SYSTEM_MEMORY_MAP_ELEMENT;
+
+typedef struct SystemMemoryMapHob {
+ //
+ // Total Clusters. In SNC2 mode there are 2 clusters and SNC4 mode has 4 clusters.
+ // All2All/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1).
+ //
+ UINT8 TotalClusters;
+
+ MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // block decoder data structure
+ UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem.
+ UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem.
+ UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem.
+ UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem.
+ UINT32 memSize; // Total physical memory size
+ UINT16 memFreq; // Mem Frequency
+ UINT8 memMode; // 0 - Independent, 1 - Lockstep
+ UINT8 volMemMode; // 0 - 1LM, 1 - 2LM
+ UINT8 CacheMemType; // 0 - DDR$DDRT
+ UINT8 DdrtIntlvGranularity; // 1 - 256B, 2 - 4KB
+ UINT16 DramType;
+ UINT8 SmbMode[MAX_SOCKET][MAX_SMB_INSTANCE]; // Stores type of smbus mode: 0 - I2C mode, 1 - I3C mode
+ UINT8 DdrVoltage;
+ UINT8 DcpmmPresent; // If at least one DCPMM Present (used by Nfit), then this should get set
+ BOOLEAN EkvPresent; // Set if EKV controller on system
+ BOOLEAN BwvPresent; // Set if BWV controller on system
+ UINT8 XMPProfilesSup;
+ UINT16 Reserved1[MAX_SOCKET];
+ UINT32 Reserved2;
+ UINT32 Reserved3;
+ UINT16 Reserved4;
+ UINT16 Reserved5;
+ UINT8 SystemRasType;
+ UINT8 RasModesEnabled; // RAS modes that are enabled
+ UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled
+ UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
+ UINT8 NumOfCluster;
+ UINT8 NumChPerMC;
+ UINT8 numberEntries; // Number of Memory Map Elements
+ SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
+ struct memSetup MemSetup;
+ MEM_RESERVED_1 Reserved142;
+ MEMMAP_SOCKET Socket[MAX_SOCKET];
+ struct memTiming profileMemTime[2];
+
+ UINT32 Reserved6;
+ UINT8 Reserved7[RESERVED_2];
+ EFI_GUID Reserved8[RESERVED_2];
+ UINT8 Reserved9;
+ RASMEMORYINFO RasMeminfo;
+ UINT8 LatchSystemShutdownState;
+ BOOLEAN IsWpqFlushSupported;
+ UINT8 EadrSupport;
+ UINT8 EadrCacheFlushMode;
+ UINT8 SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH]; //MAX_CH * MAX_SOCKET * MAX_DCPMM_CH
+ HOST_DDRT_DIMM_DEVICE_INFO_STRUCT HostDdrtDimmInfo[MAX_SOCKET][MAX_CH];
+ UINT32 DdrCacheSize[MAX_SOCKET][MAX_CH]; // Size of DDR memory reserved for 2LM cache (64MB granularity)
+ BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH]; // ADR state for Intel PMEM Modules
+ UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS
+ UINT16 MaxAveragePowerLimit; // Max Power limit in mW used for averaged power ( Valid range ends at 15000mW)
+ UINT16 MinAveragePowerLimit; // Min Power limit in mW used for averaged power ( Valid range starts from 10000mW)
+ UINT16 CurrAveragePowerLimit; // Current Power limit in mW used for average power
+ UINT16 MaxMbbPowerLimit; // Max MBB power limit ( Valid range ends at 18000mW).
+ UINT16 MinMbbPowerLimit; // Min MBB power limit ( Valid range starts from 15000mW).
+ UINT16 CurrMbbPowerLimit; // Current Power limit in mW used for MBB power
+ UINT32 MaxMbbAveragePowerTimeConstant; // Max MBB Average Power Time Constant
+ UINT32 MinMbbAveragePowerTimeConstant; // Min MBB Average Power Time Constant
+ UINT32 CurrMbbAveragePowerTimeConstant; // Current MBB Average Power Time Constant
+ UINT32 MmiohBase; // MMIOH base in 64MB granularity
+ UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (24 for 14nm silicon, 16 for 10nm silicon)
+ UINT8 NumberofChaDramClusters; // Number of CHA DRAM decoder clusters
+ UINT8 VirtualNumaEnable; // Enable or Disable Virtual NUMA
+ UINT8 VirtualNumOfCluster; // Number of Virtual NUMA nodes in each physical NUMA node (Socket or SNC cluster)
+ BOOLEAN NumaEnable; // Information if NUMA is enabled or not
+} SYSTEM_MEMORY_MAP_HOB;
+
+#pragma pack()
+
+#endif // _MEMORY_MAP_DATA_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/PartialMirrorGuid.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/PartialMirrorGuid.h
new file mode 100644
index 0000000000..17fb93a163
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/PartialMirrorGuid.h
@@ -0,0 +1,61 @@
+/** @file
+ GUID used for ADDRESS_RANGE_MIRROR_VARIABLE.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PARTIAL_MIRROR_GUID_H_
+#define _PARTIAL_MIRROR_GUID_H_
+
+#define ADDRESS_BASED_MIRROR_VARIABLE_GUID { 0x7b9be2e0, 0xe28a, 0x4197, { 0xad, 0x3e, 0x32, 0xf0, 0x62, 0xf9, 0x46, 0x2c } }
+
+#define ADDRESS_RANGE_MIRROR_VARIABLE_CURRENT L"MirrorCurrent"
+#define ADDRESS_RANGE_MIRROR_VARIABLE_REQUEST L"MirrorRequest"
+#define ADDRESS_BASED_MIRROR_VARIABLE_SIZE sizeof(ADDRESS_RANGE_MIRROR_VARIABLE_DATA)
+#define ADDRESS_BASED_MIRROR_VARIABLE_ATTRIBUTE (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS)
+#define ADDRESS_RANGE_MIRROR_VARIABLE_VERSION 1
+#define MIRROR_STATUS_SUCCESS 0
+#define MIRROR_STATUS_MIRROR_INCAPABLE 1
+#define MIRROR_STATUS_VERSION_MISMATCH 2
+#define MIRROR_STATUS_INVALID_REQUEST 3
+#define MIRROR_STATUS_UNSUPPORTED_CONFIG 4
+#define MIRROR_STATUS_OEM_SPECIFIC_CONFIGURATION 5
+
+extern EFI_GUID gAddressBasedMirrorGuid;
+
+#pragma pack(1)
+
+typedef struct {
+//
+// MirroredAmountAbove4GB is the amount of available memory above 4GB that needs to be mirrored
+// measured in basis point (hundredths of percent e.g. 12.75% = 1275).
+// In a multi-socket system, platform is required to distribute the mirrored memory ranges such that the
+// amount mirrored is approximately proportional to the amount of memory on each NUMA node. E.g. on
+// a two node machine with 64GB on node 0 and 32GB on node 1, a request for 12GB of mirrored memory
+// should be allocated with 8GB of mirror on node 0 and 4GB on node 1.
+//
+// For example, if the total memory in the system is 48GB and 12GB of memory above the 4GB addresses needs to be mirrored then the amount would be:
+// Total Memory = 48 GB
+// Total Memory above 4GB = 44 GB
+// Percentage = 8/44 * 100 = 18.18% = 1818 basis points
+// Consider a 2S system with 32 GB of memory attached to socket 0 and 16GB on socket 1,
+// then socket 0 should mirror 8 GB of memory and socket 1 mirror 4GB to maintain the requested 18%.
+// This ensures that OS has an adequate amount of mirrored memory on each NUMA domain.
+//
+ UINT8 MirrorVersion;
+ BOOLEAN MirrorMemoryBelow4GB;
+ UINT16 MirroredAmountAbove4GB;
+ UINT8 MirrorStatus;
+} ADDRESS_RANGE_MIRROR_VARIABLE_DATA;
+
+typedef struct {
+ ADDRESS_RANGE_MIRROR_VARIABLE_DATA MirrorCurrentType;
+ ADDRESS_RANGE_MIRROR_VARIABLE_DATA MirrorRequestType;
+} RASMEMORYINFO;
+#pragma pack()
+
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/PlatformInfo.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/PlatformInfo.h
new file mode 100644
index 0000000000..2bce1aa905
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/PlatformInfo.h
@@ -0,0 +1,150 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_INFO_H_
+#define _PLATFORM_INFO_H_
+
+#include <PlatformInfoTypes.h>
+
+extern EFI_GUID gEfiPlatformInfoGuid;
+
+#pragma pack(1)
+
+typedef struct {
+ UINT32 ReservedPci;
+} EFI_PLATFORM_PCI_DATA;
+
+typedef struct {
+ UINT32 ReservedCpu;
+} EFI_PLATFORM_CPU_DATA;
+
+typedef struct {
+ UINT64 SysIoApicEnable;
+ UINT8 SysSioExist;
+ UINT8 IsocEn; // Isoc Enabled
+ UINT8 MeSegEn; // Me Seg Enabled.
+ UINT8 DmiVc1; // 0 - Disable, 1 - Enable
+ UINT8 SocketConfig;
+ UINT8 DmiVcm; // 0 - Disable, 1 - Enable
+ UINT8 DmiReserved; // for alignment
+} EFI_PLATFORM_SYS_DATA;
+
+typedef struct {
+ UINT32 BiosGuardPhysBase;
+ UINT32 BiosGuardMemSize;
+ UINT32 MemTsegSize;
+ UINT32 MemIedSize;
+
+#ifdef LT_FLAG
+ UINT32 MemLtMemSize; // Below TSEG, contains (high to low: (Heap, SinitMem, reserved)3M, LtDevMemNonDMA 2M)
+ UINT32 MemDprMemSize; // 6M DPR contained in LtMem
+ UINT32 MemLtMemAddress;
+#endif // #ifdef LT_FLAG
+
+ UINT64 PsmiUcTraceRegionBase;
+ UINT64 PsmiUcTraceRegionSize;
+} EFI_PLATFORM_MEM_DATA;
+
+typedef struct {
+ UINT8 PchPciePortCfg1; // PCIE Port Configuration Strap 1
+ UINT8 PchPciePortCfg2; // PCIE Port Configuration Strap 2
+ UINT8 PchPciePortCfg3; // PCIE Port Configuration Strap 3
+ UINT8 PchPciePortCfg4; // PCIE Port Configuration Strap 4
+ UINT8 PchPciePortCfg5; // PCIE Port Configuration Strap 5
+ UINT8 PchPcieSBDE;
+ UINT8 LomLanSupported; // Indicates if PCH LAN on board is supported or not
+ UINT8 GbePciePortNum; // Indicates the PCIe port qhen PCH LAN on board is connnected.
+ UINT8 GbeRegionInvalid;
+ BOOLEAN GbeEnabled; // Indicates if the GBE is SS disabled
+ UINT8 PchStepping;
+} EFI_PLATFORM_PCH_DATA;
+
+//
+// Platform Deep Sleep Feature
+//
+typedef struct {
+ UINT8 PlatformDeepS5;
+ UINT8 DeepS5DelayTime;
+} EFI_PLATFORM_DEEPS5_DATA;
+
+typedef struct {
+ UINT8 EnableClockSpreadSpec;
+} EFI_PLATFORM_EXTERNAL_CLOCK;
+
+///
+/// Enumeration of possible Wilson City interposer types
+///
+typedef enum {
+ InterposerUnknown = 0, ///< Type is unknown and should be retrieved from the Platform HOB
+ InterposerA, ///< Interposer Type A
+ InterposerB, ///< Interposer Type B
+ InterposerMax ///< Maximum number of members of this enum
+} INTERPOSER_TYPE;
+
+#pragma pack(1)
+typedef struct {
+ UINT8 MappedMcId[MAX_IMC];
+} INTERPOSER;
+
+typedef struct {
+ INTERPOSER Interposer[InterposerMax];
+} INTERPOSER_MAP;
+#pragma pack()
+
+//
+// This HOB definition must be consistent with what is created in the
+// PlatformInfo protocol definition. This way the information in the
+// HOB can be directly copied upon the protocol and only the strings
+// will need to be updated.
+//
+typedef struct _EFI_PLATFORM_INFO {
+ UINT8 SystemUuid[16]; // 16 bytes
+ CHAR8 SerialNumber[64]; // 64 bytes
+ UINT32 Signature; // "$PIT" 0x54495024
+ UINT32 Size; // Size of the table
+ UINT16 Revision; // Revision of the table
+ UINT16 Type; // Platform Type
+ UINT32 CpuType; // Cpu Type
+ UINT8 CpuStepping; // Cpu Stepping
+ UINT32 TypeRevisionId; // Board Revision ID
+ UINT8 BoardId; // Board ID
+ UINT16 IioSku;
+ UINT16 IioRevision;
+ UINT16 PchSku;
+ UINT8 PchRevision;
+ UINT8 PchType; // Retrive PCH SKU type installed
+ UINT8 MaxNumOfPchs; // Maximum Number of installed PCHs
+ BOOLEAN ExtendedInfoValid; // If TRUE then below fields are Valid
+ UINT8 Checksum; // Checksum minus SystemUuid is valid in DXE only.
+ UINT64 TypeStringPtr;
+ UINT64 IioStringPtr;
+ UINT64 PchStringPtr;
+ EFI_PLATFORM_PCI_DATA PciData;
+ EFI_PLATFORM_CPU_DATA CpuData;
+ EFI_PLATFORM_MEM_DATA MemData;
+ EFI_PLATFORM_SYS_DATA SysData;
+ EFI_PLATFORM_PCH_DATA PchData;
+ UINT8 IioRiserId;
+ UINT8 PcieRiser1Type;
+ UINT8 PcieRiser2Type;
+ UINT8 PlatformCapabilities; // Platform capabilites describes platform is 2-socket modular board, 4S or 8S
+ //
+ // Wilson City Interposer Type
+ //
+ INTERPOSER_TYPE InterposerType[MAX_SOCKET]; // 0 - Unknown, 1 - InterposerA, 2 - InterposerB
+ UINT32 QATDis; // 0 - QAT Enabled; 1 - Disabled
+ UINT32 QATSel;
+ UINT8 MemoryTopology[MAX_SOCKET][MAX_IMC*MAX_MC_CH]; // Specifies the memory topology per socket-per channel
+ UINT8 MemoryConnectorType[MAX_SOCKET][MAX_IMC*MAX_MC_CH]; // Specifies the memory connector type per socket-per channel, type EFI_MEMORY_DIMM_CONNECTOR_TYPE
+ EFI_PLATFORM_DEEPS5_DATA DeepS5Data;
+ EFI_PLATFORM_EXTERNAL_CLOCK ExternalClock;
+} EFI_PLATFORM_INFO;
+
+#pragma pack()
+
+#endif // #ifndef _PLATFORM_INFO_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SiliconPolicyInitLibInterface.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SiliconPolicyInitLibInterface.h
new file mode 100644
index 0000000000..57037c96dd
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SiliconPolicyInitLibInterface.h
@@ -0,0 +1,78 @@
+/** @file
+ This provides a versatile abstraction for the SiliconPolicyInitLib library interface.
+
+ This defines the typedef necessary for PPI and protocol use.
+ This defines structs for PPI and protocol production and consumption.
+ There is a single GUID defining both PPI and protocol.
+
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SILICON_POLICY_INIT_LIB_INTERFACE_H_
+#define _SILICON_POLICY_INIT_LIB_INTERFACE_H_
+
+#include <Library/SiliconPolicyInitLib.h>
+
+//
+// All interface declarations should refer to the SiliconPolicyInitLib for description of functionality
+//
+
+typedef
+VOID *
+(EFIAPI *PEI_SILICON_POLICY_INIT_PRE_MEM) (
+ IN OUT VOID *Policy OPTIONAL
+ );
+
+typedef
+RETURN_STATUS
+(EFIAPI *PEI_SILICON_POLICY_DONE_PRE_MEM) (
+ IN VOID *Policy
+ );
+
+typedef
+VOID *
+(EFIAPI *PEI_SILICON_POLICY_INIT_POST_MEM) (
+ IN OUT VOID *Policy OPTIONAL
+ );
+
+typedef
+RETURN_STATUS
+(EFIAPI *PEI_SILICON_POLICY_DONE_POST_MEM) (
+ IN VOID *Policy
+ );
+
+typedef
+VOID *
+(EFIAPI *PEI_SILICON_POLICY_INIT_LATE) (
+ IN OUT VOID *Policy OPTIONAL
+ );
+
+typedef
+RETURN_STATUS
+(EFIAPI *PEI_SILICON_POLICY_DONE_LATE) (
+ IN VOID *Policy
+ );
+
+//
+// PPI structure declaration
+//
+typedef struct {
+ PEI_SILICON_POLICY_INIT_PRE_MEM SiliconPolicyInitPreMem;
+ PEI_SILICON_POLICY_DONE_PRE_MEM SiliconPolicyDonePreMem;
+ PEI_SILICON_POLICY_INIT_POST_MEM SiliconPolicyInitPostMem;
+ PEI_SILICON_POLICY_DONE_POST_MEM SiliconPolicyDonePostMem;
+} SILICON_POLICY_INIT_LIB_PPI;
+
+//
+// Protocol structure declaration
+//
+typedef struct {
+ PEI_SILICON_POLICY_INIT_LATE SiliconPolicyInitLate;
+ PEI_SILICON_POLICY_DONE_LATE SiliconPolicyDoneLate;
+} SILICON_POLICY_INIT_LIB_PROTOCOL;
+
+extern EFI_GUID gSiliconPolicyInitLibInterfaceGuid;
+
+#endif // _SILICON_POLICY_INIT_LIB_INTERFACE_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketCommonRcVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketCommonRcVariable.h
new file mode 100644
index 0000000000..8bc88cd97c
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketCommonRcVariable.h
@@ -0,0 +1,57 @@
+/** @file
+ Data format for Universal Data Structure
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __SOCKET_COMMONRC_CONFIG_DATA_H__
+#define __SOCKET_COMMONRC_CONFIG_DATA_H__
+
+
+#include <UncoreCommonIncludes.h>
+
+extern EFI_GUID gEfiSocketCommonRcVariableGuid;
+#define SOCKET_COMMONRC_CONFIGURATION_NAME L"SocketCommonRcConfig"
+
+#define UMABASEDCLUSTERING_DISABLED 0
+#define UMABASEDCLUSTERING_HEMISPHERE 2
+#define UMABASEDCLUSTERING_QUADRANT 4
+
+#pragma pack(1)
+typedef struct {
+ //
+ // Common Section of RC
+ //
+ UINT32 MmiohBase;
+ UINT16 MmiohSize;
+ UINT8 MmcfgBase;
+ UINT8 MmcfgSize;
+ UINT8 IsocEn;
+ UINT8 NumaEn;
+ UINT8 UmaBasedClustering;
+ UINT8 MirrorMode;
+ UINT8 CpuType;
+ UINT8 CpuChop;
+ UINT8 X2ApicForceEn;
+ UINT8 SystemRasType;
+ UINT8 NumCpus;
+ UINT8 ReservedS6;
+ UINT8 ReservedS7[MAX_B2P_MAILBOX_GROUPS];
+ UINT8 OcCap;
+ UINT8 IssMaxLevel;
+ UINT8 DcpmmEnable;
+ UINT8 ReservedS8;
+ UINT8 HbmSku;
+ UINT8 PbfCapableSystem;
+ UINT8 DcuRtlWaEn;
+ UINT8 SstCpCapableSystem;
+ UINT8 VirtualNumaEnable;
+} SOCKET_COMMONRC_CONFIGURATION;
+#pragma pack()
+
+#endif
+
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
new file mode 100644
index 0000000000..7df44e93c3
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
@@ -0,0 +1,444 @@
+/** @file
+ Data format for Universal Data Structure
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SOCKET_IIO_VARIABLE_H_
+#define _SOCKET_IIO_VARIABLE_H_
+
+#include <UncoreCommonIncludes.h>
+
+extern EFI_GUID gEfiSocketIioVariableGuid;
+#define SOCKET_IIO_CONFIGURATION_NAME L"SocketIioConfig"
+
+/*
+ These vars are not used anywhere - it is left here for reference as this is used in comments below.
+ Number must be used directly because of VFR compiler...
+
+ #ifndef MAX_STACKS_PER_SOCKET_VAR
+ #define MAX_STACKS_PER_SOCKET_VAR 6
+ #define MAX_PORTS_PER_SOCKET_VAR 21
+ #endif
+ #endif
+*/
+
+#if MAX_SOCKET == 1
+ #define TOTAL_VMD_STACKS_VAR 6 // MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
+
+ #define TOTAL_NTB_PORTS_VAR 5 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_IOU_VAR 5 // MAX_IOU_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_VMD_PCH_ROOTPORTS_VAR 20 // MAX_PCH_ROOTPORTS * MAX_SOCKET
+ #define TOTAL_RETIMERS_VAR 12 // MAX_SOCKET * MAX_STACKS_PER_SOCKET_VAR * MAX_RETIMERS_PER_STACK (ICX-SP related)
+
+ #define TOTAL_NPK_VAR 1 // NUMBER_TRACE_HUB_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_PORTS_VAR 21 // MAX_PORTS_PER_SOCKET_VAR * MAX_SOCKET
+ #define TOTAL_VMD_PORTS_VAR 24 // MAX_PORTS_PER_STACK * MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
+ #define TOTAL_DSA_VAR 1 // 1_DSA_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_IAX_VAR 1 // 1_IAX_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_CPM_VAR 1 // 1_CPM_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_HQM_VAR 1 // 1_HQM_PER_SOCKET * MAX_SOCKET
+
+#endif
+
+#if MAX_SOCKET == 4
+ #define TOTAL_VMD_STACKS_VAR 24 // MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
+ #define TOTAL_NTB_PORTS_VAR 20 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_IOU_VAR 20 // MAX_IOU_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_VMD_PCH_ROOTPORTS_VAR 80 // MAX_PCH_ROOTPORTS * MAX_SOCKET
+ #define TOTAL_RETIMERS_VAR 48 // MAX_SOCKET * MAX_STACKS_PER_SOCKET_VAR * MAX_RETIMERS_PER_STACK (ICX-SP related)
+ #define TOTAL_NPK_VAR 4 // NUMBER_TRACE_HUB_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_PORTS_VAR 84 // MAX_PORTS_PER_SOCKET_VAR * MAX_SOCKET
+ #define TOTAL_VMD_PORTS_VAR 96 // MAX_PORTS_PER_STACK * MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
+ #define TOTAL_DSA_VAR 4 // 1_DSA_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_IAX_VAR 4 // 1_IAX_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_CPM_VAR 4 // 1_CPM_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_HQM_VAR 4 // 1_HQM_PER_SOCKET * MAX_SOCKET
+#endif
+
+#if MAX_SOCKET == 2
+ #define TOTAL_VMD_STACKS_VAR 12 // MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
+ #define TOTAL_NTB_PORTS_VAR 10 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_IOU_VAR 10 // MAX_IOU_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_VMD_PCH_ROOTPORTS_VAR 40 // MAX_PCH_ROOTPORTS * MAX_SOCKET
+ #define TOTAL_RETIMERS_VAR 24 // MAX_SOCKET * MAX_STACKS_PER_SOCKET_VAR * MAX_RETIMERS_PER_STACK (ICX-SP related)
+ #define TOTAL_NPK_VAR 2 // NUMBER_TRACE_HUB_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_PORTS_VAR 42 // MAX_PORTS_PER_SOCKET_VAR * MAX_SOCKET
+ #define TOTAL_VMD_PORTS_VAR 48 // MAX_PORTS_PER_STACK * MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
+ #define TOTAL_DSA_VAR 2 // 1_DSA_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_IAX_VAR 2 // 1_IAX_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_CPM_VAR 2 // 1_CPM_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_HQM_VAR 2 // 1_HQM_PER_SOCKET * MAX_SOCKET
+#endif
+
+#if MAX_SOCKET > 4
+ #define TOTAL_VMD_PCH_ROOTPORTS_VAR 160 // MAX_PCH_ROOTPORTS * MAX_SOCKET
+ #define TOTAL_NTB_PORTS_VAR 40 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_IOU_VAR 40 // MAX_IOU_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_VMD_STACKS_VAR 48 // MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
+ #define TOTAL_RETIMERS_VAR 96 // MAX_SOCKET * MAX_STACKS_PER_SOCKET_VAR * MAX_RETIMERS_PER_STACK (ICX-SP related)
+ #define TOTAL_NPK_VAR 8 // NUMBER_TRACE_HUB_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_PORTS_VAR 168 // MAX_PORTS_PER_SOCKET_VAR * MAX_SOCKET
+ #define TOTAL_VMD_PORTS_VAR 192 // MAX_PORTS_PER_STACK * MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
+ #define TOTAL_DSA_VAR MAX_SOCKET // 1_DSA_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_IAX_VAR MAX_SOCKET // 1_IAX_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_CPM_VAR MAX_SOCKET // 1_CPM_PER_SOCKET * MAX_SOCKET
+ #define TOTAL_HQM_VAR MAX_SOCKET // 1_HQM_PER_SOCKET * MAX_SOCKET
+#endif
+
+#pragma pack(1)
+
+typedef struct {
+
+/**
+==================================================================================================
+================================== VTd Setup Options ==================================
+==================================================================================================
+**/
+ UINT8 VTdSupport;
+ UINT8 DmaCtrlOptIn;
+ UINT8 InterruptRemap;
+ UINT8 PostedInterrupt;
+ UINT8 ATS;
+ UINT8 CoherencySupport;
+/**
+==================================================================================================
+================================== PCIE Setup Options ==================================
+==================================================================================================
+**/
+ // Vars used to configure (disable/greyout) parts of setup menu
+ UINT8 IioPresent[MAX_SOCKET];
+ UINT8 IioStackPresent[TOTAL_IIO_STACKS]; // based on sysInfo data
+ UINT8 PchPresentOnStack[MAX_SOCKET]; // stub for multiPCH
+ UINT8 RetimerPresent[TOTAL_RETIMERS_VAR]; // retimer detected in stack
+
+ UINT8 VtdAcsWa;
+
+ // Platform data needs to update these PCI Configuration settings
+ UINT8 PcieHotPlugOnPort[TOTAL_PORTS_VAR];
+ UINT8 SLOTHPSUP[TOTAL_PORTS_VAR]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
+
+ // General PCIE Configuration
+ UINT8 ConfigIOU0[MAX_SOCKET];
+ UINT8 ConfigIOU1[MAX_SOCKET];
+ UINT8 ConfigIOU2[MAX_SOCKET];
+ UINT8 ConfigIOU3[MAX_SOCKET];
+ UINT8 ConfigIOU4[MAX_SOCKET];
+ UINT8 ConfigIOU5[MAX_SOCKET];
+ UINT8 ConfigIOU6[MAX_SOCKET];
+ UINT8 ConfigIOU7[MAX_SOCKET];
+ UINT8 PcieSubSystemMode[TOTAL_IOU_VAR];
+ UINT8 CompletionTimeoutGlobal;
+ UINT8 CompletionTimeoutGlobalValue;
+ UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup
+ UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup
+ UINT8 CoherentReadPart;
+ UINT8 CoherentReadFull;
+ UINT8 PcieGlobalAspm;
+ UINT8 StopAndScream;
+ UINT8 SnoopResponseHoldOff;
+ //
+ // PCIE capability
+ //
+ UINT8 PCIe_LTR;
+ UINT8 PcieExtendedTagField;
+ UINT8 Pcie10bitTag;
+ UINT8 PCIe_AtomicOpReq;
+ UINT8 PcieMaxReadRequestSize;
+ UINT8 PciePtm;
+
+
+ UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup
+ UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup
+ UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup
+
+ // mixc PCIE configuration
+ UINT8 PcieLinkDis[TOTAL_PORTS_VAR]; // On Setup
+ UINT8 PcieAspm[TOTAL_PORTS_VAR]; // On Setup
+ UINT8 PcieCommonClock[TOTAL_PORTS_VAR]; // On Setup
+ UINT8 PcieMaxPayload[TOTAL_PORTS_VAR]; // On Setup PRD
+ UINT8 PcieDState[TOTAL_PORTS_VAR]; // On Setup
+ UINT8 PcieL1Latency[TOTAL_PORTS_VAR]; // On Setup
+ UINT8 MsiEn[TOTAL_PORTS_VAR]; // On Setup
+ UINT8 ExtendedSync[TOTAL_PORTS_VAR]; // On Setup
+ UINT8 PciePortEnable[TOTAL_PORTS_VAR]; // On Setup
+ UINT8 IODC[TOTAL_PORTS_VAR]; // On Setup
+ UINT8 MctpEn[TOTAL_PORTS_VAR]; // On Setup
+
+ //
+ // PCIE setup options for Link Control2
+ //
+ UINT8 PciePortLinkSpeed[TOTAL_PORTS_VAR]; //on Setup
+ UINT8 ComplianceMode[TOTAL_PORTS_VAR]; // On Setup PRD
+ UINT8 PciePortLinkMaxWidth[TOTAL_PORTS_VAR]; // On Setup
+ UINT8 DeEmphasis[TOTAL_PORTS_VAR]; // On Setup
+
+ //
+ // PCIE setup options for MISCCTRLSTS
+ //
+ UINT8 EOI[TOTAL_PORTS_VAR]; // On Setup
+ UINT8 MSIFATEN[TOTAL_PORTS_VAR]; //On Setup.
+ UINT8 MSINFATEN[TOTAL_PORTS_VAR]; //On Setup.
+ UINT8 MSICOREN[TOTAL_PORTS_VAR]; //On Setup.
+ UINT8 ACPIPMEn[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 P2PRdDis[TOTAL_PORTS_VAR]; //On Setup Peer 2 peer
+ UINT8 DisPMETOAck[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ACPIHP[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ACPIPM[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 SRIS[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 TXEQ[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 SERRE[TOTAL_PORTS_VAR]; //On Setup
+ //
+ // PCIE RAS (Errors)
+ //
+
+ UINT8 PcieUnsupportedRequests[TOTAL_PORTS_VAR]; // Unsupported Request per-port option
+
+ //
+ // PCIE Link Training Ctrl
+ //
+
+
+ //
+ // North Peak (NPK)
+ //
+
+ UINT8 NorthTraceHubMode[TOTAL_NPK_VAR];
+ UINT32 NorthTraceHubMemReg0Size[TOTAL_NPK_VAR];
+ UINT32 NorthTraceHubMemReg1Size[TOTAL_NPK_VAR];
+
+ //
+ // Sierra Peak (SPK)
+ //
+ UINT8 SierraPeakMemBufferSize[MAX_SOCKET];
+
+ //
+ // MMIO poison enabling per stack
+ //
+ UINT8 PoisonMmioReadEn[TOTAL_IIO_STACKS]; // on setup
+/**
+==================================================================================================
+================================== Crystal Beach 3 Setup Options ===========================
+==================================================================================================
+**/
+ UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup
+ UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup
+ UINT8 DisableTPH;
+ UINT8 PrioritizeTPH;
+ UINT8 CbRelaxedOrdering;
+ UINT8 CbDmaMultiCastEnable; // CbDmaMultiCastEnable test enable
+
+ UINT8 DsaEn[TOTAL_DSA_VAR]; // on setup
+ UINT8 IaxEn[TOTAL_IAX_VAR]; // on setup
+ UINT8 CpmEn[TOTAL_CPM_VAR]; // on setup
+ UINT8 HqmEn[TOTAL_HQM_VAR]; // on setup
+
+/**
+==================================================================================================
+================================== MISC IOH Setup Options ==========================
+==================================================================================================
+**/
+
+ // The following are for hiding each individual device and function
+ UINT8 PEXPHIDE[TOTAL_PORTS_VAR]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD
+ UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS];
+ // Hide IOAPIC Device 5, Function 4
+ UINT8 PCUF6Hide; // Hide Device PCU Device 30, Function 6
+ UINT8 EN1K; // Enable/Disable 1K granularity of IO for P2P bridges 0:20:0:98 bit 2
+ UINT8 DualCvIoFlow; // Dual CV IO Flow
+ UINT8 Xppdef;
+ UINT8 Pci64BitResourceAllocation;
+ UINT8 PcieBiosTrainEnable; // Used as a work around for A0 PCIe
+ UINT8 MultiCastEnable; // MultiCastEnable test enable
+ UINT8 McastBaseAddrRegion; // McastBaseAddrRegion
+ UINT8 McastIndexPosition; // McastIndexPosition
+ UINT8 McastNumGroup; // McastNumGroup
+
+
+ UINT8 HidePEXPMenu[TOTAL_PORTS_VAR]; // to suppress /display the PCIe port menu
+
+/**
+==================================================================================================
+================================== NTB Related Setup Options ==========================
+==================================================================================================
+**/
+ UINT8 NtbPpd[TOTAL_NTB_PORTS_VAR]; //on setup option
+ UINT8 NtbBarSizeOverride[TOTAL_NTB_PORTS_VAR]; //on setup option
+ UINT8 NtbSplitBar[TOTAL_NTB_PORTS_VAR]; //on setup option
+ UINT8 NtbBarSizeImBar1[TOTAL_NTB_PORTS_VAR]; //on setup option
+ UINT8 NtbBarSizeImBar2[TOTAL_NTB_PORTS_VAR]; //on setup option
+ UINT8 NtbBarSizeImBar2_0[TOTAL_NTB_PORTS_VAR]; //on setup option
+ UINT8 NtbBarSizeImBar2_1[TOTAL_NTB_PORTS_VAR]; //on setup option
+ UINT8 NtbBarSizeEmBarSZ1[TOTAL_NTB_PORTS_VAR]; //on setup option
+ UINT8 NtbBarSizeEmBarSZ2[TOTAL_NTB_PORTS_VAR]; //on setup option
+ UINT8 NtbBarSizeEmBarSZ2_0[TOTAL_NTB_PORTS_VAR]; //on setup option
+ UINT8 NtbBarSizeEmBarSZ2_1[TOTAL_NTB_PORTS_VAR]; //on setup option
+ UINT8 NtbXlinkCtlOverride[TOTAL_NTB_PORTS_VAR]; //on setup option
+
+ UINT8 NtbLinkBiosTrainEn;
+/**
+==================================================================================================
+================================== VMD Related Setup Options ==========================
+==================================================================================================
+**/
+ UINT8 VMDEnabled[TOTAL_VMD_STACKS_VAR]; // indicates if VMD is enabled on given stack
+ UINT8 VMDPortEnable[TOTAL_VMD_PORTS_VAR]; // indicated if VMD is enabled on given port is enabled
+ UINT8 VMDPchPortAllowed[TOTAL_VMD_PCH_ROOTPORTS_VAR]; // indicates if VMD CAN BE enabled on given PCH Rp
+ UINT8 VMDPchPortEnable[TOTAL_VMD_PCH_ROOTPORTS_VAR]; // indicates if VMD IS enabled on given PCH Rp
+ UINT8 VMDHotPlugEnable[TOTAL_VMD_STACKS_VAR];
+ UINT8 VMDCfgBarSz[TOTAL_VMD_STACKS_VAR];
+ UINT8 VMDCfgBarAttr[TOTAL_VMD_STACKS_VAR];
+ UINT8 VMDMemBarSz1[TOTAL_VMD_STACKS_VAR];
+ UINT8 VMDMemBar1Attr[TOTAL_VMD_STACKS_VAR];
+ UINT8 VMDMemBarSz2[TOTAL_VMD_STACKS_VAR];
+ UINT8 VMDMemBar2Attr[TOTAL_VMD_STACKS_VAR];
+ UINT8 VMDDirectAssign[TOTAL_VMD_STACKS_VAR];
+
+ /**
+ ==================================================================================================
+ ================================== PCIe SSD Related Setup Options ==========================
+ ==================================================================================================
+ **/
+
+ UINT8 PcieAICEnabled[TOTAL_VMD_STACKS_VAR];
+ UINT8 PcieAICPortEnable[TOTAL_PORTS_VAR];
+ UINT8 PcieAICHotPlugEnable[TOTAL_VMD_STACKS_VAR];
+
+
+ /**
+ ==================================================================================================
+ ================================== Retimers Related Setup Options ==========================
+ ==================================================================================================
+ **/
+
+ UINT32 RetimerGlParmReg0Override[TOTAL_RETIMERS_VAR];
+ UINT32 RetimerPseudoPort0Reg2Override[TOTAL_RETIMERS_VAR];
+ UINT32 RetimerPseudoPort1Reg2Override[TOTAL_RETIMERS_VAR];
+
+ /**
+ ==================================================================================================
+ ======================== PCI-E Port Clock Gating Related Setup Options ========================
+ ==================================================================================================
+ **/
+ UINT8 PciePortClkGateEnable[TOTAL_PORTS_VAR]; // Indicates Clock gating for this PCIe port is enabled or not
+ /**
+ ==================================================================================================
+ ================================== PCIe Global Related Setup Options ==========================
+ ==================================================================================================
+ **/
+ UINT8 NoSnoopRdCfg; //on Setup
+ UINT8 NoSnoopWrCfg; //on Setup
+ UINT8 MaxReadCompCombSize; //on Setup
+ UINT8 ProblematicPort; //on Setup
+ UINT8 DmiAllocatingFlow; //on Setup
+ UINT8 PcieAllocatingFlow; //on Setup
+ UINT8 PcieHotPlugEnable; //on Setup
+ UINT8 PcieAcpiHotPlugEnable; //on Setup
+ UINT8 PcieLowLatencyRetimersEnabled;
+ UINT8 HaltOnDmiDegraded; //on Setup
+ UINT8 RxClockWA;
+ UINT8 GlobalPme2AckTOCtrl; //on Setup
+ UINT8 PcieSlotOprom1; //On Setup
+ UINT8 PcieSlotOprom2; //On Setup
+ UINT8 PcieSlotOprom3; //On Setup
+ UINT8 PcieSlotOprom4; //On Setup
+ UINT8 PcieSlotOprom5; //On Setup
+ UINT8 PcieSlotOprom6; //On Setup
+ UINT8 PcieSlotOprom7; //On Setup
+ UINT8 PcieSlotOprom8; //On Setup
+ UINT8 PcieSlotItemCtrl; //On Setup
+ UINT8 PcieRelaxedOrdering; //On Setup
+ UINT8 PciePhyTestMode; //On setup
+ UINT8 PcieEnqCmdSupport; //On setup
+ UINT16 DelayBeforePCIeLinkTraining; //On Setup
+/**
+==================================================================================================
+================================== Reserved Setup Options ==========================
+==================================================================================================
+**/
+ UINT8 ReservedS9;
+ UINT8 ReservedS10;
+ UINT8 ReservedS11; // On Setup
+ UINT8 ReservedS12; // On Setup
+ UINT8 ReservedS13; // On Setup
+ UINT8 ReservedS14; // On Setup
+ UINT8 ReservedS15; // On Setup
+ UINT8 ReservedS16; // On Setup
+ UINT8 ReservedS17; // On Setup
+ UINT8 ReservedS18; // On Setup
+ UINT8 ReservedS19; // On Setup
+ UINT8 ReservedS20; // On Setup
+ UINT32 ReservedS21[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup
+ UINT8 ReservedS22[TOTAL_PORTS_VAR]; // On Setup
+
+ UINT8 ReservedS23[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS24[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS25[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS26[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS27[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS28[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS29[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS30[TOTAL_PORTS_VAR]; //On Setup
+
+ UINT8 ReservedS31[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS32[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS33[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS34[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS35[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS36[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS37[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS38[TOTAL_PORTS_VAR]; //On Setup
+
+ UINT8 ReservedS39[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS40[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS41[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS42[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS43[TOTAL_PORTS_VAR]; //On Setup
+
+
+ UINT8 ReservedS44[TOTAL_PORTS_VAR];
+ UINT8 ReservedS45[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ReservedS46; //On Setup
+
+ UINT8 ReservedS47; //On Setup
+
+/**
+==================================================================================================
+====================== IIO Global Performance Tuner Related Setup Options =====================
+==================================================================================================
+**/
+ UINT8 PerformanceTuningMode;
+
+ /**
+ ==================================================================================================
+ ====================== PCI-E Data Link Feature Exchange Enable ===============================
+ ==================================================================================================
+ **/
+ UINT8 PcieDataLinkFeatureExchangeEnable[TOTAL_PORTS_VAR]; //On Setup
+ /**
+ ==================================================================================================
+ ====================== Variables added post Beta ===============================
+ ==================================================================================================
+ **/
+ UINT8 PcieTxRxDetPoll[TOTAL_PORTS_VAR];
+ UINT8 EcrcGenEn[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 EcrcChkEn[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 ControlIommu;
+ UINT32 VtdDisabledBitmask[MAX_SOCKET];
+ UINT8 X2ApicOptOut;
+ UINT8 SkipRetimersDetection;
+
+ UINT8 VtdPciAcsCtlWaEn; // Enables override of ACSCTL on PCIe root ports for VTd
+ UINT8 VtdPciAcsCtlBit0;
+ UINT8 VtdPciAcsCtlBit1;
+ UINT8 VtdPciAcsCtlBit2;
+ UINT8 VtdPciAcsCtlBit3;
+ UINT8 VtdPciAcsCtlBit4;
+} SOCKET_IIO_CONFIGURATION;
+#pragma pack()
+
+#endif // _SOCKET_IIO_VARIABLE_H_
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h
new file mode 100644
index 0000000000..533489fafc
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h
@@ -0,0 +1,477 @@
+/** @file
+ Data format for Ioh Memory Config Data Structure
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __SOCKET_MEMORY_CONFIG_DATA_H__
+#define __SOCKET_MEMORY_CONFIG_DATA_H__
+
+
+#include <UncoreCommonIncludes.h>
+#include <MemDefaults.h>
+
+extern EFI_GUID gEfiSocketMemoryVariableGuid;
+#define SOCKET_MEMORY_CONFIGURATION_NAME L"SocketMemoryConfig"
+
+#pragma pack(1)
+typedef struct {
+ UINT8 ReservedS48;
+ UINT8 MemoryHotPlugBase;
+ UINT8 MemoryHotPlugLen;
+ UINT8 Srat;
+ UINT8 SratMemoryHotPlug;
+ UINT8 SratCpuHotPlug;
+ UINT8 PagePolicy;
+ UINT8 PatrolScrub;
+ UINT8 PatrolScrubDuration;
+ UINT8 TempRefreshOption;
+ UINT8 HalfxRefreshValue;
+ UINT8 TwoxRefreshValue;
+ UINT8 FourxRefreshValue;
+ UINT8 NsddcEn;
+ UINT8 EsddcEn;
+ UINT8 ColumnCorrectionDisable;
+ UINT8 SaiPolicyGroupWaBiosW;
+ UINT8 PatrolScrubAddrMode;
+ UINT8 partialmirrorsad0;
+ UINT8 PartialMirrorUefi;
+ UINT16 PartialMirrorUefiPercent;
+ UINT16 partialmirrorsize[MAX_PARTIAL_MIRROR]; // Array of sizes of different partial mirrors
+ UINT8 ImmediateFailoverAction;
+ UINT8 PlusOneEn;
+ UINT8 MemCeFloodPolicy;
+ UINT16 spareErrTh;
+ UINT8 TriggerSWErrThEn;
+ UINT16 SpareSwErrTh;
+ UINT16 timeWindow;
+ UINT8 DieSparing;
+ UINT8 PclsEn;
+ UINT8 ADDDCEn;
+ UINT8 DcpmmEccModeSwitch;
+ UINT8 AdddcErrInjEn;
+ UINT8 leakyBktTimeWindow;
+ UINT8 leakyBktLo;
+ UINT8 leakyBktHi;
+ UINT16 leakyBktHour;
+ UINT8 leakyBktMinute;
+ UINT8 CmdNormalization;
+ UINT8 LrDimmBacksideVrefEn;
+ UINT8 CmdVrefEnable;
+ UINT8 DramRonEn;
+ UINT8 McRonEn;
+ UINT8 RxCtleTrnEn;
+ UINT8 RxOdtEn;
+ UINT8 LrDimmWrVrefEn;
+ UINT8 LrDimmRdVrefEn;
+ UINT8 LrDimmTxDqCentering;
+ UINT8 LrDimmRxDqCentering;
+ UINT8 txEqCalibration;
+ UINT8 CmdTxEqCalibration;
+ UINT8 RxDfe;
+ UINT8 TxRiseFallSlewRate;
+ UINT8 iModeTraining;
+ UINT8 TcoCompTraining;
+ UINT8 RoundTripLatency;
+ UINT8 DutyCycleTraining;
+ UINT8 PxcTraining;
+ UINT8 DdjcTraining;
+ UINT8 refreshMode;
+ UINT8 dllResetTestLoops;
+ UINT8 DdrMemoryType;
+ UINT8 HwMemTest;
+ UINT16 MemTestLoops;
+ UINT8 TrainingResultOffsetFunctionEnable;
+ UINT16 OffsetTxDq;
+ UINT16 OffsetRxDq;
+ UINT16 OffsetTxVref;
+ UINT16 OffsetRxVref;
+ UINT16 OffsetCmdAll;
+ UINT16 OffsetCmdVref;
+ UINT16 OffsetCtlAll;
+ UINT32 AdvMemTestOptions;
+ UINT8 AdvMemTestResetList;
+ UINT8 AdvMemTestCondition;
+ UINT16 AdvMemTestCondVdd;
+ UINT8 AdvMemTestCondTwr;
+ UINT16 AdvMemTestCondTrefi;
+ UINT32 AdvMemTestCondPause;
+ UINT8 EccSupport;
+ UINT8 EccEnable;
+ UINT8 ReservedS49;
+ UINT8 ReservedS50;
+ UINT8 ReservedS51;
+ UINT8 ReservedS52;
+ UINT16 ReservedS53;
+ UINT16 ReservedS54;
+ UINT16 ReservedS55;
+ UINT16 ReservedS56;
+ UINT16 ReservedS57;
+ UINT8 ReservedS58;
+ UINT16 ReservedS59;
+ UINT8 ReservedS60;
+ UINT16 ReservedS61;
+ UINT8 ReservedS62;
+ UINT8 ReservedS63;
+ UINT16 ReservedS64;
+ UINT16 ReservedS65;
+ UINT8 ReservedS66;
+ UINT8 ReservedS67;
+ UINT8 ReservedS68;
+ UINT8 ReservedS69;
+ UINT8 ReservedS70;
+ UINT8 ReservedS71;
+ UINT8 ReservedS72;
+ UINT8 ReservedS73;
+ UINT8 ReservedS74[16]; //[MAX_SOCKET * MAX_IMC] = [8]
+ UINT8 volMemMode;
+ UINT8 CacheMemType; //Only valid if volMemMode is 2LM
+ UINT8 DdrCacheSize;
+ UINT8 PmemCaching;
+ UINT8 ReservedS75;
+ UINT8 memInterleaveGran1LM;
+ UINT8 ReservedS76;
+ UINT8 ReservedS77;
+ UINT8 ReservedS78;
+ UINT8 ReservedS79;
+ UINT8 ReservedS80;
+ UINT8 CkeProgramming;
+ UINT8 SrefProgramming;
+ UINT8 PkgcSrefEn;
+ UINT8 CkeIdleTimer;
+ UINT8 ApdEn;
+ UINT8 PpdEn;
+ UINT8 DdrtCkeEn;
+ UINT8 OppSrefEn;
+ UINT8 OppSrefVisible; //Setup variable to hide Opportunistic Self Refresh Knob
+ UINT8 DdrtSrefEn;
+ UINT8 DataDllOff;
+ UINT8 MdllOffEn;
+ UINT8 CkMode;
+ UINT8 MemTestOnColdFastBoot;
+ UINT8 AttemptFastBoot;
+ UINT8 AttemptFastBootCold;
+ UINT8 bdatEn;
+ UINT8 ScrambleEnDDRT;
+ UINT8 ScrambleEn; // for ddr4
+ UINT8 allowCorrectableError;
+ UINT8 allowCorrectableMemTestError;
+ UINT16 ScrambleSeedLow;
+ UINT16 ScrambleSeedHigh;
+ UINT8 CustomRefreshRateEn;
+ UINT8 CustomRefreshRate;
+ UINT8 readVrefCenter;
+ UINT8 wrVrefCenter;
+ UINT8 haltOnMemErr;
+ UINT8 thermalthrottlingsupport;
+ UINT8 MemTripReporting;
+ UINT8 OffPkgMemToThermTrip;
+ UINT8 OffPkgMemToMemTrip;
+ UINT8 InPkgMemToThermTrip;
+ UINT8 InPkgMemToMemTrip;
+ UINT8 DimmTempStatValue;
+ UINT8 XMPProfilesSup;
+ UINT8 XMPMode;
+ UINT8 tCAS;
+ UINT8 tRP;
+ UINT8 tRCD;
+ UINT8 tRAS;
+ UINT8 tWR;
+ UINT16 tRFC;
+ UINT8 tRRD;
+ UINT8 tRRD_L;
+ UINT8 tRTP;
+ UINT8 tWTR;
+ UINT8 tFAW;
+ UINT8 tCWL;
+ UINT8 tRC;
+ UINT8 commandTiming;
+ UINT16 tREFI;
+ UINT8 DdrFreqLimit;
+ UINT16 Vdd;
+ UINT8 lrdimmModuleDelay;
+ UINT32 rmtPatternLength;
+ UINT32 rmtPatternLengthExt;
+ UINT8 RecEnDelayAverage;
+ UINT8 check_pm_sts;
+ UINT8 check_platform_detect;
+ UINT8 MemPwrSave;
+ UINT8 ElectricalThrottlingMode;
+ UINT8 MultiThreaded;
+ UINT8 promoteMrcWarnings;
+ UINT8 promoteWarnings;
+ UINT8 oppReadInWmm;
+ UINT16 normOppInterval;
+ UINT8 ReservedS81[96]; //[MAX_SETUP_SOCKET * MAX_SETUP_IMC * MAX_SETUP_MC_CH] = [8 * 4 * 3 = 96]
+ UINT8 mdllSden;
+ UINT8 memhotSupport;
+ UINT8 MemHotIn;
+ UINT8 MemHotOut;
+ UINT8 MemHotOuputAssertThreshold;
+ UINT8 ADREn;
+ UINT8 RankMargin;
+ UINT8 EnableBacksideRMT;
+ UINT8 EnableBacksideCMDRMT;
+ UINT8 EnableNgnBcomMargining;
+ UINT8 ReservedS82;
+ UINT8 RankSparing;
+ UINT8 multiSparingRanks;
+ UINT8 ReservedS83;
+ UINT8 dimmIsolation;
+ UINT8 smbSpeed;
+ UINT8 SmbSpdAccess;
+ UINT8 SpdPrintEn;
+ UINT16 SpdPrintLength;
+ UINT8 EnforcePOR;
+ UINT8 pda;
+ UINT8 turnaroundOpt;
+ UINT8 turnaroundOptDdrt;
+ UINT8 oneRankTimingMode;
+ UINT8 eyeDiagram;
+ UINT8 NvmdimmPerfConfig;
+ UINT8 ReservedS84;
+ UINT8 ReservedS85;
+ UINT8 ReservedS86;
+ UINT8 ReservedS87;
+ UINT8 ReservedS88;
+ UINT8 ReservedS89;
+ UINT8 ReservedS90;
+ UINT8 ReservedS91;
+ UINT8 ReservedS92;
+ UINT8 ReservedS93;
+ UINT8 ReservedS94;
+ UINT8 ReservedS95;
+ UINT8 ReservedS96;
+ UINT8 ReservedS97;
+ UINT8 ReservedS98;
+ UINT8 ReservedS99;
+ UINT8 ReservedS100;
+ UINT8 ReservedS101;
+ UINT8 ReservedS102;
+ UINT8 ReservedS103;
+ UINT8 ReservedS104;
+ UINT8 DramRaplPwrLimitLockCsr;
+ UINT8 DramRaplEnable;
+ UINT8 BwLimitTfOvrd;
+ UINT8 perbitmargin;
+ UINT8 DramRaplExtendedRange;
+ UINT8 CmsEnableDramPm;
+ UINT8 logParsing;
+ UINT8 WritePreamble;
+ UINT8 ReadPreamble;
+ UINT8 WrCRC;
+ UINT8 AepOnSystem;
+ UINT8 EkvOnSystem; // 0 => Do not suppress power management policy for BWV, 1 => suppress power management policy for BWV.
+ UINT8 BwvOnSystem; // 0 => Do not suppress power management policy for EKV, 1 => suppress power management policy for EKV.
+ // NGN options
+ UINT8 LockNgnCsr;
+ UINT8 NgnCmdTime;
+ UINT8 NgnEccCorr;
+ UINT8 NgnEccWrChk;
+ UINT8 NgnEccRdChk;
+ UINT8 NgnEccExitCorr;
+ UINT8 NgnDebugLock;
+ UINT8 NgnArsPublish;
+ UINT8 RmtOnColdFastBoot;
+ UINT8 LegacyRmt;
+ UINT8 mrcRepeatTest;
+ UINT8 ReservedS105;
+ UINT8 ReservedS106;
+ UINT8 ReservedS107;
+ UINT8 staggerref;
+ UINT32 memFlows;
+ UINT32 memFlowsExt;
+ UINT32 memFlowsExt2;
+ UINT32 memFlowsExt3;
+ UINT8 Blockgnt2cmd1cyc;
+ UINT8 TrefiPerChannel;
+ UINT8 TrefiNumofRank;
+ UINT16 TrefiDelay;
+ UINT8 Disddrtopprd;
+ UINT16 Reserved;
+ UINT8 setSecureEraseAllDIMMs;
+ UINT8 setSecureEraseSktCh[64]; // [MAX_SOCKET * MAX_IMC * MAX_MC_CH]
+ UINT8 SetSecureEraseSktChHob[64]; // [MAX_SOCKET * MAX_IMC * MAX_MC_CH]
+ UINT8 AppDirectMemoryHole;
+ UINT8 LatchSystemShutdownState;
+ UINT8 ExtendedType17;
+ //
+ // PPR related
+ //
+ UINT8 pprType;
+ UINT8 pprErrInjTest;
+ // CR QoS Configuration Profiles
+ UINT8 FastGoConfig;
+ UINT8 ReservedS108;
+ UINT8 LegacyADRModeEn;
+ UINT8 MinNormalMemSize;
+ UINT8 ADRDataSaveMode;
+ UINT8 eraseArmNVDIMMS;
+ UINT8 restoreNVDIMMS;
+ UINT8 interNVDIMMS;
+ UINT8 imcBclk;
+ UINT8 spdCrcCheck;
+ UINT8 ReservedS109;
+ UINT8 SETUP_REMOVE_SanitizeOverwriteNvmDimm; // removed
+ UINT8 EliminateDirectoryInFarMemory;
+ UINT8 NvmdimmPowerCyclePolicy;
+
+ //CMI Init option
+ UINT8 CmiInitOption;
+ //
+ // Cmd setup hold percent offset for 2n timing
+ //
+ UINT8 cmdSetupPercentOffset;
+ UINT8 ShortStroke2GB;
+ UINT8 NvDimmEnergyPolicy; //Energy Policy Management
+ UINT8 ReservedS110;
+ UINT8 ReservedS111;
+ UINT8 ReservedS112;
+ UINT8 ReservedS113;
+ UINT8 DisableDirForAppDirect;
+ UINT8 NvmMediaStatusException;
+ UINT8 NvmQos;
+ UINT8 ReservedS114;
+ UINT8 ReservedS115;
+ UINT8 ReservedS116;
+
+ //
+ // FIS 2.x
+ //
+ UINT16 DcpmmAveragePowerLimit; // Power limit in mW used for averaged power ( Valid range starts from 10000mW).
+ UINT8 DcpmmAveragePowerTimeConstant; // Value used as a base time window for power usage measurements Turbo Mode Support(in mSec).
+ UINT32 DcpmmMbbAveragePowerTimeConstant; // Value used as a base time window for power usage measurements Memory Bandwidth Boost Support(in mSec).
+ UINT8 DcpmmMbbFeature; // Allows enabling and disabling the feature (Turbo Mode State/Memory Bandwidth Boost).
+ UINT16 DcpmmMbbMaxPowerLimit; // Power limit in mW used for limiting the Turbo Mode/Memory Bandwidth Boost
+ // power consumption (Valid range starts from 15000mW).
+
+ UINT8 ReservedS117;
+ UINT8 ReservedS118;
+ UINT8 ReservedS119;
+
+ UINT8 ReservedS120;
+ UINT8 LsxImplementation;
+ UINT8 FactoryResetClear;
+ UINT8 EadrSupport;
+ UINT32 NvdimmSmbusMaxAccessTime;
+ UINT32 NvdimmSmbusReleaseDelay;
+ UINT8 NfitPublishMailboxStructs;
+
+ //
+ // fADR setup option
+ //
+ UINT8 FadrSupport;
+
+ //
+ // Biased 2-way near memory cache support options
+ //
+ UINT8 EnableTwoWayNmCache; // Enable or disable biased 2-way near memory cache.
+ UINT16 NonPreferredWayMask; // A 10-bit mask to control the bias counter ratio.
+ UINT8 PreferredReadFirst; // Reads are issued to the non-preferred or preferred way first.
+
+ //
+ // Boot-time fast zero memory setup option
+ //
+ UINT8 FastZeroMemSupport; // Enable or disable boot-time fast zero memory support.
+
+ //
+ // XOR decoder options
+ //
+ UINT8 ReservedS121;
+ UINT8 ReservedS122;
+ UINT8 ReservedS123;
+ UINT8 ReservedS124;
+ UINT8 ReservedS125;
+ UINT8 ReservedS126;
+ UINT8 ReservedS127;
+
+ UINT8 ReservedS128;
+ UINT8 ReservedS129;
+
+ UINT8 ReservedS130;
+ UINT16 ReservedS131;
+ UINT8 ReservedS132;
+ UINT8 ReservedS133;
+ UINT8 ReservedS134;
+ UINT8 ReservedS135;
+ UINT8 DcpmmApiVersion200OnSystem; // 0 => Suppress DcpmmAveragePowerTimeConstant, 1 => Do not suppress DcpmmAveragePowerTimeConstant.
+ UINT8 DcpmmApiVersion201OnSystem; // 0 => Suppress DcpmmAveragePowerTimeConstant, 1 => Do not suppress DcpmmAveragePowerTimeConstant.
+ UINT8 DcpmmApiVersion200OrGreaterOnSystem;
+ UINT8 ReservedS136;
+ UINT8 EnforcePopulationPor;
+
+ //
+ // DFE Path Finding
+ //
+ UINT8 EnableTapSweep;
+
+ UINT8 DfeGainBias;
+
+ UINT8 Tap1Start;
+ UINT8 Tap1End;
+ UINT8 Tap1Size;
+
+ UINT8 Tap2Start;
+ UINT8 Tap2End;
+ UINT8 Tap2Size;
+
+ UINT8 Tap3Start;
+ UINT8 Tap3End;
+ UINT8 Tap3Size;
+
+ UINT8 Tap4Start;
+ UINT8 Tap4End;
+ UINT8 Tap4Size;
+
+ UINT8 TrainingCompOptions; // Memory Training Comp Options Values.
+
+ UINT8 PeriodicRcomp; // Memory Periodic Rcomp Auto/Enable/Disable.
+ UINT8 PeriodicRcompInterval; // Memory Periodic Rcomp Interval.
+
+ UINT8 ReservedS137;
+
+ UINT8 AepNotSupportedException;
+
+ UINT8 ReservedS138;
+
+ UINT8 ReservedS139;
+ UINT8 PanicWm;
+
+ UINT16 OffsetRecEn;
+
+ UINT8 EadrCacheFlushMode;
+ UINT8 ReservedS140;
+ UINT8 ReservedS141;
+ UINT8 ReservedS142;
+ UINT8 ReservedS143;
+
+ UINT8 ReservedS144;
+ UINT8 ReservedS145;
+ UINT8 LrdimmDbDfeTraining;
+
+ UINT8 ReservedS146;
+ UINT8 ReservedS147;
+ UINT8 ReservedS148;
+ UINT8 AdvMemTestRetryAfterRepair;
+ UINT8 AdvMemTestPpr;
+ UINT8 AdvMemTestRankListNumEntries;
+ UINT32 AdvMemTestRankList[ADV_MT_LIST_LIMIT];
+
+ UINT32 SmartTestKey;
+ UINT8 SetMemTested;
+
+ //
+ // RMT minimum margin check
+ //
+ UINT8 RmtMinimumMarginCheck;
+
+ UINT8 ReservedS149;
+} SOCKET_MEMORY_CONFIGURATION;
+
+#pragma pack()
+
+#endif
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMpLinkVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMpLinkVariable.h
new file mode 100644
index 0000000000..d279066b68
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMpLinkVariable.h
@@ -0,0 +1,320 @@
+/** @file
+ Data format for Universal Data Structure
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __SOCKET_MP_LINK_CONFIG_DATA_H__
+#define __SOCKET_MP_LINK_CONFIG_DATA_H__
+
+#include <UncoreCommonIncludes.h>
+
+extern EFI_GUID gEfiSocketMpLinkVariableGuid;
+#define SOCKET_MP_LINK_CONFIGURATION_NAME L"SocketMpLinkConfig"
+
+#pragma pack(1)
+typedef struct {
+ // SKXTODO: rename to Kti when removing HSX code
+ UINT8 QpiSetupNvVariableStartTag; // This must be the very first one of the whole KTI Setup NV variable!
+
+ //
+ // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
+ // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook
+ // which updates the KTI resource map
+ //
+ //
+ // KTI Host structure inputs
+ //
+ UINT8 BusRatio[MAX_SOCKET];
+ UINT8 D2KCreditConfig; // 1 - Min, 2 - Med (Default), 3- Max
+ UINT8 SnoopThrottleConfig; // 0 - Disabled, 1 - Min, 2 - Med (Default), 3- Max
+ UINT8 SnoopAllCores; // 0 - Disabled, 1 - Enabled, 2 - Auto
+ UINT8 LegacyVgaSoc; // Socket that claims the legacy VGA range; valid values are 0-3; 0 is default.
+ UINT8 LegacyVgaStack; // Stack that claims the legacy VGA range; valid values are 0-3; 0 is default.
+ UINT8 P2pRelaxedOrdering; // 1 - Enable; 0 - Disable
+ UINT8 DebugPrintLevel; // Bit 0 - Fatal, Bit1 - Warning, Bit2 - Info Summary; Bit 3 - Info detailed. 1 - Enable; 0 - Disable
+ UINT8 DegradePrecedence; // Use DEGRADE_PRECEDENCE definition; TOPOLOGY_PRECEDENCE is default
+ UINT8 Degrade4SPreference; // 4S1LFullConnect topology is default; another option is 4S2LRing topology.
+
+ //
+ // Phy/Link Layer Options
+ //
+ UINT8 QpiLinkSpeedMode; // Link speed mode selection; 0 - Slow Speed; 1- Full Speed
+ UINT8 QpiLinkSpeed; // One of SPEED_REC_96GT, SPEED_REC_104GT, MAX_KTI_LINK_SPEED (default), FREQ_PER_LINK
+ UINT8 KtiLinkL0pEn; // 0 - Disable, 1 - Enable, 2- Auto (default)
+ UINT8 KtiLinkL1En; // 0 - Disable, 1 - Enable, 2- Auto (default)
+ UINT8 KtiFailoverEn; // 0 - Disable, 1 - Enable, 2- Auto (default)
+ UINT8 KtiLbEn; // 0 - Disable(default), 1 - Enable
+ UINT8 KtiCrcMode; // 0 - 8 bit CRC 1 - 16 bit CRC Mode
+ UINT8 QpiCpuSktHotPlugEn; // 0 - Disable (default), 1 - Enable
+ UINT8 KtiCpuSktHotPlugTopology; // 0 - 4S Topology (default), 1 - 8S Topology
+ UINT8 KtiSkuMismatchCheck; // 0 - No, 1 - Yes (default)
+ UINT8 KtiLinkVnaOverride; // 0x100 - per link, 0xff - max (default), 0x00 - min
+ UINT8 SncEn; // 0 - Disable (default), 1 - Enable
+ UINT8 IoDcMode; // 0 - Disable IODC, 1 - AUTO (default), 2 - IODC_EN_REM_INVITOM_PUSH, 3 - IODC_EN_REM_INVITOM_ALLOCFLOW
+ // 4 - IODC_EN_REM_INVITOM_ALLOC_NONALLOC, 5 - IODC_EN_REM_INVITOM_AND_WCILF
+ UINT8 DirectoryModeEn; // 0 - Disable; 1 - Enable (default)
+ UINT8 XptPrefetchEn; // XPT Prefetch : 1 - Enable (Default); 0 - Disable
+ UINT8 KtiPrefetchEn; // KTI Prefetch : 1 - Enable (Default); 0 - Disable
+ UINT8 XptRemotePrefetchEn; // XPT Remote Prefetch : 1 - Enable (Default); 0 - Disable
+ UINT8 RdCurForXptPrefetchEn; // RdCur for XPT Prefetch : 0 - Disable, 1 - Enable, 2- Auto (default)
+ UINT8 IrqThreshold; // KTI IRQ Threshold setting
+ UINT8 TorThresLoctoremNorm; // TOR threshold - Loctorem threshold normal
+ UINT8 TorThresLoctoremEmpty; // TOR threshold - Loctorem threshold empty
+ UINT8 MbeBwCal; // 0 - Linear, 1 - Biased, 2 - Legacy, 3 - AUTO (default = Linear)
+ UINT8 TscSyncEn; // TSC Sync Enable: 0 - Disable; 1 - Enable; 2 - AUTO (default)
+ UINT8 StaleAtoSOptEn; // HA A to S directory optimization
+ UINT8 LLCDeadLineAlloc; // Never fill dead lines in LLC: 1 - Enable, 0 - Disable
+ UINT8 SplitLock; // Setting this bit removes the Ubox PCU handshake during stopreq and startreq only
+ // for splitlocks: - Enable, 0 - Disable
+ UINT8 KtiAdaptationEn; // 0 - Disable, 1 - Enable
+ UINT8 KtiAdaptationSpeed; // Use KTI_LINK_SPEED definition; MAX_KTI_LINK_SPEED - Auto (i.e BIOS choosen speed)
+
+ UINT8 ReservedS150;
+ UINT8 ReservedS151;
+ UINT8 ReservedS152;
+ UINT8 ReservedS153;
+ UINT8 ReservedS154;
+ UINT8 ReservedS155;
+ UINT8 ReservedS156;
+ UINT8 ReservedS157;
+ UINT8 ReservedS158;
+ UINT8 ReservedS159;
+ UINT8 ReservedS160;
+ UINT8 ReservedS161;
+ UINT8 ReservedS162;
+ UINT8 ReservedS163;
+ UINT8 ReservedS164;
+ UINT8 ReservedS165;
+ UINT8 ReservedS166;
+ UINT8 ReservedS167;
+ UINT8 ReservedS168;
+ UINT8 ReservedS169;
+ UINT8 ReservedS170;
+ UINT8 ReservedS171;
+ UINT8 ReservedS172;
+ UINT8 ReservedS173;
+ UINT8 ReservedS174;
+ UINT8 ReservedS175;
+ UINT8 ReservedS176;
+ UINT8 ReservedS177;
+ UINT8 ReservedS178;
+
+ UINT8 ReservedS179;
+ UINT8 ReservedS180;
+ UINT8 ReservedS181;
+ UINT8 ReservedS182;
+ UINT8 ReservedS183;
+ UINT8 ReservedS184;
+ UINT8 ReservedS185;
+ UINT32 ReservedS186;
+
+ UINT8 ReservedS187;
+ UINT8 ReservedS188;
+
+#define UPICPUPRTVARIABLE(x) x##KtiPortDisable;x##KtiLinkSpeed;x##KtiLinkVnaOverride;
+
+ UINT8 KtiCpuPerPortStartTag;
+ UPICPUPRTVARIABLE (UINT8 Cpu0P0)
+ UPICPUPRTVARIABLE (UINT8 Cpu0P1)
+ UPICPUPRTVARIABLE (UINT8 Cpu0P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTVARIABLE (UINT8 Cpu0P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTVARIABLE (UINT8 Cpu0P4)
+ UPICPUPRTVARIABLE (UINT8 Cpu0P5)
+#endif
+#if MAX_SOCKET > 1
+ UPICPUPRTVARIABLE (UINT8 Cpu1P0)
+ UPICPUPRTVARIABLE (UINT8 Cpu1P1)
+ UPICPUPRTVARIABLE (UINT8 Cpu1P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTVARIABLE (UINT8 Cpu1P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTVARIABLE (UINT8 Cpu1P4)
+ UPICPUPRTVARIABLE (UINT8 Cpu1P5)
+#endif
+#endif
+#if MAX_SOCKET > 2
+ UPICPUPRTVARIABLE (UINT8 Cpu2P0)
+ UPICPUPRTVARIABLE (UINT8 Cpu2P1)
+ UPICPUPRTVARIABLE (UINT8 Cpu2P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTVARIABLE (UINT8 Cpu2P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTVARIABLE (UINT8 Cpu2P4)
+ UPICPUPRTVARIABLE (UINT8 Cpu2P5)
+#endif
+#endif
+#if MAX_SOCKET > 3
+ UPICPUPRTVARIABLE (UINT8 Cpu3P0)
+ UPICPUPRTVARIABLE (UINT8 Cpu3P1)
+ UPICPUPRTVARIABLE (UINT8 Cpu3P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTVARIABLE (UINT8 Cpu3P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTVARIABLE (UINT8 Cpu3P4)
+ UPICPUPRTVARIABLE (UINT8 Cpu3P5)
+#endif
+#endif
+#if (MAX_SOCKET > 4)
+ UPICPUPRTVARIABLE (UINT8 Cpu4P0)
+ UPICPUPRTVARIABLE (UINT8 Cpu4P1)
+ UPICPUPRTVARIABLE (UINT8 Cpu4P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTVARIABLE (UINT8 Cpu4P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTVARIABLE (UINT8 Cpu4P4)
+ UPICPUPRTVARIABLE (UINT8 Cpu4P5)
+#endif
+#endif
+#if (MAX_SOCKET > 5)
+ UPICPUPRTVARIABLE (UINT8 Cpu5P0)
+ UPICPUPRTVARIABLE (UINT8 Cpu5P1)
+ UPICPUPRTVARIABLE (UINT8 Cpu5P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTVARIABLE (UINT8 Cpu5P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTVARIABLE (UINT8 Cpu5P4)
+ UPICPUPRTVARIABLE (UINT8 Cpu5P5)
+#endif
+#endif
+#if (MAX_SOCKET > 6)
+ UPICPUPRTVARIABLE (UINT8 Cpu6P0)
+ UPICPUPRTVARIABLE (UINT8 Cpu6P1)
+ UPICPUPRTVARIABLE (UINT8 Cpu6P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTVARIABLE (UINT8 Cpu6P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTVARIABLE (UINT8 Cpu6P4)
+ UPICPUPRTVARIABLE (UINT8 Cpu6P5)
+#endif
+#endif
+#if (MAX_SOCKET > 7)
+ UPICPUPRTVARIABLE (UINT8 Cpu7P0)
+ UPICPUPRTVARIABLE (UINT8 Cpu7P1)
+ UPICPUPRTVARIABLE (UINT8 Cpu7P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTVARIABLE (UINT8 Cpu7P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTVARIABLE (UINT8 Cpu7P4)
+ UPICPUPRTVARIABLE (UINT8 Cpu7P5)
+#endif
+#endif
+
+#define UPICPUPRTDFXVARIABLE(x) x##ReservedS189;x##ReservedS190;x##ReservedS191;x##ReservedS246;
+
+ UINT8 DfxKtiCpuPerPortStartTag;
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu0P0)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu0P1)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu0P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu0P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu0P4)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu0P5)
+#endif
+#if MAX_SOCKET > 1
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu1P0)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu1P1)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu1P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu1P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu1P4)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu1P5)
+#endif
+#endif
+#if MAX_SOCKET > 2
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu2P0)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu2P1)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu2P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu2P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu2P4)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu2P5)
+#endif
+#endif
+#if MAX_SOCKET > 3
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu3P0)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu3P1)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu3P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu3P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu3P4)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu3P5)
+#endif
+#endif
+#if MAX_SOCKET > 4
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu4P0)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu4P1)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu4P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu4P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu4P4)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu4P5)
+#endif
+#endif
+#if MAX_SOCKET > 5
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu5P0)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu5P1)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu5P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu5P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu5P4)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu5P5)
+#endif
+#endif
+#if MAX_SOCKET > 6
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu6P0)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu6P1)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu6P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu6P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu6P4)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu6P5)
+#endif
+#endif
+#if MAX_SOCKET > 7
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu7P0)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu7P1)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu7P2)
+#if MAX_KTI_PORTS > 3
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu7P3)
+#endif
+#if MAX_KTI_PORTS > 5
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu7P4)
+ UPICPUPRTDFXVARIABLE (UINT8 Cpu7P5)
+#endif
+#endif
+
+ UINT8 QpiSetupNvVariableEndTag; // This must be the last one of the whole KTI Setup NV variable
+} SOCKET_MP_LINK_CONFIGURATION;
+
+#pragma pack()
+
+#endif // __SOCKET_MP_LINK_CONFIG_DATA_H__
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h
new file mode 100644
index 0000000000..567a44e73f
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h
@@ -0,0 +1,60 @@
+/** @file
+ UEFI variables used by DXE to pass PCI resource reconfiguration request to PEI.
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SOCKET_PCI_RESOURCE_CONFIG_DATA_H_
+#define _SOCKET_PCI_RESOURCE_CONFIG_DATA_H_
+
+extern EFI_GUID gEfiSocketPciResourceDataGuid;
+
+/**
+ * PCI MMIO and IO resource reconfiguration request structure.
+ **/
+#define SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME L"SystemPciResourceConfigData"
+
+typedef struct {
+ UINT64 Base; ///< Base (starting) address of a range (I/O, 32 and 64-bit mmio regions)
+ UINT64 Limit; ///< Limit (last valid) address of a range
+} PCIE_BASE_LIMIT;
+
+typedef struct {
+ PCIE_BASE_LIMIT Io; ///< Base and limit of I/O range assigned to entity
+ PCIE_BASE_LIMIT LowMmio; ///< Base and limit of low MMIO region for entity
+ PCIE_BASE_LIMIT HighMmio; ///< Base and limit of high (64-bit) MMIO region for entity
+} PCI_BASE_LIMITS;
+
+typedef struct {
+ PCI_BASE_LIMITS SocketLimits; ///< Base and Limit of all PCIe resources for the socket
+ PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket
+} SOCKET_PCI_BASE_LIMITS;
+
+typedef struct {
+ //
+ // Save basic system configuration parameters along with the resource map to detect a change.
+ // Remember low and high I/O memory range when saving recource configuration. It is used to verify
+ // whether system memory map changed. Remember also stacks configured when creating the map.
+ // If anything changed reset the system PCI resource configuration.
+ //
+ UINT64 MmioHBase;
+ UINT64 MmioHLimit;
+ UINT32 MmioLBase;
+ UINT32 MmioLLimit;
+ UINT16 IoBase;
+ UINT16 IoLimit;
+ UINT16 StackPresentBitmap[MAX_SOCKET];
+ //
+ // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
+ // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook
+ // which updates the KTI resource map.
+ //
+ SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of all PCIe resources for each socket
+} SYSTEM_PCI_BASE_LIMITS;
+
+
+#endif // _SOCKET_PCI_RESOURCE_CONFIG_DATA_H_
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h
new file mode 100644
index 0000000000..460e6e300b
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h
@@ -0,0 +1,300 @@
+/** @file
+ Data format for Universal Data Structure
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __SOCKET_POWERMANAGEMENT_CONFIGURATION_DATA_H__
+#define __SOCKET_POWERMANAGEMENT_CONFIGURATION_DATA_H__
+
+
+#include <UncoreCommonIncludes.h>
+
+extern EFI_GUID gEfiSocketPowermanagementVarGuid;
+#define SOCKET_POWERMANAGEMENT_CONFIGURATION_NAME L"SocketPowerManagementConfig"
+
+#define NUM_CST_LAT_MSR 3
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 WFRWAEnable;
+ UINT8 UncoreFreqScaling;
+ UINT8 InputUncoreFreq;
+ UINT8 ProcessorEistSupport; // Gates EIST based on CPUID ECX[7]
+ UINT8 ProcessorEistEnable; // EIST or GV3 setup option
+ UINT8 GpssTimer; // Global P-state Selection timer setup option
+
+ // Intel Speed Select (ISS)
+ UINT8 IssTdpLevel;
+ UINT8 DynamicIss;
+
+ // Config TDP
+ UINT8 ConfigTdpLevel;
+ UINT8 ConfigTdpLock;
+
+ // Individual controls for ACPI sleep states
+ // ** These can be overridden by AcpiSleepState because these knobs are not available to CRB **
+ //
+ UINT8 AcpiS3Enable;
+ UINT8 AcpiS4Enable;
+
+ //
+ //HWPM starts
+ //
+ UINT8 ProcessorHWPMEnable;
+ UINT8 ProcessorHWPMInterrupt;
+ UINT8 ProcessorEPPEnable;
+ UINT8 ProcessorEppProfile;
+ UINT8 ProcessorAPSrocketing;
+ UINT8 ProcessorScalability;
+ UINT8 ProcessorRaplPrioritization;
+ UINT8 ProcessorOutofBandAlternateEPB;
+ //
+ //HWPM ends
+ //
+ UINT8 ProcessorEistPsdFunc; // EIST/PSD Function select option
+ UINT8 BootPState; // Boot Performance Mode
+
+ //
+ // Active PBF (Prioritized Base Frequency)
+ //
+ UINT8 ProcessorActivePbf;
+ //
+ // Configure PBF High Priority Cores
+ //
+ UINT8 ProcessorConfigurePbf;
+
+ //
+ // Processor Control
+ //
+ UINT8 TurboMode;
+ UINT8 EnableXe;
+
+ //OverClocking
+ UINT8 HideOverclockingLock;
+ UINT8 OverclockingLock;
+ UINT8 AvxSupport;
+
+ UINT8 AvxLicensePreGrant;
+ UINT8 AvxIccpLevel;
+
+ UINT8 TurboRatioLimitRatio[8];
+ UINT8 TurboRatioLimitCores[8];
+
+ UINT8 C2C3TT;
+ UINT8 DynamicL1; // Enabling Dynamic L1
+ UINT8 ProcessorCcxEnable; // Enabling CPU C states of processor
+ UINT8 PackageCState; // Package C-State Limit
+ UINT8 EnableLowerLatencyMode; // Enable Lower Latency Mode for register accesses
+ UINT8 C3Enable; // Enable/Disable NHM C3(ACPI C2) report to OS
+ UINT8 C6Enable; // Enable/Disable NHM C6(ACPI C3) report to OS
+ UINT8 ProcessorC1eEnable; // Enabling C1E state of processor
+ UINT8 OSCx; // ACPI C States
+ UINT8 C1AutoDemotion; // Enabling C1 auto demotion
+ UINT8 C1AutoUnDemotion; // Enabling C1 auto un-demotion
+ UINT8 MonitorMWait; // Enabling IO MWAIT
+
+ UINT8 CStateLatencyCtrlValid[NUM_CST_LAT_MSR]; // C_STATE_LATENCY_CONTROL_x.Valid
+ UINT8 CStateLatencyCtrlMultiplier[NUM_CST_LAT_MSR]; // C_STATE_LATENCY_CONTROL_x.Multiplier
+ UINT16 CStateLatencyCtrlValue[NUM_CST_LAT_MSR]; // C_STATE_LATENCY_CONTROL_x.Value
+
+ UINT8 TStateEnable; // T states enable?
+ UINT8 OnDieThermalThrottling; // Throtte ratio
+ UINT8 ProchotLock;
+ UINT8 EnableProcHot;
+ UINT8 EnableThermalMonitor;
+ UINT8 ThermalMonitorStatusFilter;
+ UINT8 ThermalMonitorStatusFilterTimeWindow;
+ UINT8 ProchotResponse;
+ UINT8 EETurboDisable;
+ UINT8 SapmctlValCtl;
+ UINT8 PwrPerfTuning;
+ UINT8 AltEngPerfBIAS;
+ UINT8 PwrPerfSwitch;
+ UINT8 WorkLdConfig;
+ UINT16 EngAvgTimeWdw1;
+
+ UINT8 ProchotResponseRatio;
+ UINT8 TCCActivationOffset;
+
+ UINT8 P0TtlTimeLow1;
+ UINT8 P0TtlTimeHigh1;
+
+ UINT8 PkgCLatNeg;
+ UINT8 LTRSwInput;
+ UINT8 SAPMControl;
+ UINT8 CurrentConfig;
+ UINT8 PriPlnCurCfgValCtl;
+ UINT8 Psi3Code;
+ UINT16 CurrentLimit;
+
+ UINT8 Psi3Thshld;
+ UINT8 Psi2Code;
+ UINT8 Psi2Thshld;
+ UINT8 Psi1Code;
+ UINT8 Psi1Thshld;
+
+ //Power Management Setup options
+ UINT8 PkgCstEntryValCtl;
+ UINT8 NativeAspmEnable;
+
+ // PRIMARY_PLANE_CURRENT_CONFIG_CONTROL 0x601
+ UINT8 PpcccLock;
+
+ UINT8 SnpLatVld;
+ UINT8 SnpLatOvrd;
+ UINT8 SnpLatMult;
+ UINT16 SnpLatVal;
+ UINT16 NonSnpLatVld;
+ UINT8 NonSnpLatOvrd;
+ UINT8 NonSnpLatMult;
+ UINT16 NonSnpLatVal;
+
+ // DYNAMIC_PERF_POWER_CTL (CSR 1:30:2:0x64)
+ UINT8 EepLOverride;
+ UINT8 EepLOverrideEn;
+ UINT8 ITurboOvrdEn;
+ UINT8 CstDemotOvrdEN;
+ UINT8 TrboDemotOvrdEn;
+ UINT8 UncrPerfPlmtOvrdEn;
+ UINT8 EetOverrideEn;
+ UINT8 IoBwPlmtOvrdEn;
+ UINT8 ImcApmOvrdEn; // unused
+ UINT8 IomApmOvrdEn;
+ UINT8 KtiApmOvrdEn;
+ UINT8 PerfPLmtThshld;
+
+ // SAPMCTL_CFG (CSR 1:30:1:0xB0)
+ UINT8 Iio0PkgcClkGateDis[MAX_SOCKET]; //Bit[0]
+ UINT8 Iio1PkgcClkGateDis[MAX_SOCKET]; //Bit[1]
+ UINT8 Iio2PkgcClkGateDis[MAX_SOCKET]; //Bit[2]
+ UINT8 Kti01PkgcClkGateDis[MAX_SOCKET]; //Bit[3]
+ UINT8 Kti23PkgcClkGateDis[MAX_SOCKET]; //Bit[4]
+ UINT8 Kti45PkgcClkGateDis[MAX_SOCKET]; //Bit[5]
+ UINT8 P0pllOffEna[MAX_SOCKET]; //Bit[16]
+ UINT8 P1pllOffEna[MAX_SOCKET]; //Bit[17]
+ UINT8 P2pllOffEna[MAX_SOCKET]; //Bit[18]
+ UINT8 Mc0pllOffEna[MAX_SOCKET]; //Bit[22]
+ UINT8 Mc1pllOffEna[MAX_SOCKET]; //Bit[23]
+ UINT8 Mc0PkgcClkGateDis[MAX_SOCKET]; //Bit[6]
+ UINT8 Mc1PkgcClkGateDis[MAX_SOCKET]; //Bit[7]
+ UINT8 Kti01pllOffEna[MAX_SOCKET]; //Bit[19]
+ UINT8 Kti23pllOffEna[MAX_SOCKET]; //Bit[20]
+ UINT8 Kti45pllOffEna[MAX_SOCKET]; //Bit[21]
+ UINT8 SetvidDecayDisable[MAX_SOCKET]; //Bit[30];
+ UINT8 SapmCtlLock[MAX_SOCKET]; //Bit[31];
+
+ // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xe4)
+ UINT8 PerfPLimitClip;
+ UINT8 PerfPLimitEn;
+
+ // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xe4) >= HSX C stepping
+ UINT8 PerfPlimitDifferential;
+ UINT8 PerfPLimitClipC;
+
+ // SKX: PKG_CST_ENTRY_CRITERIA_MASK2 (CSR 1:30:2:0x90)
+ UINT8 Kti0In[MAX_SOCKET];
+ UINT8 Kti1In[MAX_SOCKET];
+ UINT8 Kti2In[MAX_SOCKET];
+
+ // SKX: PKG_CST_ENTRY_CRITERIA_MASK (CSR 1:30:2:0x8c)
+ UINT8 PcieIio0In[MAX_SOCKET];
+ UINT8 PcieIio1In[MAX_SOCKET];
+ UINT8 PcieIio2In[MAX_SOCKET];
+ UINT8 PcieIio3In[MAX_SOCKET];
+ UINT8 PcieIio4In[MAX_SOCKET];
+ UINT8 PcieIio5In[MAX_SOCKET];
+
+ // WRITE_PKGC_SA_PS_CRITERIA (B2P)
+ UINT8 EnablePkgcCriteria;
+ UINT8 PkgCCriteriaLogicalIpType[MAX_SOCKET];
+ UINT8 EnablePkgCCriteriaKti[MAX_SOCKET];
+ UINT8 EnablePkgCCriteriaRlink[MAX_SOCKET];
+ UINT8 EnablePkgCCriteriaFxr[MAX_SOCKET];
+ UINT8 EnablePkgCCriteriaMcddr[MAX_SOCKET];
+ UINT8 EnablePkgCCriteriaHbm[MAX_SOCKET];
+ UINT8 EnablePkgCCriteriaIio[MAX_SOCKET];
+ UINT8 EnablePkgCCriteriaHqm[MAX_SOCKET];
+ UINT8 EnablePkgCCriteriaNac[MAX_SOCKET];
+ UINT8 EnablePkgCCriteriaTip[MAX_SOCKET];
+ UINT8 EnablePkgCCriteriaMdfs[MAX_SOCKET];
+ UINT8 EnablePkgCCriteriaHcx[MAX_SOCKET];
+ UINT8 EnablePkgCCriteriaDino[MAX_SOCKET];
+ UINT8 PkgCCriteriaLogicalIpTypeMcddr[MAX_SOCKET];
+ UINT8 PkgCCriteriaLogicalIpTypeHbm[MAX_SOCKET];
+ UINT8 PkgCCriteriaLogicalIpTypeIio[MAX_SOCKET];
+ UINT8 PkgCCriteriaInstanceNoKti[MAX_SOCKET];
+ UINT8 EnableLinkInL1Kti[MAX_SOCKET];
+ UINT8 PkgCCriteriaInstanceNoRlink[MAX_SOCKET];
+ UINT8 EnableLinkInL1Rlink[MAX_SOCKET];
+ UINT8 PkgCCriteriaInstanceNoFxr[MAX_SOCKET];
+ UINT8 PkgcCriteraPsMaskFxr[MAX_SOCKET];
+ UINT8 PkgCCriteriaAllowedPsMaskFxr[MAX_SOCKET];
+ UINT8 PkgCCriteriaInstanceNoMcddr[MAX_SOCKET];
+ UINT8 PkgcCriteriaPsOptionMcddr[MAX_SOCKET];
+ UINT8 PkgCCriteriaInstanceNoHbm[MAX_SOCKET];
+ UINT8 PkgcCriteriaPsOptionHbm[MAX_SOCKET];
+ UINT8 PkgCCriteriaInstanceNoIio[MAX_SOCKET];
+ UINT8 EnableLinkInL1Iio[MAX_SOCKET];
+ UINT8 PkgCCriteriaInstanceNoHqm[MAX_SOCKET];
+ UINT8 PkgcCriteraPsMaskHqm[MAX_SOCKET];
+ UINT8 PkgCCriteriaAllowedPsMaskHqm[MAX_SOCKET];
+ UINT8 PkgCCriteriaInstanceNoNac[MAX_SOCKET];
+ UINT8 PkgcCriteraPsMaskNac[MAX_SOCKET];
+ UINT8 PkgCCriteriaAllowedPsMaskNac[MAX_SOCKET];
+ UINT8 PkgCCriteriaInstanceNoTip[MAX_SOCKET];
+ UINT8 PkgcCriteraPsMaskTip[MAX_SOCKET];
+ UINT8 PkgCCriteriaAllowedPsMaskTip[MAX_SOCKET];
+ UINT8 PkgCCriteriaInstanceNoMdfs[MAX_SOCKET];
+ UINT8 AllowLpStateMdfs[MAX_SOCKET];
+ UINT8 PkgCCriteriaInstanceNoHcx[MAX_SOCKET];
+ UINT8 PkgcCriteraPsMaskHcx[MAX_SOCKET];
+ UINT8 PkgCCriteriaAllowedPsMaskHcx[MAX_SOCKET];
+ UINT8 PkgCCriteriaInstanceNoDino[MAX_SOCKET];
+ UINT8 PkgcCriteraPsMaskDino[MAX_SOCKET];
+ UINT8 PkgCCriteriaAllowedPsMaskDino[MAX_SOCKET];
+
+ UINT8 FastRaplDutyCycle;
+ UINT8 TurboPowerLimitLock;
+ UINT8 TurboPowerLimitCsrLock;
+ UINT8 PowerLimit1En;
+ UINT16 PowerLimit1Power;
+ UINT16 PowerLimit1Time;
+ UINT8 PowerLimit2En;
+ UINT16 PowerLimit2Power;
+ UINT16 PowerLimit2Time;
+
+ UINT8 PmaxDetector;
+ UINT8 PmaxAutoAdjustment;
+ UINT8 PmaxLoadLine;
+ UINT8 PmaxSign;
+ UINT8 PmaxOffset;
+ UINT8 PmaxOffsetNegative;
+ UINT8 PmaxTriggerSetup;
+
+ //XTU 3.0
+
+ UINT8 MaxEfficiencyRatio[MAX_SOCKET];
+ UINT8 MaxNonTurboRatio[MAX_SOCKET];
+
+ UINT8 VccSAandVccIOdisable;
+ // Software LTR Override Control
+ UINT8 SwLtrOvrdCtl;
+ UINT8 EnhancedPmaxDetector;
+ UINT8 PcodeWdogTimerEn;
+
+ UINT8 RunCpuPpmInPei;
+
+ UINT8 UncoreFreqRaplLimit;
+} SOCKET_POWERMANAGEMENT_CONFIGURATION;
+#pragma pack()
+
+#endif
+
+
+
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h
new file mode 100644
index 0000000000..52ab370ce7
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h
@@ -0,0 +1,143 @@
+/** @file
+ Data format for Universal Data Structure
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__
+#define __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__
+
+#include <UncoreCommonIncludes.h>
+
+extern EFI_GUID gEfiSocketProcessorCoreVarGuid;
+#define SOCKET_PROCESSORCORE_CONFIGURATION_NAME L"SocketProcessorCoreConfig"
+
+#pragma pack(1)
+
+typedef struct {
+
+ UINT8 CpuidMaxValue;
+
+ UINT8 ProcessorHyperThreadingDisable; // Hyper Threading [ALL]
+ UINT8 ProcessorVmxEnable; // Enabling VMX
+ UINT8 ProcessorSmxEnable; // Enabling SMX (TXT LT)
+ UINT8 ProcessorLtsxEnable; // Enabling TXT (TXT LT-SX)
+ UINT8 ThreeStrikeTimer; // Disable 3strike timer
+ UINT8 FastStringEnable; // Fast String
+ UINT8 MachineCheckEnable; // Machine Check
+ UINT8 MlcStreamerPrefetcherEnable; // Hardware Prefetch
+ UINT8 MlcSpatialPrefetcherEnable; // Adjacent Cache Line Prefetch
+ UINT8 DCUStreamerPrefetcherEnable; // DCU Streamer Prefetcher
+ UINT8 DCUIPPrefetcherEnable; // DCU IP Prefetcher
+ UINT8 DCUModeSelection; // DCU Mode Selection
+ UINT8 ProcessorX2apic; // Enable Processor XAPIC
+ UINT8 BspSelection; // Select BSP
+ UINT8 IedTraceSize; // IED trace size
+ UINT8 TsegSize; // TSEG size
+ UINT8 AllowMixedPowerOnCpuRatio; // Allow Mixed PowerOn CpuRatio
+ UINT8 CheckCpuBist; // check and disable BIST faile core or ignore
+ UINT8 CoreFailover; // Enable spare core(s) in place of core(s) that fail BIST
+ UINT64 ReservedS192;
+ UINT8 ProcessorFlexibleRatio; // Non-Turbo Mode Processor Core Ratio Multiplier
+ UINT8 ProcessorFlexibleRatioOverrideEnable; // Non-Turbo Mode Processor Core Ratio Multiplier Enable
+ UINT8 ForcePhysicalModeEnable; // Force physical destionation mode
+ UINT8 LlcPrefetchEnable; // LLC Prefetch
+ UINT8 CpuMtoIWa; // MtoI Workaround;
+ UINT8 ProcessorVirtualWireMode;
+
+ UINT8 ProcessorMsrLockControl; // MSR Lock Bit Control
+ UINT8 ProcessorMsrPkgCstConfigControlLock; // MSR PKG_CST_CONFIG_CONTROL lock
+ UINT8 DebugInterface; // IA32_DEBUG_INTERFACE_MSR
+ UINT8 AesEnable;
+ UINT8 PpinControl; // PPIN Control MSR
+ UINT8 LockChipset; // Lock Chipset
+ UINT8 BiosAcmErrorReset; // Disable LT-SX and reset system when BIOS ACM error occurs
+ UINT8 AcmType; // 0x80 = debug signed ACM; 0x40 = NPW production signed ACM; 0x00 = PW production signed ACM
+
+ // SecurityPolicy Stalagmite
+ #include <Guid/SecurityPolicy_Flat.h>
+
+ UINT8 SkipStopPbet; // Skip StopPbet
+
+ UINT64 CoreDisableMask[MAX_SOCKET]; // one for each CPU socket
+
+ // IOT/OCLA configs
+#ifndef OCLA_TOR_ENTRY_MAX
+ #define OCLA_TOR_ENTRY_MIN 0
+ #define OCLA_TOR_ENTRY_MAX 0x11 // 15 or 17 depending on Isoch on/off
+ #define OCLA_TOR_ENTRY_DEFAULT 1
+ #define OCLA_WAY_MIN 0
+ #define OCLA_WAY_MAX 8 // max 8 LLC ways out of 11 can be reserved for OCLA
+ #define OCLA_WAY_DEFAULT 1
+#endif
+ UINT8 IotEn[MAX_SOCKET];
+ UINT8 OclaMaxTorEntry[MAX_SOCKET];
+ UINT8 OclaMinWay[MAX_SOCKET];
+ UINT32 IioLlcWaysMask; // MSR CBO_SLICE0_CR_IIO_LLC_WAYS bitmask.
+ UINT32 ExpandedIioLlcWaysMask; // MSR INGRESS_SPARE[10:0] bitmask. - Only Bits[10:0] are used
+ UINT32 RemoteWaysMask; // MSR INGRESS_SPARE[26:16] bitmask. - Only Bits[10:0] are used
+
+ UINT8 PCIeDownStreamPECIWrite;
+
+ //
+ // SMM Blocked and SMM Delayed
+ //
+ UINT8 SmmBlockedDelayed;
+
+ //
+ // eSMM Save State Mode
+ //
+ UINT8 eSmmSaveState;
+
+ UINT8 PeciInTrustControlBit; //On Setup
+ UINT8 PeciAgtLegacyTrustBit;
+ UINT8 PeciAgtSmbusTrustBit;
+ UINT8 PeciAgtIeTrustBit;
+ UINT8 PeciAgtGenericTrustBit;
+ UINT8 PeciAgtEspiTrustBit;
+ UINT8 Poison;
+ UINT8 Viral;
+ UINT8 EVMode;
+ UINT8 SmbusErrorRecovery;
+ UINT8 CpuL1NextPagePrefetcherDisable;
+ UINT8 CpuPaLimit;
+ UINT8 RdtCatOpportunisticTuning;
+ UINT8 CpuDbpEnable; // Enable/Disable DBP-F
+ UINT8 GlobalPsmiEnable;
+ UINT8 PsmiTrace[MAX_SOCKET];
+ UINT8 PsmiHandlerSize[MAX_SOCKET];
+ UINT8 PsmiTraceRegion0[MAX_SOCKET];
+ UINT8 PsmiTraceBufferSizeRegion0[MAX_SOCKET];
+ UINT8 PsmiTraceMemTypeRegion0[MAX_SOCKET];
+ UINT8 PsmiTraceRegion1[MAX_SOCKET];
+ UINT8 PsmiTraceBufferSizeRegion1[MAX_SOCKET];
+ UINT8 PsmiTraceMemTypeRegion1[MAX_SOCKET];
+ UINT8 PsmiTraceRegion2[MAX_SOCKET];
+ UINT8 PsmiTraceBufferSizeRegion2[MAX_SOCKET];
+ UINT8 PsmiTraceMemTypeRegion2[MAX_SOCKET];
+ UINT8 PsmiTraceRegion3[MAX_SOCKET];
+ UINT8 PsmiTraceBufferSizeRegion3[MAX_SOCKET];
+ UINT8 PsmiTraceMemTypeRegion3[MAX_SOCKET];
+ UINT8 PsmiTraceRegion4[MAX_SOCKET];
+ UINT8 PsmiTraceBufferSizeRegion4[MAX_SOCKET];
+ UINT8 PsmiTraceMemTypeRegion4[MAX_SOCKET];
+ UINT8 L2RfoPrefetchDisable; // L2 RFO Prefetch
+ UINT8 AmpPrefetchEnable;
+ UINT8 TscResetEnable;
+ UINT8 AcExceptionOnSplitLockEnable;
+ // FuSa (SAF) Start
+ UINT8 SafSupport;
+ UINT8 EnableSaf;
+ // FuSa (SAF) End
+ UINT8 CFRS3mEnable;
+ UINT8 CFRS3mManualCommit;
+ UINT8 CFRPucodeEnable;
+ UINT8 CFRPucodeManualCommit;
+ UINT8 CpuCrashLogGprs;
+} SOCKET_PROCESSORCORE_CONFIGURATION;
+#pragma pack()
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketVariable.h
new file mode 100644
index 0000000000..49de34bcb2
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketVariable.h
@@ -0,0 +1,36 @@
+/** @file
+ Data format for Socket Data Structure
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __SOCKET_CONFIG_DATA_H__
+#define __SOCKET_CONFIG_DATA_H__
+
+#include <UncoreCommonIncludes.h>
+#include <Guid/SocketIioVariable.h>
+#include <Guid/SocketCommonRcVariable.h>
+#include <Guid/SocketPowermanagementVariable.h>
+#include <Guid/SocketProcessorCoreVariable.h>
+#include <Guid/SocketMpLinkVariable.h>
+#include <Guid/SocketMemoryVariable.h>
+
+#pragma pack(1)
+
+typedef struct {
+ SOCKET_IIO_CONFIGURATION IioConfig;
+ SOCKET_COMMONRC_CONFIGURATION CommonRcConfig;
+ SOCKET_MP_LINK_CONFIGURATION UpiConfig;
+ SOCKET_MEMORY_CONFIGURATION MemoryConfig;
+ SOCKET_POWERMANAGEMENT_CONFIGURATION PowerManagementConfig;
+ SOCKET_PROCESSORCORE_CONFIGURATION SocketProcessorCoreConfiguration;
+} SOCKET_CONFIGURATION;
+
+
+
+#pragma pack()
+#endif
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/StatusCodeDataTypeExDebug.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/StatusCodeDataTypeExDebug.h
new file mode 100644
index 0000000000..369732921e
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/StatusCodeDataTypeExDebug.h
@@ -0,0 +1,50 @@
+/** @file
+ GUID and structure used for debug status code policy.
+
+ @copyright
+ Copyright 2017 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _STATUS_CODE_DATA_TYPE_EX_DEBUG_GUID_H_
+#define _STATUS_CODE_DATA_TYPE_EX_DEBUG_GUID_H_
+
+#define STATUS_CODE_DATA_TYPE_EX_DEBUG_GUID \
+ { 0x7859daa2, 0x926e, 0x4b01,{0x85, 0x86, 0xc6, 0x2d, 0x45, 0x64, 0x21, 0xd2} }
+
+#define MAX_EX_DEBUG_SIZE 0x200 // Inherited from PEI status code max
+#define MAX_EX_DEBUG_STR_LEN (MAX_EX_DEBUG_SIZE - sizeof(EX_DEBUG_INFO))
+
+typedef
+CHAR8 *
+(EFIAPI *PROCESS_BUFFER) (
+ IN VOID *ProcessDataPtr,
+ IN CHAR8 *Buffer,
+ IN OUT UINTN *BufferSize
+ );
+
+typedef
+VOID *
+(EFIAPI *PRINT_SYNC_ACQUIRE) (
+ VOID
+ );
+
+typedef
+VOID *
+(EFIAPI *PRINT_SYNC_RELEASE) (
+ VOID
+ );
+
+typedef struct {
+ PROCESS_BUFFER ProcessBuffer; // Buffer processing function
+ VOID *ProcessDataPtr; // Data needed for processing
+ PRINT_SYNC_ACQUIRE PrintSyncAcquire; // Acquire sync function
+ PRINT_SYNC_RELEASE PrintSyncRelease; // Release sync function
+ UINT32 DebugStringLen;
+ CHAR8 *DebugString; // Provided debug string
+} EX_DEBUG_INFO;
+
+extern EFI_GUID gStatusCodeDataTypeExDebugGuid;
+
+#endif // _STATUS_CODE_DATA_TYPE_EX_DEBUG_GUID_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
new file mode 100644
index 0000000000..df11dda735
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
@@ -0,0 +1,398 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IIO_CONFIG_H
+#define _IIO_CONFIG_H
+#include <ConfigBlock/TraceHubConfig.h>
+
+#pragma pack(1) //to align members on byte boundary
+/**
+The Silicon Policy allows the platform code to publish a set of configuration
+information that the RC drivers will use to configure the silicon hardware.
+**/
+typedef struct {
+ UINT8 ReservedAJ[MAX_TOTAL_PORTS];
+ UINT8 ReservedAK[MAX_TOTAL_PORTS];
+ UINT8 ReservedAL[MAX_TOTAL_PORTS];
+ UINT8 ReservedAM[MAX_TOTAL_PORTS];
+ UINT8 ReservedAN[MAX_TOTAL_PORTS];
+ UINT8 ReservedAO[MAX_TOTAL_PORTS];
+ UINT8 ReservedAP[MAX_TOTAL_PORTS];
+ UINT8 ReservedAQ[MAX_TOTAL_PORTS];
+ UINT8 ReservedAR[MAX_TOTAL_PORTS];
+ UINT8 ReservedAS[MAX_TOTAL_PORTS];
+ UINT8 ReservedAT[MAX_TOTAL_PORTS];
+ UINT8 ReservedAU[MAX_TOTAL_PORTS];
+ UINT8 ReservedAV[MAX_TOTAL_PORTS];
+ UINT8 ReservedAW[MAX_TOTAL_PORTS];
+ UINT8 ReservedAX[MAX_TOTAL_PORTS];
+ UINT8 ReservedAY[MAX_TOTAL_PORTS];
+ UINT8 ReservedE[MAX_TOTAL_PORTS];
+ UINT8 ReservedF[MAX_TOTAL_PORTS];
+ UINT8 ReservedG[MAX_TOTAL_PORTS];
+ UINT8 ReservedAZ[MAX_TOTAL_PORTS];
+ UINT8 ReservedBA[MAX_TOTAL_PORTS];
+
+ UINT8 PciePortClkGateEnable[MAX_TOTAL_PORTS];
+ UINT8 ExtendedSync[MAX_TOTAL_PORTS];
+ UINT8 PciePortEnable[MAX_TOTAL_PORTS];
+ UINT8 PcieMaxPayload[MAX_TOTAL_PORTS];
+ UINT8 PcieAspm[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; // On Setup
+ UINT8 PcieTxRxDetPoll[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET];
+ UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS];
+ UINT8 PciePtm;
+ UINT8 PcieHotPlugEnable;
+ UINT8 PCIe_LTR;
+ UINT8 PcieUnsupportedRequests[MAX_TOTAL_PORTS];
+ UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup
+ UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup
+ UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup
+ UINT8 ComplianceMode[MAX_TOTAL_PORTS];
+} IIO_PCIE_CONFIG_DATA;
+
+typedef struct _IIO_RETIMER_DATA {
+ UINT8 RetimerPresent; // eq. 0 => there is no retimer data
+ UINT32 GlParamReg0; // current value of Global Param. Reg. 0
+ UINT32 GlParamReg1; // current value of Global Param. Reg. 1
+ UINT32 PseudoPort0Reg2; // current value of Pseudo Port0 Reg. 2
+ UINT32 PseudoPort1Reg2; // current value of Pseudo Port1 Reg. 2
+ UINT32 GlParmReg0Override; // value to write to Global Param. Reg. 0
+ UINT32 PseudoPort0Reg2Override; // value to write to Pseudo Port0 Reg. 2
+ UINT32 PseudoPort1Reg2Override; // value to write to Pseudo Port1 Reg. 2
+} IIO_RETIMER_DATA;
+
+typedef struct {
+/**
+==================================================================================================
+================================== VTd Setup Options ==================================
+==================================================================================================
+**/
+ UINT8 VTdSupport;
+ UINT8 DmaCtrlOptIn;
+ UINT8 InterruptRemap;
+ UINT8 PostedInterrupt;
+ UINT8 ATS;
+ UINT8 CoherencySupport;
+ UINT8 VtdAcsWa;
+ UINT8 VtdPciAcsCtl; // Value to set in PCIe ACSCTL register if reqeusted
+
+/**
+==================================================================================================
+================================== PCIE Setup Options ==================================
+==================================================================================================
+**/
+ // Platform data needs to update these PCI Configuration settings
+ UINT8 SLOTEIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
+ UINT8 SLOTHPCAP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6)
+ UINT8 SLOTHPSUP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
+ UINT8 SLOTPIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
+ UINT8 SLOTAIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
+ UINT8 SLOTMRLSP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2)
+ UINT8 SLOTPCP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1)
+ UINT8 SLOTABP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
+ UINT8 PcieSSDCapable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Indicate if Port will PcieSSD capable.
+
+ UINT8 PcieHotPlugOnPort[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; // manual override of hotplug for port
+
+ // General PCIE Configuration
+ UINT8 PcieSubSystemMode[MAX_SOCKET][MAX_IOU_PER_SOCKET]; //on Setup
+
+ UINT8 CompletionTimeoutGlobal;
+ UINT8 CompletionTimeoutGlobalValue;
+ UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup
+ UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup
+ UINT8 CoherentReadPart;
+ UINT8 CoherentReadFull;
+ UINT8 PcieGlobalAspm;
+ UINT8 StopAndScream;
+ UINT8 SnoopResponseHoldOff;
+ //
+ // PCIE capability
+ //
+ UINT8 PcieExtendedTagField;
+ UINT8 Pcie10bitTag;
+ UINT8 PCIe_AtomicOpReq;
+ UINT8 PcieMaxReadRequestSize;
+
+
+ // mixc PCIE configuration
+ UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup
+ UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup
+ UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup
+ UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; //On Setup
+ UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; //On Setup
+ UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup
+ UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup
+ //
+ // VPP Control
+ //
+ BOOLEAN VppEnabled[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -- Disable, 01 -- Enable //no setup option defined- aj
+ UINT8 VppPort[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -- Port 0, 01 -- Port 1 //no setup option defined- aj
+ UINT8 VppAddress[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 01-07 for SMBUS address of Vpp //no setup option defined- aj
+
+ //
+ // Mux and channel for segment
+ //
+ UINT8 MuxAddress[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // SMBUS address of MUX //no setup option defined
+ UINT8 ChannelID[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -- channel 0, 01 -- channel 1 //no setup option defined
+
+ //
+ // PCIE setup options for Link Control2
+ //
+ UINT8 PciePortLinkMaxWidth[MAX_TOTAL_PORTS]; // On Setup
+ UINT8 DeEmphasis[MAX_TOTAL_PORTS]; // On Setup
+
+ //
+ // PCIE RAS (Errors)
+ //
+ UINT8 Serr;
+ UINT8 Perr;
+ UINT8 IioErrorEn;
+ UINT8 LerEn;
+ UINT8 WheaPcieErrInjEn;
+
+ //
+ // PciePll
+ //
+ UINT8 PciePllSsc; //On Setup
+
+ //
+ // PCIE Link Training Ctrl
+ //
+ UINT16 DelayBeforePCIeLinkTraining; //On Setup
+
+ //
+ // Retimers related config
+ //
+ IIO_RETIMER_DATA Retimer[MAX_SOCKET][MAX_IIO_STACK][MAX_RETIMERS_PER_STACK];
+ BOOLEAN SkipRetimersDetection; // Skip detection of retimers in UBA code
+
+/**
+==================================================================================================
+================================== Crystal Beach 3 Setup Options ===========================
+==================================================================================================
+**/
+ UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup
+ UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup
+ UINT8 DisableTPH;
+ UINT8 PrioritizeTPH;
+ UINT8 CbRelaxedOrdering;
+ UINT8 CbDmaMultiCastEnable; // MultiCastEnable test enable
+
+ UINT8 DsaEn[NUM_DSA*MAX_SOCKET]; // on setup
+ UINT8 IaxEn[NUM_IAX*MAX_SOCKET]; // on setup
+ UINT8 CpmEn[NUM_CPM*MAX_SOCKET]; // on setup
+ UINT8 HqmEn[NUM_HQM*MAX_SOCKET]; // on setup
+
+/**
+==================================================================================================
+================================== MISC IOH Setup Options ==========================
+==================================================================================================
+**/
+
+ // The following are for hiding each individual device and function
+ UINT8 PEXPHIDE[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD
+ UINT8 PCUF6Hide; // Hide Device PCU Device 30, Function 6
+ UINT8 EN1K; // Enable/Disable 1K granularity of IO for P2P bridges 0:20:0:98 bit 2
+ UINT8 DualCvIoFlow; // Dual CV IO Flow
+ UINT8 PcieBiosTrainEnable; // Used as a work around for A0 PCIe
+ UINT8 MultiCastEnable; // MultiCastEnable test enable
+ UINT8 McastBaseAddrRegion; // McastBaseAddrRegion
+ UINT8 McastIndexPosition; // McastIndexPosition
+ UINT8 McastNumGroup; // McastNumGroup
+ UINT8 MctpEn[MAX_TOTAL_PORTS]; // Enable/Disable MCTP for each Root Port
+
+ UINT8 LegacyVgaSoc;
+ UINT8 LegacyVgaStack;
+
+ UINT8 HidePEXPMenu[MAX_TOTAL_PORTS]; // to suppress /display the PCIe port menu
+
+ BOOLEAN PoisonMmioReadEn[MAX_SOCKET][MAX_IIO_STACK]; // on setup
+
+/**
+==================================================================================================
+================================== NTB Related Setup Options ==========================
+==================================================================================================
+**/
+ UINT8 NtbPpd[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; //on setup option
+ UINT8 NtbBarSizeOverride[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; //on setup option
+ UINT8 NtbSplitBar[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; //on setup option
+ UINT8 NtbBarSizeImBar1[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; //on setup option
+ UINT8 NtbBarSizeImBar2[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; //on setup option
+ UINT8 NtbBarSizeImBar2_0[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; //on setup option
+ UINT8 NtbBarSizeImBar2_1[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; //on setup option
+ UINT8 NtbBarSizeEmBarSZ1[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; //on setup option
+ UINT8 NtbBarSizeEmBarSZ2[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; //on setup option
+ UINT8 NtbBarSizeEmBarSZ2_0[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; //on setup option
+ UINT8 NtbBarSizeEmBarSZ2_1[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; //on setup option
+ UINT8 NtbXlinkCtlOverride[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; //on setup option
+
+ UINT8 NtbLinkBiosTrainEn; // on setup option
+/**
+==================================================================================================
+================================== VMD Related Setup Options ==========================
+==================================================================================================
+**/
+ UINT8 VMDEnabled[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET];
+ UINT8 VMDPortEnable[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET];
+ UINT8 VMDHotPlugEnable[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET];
+ UINT8 VMDCfgBarSz[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET];
+ UINT8 VMDCfgBarAttr[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET];
+ UINT8 VMDMemBarSz1[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET];
+ UINT8 VMDMemBar1Attr[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET];
+ UINT8 VMDMemBarSz2[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET];
+ UINT8 VMDMemBar2Attr[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET];
+ UINT8 VMDPchPortEnable[MAX_SOCKET][MAX_VMD_ROOTPORTS_PER_PCH];
+ UINT8 VMDDirectAssign[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET];
+
+ /**
+ ==================================================================================================
+ ================================== PcieSSD Related Setup Options ==========================
+ ==================================================================================================
+ **/
+ UINT8 PcieAICEnabled[MAX_SOCKET*MAX_STACKS_PER_SOCKET]; // Indicate if PCIE AIC Device will be connected behind an specific IOUx
+ UINT8 PcieAICPortEnable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET];
+ UINT8 PcieAICHotPlugEnable[MAX_SOCKET*MAX_STACKS_PER_SOCKET];
+
+
+/**
+==================================================================================================
+================================== Gen3 Related Setup Options ==========================
+==================================================================================================
+**/
+
+ //PCIE Global Option
+ UINT8 NoSnoopRdCfg; //on Setup
+ UINT8 NoSnoopWrCfg; //on Setup
+ UINT8 MaxReadCompCombSize; //on Setup
+ UINT8 ProblematicPort; //on Setup
+ UINT8 DmiAllocatingFlow; //on Setup
+ UINT8 PcieAllocatingFlow; //on Setup
+ UINT8 PcieAcpiHotPlugEnable; //on Setup
+ BOOLEAN PcieLowLatencyRetimersEnabled;
+ UINT8 HaltOnDmiDegraded; //on Setup
+ UINT8 GlobalPme2AckTOCtrl; //on Setup
+
+ UINT8 PcieSlotOprom1; //On Setup
+ UINT8 PcieSlotOprom2; //On Setup
+ UINT8 PcieSlotOprom3; //On Setup
+ UINT8 PcieSlotOprom4; //On Setup
+ UINT8 PcieSlotOprom5; //On Setup
+ UINT8 PcieSlotOprom6; //On Setup
+ UINT8 PcieSlotOprom7; //On Setup
+ UINT8 PcieSlotOprom8; //On Setup
+ UINT8 PcieSlotItemCtrl; //On Setup
+ UINT8 PcieRelaxedOrdering; //On Setup
+ UINT8 PciePhyTestMode; //On setup
+ UINT8 PcieEnqCmdSupport; //On setup
+/**
+==================================================================================================
+================================== IOAPIC Related Setup Options ==========================
+==================================================================================================
+**/
+
+ UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS];
+/**
+==================================================================================================
+================================== Security Related Setup Options ==========================
+==================================================================================================
+**/
+ UINT8 LockChipset;
+ UINT8 PeciInTrustControlBit;
+ UINT8 PeciAgtLegacyTrustBit;
+ UINT8 PeciAgtSmbusTrustBit;
+ UINT8 PeciAgtIeTrustBit;
+ UINT8 PeciAgtGenericTrustBit;
+ UINT8 PeciAgtEspiTrustBit;
+ UINT8 ProcessorX2apic;
+ UINT8 ProcessorMsrLockControl;
+ UINT8 Xppdef;
+ UINT8 Pci64BitResourceAllocation;
+ UINT8 Imr2SupportEnable;
+/**
+==================================================================================================
+================================== Reserved Setup Options ==========================
+==================================================================================================
+**/
+ UINT8 ReservedQ; // On Setup
+ UINT8 ReservedR;
+ UINT8 ReservedS; // On Setup
+ UINT8 ReservedT; // On Setup
+ UINT8 ReservedU; // On Setup
+ UINT8 ReservedV; // On Setup
+ UINT8 ReservedW; // On Setup
+ UINT8 ReservedX; // On Setup
+ UINT8 ReservedY; // On Setup
+ UINT8 ReservedZ; // On Setup
+ UINT8 ReservedAA; // On Setup
+ UINT8 ReservedAB; // On Setup
+
+ UINT32 ReservedAC[MAX_SOCKET][NUM_DEVHIDE_UNCORE_STACKS][NUM_DEVHIDE_REGS_PER_STACK];
+ UINT32 ReservedAD[MAX_SOCKET][NUM_DEVHIDE_IIO_STACKS][NUM_DEVHIDE_REGS_PER_STACK];
+
+ UINT8 ReservedAE[MAX_TOTAL_PORTS]; // On Setup
+
+ UINT8 ReservedAF[MAX_TOTAL_PORTS];
+ UINT8 ReservedAG[MAX_TOTAL_PORTS]; // On Setup
+ BOOLEAN ReservedAH; // On Setup
+
+
+/**
+==================================================================================================
+====================== IIO Global Performance Tuner Related Setup Options =====================
+==================================================================================================
+**/
+ UINT8 PerformanceTuningMode;
+
+/**
+=================================================================================================
+====================== PCI-E Data Link Feature Exchange Enable ===============================
+==================================================================================================
+**/
+ UINT8 PcieDataLinkFeatureExchangeEnable[MAX_TOTAL_PORTS]; //On Setup
+
+/**
+==================================================================================================
+====================== IIO Trace Hub struct for setup options =================================
+==================================================================================================
+**/
+ TRACE_HUB_CONFIG CpuTraceHubConfig[MAX_SOCKET][NUMBER_TRACE_HUB_PER_SOCKET];
+
+ UINT8 SLOTIMP[MAX_TOTAL_PORTS];
+ UINT8 SLOTSPLS[MAX_TOTAL_PORTS];
+ UINT8 SLOTSPLV[MAX_TOTAL_PORTS];
+ UINT16 SLOTPSP[MAX_TOTAL_PORTS];
+ UINT8 ConfigIOU[MAX_SOCKET][MAX_IOU_PER_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4)
+
+ UINT8 EOI[MAX_TOTAL_PORTS];
+ UINT8 MSIFATEN[MAX_TOTAL_PORTS];
+ UINT8 MSINFATEN[MAX_TOTAL_PORTS];
+ UINT8 MSICOREN[MAX_TOTAL_PORTS];
+ UINT8 ACPIPMEn[MAX_TOTAL_PORTS];
+ UINT8 DISL0STx[MAX_TOTAL_PORTS];
+ UINT8 P2PRdDis[MAX_TOTAL_PORTS];
+ UINT8 DisPMETOAck[MAX_TOTAL_PORTS];
+ UINT8 ACPIHP[MAX_TOTAL_PORTS];
+ UINT8 ACPIPM[MAX_TOTAL_PORTS];
+ UINT8 SRIS[MAX_TOTAL_PORTS];
+ UINT8 TXEQ[MAX_TOTAL_PORTS];
+ UINT8 EcrcGenEn[MAX_TOTAL_PORTS];
+ UINT8 EcrcChkEn[MAX_TOTAL_PORTS];
+ UINT8 SERRE[MAX_TOTAL_PORTS];
+
+ //
+ // Sierra Peak (SPK)
+ //
+ UINT8 SierraPeakMemBufferSize[MAX_SOCKET]; // on setup
+ IIO_PCIE_CONFIG_DATA IioPcieConfig;
+
+ UINT32 VtdDisabledBitmask[MAX_SOCKET];
+} IIO_CONFIG;
+#pragma pack()
+
+#endif // _IIO_CONFIG_H
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioPlatformData.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioPlatformData.h
new file mode 100644
index 0000000000..088cc471f4
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioPlatformData.h
@@ -0,0 +1,204 @@
+/** @file
+ This file provides required platform data structure for IOH.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IIO_PLATFORM_DATA_H_
+#define _IIO_PLATFORM_DATA_H_
+
+#include <Upi/KtiSi.h>
+#include <IioRegs.h>
+#include <IioConfig.h>
+
+typedef enum {
+ DmiTypeVc0,
+ DmiTypeVc1,
+ DmiTypeVcm,
+ MaxDmiVcType
+} DMI_VC_TYPE;
+
+typedef enum {
+ DmiTypeTc0,
+ DmiTypeTc1,
+ DmiTypeTc2,
+ DmiTypeTc3,
+ DmiTypeTc4,
+ DmiTypeTc5,
+ DmiTypeTc6,
+ DmiTypeTc7,
+ MaxDmiTcType
+}DMI_TC_TYPE;
+
+#pragma pack(1)
+
+typedef union {
+ struct {
+ UINT32 Value;
+ UINT32 ValueHigh;
+ } Address32bit;
+ UINT64 Address64bit;
+} IIO_PTR_ADDRESS;
+
+/*
+ * Following are the data structure defined to support multiple CBDMA types on a system
+ */
+
+typedef struct {
+ UINT32 NoSnoopSupported : 1;
+ UINT32 RelaxOrderSupported : 1;
+} CB_CONFIG_CAPABILITY;
+
+typedef struct {
+ UINT8 CB_VER;
+ UINT8 BusNo;
+ UINT8 DevNo;
+ UINT8 FunNo;
+ UINT8 MaxNoChannels;
+ CB_CONFIG_CAPABILITY CBConfigCap;
+} CBDMA_CONTROLLER;
+
+typedef struct {
+ CBDMA_CONTROLLER CbDmaDevice;
+} DMA_HOST;
+
+// <<<< end of CBDMA data structures >>>>
+
+typedef struct {
+ UINT8 LinkWidth;
+ UINT8 LinkSpeed;
+} IIO_DMI_DATA;
+
+typedef struct {
+ UINT8 SystemRasType;
+ BOOLEAN IsocEnable;
+ UINT8 EVMode;
+ UINT32 meRequestedSize;
+ UINT32 ieRequestedSize;
+ UINT8 DmiVc[MaxDmiVcType];
+ UINT8 DmiVcId[MaxDmiVcType];
+ UINT8 DmiTc[MaxDmiTcType];
+ UINT8 PlatformType;
+ UINT8 IOxAPICCallbackBootEvent;
+ UINT8 RasOperation;
+ UINT8 SocketUnderOnline;
+ UINT8 CompletedReadyToBootEventServices;
+ UINT8 SocketPresent[MaxIIO];
+ UINT8 SocketBaseBusNumber[MaxIIO];
+ UINT8 SocketLimitBusNumber[MaxIIO];
+ UINT32 StackPresentBitmap[MaxIIO];
+ UINT64_STRUCT SegMmcfgBase[MaxIIO];
+ UINT8 SegmentSocket[MaxIIO];
+ UINT8 SocketStackPersonality[MaxIIO][MAX_IIO_STACK];
+ UINT8 SocketStackBus[MaxIIO][MAX_IIO_STACK];
+ UINT8 SocketStackBaseBusNumber[MaxIIO][MAX_IIO_STACK];
+ UINT8 SocketStackLimitBusNumber[MaxIIO][MAX_IIO_STACK];
+ UINT32 SocketStackMmiolBase[MaxIIO][MAX_IIO_STACK];
+ UINT32 SocketStackMmiolLimit[MaxIIO][MAX_IIO_STACK];
+ UINT8 SocketPortBusNumber[MaxIIO][NUMBER_PORTS_PER_SOCKET];
+ UINT8 StackPerPort[MaxIIO][NUMBER_PORTS_PER_SOCKET];
+ UINT8 SocketUncoreBusNumber[MaxIIO][MAX_UNCORE_STACK]; // 10nm only
+ UINT32 PchIoApicBase;
+ UINT32 PciResourceMem32Base[MaxIIO];
+ UINT32 PciResourceMem32Limit[MaxIIO];
+ UINT8 Pci64BitResourceAllocation;
+ UINT32 StackPciResourceMem32Limit[MaxIIO][MAX_IIO_STACK];
+ UINT32 VtdBarAddress[MaxIIO][MAX_IIO_STACK];
+ UINT32 IoApicBase[MaxIIO][MAX_IIO_STACK];
+ UINT32 RcBaseAddress;
+ UINT64 PciExpressBase;
+ UINT32 PmBase[MaxIIO];
+ UINT32 PchSegRegBaseAddress[MaxIIO];
+ UINT8 PcieRiser1Type;
+ UINT8 PcieRiser2Type;
+ UINT8 DmiVc1;
+ UINT8 DmiVcm;
+ UINT8 Emulation;
+ UINT8 SkuPersonality[MAX_SOCKET];
+ UINT8 StackPersonality[MaxIIO][MAX_IIO_STACK];
+ UINT8 StackId[MaxIIO][MAX_IIO_STACK];
+ UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK];
+ UINT8 IODC;
+ UINT8 MultiPch;
+ UINT8 FpgaActive[MaxIIO];
+ UINT32 TraceHubMemBase;
+ UINT8 DmiSocketMap;
+ IIO_DMI_DATA DmiSocketData[MAX_SOCKET];
+ UINT64 PciTrainingStartTime; // time in microseconds
+} IIO_V_DATA;
+
+typedef struct {
+ UINT8 Device;
+ UINT8 Function;
+} IIO_PORT_INFO;
+
+typedef struct {
+ UINT8 Valid;
+ UINT8 IioUplinkPortIndex; //defines platform specific uplink port index (if any else FF)
+ IIO_PORT_INFO UplinkPortInfo;
+} IIO_UPLINK_PORT_INFO;
+
+typedef struct _INTEL_IIO_PORT_INFO {
+ UINT8 Device;
+ UINT8 Function;
+ UINT8 Reserved137;
+ UINT8 Reserved138;
+ UINT8 Reserved139;
+ UINT8 Reserved140;
+ UINT8 Reserved141;
+ UINT8 SuperClusterPort;
+ UINT8 NtbDevice;
+ UINT8 NtbFunction;
+} INTEL_IIO_PORT_INFO;
+
+typedef struct _INTEL_DMI_PCIE_INFO {
+ INTEL_IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET];
+} INTEL_DMI_PCIE_INFO;
+
+typedef struct _INTEL_IIO_PRELINK_DATA {
+ INTEL_DMI_PCIE_INFO PcieInfo;
+ IIO_UPLINK_PORT_INFO UplinkInfo[MaxIIO];
+} INTEL_IIO_PRELINK_DATA;
+
+typedef struct {
+ UINT8 PciePortPresent[MaxIIO*NUMBER_PORTS_PER_SOCKET];
+ UINT8 PciePortConfig[MaxIIO*NUMBER_PORTS_PER_SOCKET];
+ UINT8 PciePortOwnership[MaxIIO*NUMBER_PORTS_PER_SOCKET];
+ UINT8 CurrentPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET];
+ UINT8 MaxPXPMap[MaxIIO * NUMBER_PORTS_PER_SOCKET]; // Max link width
+ BOOLEAN LaneReversedPXPMap[MaxIIO][MAX_IOU_PER_SOCKET];
+ UINT8 PciePortMaxWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET];
+ UINT8 PciePortNegWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET];
+ UINT8 PciePortNegSpeed[MaxIIO*NUMBER_PORTS_PER_SOCKET];
+ UINT8 RetimerConnectCount[MaxIIO*NUMBER_PORTS_PER_SOCKET];
+ IIO_PTR_ADDRESS PtrAddress;
+ IIO_PTR_ADDRESS PtrPcieTopology;
+ UINT64 McastRsvdMemory;
+ DMA_HOST DMAhost[MaxIIO];
+ UINT8 resetRequired;
+ UINT8 MaxPciePortNumberPerSocket[MaxIIO];
+
+ //
+ // IsSocketSmbEnabled and TimeoutOnVppOccured are needed only as a WA for SMB issue in socket
+ //
+ BOOLEAN IsSocketSmbEnabled[MaxIIO]; // contains TRUE if socket smb controller was enabled for given IIO (socket)
+ BOOLEAN TimeoutOnVppOccurred[MaxIIO]; // contains TRUE if there was a timeout after VPP programming
+} IIO_OUT_DATA;
+
+typedef struct {
+ IIO_V_DATA IioVData;
+ INTEL_IIO_PRELINK_DATA PreLinkData;
+ IIO_OUT_DATA IioOutData;
+} IIO_VAR;
+
+typedef struct {
+ IIO_CONFIG SetupData;
+ IIO_VAR IioVar;
+} IIO_GLOBALS;
+
+#pragma pack()
+
+#endif //_IIO_PLATFORM_DATA_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
new file mode 100644
index 0000000000..98f759be81
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
@@ -0,0 +1,179 @@
+/** @file
+
+ @copyright
+ Copyright 2010 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IIO_REGS_H_
+#define _IIO_REGS_H_
+
+#include <IioSetupDefinitions.h>
+
+/**
+==================================================================================================
+================================== General Definitions ==================================
+==================================================================================================
+**/
+//-----------------------------------------------------------------------------------
+// PCIE port index for SKX
+//------------------------------------------------------------------------------------
+#define SOCKET_0_INDEX 0
+#define SOCKET_1_INDEX 21
+#define SOCKET_2_INDEX 42
+#define SOCKET_3_INDEX 63
+#define SOCKET_4_INDEX 84
+#define SOCKET_5_INDEX 105
+#define SOCKET_6_INDEX 126
+#define SOCKET_7_INDEX 147
+
+//-----------------------------------------------------------------------------------
+// Number's ports per stack definitions for 10nm
+//------------------------------------------------------------------------------------
+
+// STACK0 for: ICX-SP
+#define NUMBER_PORTS_PER_STACK0_10NM 1
+
+// NON-STACK0 for: ICX-SP
+#define NUMBER_PORTS_PER_NON_STACK0_10NM 4
+
+#define MAX_UNCORE_STACK 2 // MAX_LOGIC_IIO_STACK - MAX_IIO_STACK
+
+#define MaxIIO MAX_SOCKET
+
+#define TOTAL_CB3_DEVICES 64 // IOAT_TOTAL_FUNCS * MAX_SOCKET. Note: this covers up to 8S.
+#define MAX_TOTAL_PORTS (MAX_SOCKET * NUMBER_PORTS_PER_SOCKET) //NUMBER_PORTS_PER_SOCKET * MaxIIO. As now, treats setup S0-S3 = S4_S7 as optimal
+
+ #define NUM_IAX 1 //number of IAX per Socket
+ #define NUM_DSA 1 //number of DSA per Socket
+ #define NUM_CPM 1 //number of CPM per Socket
+ #define NUM_HQM 1 //number of HQM per Socket
+
+#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. Not reflect architecture but only sysHost structure!
+
+#define NUMBER_NTB_PORTS_PER_SOCKET 5
+
+#ifndef MAX_STACKS_PER_SOCKET
+ #define MAX_STACKS_PER_SOCKET 6
+ #define MAX_IIO_PORTS_PER_STACK NUMBER_PORTS_PER_NON_STACK0_10NM
+#endif
+
+#define MAX_IOU_PER_SOCKET 5 // Max IOU number per socket for all silicon generation, SKX, ICX
+
+#define MAX_VMD_ROOTPORTS_PER_PCH 20 // Max number of rootports in PCH
+#define MAX_VMD_STACKS_PER_SOCKET 6 // Max number of stacks per socket supported by VMD
+
+#define MAX_RETIMERS_PER_STACK 2 // Max number of retimers per pcie controller (ICX-SP)
+
+#ifndef NELEMENTS
+#define NELEMENTS(Array) (sizeof(Array)/sizeof((Array)[0]))
+#endif
+
+
+/**
+==================================================================================================
+================================== IIO Root Port Definitions ====================
+==================================================================================================
+**/
+// Max BDFs definitions
+#define MAX_FUNC_NUM 8
+#define MAX_DEV_NUM 32
+#define MAX_BUS_NUM 256
+
+#define PORT_0_INDEX 0
+#define PORT_A_INDEX 1
+#define PORT_B_INDEX 2
+#define PORT_C_INDEX 3
+#define PORT_D_INDEX 4
+#define PORT_E_INDEX 5
+#define PORT_F_INDEX 6
+#define PORT_G_INDEX 7
+#define PORT_H_INDEX 8
+
+//-----------------------------------------------------------------------------------
+// Port Index definition for SKX
+//------------------------------------------------------------------------------------
+#define PCIE_PORT_2_DEV 0x02
+// IOU0
+#define PORT_1A_INDEX 1
+#define PORT_1B_INDEX 2
+#define PORT_1C_INDEX 3
+#define PORT_1D_INDEX 4
+// IOU1
+#define PORT_2A_INDEX 5
+#define PORT_2B_INDEX 6
+#define PORT_2C_INDEX 7
+#define PORT_2D_INDEX 8
+// IOU2
+#define PORT_3A_INDEX 9
+#define PORT_3B_INDEX 10
+#define PORT_3C_INDEX 11
+#define PORT_3D_INDEX 12
+//MCP0
+#define PORT_4A_INDEX 13
+#define PORT_4B_INDEX 14
+#define PORT_4C_INDEX 15
+#define PORT_4D_INDEX 16
+//MCP1
+#define PORT_5A_INDEX 17
+#define PORT_5B_INDEX 18
+#define PORT_5C_INDEX 19
+#define PORT_5D_INDEX 20
+
+//-----------------------------------------------------------------------------------
+// Port Index definition for ICX-SP
+//------------------------------------------------------------------------------------
+
+// IOU0
+#define PORT_1A_INDEX_1 1
+#define PORT_1B_INDEX_1 2
+#define PORT_1C_INDEX_1 3
+#define PORT_1D_INDEX_1 4
+// IOU1
+#define PORT_2A_INDEX_2 5
+#define PORT_2B_INDEX_2 6
+#define PORT_2C_INDEX_2 7
+#define PORT_2D_INDEX_2 8
+// IOU2
+#define PORT_3A_INDEX_3 9
+#define PORT_3B_INDEX_3 10
+#define PORT_3C_INDEX_3 11
+#define PORT_3D_INDEX_3 12
+// IOU3
+#define PORT_4A_INDEX_4 13
+#define PORT_4B_INDEX_4 14
+#define PORT_4C_INDEX_4 15
+#define PORT_4D_INDEX_4 16
+// IOU4
+#define PORT_5A_INDEX_5 17
+#define PORT_5B_INDEX_5 18
+#define PORT_5C_INDEX_5 19
+#define PORT_5D_INDEX_5 20
+
+//
+// Port Config Mode
+//
+#define REGULAR_PCIE_OWNERSHIP 0
+#define VMD_OWNERSHIP 3
+#define PCIEAIC_OCL_OWNERSHIP 4
+
+#define NUMBER_TRACE_HUB_PER_SOCKET 1
+
+//
+// 8 stacks per each socket:
+// - 6 IIO stacks (used only on 14nm systems - 10nm doesn't hide per-IP)
+// - 2 uncore stacks (used only for 10nm systems - 14nm doesn't have such stacks)
+//
+#define NUM_DEVHIDE_REGS_PER_STACK 8 // devHide 32-bit register for each function on stack
+#define NUM_DEVHIDE_UNCORE_STACKS 2 // number of uncore stacks in setup structure
+#define NUM_DEVHIDE_IIO_STACKS 6 // number of IIO stacks ins etup structure
+
+#if MaxIIO > 4
+#define MAX_DEVHIDE_REGS_PER_SYSTEM 512 // MAX_DEVHIDE_REGS_PER_SOCKET * MaxIIO
+#else
+#define MAX_DEVHIDE_REGS_PER_SYSTEM 256 // MAX_DEVHIDE_REGS_PER_SOCKET * MaxIIO
+#endif
+
+#endif //_IIO_REGS_H_
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h
new file mode 100644
index 0000000000..55496e60d4
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h
@@ -0,0 +1,60 @@
+/** @file
+ Definitions shared with HFR/VFR files.
+
+ @copyright
+ Copyright 2006 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IIOSETUPDEFINITIONS_H_
+#define _IIOSETUPDEFINITIONS_H_
+
+//-----------------------------------------------------------------------------------
+// Number of ports per socket for CPUs
+//------------------------------------------------------------------------------------
+#define NUMBER_PORTS_PER_SOCKET_ICX 21
+#define NUMBER_PORTS_PER_SOCKET_SKX 21
+#define NUMBER_PORTS_PER_SOCKET_CPX 13
+
+//-----------------------------------------------------------------------------------
+// General NUMBER_PORTS_PER_SOCKET definition
+//------------------------------------------------------------------------------------
+#define NUMBER_PORTS_PER_SOCKET NUMBER_PORTS_PER_SOCKET_SKX
+
+/**
+==================================================================================================
+================= Equates common for Setup options (.vfr/.hfr) and source files (.c/.h) ==========
+==================================================================================================
+**/
+
+#define IIO_BIFURCATE_xxxxxxxx 0xFE
+#define IIO_BIFURCATE_x4x4x4x4 0x0
+#define IIO_BIFURCATE_x4x4xxx8 0x1
+#define IIO_BIFURCATE_xxx8x4x4 0x2
+#define IIO_BIFURCATE_xxx8xxx8 0x3
+#define IIO_BIFURCATE_xxxxxx16 0x4
+#define IIO_BIFURCATE_x2x2x4x8 0x5
+#define IIO_BIFURCATE_x4x2x2x8 0x6
+#define IIO_BIFURCATE_x8x2x2x4 0x7
+#define IIO_BIFURCATE_x8x4x2x2 0x8
+#define IIO_BIFURCATE_x2x2x4x4x4 0x9
+#define IIO_BIFURCATE_x4x2x2x4x4 0xA
+#define IIO_BIFURCATE_x4x4x2x2x4 0xB
+#define IIO_BIFURCATE_x4x4x4x2x2 0xC
+#define IIO_BIFURCATE_x2x2x2x2x8 0xD
+#define IIO_BIFURCATE_x8x2x2x2x2 0xE
+#define IIO_BIFURCATE_x2x2x2x2x4x4 0xF
+#define IIO_BIFURCATE_x2x2x4x2x2x4 0x10
+#define IIO_BIFURCATE_x2x2x4x4x2x2 0x11
+#define IIO_BIFURCATE_x4x2x2x2x2x4 0x12
+#define IIO_BIFURCATE_x4x2x2x4x2x2 0x13
+#define IIO_BIFURCATE_x4x4x2x2x2x2 0x14
+#define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15
+#define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16
+#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17
+#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18
+#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19
+#define IIO_BIFURCATE_AUTO 0xFF
+
+#endif /* _IIOSETUPDEFINITIONS_H_ */
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioUniversalData.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioUniversalData.h
new file mode 100644
index 0000000000..32fc4a2978
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioUniversalData.h
@@ -0,0 +1,166 @@
+/** @file
+ Data format for Universal Data Structure
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IIO_UNIVERSAL_DATA_
+#define _IIO_UNIVERSAL_DATA_
+
+#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, { 0xBA, 0x53, 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } }
+#include "SysHost.h"
+#include "IioPlatformData.h"
+#include "UncoreCommonIncludes.h"
+#include <Guid/SocketVariable.h>
+
+//--------------------------------------------------------------------------------------//
+// Structure definitions for Universal Data Store (UDS)
+//--------------------------------------------------------------------------------------//
+#define UINT64 unsigned long long
+
+#pragma pack(1)
+
+
+typedef struct {
+ UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
+ UINT8 PeerSocId; // Socket ID
+ UINT8 PeerSocType; // Socket Type (0 - CPU; 1 - IIO)
+ UINT8 PeerPort; // Port of the peer socket
+}QPI_PEER_DATA;
+
+typedef struct {
+ UINT8 Valid;
+ UINT32 MmioBar[TYPE_MAX_MMIO_BAR];
+ UINT8 PcieSegment;
+ UINT64_STRUCT SegMmcfgBase;
+ UINT16 stackPresentBitmap;
+ UINT16 M2PciePresentBitmap;
+ UINT8 TotM3Kti;
+ UINT8 TotCha;
+ UINT32 ChaList[MAX_CHA_MAP];
+ UINT32 SocId;
+ QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info
+} QPI_CPU_DATA;
+
+typedef struct {
+ UINT8 Valid;
+ UINT8 SocId;
+ QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
+} QPI_IIO_DATA;
+
+typedef struct {
+ IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET];
+} IIO_DMI_PCIE_INFO;
+
+typedef struct _STACK_RES {
+ UINT8 Personality;
+ UINT8 BusBase;
+ UINT8 BusLimit;
+ UINT16 PciResourceIoBase;
+ UINT16 PciResourceIoLimit;
+ UINT32 IoApicBase;
+ UINT32 IoApicLimit;
+ UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map
+ UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map
+ UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map
+ UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map
+ UINT32 PciResourceMem32Base; // Base of low MMIO resource available for PCI devices
+ UINT32 PciResourceMem32Limit; // Limit of low MMIO resource available for PCI devices
+ UINT64 PciResourceMem64Base; // Base of high MMIO resource available for PCI devices
+ UINT64 PciResourceMem64Limit; // Limit of high MMIO resource available for PCI devices
+ UINT32 VtdBarAddress;
+ UINT32 Mmio32MinSize; // Minimum required size of MMIO32 resource needed for this stack
+} STACK_RES;
+
+typedef struct {
+ UINT8 Valid;
+ UINT8 SocketID; // Socket ID of the IIO (0..3)
+ UINT8 BusBase;
+ UINT8 BusLimit;
+ UINT16 PciResourceIoBase;
+ UINT16 PciResourceIoLimit;
+ UINT32 IoApicBase;
+ UINT32 IoApicLimit;
+ UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
+ UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
+ UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
+ UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
+ STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
+ UINT32 RcBaseAddress;
+ IIO_DMI_PCIE_INFO PcieInfo;
+ UINT8 DmaDeviceCount;
+} IIO_RESOURCE_INSTANCE;
+
+typedef struct {
+ UINT16 PlatGlobalIoBase; // Global IO Base
+ UINT16 PlatGlobalIoLimit; // Global IO Limit
+ UINT32 PlatGlobalMmio32Base; // Global Mmiol base
+ UINT32 PlatGlobalMmio32Limit; // Global Mmiol limit
+ UINT64 PlatGlobalMmio64Base; // Global Mmioh Base [43:0]
+ UINT64 PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0]
+ QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
+ QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
+ UINT32 MemTsegSize;
+ UINT32 MemIedSize;
+ UINT64 PciExpressBase;
+ UINT32 PciExpressSize;
+ UINT32 MemTolm;
+ IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET];
+ UINT8 numofIIO;
+ UINT8 MaxBusNumber;
+ UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
+ UINT8 EVMode;
+ UINT8 Pci64BitResourceAllocation;
+ UINT8 SkuPersonality[MAX_SOCKET];
+ UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK];
+ UINT16 IoGranularity;
+ UINT32 MmiolGranularity;
+ UINT64_STRUCT MmiohGranularity;
+ UINT8 RemoteRequestThreshold; //5370389
+ UINT32 UboxMmioSize;
+ UINT32 MaxAddressBits;
+} PLATFORM_DATA;
+
+typedef struct {
+ UINT8 CurrentUpiiLinkSpeed;// Current programmed UPI Link speed (Slow/Full speed mode)
+ UINT8 CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT)
+ UINT8 OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC
+ UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
+ UINT8 IsocEnable;
+ UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
+ UINT32 ieRequestedSize; // Size of the memory range requested by IE FW, in MB
+ UINT8 DmiVc1;
+ UINT8 DmiVcm;
+ UINT32 CpuPCPSInfo;
+ UINT8 cpuSubType;
+ UINT8 SystemRasType;
+ UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
+ UINT16 tolmLimit;
+ UINT32 tohmLimit;
+ RC_VERSION RcVersion;
+ BOOLEAN MsrTraceEnable;
+ UINT8 DdrXoverMode; // DDR 2.2 Mode
+ // For RAS
+ UINT8 bootMode;
+ UINT8 OutClusterOnDieEn; // Whether RC enabled COD support
+ UINT8 OutSncEn;
+ UINT8 OutNumOfCluster;
+ UINT8 imcEnabled[MAX_SOCKET][MAX_IMC];
+ UINT16 LlcSizeReg;
+ UINT8 chEnabled[MAX_SOCKET][MAX_CH];
+ UINT8 memNode[MC_MAX_NODE];
+ UINT8 IoDcMode;
+ UINT8 ReservedBC;
+} SYSTEM_STATUS;
+
+typedef struct {
+ PLATFORM_DATA PlatformData;
+ SYSTEM_STATUS SystemStatus;
+ UINT32 OemValue;
+} IIO_UDS;
+#pragma pack()
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/ImonVrSvid.h b/Silicon/Intel/WhitleySiliconPkg/Include/ImonVrSvid.h
new file mode 100644
index 0000000000..75b73113ac
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/ImonVrSvid.h
@@ -0,0 +1,26 @@
+/** @file
+
+ ImonVrSvid.h
+
+ API Header for IMON VR PCD Structure
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IMON_VR_SVID_H_
+#define _IMON_VR_SVID_H_
+
+//Maximum IMON COUNT
+#define MAX_IMON_COUNT 16
+
+//End of List
+#define IMON_ADDR_LIST_END 0xFF
+
+typedef struct {
+ UINT8 VrSvid[MAX_IMON_COUNT];
+} VCC_IMON;
+
+#endif //_IMON_VR_SVID_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/KtiSetupDefinitions.h b/Silicon/Intel/WhitleySiliconPkg/Include/KtiSetupDefinitions.h
new file mode 100644
index 0000000000..bea4f72ce9
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/KtiSetupDefinitions.h
@@ -0,0 +1,22 @@
+/** @file
+
+ @copyright
+ Copyright 2006 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _kti_setup_definitions_h
+#define _kti_setup_definitions_h
+
+//
+// Link speed
+//
+//
+// ICX KTI Speed options
+//
+#define SPEED_REC_96GT 0
+#define SPEED_REC_104GT 1
+#define SPEED_REC_112GT 2
+
+#endif // _kti_setup_definitions_h
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/CompressedVariableLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/CompressedVariableLib.h
new file mode 100644
index 0000000000..0a212840e4
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/CompressedVariableLib.h
@@ -0,0 +1,35 @@
+/** @file
+ Interface header file for the Compressed Variable library class.
+
+ @copyright
+ Copyright 2020 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _COMPRESSED_VARIABLE_LIB_H_
+#define _COMPRESSED_VARIABLE_LIB_H_
+
+#include <Uefi.h>
+
+/**
+ Retrieve data from a HOB(s), then compress and save the data.
+
+ @param[in] HobGuid GUID of the HOB to save.
+ @param[in] VariableName Name of the variable to save as.
+ @param[in] VariableGuid GUID of the variable to save as.
+
+ @retval EFI_SUCCESS The variable was saved successfully.
+ @retval !EFI_SUCCESS Failure.
+
+**/
+
+EFI_STATUS
+EFIAPI
+SaveVariableFromHob (
+ IN EFI_GUID HobGuid,
+ IN CHAR16 *VariableName,
+ IN EFI_GUID VariableGuid
+ );
+
+#endif // #ifndef _COMPRESSED_VARIABLE_LIB_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/EmulationConfigurationLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EmulationConfigurationLib.h
new file mode 100644
index 0000000000..be12385348
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EmulationConfigurationLib.h
@@ -0,0 +1,34 @@
+/** @file
+
+ @copyright
+ Copyright 2017 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _EMULATION_CONFIGURATION_LIB_H_
+#define _EMULATION_CONFIGURATION_LIB_H_
+
+#include <Uefi.h>
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 UbiosGenerationSetting; // indicate if uBIOS generation is enable or not in setup menu
+ UINT8 HybridSystemLevelEmulationSetting; // indicate if HSLE is enable or not in setup menu
+ UINT8 UbiosOutputMode; // indicate if we should output register writes to the serial port
+ UINT32 LoopBackLabelNumber; // used to create ASM reads for emulation
+ UINT8 FnvAccessValue; // indicate if FNV access enable or not
+ UINT8 MsrTraceEnable; // indicate if Mrs Trace is enable or not in setup menu
+ UINT8 MsrTraceOutputMode; // indicate if Mrs Trace Asm Output Mode
+} EMULATION_SETTING;
+
+#pragma pack()
+
+#define ASM_OUTPUT_ENABLE BIT0 // flag to indicate ASM output is enabled
+
+#define FNV_ACCESS_DISABLE 0 // flag to indicate FNV access is disabled
+
+#define MSR_OUTPUT_DISABLE 0 // flag to indicate Mrs Trace Asm Output is disabled
+
+#endif // _EMULATION_CONFIGURATION_LIB_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/MemTypeLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/MemTypeLib.h
new file mode 100644
index 0000000000..d5cf1c01d0
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/MemTypeLib.h
@@ -0,0 +1,32 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _MEMTYPELIB_H_
+#define _MEMTYPELIB_H_
+
+typedef enum {
+ MemTypeNone = 0,
+ MemType1lmDdr,
+ MemType1lmAppDirect,
+ MemType1lmAppDirectReserved,
+ MemType1lmCtrl,
+ MemType1lmHbm,
+ MemTypeNxm,
+ MemType2lmDdrCacheMemoryMode,
+ MemType2lmDdrWbCacheAppDirect,
+ MemType2lmHbmCacheDdr,
+ MemType2lmHbmCacheMemoryMode,
+ MemTypeCxlAccVolatileMem,
+ MemTypeCxlAccPersistentMem,
+ MemTypeFpga,
+ MemTypeCxlExpVolatileMem,
+ MemTypeCxlExpPersistentMem,
+ MemTypeMax
+} MEM_TYPE;
+
+#endif // _MEMTYPELIB_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/MemVrSvidMapLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/MemVrSvidMapLib.h
new file mode 100644
index 0000000000..8eae5c64df
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/MemVrSvidMapLib.h
@@ -0,0 +1,66 @@
+/** @file
+
+ MemVrSvidMapLib.h
+
+ API Header for VrSvid Mapping
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _MEM_VR_SVID_MAP_LIB_H_
+#define _MEM_VR_SVID_MAP_LIB_H_
+
+#define MAX_SVID_MC 16
+#define MAX_SVID_SOCKET 16
+
+typedef struct {
+ UINT8 Mc[MAX_SVID_MC]; // Store SVID for Socket\MC Pair
+} SVID_SOCKET;
+
+typedef struct {
+ SVID_SOCKET Socket[MAX_SVID_SOCKET];
+} MEM_SVID_MAP;
+
+
+/**
+ Get SVID Mapping from Socket and MCID
+
+ @param[in] Socket - Socket Id - 0 based
+ @param[in] McId - Memory controller 0 based
+ @param[in] SvidValue - SVID Value
+
+ @retval EFI_SUCCESS - Value found
+ @retval EFI_NOT_FOUND - Value not found
+
+**/
+EFI_STATUS
+EFIAPI
+GetSvidMap (
+ IN UINT8 Socket,
+ IN UINT8 McId,
+ IN UINT8 *SvidValue
+ );
+
+/**
+ Set SVID Mapping for given Socket and MCID
+
+ @param[in] Socket - Socket Id - 0 based
+ @param[in] McId - Memory controller 0 based
+ @param[in] SvidValue - SVID Value
+
+ @retval EFI_SUCCESS - Value set successfully
+ @retval EFI_NOT_FOUND - Value not set
+
+**/
+EFI_STATUS
+EFIAPI
+SetSvidMap (
+ IN UINT8 Socket,
+ IN UINT8 McId,
+ IN UINT8 SvidValue
+ );
+
+#endif //_MEM_VR_SVID_MAP_LIB_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/PchInfoLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/PchInfoLib.h
new file mode 100644
index 0000000000..adda16bdc2
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/PchInfoLib.h
@@ -0,0 +1,22 @@
+/** @file
+ Header file for PchInfoLib.
+
+ @copyright
+ Copyright 2014 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_INFO_LIB_H_
+#define _PCH_INFO_LIB_H_
+
+#include <PchAccess.h>
+
+typedef enum {
+ PchH = 1,
+ PchLp,
+ PchMini,
+ PchUnknownSeries
+} PCH_SERIES;
+
+#endif // _PCH_INFO_LIB_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/PlatformHooksLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/PlatformHooksLib.h
new file mode 100644
index 0000000000..1f31ffed74
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/PlatformHooksLib.h
@@ -0,0 +1,17 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+UINT32
+IsSioExist (
+ VOID
+ );
+
+VOID
+InitializeSio (
+ VOID
+ );
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/SemaphoreLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/SemaphoreLib.h
new file mode 100644
index 0000000000..0287e98b4d
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/SemaphoreLib.h
@@ -0,0 +1,326 @@
+/** @file
+ The Semaphore Library API provides the necessary functions to acquire/release
+ the global or a socket's semaphore.
+
+ This API is designed to allow a calling agent to acquire a global (the SBSP)
+ semaphore or a socket's semaphore. It also provides functionality to release
+ the semaphore and check if ownership has been obtained. If a semaphore is
+ desired, an agent should first attempt to acquire it, then check if it has
+ ownership. If ownership has not been obtained, the agent must wait until
+ ownership has been obtained before proceeding. Once the desired task is complete
+ the semaphore must be released. Semaphores should be used for when ensuring
+ exclusive access to resoruces among CPU sockets is necessary.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SEMAPHORE_LIB_H_
+#define _SEMAPHORE_LIB_H_
+
+#include <Uefi.h>
+
+///
+/// Used to identify which System Sempahore is being accessed. There are
+/// currently two System Semaphores available for use (0 and 1).
+///
+typedef enum {
+ SystemSemaphore0, ///< Semaphore 0 - Used for SPD/SMBus access
+ SystemSemaphore1, ///< Semaphore 1 - Used for Debug print
+ SystemSemaphoreMax
+} SYSTEM_SEMAPHORE_NUMBER;
+
+///
+/// Used to identify which Local Sempahore is being accessed. There are
+/// currently two Local Semaphores available for use (0 and 1).
+///
+typedef enum {
+ LocalSemaphore0,
+ LocalSemaphore1,
+ LocalSemaphoreMax
+} LOCAL_SEMAPHORE_NUMBER;
+
+#define DO_NOT_ADD_TO_QUEUE FALSE
+#define ADD_TO_QUEUE TRUE
+
+/**
+ Acquire a global (BSP) semaphore for the calling socket.
+
+ Used for ensuring exclusive access to resources among CPU sockets.
+
+ IMPORTANT:
+ The functions must be called in the sequence below:
+ ......
+ Owned = AcquireGlobalSemaphore (SystemSemaphore0, ADD_TO_QUEUE, &QNum);
+ while (!Owned) {
+ Owned = IsGlobalSemaphoreOwned (SystemSemaphore0, QNum));
+ }
+ DoSomething ();
+ ReleaseGlobalSemaphore (SystemSemaphore0);
+ ......
+
+ @param[in] SemaphoreNumber - SYSTEMSEMAPHORE register number (0 or 1)
+ @param[in] AddToQueue - specifices whether to add the requesting
+ socket to the queue (TRUE or FALSE)
+ @param[out] QueueNumber - assigned place in line of semaphore request,
+ if adding to queue
+
+ @retval TRUE - successfully acquired semaphore
+ @retval FALSE - semaphore not acquired
+**/
+BOOLEAN
+EFIAPI
+AcquireGlobalSemaphore (
+ IN SYSTEM_SEMAPHORE_NUMBER SemaphoreNumber,
+ IN BOOLEAN AddToQueue,
+ OUT UINT32 *QueueNumber OPTIONAL
+ );
+
+/**
+ Checks if a global (BSP) semaphore is owned by the calling socket.
+
+ Used for ensuring exclusive access to resources among CPU sockets.
+
+ IMPORTANT:
+ The functions must be called in the sequence below:
+ ......
+ Owned = AcquireGlobalSemaphore (SystemSemaphore0, ADD_TO_QUEUE, &QNum);
+ while (!Owned) {
+ Owned = IsGlobalSemaphoreOwned (SystemSemaphore0, QNum));
+ }
+ DoSomething ();
+ ReleaseGlobalSemaphore (SystemSemaphore0);
+ ......
+
+ @param[in] SemaphoreNumber - SYSTEMSEMAPHORE register number (0 or 1)
+ @param[in] QueueNumber - assigned place in line of semaphore request
+ that was returned by AcquireGlobalSemaphore
+
+ @retval TRUE - successfully acquired semaphore
+ @retval FALSE - semaphore not acquired
+**/
+BOOLEAN
+EFIAPI
+IsGlobalSemaphoreOwned (
+ IN SYSTEM_SEMAPHORE_NUMBER SemaphoreNumber,
+ IN UINT32 QueueNumber
+ );
+
+/**
+ Release a global (BSP) semaphore owned by the calling socket.
+
+ Used for ensuring exclusive access to resources among CPU sockets.
+
+ IMPORTANT:
+ The functions must be called in the sequence below:
+ ......
+ Owned = AcquireGlobalSemaphore (SystemSemaphore0, ADD_TO_QUEUE, &QNum);
+ while (!Owned) {
+ Owned = IsGlobalSemaphoreOwned (SystemSemaphore0, QNum));
+ }
+ DoSomething ();
+ ReleaseGlobalSemaphore (SystemSemaphore0);
+ ......
+
+ @param[in] SemaphoreNumber - SYSTEMSEMAPHORE register number (0 or 1)
+
+ @retval EFI_SUCCESS - successfully released semaphore
+ @retval EFI_DEVICE_ERROR - error releasing semaphore
+**/
+EFI_STATUS
+EFIAPI
+ReleaseGlobalSemaphore (
+ IN SYSTEM_SEMAPHORE_NUMBER SemaphoreNumber
+ );
+
+
+/**
+ Acquire a socket semaphore for the calling socket.
+
+ Used for ensuring exclusive access to resources among CPU sockets.
+
+ IMPORTANT:
+ The functions must be called in the sequence below:
+ ......
+ Owned = AcquireSocketSemaphore (Socket, SystemSemaphore0, ADD_TO_QUEUE, &QNum);
+ while (!Owned) {
+ Owned = IsSocketSemaphoreOwned (Socket, SystemSemaphore0, QNum));
+ }
+ DoSomething ();
+ ReleaseSocketSemaphore (Socket, SystemSemaphore0);
+ ......
+
+ @param[in] Socket - Socket where the semaphore is located
+ @param[in] SemaphoreNumber - SYSTEMSEMAPHORE register number (0 or 1)
+ @param[in] AddToQueue - specifices whether to add the requesting
+ socket to the queue (TRUE or FALSE)
+ @param[out] QueueNumber - assigned place in line of semaphore request,
+ if adding to queue
+
+ @retval TRUE - successfully acquired semaphore
+ @retval FALSE - semaphore not acquired
+**/
+BOOLEAN
+EFIAPI
+AcquireSocketSemaphore (
+ IN UINT8 Socket,
+ IN SYSTEM_SEMAPHORE_NUMBER SemaphoreNumber,
+ IN BOOLEAN AddToQueue,
+ OUT UINT32 *QueueNumber OPTIONAL
+ );
+
+/**
+ Checks if a socket semaphore is owned by the calling socket.
+
+ Used for ensuring exclusive access to resources among CPU sockets.
+
+ IMPORTANT:
+ The functions must be called in the sequence below:
+ ......
+ Owned = AcquireSocketSemaphore (Socket, SystemSemaphore0, ADD_TO_QUEUE, &QNum);
+ while (!Owned) {
+ Owned = IsSocketSemaphoreOwned (Socket, SystemSemaphore0, QNum));
+ }
+ DoSomething ();
+ ReleaseSocketSemaphore (Socket, SystemSemaphore0);
+ ......
+
+ @param[in] Socket - Socket where the semaphore is located
+ @param[in] SemaphoreNumber - SYSTEMSEMAPHORE register number (0 or 1)
+ @param[in] QueueNumber - assigned place in line of semaphore request
+ that was returned by AcquireSocketSemaphore
+
+ @retval TRUE - successfully acquired semaphore
+ @retval FALSE - semaphore not acquired
+**/
+BOOLEAN
+EFIAPI
+IsSocketSemaphoreOwned (
+ IN UINT8 Socket,
+ IN SYSTEM_SEMAPHORE_NUMBER SemaphoreNumber,
+ IN UINT32 QueueNumber
+ );
+
+/**
+ Release a socket semaphore owned by the calling socket.
+
+ Used for ensuring exclusive access to resources among CPU sockets.
+
+ IMPORTANT:
+ The functions must be called in the sequence below:
+ ......
+ Owned = AcquireSocketSemaphore (Socket, SystemSemaphore0, ADD_TO_QUEUE, &QNum);
+ while (!Owned) {
+ Owned = IsSocketSemaphoreOwned (Socket, SystemSemaphore0, QNum));
+ }
+ DoSomething ();
+ ReleaseSocketSemaphore (Socket, SystemSemaphore0);
+ ......
+
+ @param[in] Socket - Socket to release semaphore
+ @param[in] SemaphoreNumber - SYSTEMSEMAPHORE register number (0 or 1)
+
+ @retval EFI_SUCCESS - successfully released semaphore
+ @retval EFI_DEVICE_ERROR - error releasing semaphore
+**/
+EFI_STATUS
+EFIAPI
+ReleaseSocketSemaphore (
+ IN UINT8 Socket,
+ IN SYSTEM_SEMAPHORE_NUMBER SemaphoreNumber
+ );
+
+/**
+ Acquire a local semaphore for the calling thread.
+
+ Used for ensuring exclusive access to resources among CPU threads.
+
+ IMPORTANT:
+ The functions must be called in the sequence below:
+ ......
+ Owned = AcquireLocalSemaphore (LocalSemaphore0, ADD_TO_QUEUE, &QNum);
+ while (!Owned) {
+ Owned = IsLocalSemaphoreOwned (LocalSemaphore0, QNum));
+ }
+ DoSomething ();
+ ReleaseLocalSemaphore (LocalSemaphore0);
+ ......
+
+ @param[in] SemaphoreNumber - LOCALSEMAPHORE register number (0 or 1)
+ @param[in] AddToQueue - specifices whether to add the requesting
+ thread to the queue (TRUE or FALSE)
+ @param[out] QueueNumber - assigned place in line of semaphore request,
+ if adding to queue
+
+ @retval TRUE - successfully acquired semaphore
+ @retval FALSE - semaphore not acquired
+**/
+BOOLEAN
+EFIAPI
+AcquireLocalSemaphore (
+ IN LOCAL_SEMAPHORE_NUMBER SemaphoreNumber,
+ IN BOOLEAN AddToQueue,
+ OUT UINT32 *QueueNumber OPTIONAL
+ );
+
+/**
+ Checks if a local semaphore is owned by the calling thread.
+
+ Used for ensuring exclusive access to resources among CPU threads.
+
+ IMPORTANT:
+ The functions must be called in the sequence below:
+ ......
+ Owned = AcquireLocalSemaphore (LocalSemaphore0, ADD_TO_QUEUE, &QNum);
+ while (!Owned) {
+ Owned = IsLocalSemaphoreOwned (LocalSemaphore0, QNum));
+ }
+ DoSomething ();
+ ReleaseLocalSemaphore (LocalSemaphore0);
+ ......
+
+ @param[in] SemaphoreNumber - LOCALSEMAPHORE register number (0 or 1)
+ @param[in] QueueNumber - assigned place in line of semaphore request
+ that was returned by AcquireLocalSemaphore
+
+ @retval TRUE - successfully acquired semaphore
+ @retval FALSE - semaphore not acquired
+**/
+BOOLEAN
+EFIAPI
+IsLocalSemaphoreOwned (
+ IN LOCAL_SEMAPHORE_NUMBER SemaphoreNumber,
+ IN UINT32 QueueNumber
+ );
+
+/**
+ Release a local semaphore owned by the calling thread.
+
+ Used for ensuring exclusive access to resources among CPU threads.
+
+ IMPORTANT:
+ The functions must be called in the sequence below:
+ ......
+ Owned = AcquireLocalSemaphore (LocalSemaphore0, ADD_TO_QUEUE, &QNum);
+ while (!Owned) {
+ Owned = IsLocalSemaphoreOwned (LocalSemaphore0, QNum));
+ }
+ DoSomething ();
+ ReleaseLocalSemaphore (LocalSemaphore0);
+ ......
+
+ @param[in] SemaphoreNumber - LOCALSEMAPHORE register number (0 or 1)
+
+ @retval EFI_SUCCESS - successfully released semaphore
+ @retval EFI_INVALID_PARAMETER - semaphore number is out of range
+ @retval EFI_DEVICE_ERROR - error releasing semaphore
+**/
+EFI_STATUS
+EFIAPI
+ReleaseLocalSemaphore (
+ IN LOCAL_SEMAPHORE_NUMBER SemaphoreNumber
+ );
+
+#endif // _SEMAPHORE_LIB_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/MaxCore.h b/Silicon/Intel/WhitleySiliconPkg/Include/MaxCore.h
new file mode 100644
index 0000000000..6cde7ac633
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/MaxCore.h
@@ -0,0 +1,20 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// This defines the maximum number of cores supported by some modules.
+// It is generally better to use a dynamic solution.
+// This is also defined by build tools for some special build
+// environments used in validation that do not support EDK II build
+// and thus can't use PCD.
+//
+
+#ifndef MAX_CORE
+#define MAX_CORE (FixedPcdGet32 (PcdMaxCpuCoreCount))
+#endif
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/MaxSocket.h b/Silicon/Intel/WhitleySiliconPkg/Include/MaxSocket.h
new file mode 100644
index 0000000000..06f2e54db3
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/MaxSocket.h
@@ -0,0 +1,20 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// This defines the maximum number of sockets supported by some modules.
+// It is generally better to use a dynamic solution.
+// This is also defined by build tools for some special build
+// environments used in validation that do not support EDK II build
+// and thus can't use PCD.
+//
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET (FixedPcdGet32 (PcdMaxCpuSocketCount))
+#endif
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/MaxThread.h b/Silicon/Intel/WhitleySiliconPkg/Include/MaxThread.h
new file mode 100644
index 0000000000..3240fc7166
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/MaxThread.h
@@ -0,0 +1,20 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// This defines the maximum number of threads supported by some modules.
+// It is generally better to use a dynamic solution.
+// This is also defined by build tools for some special build
+// environments used in validation that do not support EDK II build
+// and thus can't use PCD.
+//
+
+#ifndef MAX_THREAD
+#define MAX_THREAD (FixedPcdGet32 (PcdMaxCpuThreadCount))
+#endif
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h b/Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h
new file mode 100644
index 0000000000..6958b1431b
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h
@@ -0,0 +1,41 @@
+/** @file
+ Mem common Hearder File
+
+ @copyright
+ Copyright 2017 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __MEM_COMMON_H__
+#define __MEM_COMMON_H__
+
+#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket
+
+typedef enum {
+ ReservedMemSs,
+ Ddr4MemSs = 1,
+ Ddr5MemSs = 2,
+ LpDdr4MemSs = 3,
+ LpDdr5MemSs = 4,
+ Hbm2MemSs = 5,
+ MrcMstMax,
+ MrcMstDelim = MAX_INT32
+} MRC_MST;
+
+typedef enum {
+ TYPE_SCF_BAR = 0,
+ TYPE_PCU_BAR,
+ TYPE_MEM_BAR0,
+ TYPE_MEM_BAR1,
+ TYPE_MEM_BAR2,
+ TYPE_MEM_BAR3,
+ TYPE_MEM_BAR4,
+ TYPE_MEM_BAR5,
+ TYPE_MEM_BAR6,
+ TYPE_MEM_BAR7,
+ TYPE_SBREG_BAR,
+ TYPE_MAX_MMIO_BAR
+} MMIO_BARS;
+
+#endif //#ifndef __MEM_COMMON_H__
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Memory/Ddr4SpdRegisters.h b/Silicon/Intel/WhitleySiliconPkg/Include/Memory/Ddr4SpdRegisters.h
new file mode 100644
index 0000000000..0b002311fb
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Memory/Ddr4SpdRegisters.h
@@ -0,0 +1,38 @@
+/** @file
+
+ @copyright
+ Copyright 2019 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DDR4_SPD_REGS_H_
+#define _DDR4_SPD_REGS_H_
+
+//
+// DDR4 SPD Spec 4.0 Register Definitions
+//
+
+/* Byte 132 (0x084) (Registered): RDIMM Thermal Heat Spreader Solution */
+
+#define SPD_RDIMM_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION_REG 0x0084
+
+typedef union {
+ struct {
+ UINT8 heat_spreader_thermal_characteristics : 7;
+ /* Bits[0:6]
+ Heat Spreader Thermal Characteristics
+ 0 = Undefined
+ All other settings to be defined
+ */
+ UINT8 heat_spreader_solution : 1;
+ /* Bits[7]
+ Heat Spreader Solution
+ 0 = Heat spreader solution is not incorporated onto this assembly
+ 1 = Heat spreader solution is incorporated onto this assembly
+ */
+ } Bits;
+ UINT8 Data;
+} RDIMM_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION_STRUCT;
+
+#endif // #ifndef _DDR4_SPD_REGS_H_
\ No newline at end of file
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Memory/ProcSmbChipCommon.h b/Silicon/Intel/WhitleySiliconPkg/Include/Memory/ProcSmbChipCommon.h
new file mode 100644
index 0000000000..ae47ef2034
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Memory/ProcSmbChipCommon.h
@@ -0,0 +1,28 @@
+/** @file
+ ProcSmbChipCommon.h
+
+ @copyright
+ Copyright 2019 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PROC_SMB_CHIP_COMMON_H_
+#define _PROC_SMB_CHIP_COMMON_H_
+
+#include <MemDefaults.h>
+
+//
+// Available SMBus clock periods to be programmed.
+//
+typedef enum {
+ SmbClk100K = SMB_CLK_100K, // 100 Khz in I2C mode; 4Mhz in I3C mode
+ SmbClk400K = SMB_CLK_400K, // 400 Khz in I2C mode; 6Mhz in I3C mode
+ SmbClk700K = SMB_CLK_700K, // 700 Khz in I2C mode; 8Mhz in I3C mode
+ SmbClk1M = SMB_CLK_1M, // 1 Mhz in I2C mode; 10Mhz in I3C mode
+ SmbClkPeriodMax
+} SMB_CLOCK_FREQUENCY;
+
+#define MAX_SMB_INSTANCE 2 // Maximum number of SMBUS Instances
+
+#endif // _PROC_SMB_CHIP_COMMON_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Platform.h b/Silicon/Intel/WhitleySiliconPkg/Include/Platform.h
new file mode 100644
index 0000000000..b8ed188f16
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Platform.h
@@ -0,0 +1,266 @@
+/** @file
+ Platform specific information
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <BackCompatible.h>
+#include <Uefi.h>
+#include <Library/PcdLib.h>
+
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+//
+// Assigning default ID and base addresses here, these definitions are used by ACPI tables
+//
+
+#define PCH_IOAPIC (UINT64)BIT0
+#define PCH_IOAPIC_ID 0x08
+#define PCH_IOAPIC_ADDRESS 0xFEC00000 // This must get range from Legacy IIO
+#define PCH_INTERRUPT_BASE 0
+
+#define PC00_IOAPIC (UINT64)BIT1 //Because PCH_IOAPIC gets the first bit, these bit values will be 1+PC number.
+#define PC00_IOAPIC_ID 0x09
+#define PC00_INTERRUPT_BASE 24
+
+#define PC01_IOAPIC (UINT64)BIT2
+#define PC01_IOAPIC_ID 0x0A
+#define PC01_INTERRUPT_BASE 32
+
+#define PC02_IOAPIC (UINT64)BIT3
+#define PC02_IOAPIC_ID 0x0B
+#define PC02_INTERRUPT_BASE 40
+
+#define PC03_IOAPIC (UINT64)BIT4
+#define PC03_IOAPIC_ID 0x0C
+#define PC03_INTERRUPT_BASE 48
+
+#define PC04_IOAPIC (UINT64)BIT5
+#define PC04_IOAPIC_ID 0x0D
+#define PC04_INTERRUPT_BASE 56
+
+#define PC05_IOAPIC (UINT64)BIT6
+#define PC05_IOAPIC_ID 0x0E
+#define PC05_INTERRUPT_BASE 64
+
+#define PC06_IOAPIC (UINT64)BIT7
+#define PC06_IOAPIC_ID 0x0F
+#define PC06_INTERRUPT_BASE 72
+
+#define PC07_IOAPIC (UINT64)BIT8
+#define PC07_IOAPIC_ID 0x10
+#define PC07_INTERRUPT_BASE 80
+
+#define PC08_IOAPIC (UINT64)BIT9
+#define PC08_IOAPIC_ID 0x11
+#define PC08_INTERRUPT_BASE 88
+
+#define PC09_IOAPIC (UINT64)BIT10
+#define PC09_IOAPIC_ID 0x12
+#define PC09_INTERRUPT_BASE 96
+
+#define PC10_IOAPIC (UINT64)BIT11
+#define PC10_IOAPIC_ID 0x13
+#define PC10_INTERRUPT_BASE 104
+
+#define PC11_IOAPIC (UINT64)BIT12
+#define PC11_IOAPIC_ID 0x14
+#define PC11_INTERRUPT_BASE 112
+
+#define PC12_IOAPIC (UINT64)BIT13
+#define PC12_IOAPIC_ID 0x15
+#define PC12_INTERRUPT_BASE 120
+
+#define PC13_IOAPIC (UINT64)BIT14
+#define PC13_IOAPIC_ID 0x16
+#define PC13_INTERRUPT_BASE 128
+
+#define PC14_IOAPIC (UINT64)BIT15
+#define PC14_IOAPIC_ID 0x17
+#define PC14_INTERRUPT_BASE 136
+
+#define PC15_IOAPIC (UINT64)BIT16
+#define PC15_IOAPIC_ID 0x18
+#define PC15_INTERRUPT_BASE 144
+
+#define PC16_IOAPIC (UINT64)BIT17
+#define PC16_IOAPIC_ID 0x19
+#define PC16_INTERRUPT_BASE 152
+
+#define PC17_IOAPIC (UINT64)BIT18
+#define PC17_IOAPIC_ID 0x1A
+#define PC17_INTERRUPT_BASE 160
+
+#define PC18_IOAPIC (UINT64)BIT19
+#define PC18_IOAPIC_ID 0x1B
+#define PC18_INTERRUPT_BASE 168
+
+#define PC19_IOAPIC (UINT64)BIT20
+#define PC19_IOAPIC_ID 0x1C
+#define PC19_INTERRUPT_BASE 176
+
+#define PC20_IOAPIC (UINT64)BIT21
+#define PC20_IOAPIC_ID 0x1D
+#define PC20_INTERRUPT_BASE 184
+
+#define PC21_IOAPIC (UINT64)BIT22
+#define PC21_IOAPIC_ID 0x1E
+#define PC21_INTERRUPT_BASE 192
+
+#define PC22_IOAPIC (UINT64)BIT23
+#define PC22_IOAPIC_ID 0x1F
+#define PC22_INTERRUPT_BASE 200
+
+#define PC23_IOAPIC (UINT64)BIT24
+#define PC23_IOAPIC_ID 0x20
+#define PC23_INTERRUPT_BASE 208
+
+#define PC24_IOAPIC (UINT64)BIT25
+#define PC24_IOAPIC_ID 0x21
+#define PC24_INTERRUPT_BASE 216
+
+#define PC25_IOAPIC (UINT64)BIT26
+#define PC25_IOAPIC_ID 0x22
+#define PC25_INTERRUPT_BASE 224
+
+#define PC26_IOAPIC (UINT64)BIT27
+#define PC26_IOAPIC_ID 0x23
+#define PC26_INTERRUPT_BASE 232
+
+#define PC27_IOAPIC (UINT64)BIT28
+#define PC27_IOAPIC_ID 0x24
+#define PC27_INTERRUPT_BASE 240
+
+#define PC28_IOAPIC (UINT64)BIT29
+#define PC28_IOAPIC_ID 0x25
+#define PC28_INTERRUPT_BASE 248
+
+#define PC29_IOAPIC (UINT64)BIT30
+#define PC29_IOAPIC_ID 0x26
+#define PC29_INTERRUPT_BASE 256
+
+#define PC30_IOAPIC (UINT64)BIT31
+#define PC30_IOAPIC_ID 0x27
+#define PC30_INTERRUPT_BASE 264
+
+#define PC31_IOAPIC (UINT64)BIT32
+#define PC31_IOAPIC_ID 0x28
+#define PC31_INTERRUPT_BASE 272
+
+#define PC32_IOAPIC (UINT64)BIT33
+#define PC32_IOAPIC_ID 0x29
+#define PC32_INTERRUPT_BASE 280
+
+#define PC33_IOAPIC (UINT64)BIT34
+#define PC33_IOAPIC_ID 0x2A
+#define PC33_INTERRUPT_BASE 288
+
+#define PC34_IOAPIC (UINT64)BIT35
+#define PC34_IOAPIC_ID 0x2B
+#define PC34_INTERRUPT_BASE 296
+
+#define PC35_IOAPIC (UINT64)BIT36
+#define PC35_IOAPIC_ID 0x2C
+#define PC35_INTERRUPT_BASE 304
+
+#define PC36_IOAPIC (UINT64)BIT37
+#define PC36_IOAPIC_ID 0x2D
+#define PC36_INTERRUPT_BASE 312
+
+#define PC37_IOAPIC (UINT64)BIT38
+#define PC37_IOAPIC_ID 0x2E
+#define PC37_INTERRUPT_BASE 320
+
+#define PC38_IOAPIC (UINT64)BIT39
+#define PC38_IOAPIC_ID 0x2F
+#define PC38_INTERRUPT_BASE 328
+
+#define PC39_IOAPIC (UINT64)BIT40
+#define PC39_IOAPIC_ID 0x30
+#define PC39_INTERRUPT_BASE 336
+
+#define PC40_IOAPIC (UINT64)BIT41
+#define PC40_IOAPIC_ID 0x31
+#define PC40_INTERRUPT_BASE 344
+
+#define PC41_IOAPIC (UINT64)BIT42
+#define PC41_IOAPIC_ID 0x32
+#define PC41_INTERRUPT_BASE 352
+
+#define PC42_IOAPIC (UINT64)BIT43
+#define PC42_IOAPIC_ID 0x33
+#define PC42_INTERRUPT_BASE 360
+
+#define PC43_IOAPIC (UINT64)BIT44
+#define PC43_IOAPIC_ID 0x34
+#define PC43_INTERRUPT_BASE 368
+
+#define PC44_IOAPIC (UINT64)BIT45
+#define PC44_IOAPIC_ID 0x35
+#define PC44_INTERRUPT_BASE 376
+
+#define PC45_IOAPIC (UINT64)BIT46
+#define PC45_IOAPIC_ID 0x36
+#define PC45_INTERRUPT_BASE 384
+
+#define PC46_IOAPIC (UINT64)BIT47
+#define PC46_IOAPIC_ID 0x37
+#define PC46_INTERRUPT_BASE 392
+
+#define PC47_IOAPIC (UINT64)BIT48
+#define PC47_IOAPIC_ID 0x38
+#define PC47_INTERRUPT_BASE 400
+
+//
+// Define platform base
+// Note: All the PCH devices must get Legacy IO resources within first 16KB
+// since KTI RC allcoates range 0-16KB for the legacy IIO.
+//
+#define PCH_ACPI_BASE_ADDRESS PcdGet16 (PcdAcpiBaseAddress) // ACPI Power Management I/O Register Base Address
+
+#define PCH_TCO_BASE_ADDRESS PcdGet16 (PcdTcoBaseAddress)
+
+#define SIO_GPIO_BASE_ADDRESS 0x0800
+
+//
+// SMBUS Data
+//
+#define PCH_SMBUS_BASE_ADDRESS 0x0780
+
+//
+// CMOS usage
+//
+
+// Second bank
+//
+#define CMOS_PLATFORM_ID_LO 0x18 // Second bank CMOS location of Platform ID
+#define CMOS_PLATFORM_ID_HI 0x19 //
+
+#define PCI_BUS_NUMBER_PCH_HPET 0x0
+#define PCI_DEVICE_NUMBER_PCH_HPET 0x1F
+
+#define PCI_FUNCTION_NUMBER_PCH_HPET0 0x00
+
+#define PCI_BUS_NUMBER_PCH_IOAPIC 0x00
+#define PCI_DEVICE_NUMBER_PCH_IOAPIC 0x1E
+
+#define PCI_FUNCTION_NUMBER_PCH_IOAPIC 0x0
+
+//
+// AHCI port offset values
+//
+#define EFI_AHCI_PORT_START 0x0100
+#define EFI_AHCI_PORT_REG_WIDTH 0x0080
+#define EFI_AHCI_PORT_CLB 0x0000
+#define EFI_AHCI_PORT_CLBU 0x0004
+#define EFI_AHCI_PORT_FB 0x0008
+#define EFI_AHCI_PORT_FBU 0x000C
+#define EFI_AHCI_PORT_IS 0x0010
+#define EFI_AHCI_PORT_IE 0x0014
+#define EFI_AHCI_PORT_CMD 0x0018
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
new file mode 100644
index 0000000000..ca91434663
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
@@ -0,0 +1,106 @@
+/** @file
+
+ @copyright
+ Copyright 2020 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_INFO_TYPES_H_
+#define _PLATFORM_INFO_TYPES_H_
+
+//
+// DIMM Connector type
+//
+typedef enum {
+ DimmConnectorPth = 0x00, // Through hole connector
+ DimmConnectorSmt, // Surface mount connector
+ DimmConnectorMemoryDown, // Platform soldered DRAMs
+ DimmConnectorIgnore, // Ignore connector type
+ DimmConnectorMax
+} EFI_MEMORY_DIMM_CONNECTOR_TYPE;
+
+//
+// Platform types - used with EFI_PLATFORM_INFO BoardId
+//
+typedef enum {
+ StartOfEfiPlatformTypeEnum = 0x00,
+ //For PPO
+ TypeNeonCityEPRP,
+ TypeWolfPass,
+ TypeTennesseePass,
+ TypeHedtCRB,
+ TypeLightningRidgeEXRP,
+ TypeLightningRidgeEX8S1N,
+ TypeBarkPeak,
+ TypeYubaCityRP,
+ TypeRidgeport,
+ //End PPO
+ TypeWilsonCityRP,
+ TypeWilsonCityModular,
+ TypeCoyotePass,
+ TypeIdaville,
+ TypeMoroCityRP,
+ TypeBrightonCityRp,
+ TypeJacobsville,
+ TypeSnrSvp,
+ TypeSnrSvpSodimm,
+ TypeJacobsvilleMDV,
+ TypeFrostCreekRP,
+ TypeVictoriaCanyonRP,
+ TypeArcherCityRP,
+ TypeNeonCityEPECB,
+ TypeIsoscelesPeak,
+ TypeWilsonPointRP,
+ TypeWilsonPointModular,
+ TypeBretonSound,
+ TypeWilsonCityPPV,
+ TypeCooperCityRP,
+ TypeWilsonCitySMT,
+ TypeSnrSvpSodimmB,
+ TypeArcherCityModular,
+ TypeArcherCityEVB,
+ TypeArcherCityXPV,
+ TypeBigPineKey,
+ TypeExperWorkStationRP,
+ EndOfEfiPlatformTypeEnum
+} EFI_PLATFORM_TYPE;
+
+#define TypePlatformUnknown 0xFF
+#define TypePlatformMin StartOfEfiPlatformTypeEnum + 1
+#define TypePlatformMax EndOfEfiPlatformTypeEnum - 1
+#define TypePlatformDefault TypeWilsonPointRP
+
+//
+// CPU type: Standard (no MCP), -F, etc
+//
+typedef enum {
+ CPU_TYPE_STD,
+ CPU_TYPE_F,
+ CPU_TYPE_P,
+ CPU_TYPE_MAX
+} CPU_TYPE;
+
+#define CPU_TYPE_STD_MASK (1 << CPU_TYPE_STD)
+#define CPU_TYPE_F_MASK (1 << CPU_TYPE_F)
+#define CPU_TYPE_P_MASK (1 << CPU_TYPE_P)
+
+typedef enum {
+ DaisyChainTopology = 0x00,
+ InvSlotsDaisyChainTopology,
+ TTopology
+} EFI_MEMORY_TOPOLOGY_TYPE;
+
+//
+// Values for SocketConfig
+//
+
+#define SOCKET_UNDEFINED 0
+#define SOCKET_4S 1
+#define SOCKET_HEDT 2
+#define SOCKET_1S 3
+#define SOCKET_1SWS 4
+#define SOCKET_8S 5
+#define SOCKET_2S 6
+
+#endif // #ifndef _PLATFORM_INFO_TYPES_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/DynamicSiLibraryPpi.h b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/DynamicSiLibraryPpi.h
new file mode 100644
index 0000000000..c6915582c6
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/DynamicSiLibraryPpi.h
@@ -0,0 +1,474 @@
+/** @file
+ UBS silicon access PPI
+
+ This PPI abstracts all UBA silicon accesses
+
+ @copyright
+ Copyright 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DYNAMIC_SI_LIBARY_PPI_H_
+#define _DYNAMIC_SI_LIBARY_PPI_H_
+
+// {C1176733-159F-42d5-BCB9-320660B17310}
+#define DYNAMIC_SI_LIBARY_PPI_GUID \
+ { 0x4e18e22b, 0x5034, 0x4512, { 0xb7, 0xe5, 0x0b, 0xf1, 0x9d, 0xe3, 0x59, 0x8c } }
+
+#define UBA_ACCESS_PPI_VERSION 01
+#define UBA_ACCESS_PPI_SIGNATURE SIGNATURE_32('D', 'S', 'L', 'P')
+
+#include <Library/SpsPeiLib.h>
+#include <IioPlatformData.h>
+#include <GpioConfig.h>
+#include <Library/PchInfoLib.h>
+#include <Library/GpioLib.h>
+
+//
+// Functions
+//
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_GET_GPIO_INPUT_VALUE) (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *InputVal
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_SET_GPIO_OUTPUT_VALUE) (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 Value
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_GPIO_SET_PAD) (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_CONFIG *GpioData
+ );
+
+typedef
+UINT16
+(EFIAPI *PEI_GET_PCH_DEVICE_ID) (
+ VOID
+ );
+
+typedef
+PCH_SERIES
+(EFIAPI *PEI_GET_PCH_SERIES) (
+ VOID
+ );
+
+typedef
+PCH_STEPPING
+(EFIAPI *PEI_GET_PCH_STEPPING) (
+ VOID
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_IS_PCH_GBE_REGION_VALID) (
+ VOID
+ );
+
+typedef
+UINT32
+(EFIAPI *PEI_GET_PCH_GBE_PORT_NUMBER) (
+ VOID
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_IS_PCH_GBE_PRESENT) (
+ VOID
+ );
+
+typedef
+VOID
+(EFIAPI *PEI_PchDisableGbe) (
+ VOID
+ );
+
+typedef
+VOID
+(EFIAPI *PEI_PchDisableGbeByPchId) (
+ IN UINT8 PchId
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_GpioConfigurePadsByPchId) (
+ IN UINT8 PchId,
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_GpioGetInputValueByPchId) (
+ IN UINT8 PchId,
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *InputVal
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PeiGetCurrenClockingMode) (
+ OUT CLOCKING_MODES *ClockingMode
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_GetPchPcieRpDevFunByPchId) (
+ IN UINT8 PchId,
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_IsSimicsEnvironment) (
+ VOID
+ );
+
+typedef
+UINT8
+(EFIAPI *PEI_GetPchMaxSataPortNum) (
+ VOID
+ );
+
+typedef
+UINT8
+(EFIAPI *PEI_GetPchMaxsSataPortNum) (
+ VOID
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_GpioSetPadConfigByPchId) (
+ IN UINT8 PchId,
+ IN GPIO_PAD GpioPad,
+ IN GPIO_CONFIG *GpioData
+ );
+
+typedef
+UINT8
+(EFIAPI *PEI_GetPchMaxPciePortNum) (
+ VOID
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PchGetSataLaneNumByPchId) (
+ IN UINT8 PchId,
+ UINT32 SataLaneIndex,
+ UINT8 *LaneNum
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PchGetPcieLaneNumByPchId) (
+ IN UINT8 PchId,
+ UINT32 PcieLaneIndex,
+ UINT8 *LaneNum
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PchGetsSataLaneNumByPchId) (
+ IN UINT8 PchId,
+ UINT32 SataLaneIndex,
+ UINT8 *LaneNum
+ );
+
+typedef
+UINTN
+(EFIAPI *PEI_MmPciBase) (
+ IN UINT32 Bus,
+ IN UINT32 Device,
+ IN UINT32 Function
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_HybridSystemLevelEmulationEnabled) (
+ VOID
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_IioIsSocketPresent) (
+ IN UINT8 IioIndex
+ );
+
+typedef
+UINT8
+(EFIAPI *PEI_GetMaxPortNumPerSocket) (
+ VOID
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_IsVMDEnabledForPort) (
+ IN UINT8 IioIndex,
+ IN UINT8 PortIndex
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_IioAreLanesAssignedToPort) (
+ IN IIO_GLOBALS *IioGlobalData,
+ IN UINT8 IioIndex,
+ IN UINT8 PortIndex
+ );
+
+typedef
+UINT8
+(EFIAPI *PEI_GetPortIndexbyStack) (
+ IN UINT8 StackIndex,
+ IN UINT8 PortIndex
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_IsDmiStack) (
+ IN UINT8 Stack
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_IsCpuAndRevision) (
+ IN UINT8 CpuType,
+ IN UINT16 Revision
+ );
+
+typedef
+UINT8
+(EFIAPI *PEI_GetMaxStackNumPerSocket) (
+ VOID
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_IioIsStackPresent) (
+ IN UINT8 IioIndex,
+ IN UINT8 StackIndex
+ );
+
+typedef
+UINT8
+(EFIAPI *PEI_GetMaxPortNumPerStack) (
+ IN UINT8 Stack
+ );
+
+//
+// From KtiApi.h
+//
+typedef
+BOOLEAN
+(EFIAPI *PEI_SocketPresent) (
+ IN UINT32 SocId
+ );
+
+/**
+ Get SVID Mapping from Socket and MCID
+
+ @param[in] Socket - Socket Id - 0 based
+ @param[in] McId - Memory controller 0 based
+ @param[in] SvidValue - SVID Value
+
+ @retval EFI_SUCCESS - Value found
+ @retval EFI_NOT_FOUND - Value not found
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_GetSvidMap) (
+ IN UINT8 Socket,
+ IN UINT8 McId,
+ IN UINT8 *SvidValue
+ );
+
+typedef
+UINT16
+(EFIAPI *PEI_PmcGetAcpiBase) (
+ VOID
+ );
+
+typedef
+UINT16
+(EFIAPI *PEI_PmcGetAcpiBaseByPchId) (
+ IN UINT8 PchId
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PchLpcIoDecodeRangesSet) (
+ IN UINT16 LpcIoDecodeRanges
+ );
+
+typedef
+VOID
+(EFIAPI *PEI_CheckPowerOffNow) (
+ VOID
+ );
+
+typedef
+VOID
+(EFIAPI *PEI_PmcSetPlatformStateAfterPowerFailure) (
+ IN UINT8 PowerStateAfterG3
+ );
+
+typedef
+VOID
+(EFIAPI *PEI_PmcClearPowerFailureStatus) (
+ VOID
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_PmcIsPowerFailureDetected) (
+ VOID
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PchLpcGenIoRangeSet) (
+ IN UINT16 Address,
+ IN UINTN Length
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PchLpcIoEnableDecodingSet) (
+ IN UINT16 LpcIoEnableDecoding
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PchPcrAndThenOr32) (
+ IN PCH_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PchPcrRead32ByPchId) (
+ IN UINT8 PchId,
+ IN PCH_SBI_PID Pid,
+ IN UINT16 Offset,
+ OUT UINT32 *OutData
+ );
+
+typedef
+UINT8
+(EFIAPI *PEI_ReadNmiEn) (
+ VOID
+ );
+
+typedef
+UINT8
+(EFIAPI *PEI_GetPchXhciMaxUsb2PortNum) (
+ VOID
+ );
+
+typedef
+UINT8
+(EFIAPI *PEI_GetPchXhciMaxUsb3PortNum) (
+ VOID
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_PchIsGbeAvailable) (
+ VOID
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_EnableMcaOnCacheableMmio) (
+ VOID
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *PEI_X2ApicIdDetect) (
+ IN VOID *Host
+ );
+
+//
+// Abstracting silicon functional implementations from OpenBoardPkg code
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Version;
+
+ PEI_GET_GPIO_INPUT_VALUE GpioGetInputValue;
+ PEI_SET_GPIO_OUTPUT_VALUE GpioSetOutputValue;
+ PEI_GPIO_SET_PAD GpioSetPadConfig;
+
+ PEI_GET_PCH_DEVICE_ID GetPchLpcDeviceId;
+ PEI_GET_PCH_SERIES GetPchSeries;
+ PEI_GET_PCH_STEPPING PchStepping;
+ PEI_IS_PCH_GBE_REGION_VALID PchIsGbeRegionValid;
+ PEI_GET_PCH_GBE_PORT_NUMBER PchGetGbePortNumber;
+ PEI_IS_PCH_GBE_PRESENT PchIsGbePresent;
+
+ PEI_PchDisableGbeByPchId PchDisableGbeByPchId;
+ PEI_GpioConfigurePadsByPchId GpioConfigurePadsByPchId;
+ PEI_GpioSetPadConfigByPchId GpioSetPadConfigByPchId;
+ PEI_GpioGetInputValueByPchId GpioGetInputValueByPchId;
+ PEI_PeiGetCurrenClockingMode PeiGetCurrenClockingMode;
+ PEI_GetPchPcieRpDevFunByPchId GetPchPcieRpDevFunByPchId;
+ PEI_IsSimicsEnvironment IsSimicsEnvironment;
+ PEI_GetPchMaxSataPortNum GetPchMaxSataPortNum;
+ PEI_GetPchMaxsSataPortNum GetPchMaxsSataPortNum;
+ PEI_GetPchMaxPciePortNum GetPchMaxPciePortNum;
+ PEI_PchGetSataLaneNumByPchId PchGetSataLaneNumByPchId;
+ PEI_PchGetsSataLaneNumByPchId PchGetsSataLaneNumByPchId;
+ PEI_PchGetPcieLaneNumByPchId PchGetPcieLaneNumByPchId;
+ PEI_MmPciBase MmPciBase;
+ PEI_HybridSystemLevelEmulationEnabled HybridSystemLevelEmulationEnabled;
+ PEI_IioIsSocketPresent IioIsSocketPresent;
+ PEI_GetMaxPortNumPerSocket GetMaxPortNumPerSocket;
+ PEI_IsVMDEnabledForPort IsVMDEnabledForPort;
+ PEI_IioAreLanesAssignedToPort IioAreLanesAssignedToPort;
+ PEI_GetPortIndexbyStack GetPortIndexbyStack;
+ PEI_IsDmiStack IsDmiStack;
+ PEI_IsCpuAndRevision IsCpuAndRevision;
+ PEI_PchDisableGbe PchDisableGbe;
+ PEI_GetMaxStackNumPerSocket GetMaxStackNumPerSocket;
+ PEI_IioIsStackPresent IioIsStackPresent;
+ PEI_GetMaxPortNumPerStack GetMaxPortNumPerStack;
+ PEI_SocketPresent SocketPresent;
+ PEI_GetSvidMap GetSvidMap;
+
+ PEI_PmcGetAcpiBase PmcGetAcpiBase;
+ PEI_PmcGetAcpiBaseByPchId PmcGetAcpiBaseByPchId;
+ PEI_PchLpcIoDecodeRangesSet PchLpcIoDecodeRangesSet;
+ PEI_CheckPowerOffNow CheckPowerOffNow;
+ PEI_PmcSetPlatformStateAfterPowerFailure PmcSetPlatformStateAfterPowerFailure;
+ PEI_PmcClearPowerFailureStatus PmcClearPowerFailureStatus;
+ PEI_PmcIsPowerFailureDetected PmcIsPowerFailureDetected;
+ PEI_PchLpcGenIoRangeSet PchLpcGenIoRangeSet;
+ PEI_PchLpcIoEnableDecodingSet PchLpcIoEnableDecodingSet;
+ PEI_PchPcrAndThenOr32 PchPcrAndThenOr32;
+ PEI_PchPcrRead32ByPchId PchPcrRead32ByPchId;
+ PEI_ReadNmiEn ReadNmiEn;
+
+ PEI_GetPchXhciMaxUsb2PortNum GetPchXhciMaxUsb2PortNum;
+ PEI_GetPchXhciMaxUsb3PortNum GetPchXhciMaxUsb3PortNum;
+ PEI_PchIsGbeAvailable PchIsGbeAvailable;
+ PEI_EnableMcaOnCacheableMmio EnableMcaOnCacheableMmio;
+ PEI_X2ApicIdDetect X2ApicIdDetect;
+} DYNAMIC_SI_LIBARY_PPI;
+
+extern EFI_GUID gDynamicSiLibraryPpiGuid;
+
+#endif // _DYNAMIC_SI_LIBARY_PPI_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
new file mode 100644
index 0000000000..6c5ca06bc1
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
@@ -0,0 +1,2112 @@
+/** @file
+ Header file defining MEMORY_POLICY_PPI, which is for platform code to set platform
+ specific configurations of memory reference code.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _MEMORY_POLICY_PPI_H_
+#define _MEMORY_POLICY_PPI_H_
+
+#include <MemHostChipCommon.h>
+#include <PlatformHost.h>
+#include <Memory/ProcSmbChipCommon.h>
+#include <Guid/MemBootHealthGuid.h>
+#include <PlatformInfoTypes.h>
+
+
+///
+/// Number of group of BIOS-to-Pcode Mailbox command.
+//
+#define MAX_B2P_MAILBOX_GROUPS 32
+
+#pragma pack(push, 1)
+
+///
+/// Memory Timings Settings.
+//
+struct memTiming {
+
+ ///
+ /// @brief
+ /// Column Latency.
+ /// @details
+ /// Column Latency (CL) time is the number of clock cycles needed to access a
+ /// certain column of data in RAM. It's also known as CAS (column address
+ /// strobe) time.
+ //
+ UINT8 nCL;
+
+ ///
+ /// @brief
+ /// Row Precharge.
+ /// @details
+ /// RP (row precharge) time is the number of clock cycles needed to terminate
+ /// access to an open row of memory, and open access to the next row.
+ //
+ UINT8 nRP;
+
+ ///
+ /// @brief
+ /// RAS to CAS Delay.
+ /// @details
+ /// RAS to CAS Delay (RCD) is the number of clock cycles delay required
+ /// between an active command row address strobe (RAS) and a CAS. It is
+ /// the time required between the memory controller asserting a row address,
+ /// and then asserting a column address during the subsequent read or write
+ /// command. RCD stands for row address to column address delay time.
+ //
+ UINT8 nRCD;
+
+ ///
+ /// @brief
+ /// Row to Row Delay.
+ /// @details
+ /// Active to Active Delay, Row to Row Delay or RAS to RAS Delay. The amount of
+ /// cycles that taken to activate the next bank of memory.
+ //
+ UINT8 nRRD;
+ UINT8 nRRD_L;
+
+ ///
+ /// @brief
+ /// Write to Read Delay.
+ /// @details
+ /// Write to Read Delay. The amount of cycles required between a valid write
+ /// command and the next read command.
+ //
+ UINT8 nWTR;
+
+ ///
+ /// @brief
+ /// Row Active Strobe.
+ /// @details
+ /// Row Active Strobe (RAS) time is the minimum number of clock cycles needed
+ /// to access a certain row of data in RAM between the data request and the
+ /// precharge command. It's known as active to precharge delay.
+ //
+ UINT8 nRAS;
+
+ ///
+ /// @brief
+ /// Read To Precharge delay.
+ /// @details
+ /// The number of clocks between a read command to a row pre-charge command.
+ //
+ UINT8 nRTP;
+
+ ///
+ /// @brief
+ /// Write Recovery time.
+ /// @details
+ /// The amount of cycles that are required between a valid
+ /// write operation and precharge, to make sure that data is written properly.
+ ///
+ UINT8 nWR;
+
+ ///
+ /// @brief
+ /// Four Activate Window.
+ /// @details
+ /// Four Activate Window, which specifies the time window in wich four activates
+ /// are allowed on the same rank.
+ //
+ UINT8 nFAW;
+
+ ///
+ /// CAS (WRITE) latency (CWL).
+ //
+ UINT8 nCWL;
+
+ ///
+ /// @brief
+ /// Row Cycle.
+ /// @details
+ /// Row Cycle time, the minimum time in cycles taken for a row to complete a full
+ /// cycle, which typically can be calculated by nRC = nRAS + nRP.
+ //
+ UINT8 nRC;
+
+ ///
+ /// @brief
+ /// Command Rate.
+ /// @details
+ /// Command Rate / Command per Clock (1T/2T) is the delay between a memory chip
+ /// is selected and the first active command can be issued.
+ //
+ UINT8 nCMDRate;
+
+ ///
+ /// The limit of DDR frequency ratio, based on base clock frequency.
+ //
+ UINT8 ddrFreqLimit;
+
+ ///
+ /// Vdd for DRAM core.
+ //
+ UINT16 vdd;
+
+ ///
+ /// XMP Memory Controller Voltage Level.
+ //
+ UINT8 ucVolt;
+
+ ///
+ /// Bits map to indicate if a CAS in a CAS list is supported.
+ //
+ UINT64 casSup;
+
+ ///
+ /// Refresh Interval.
+ //
+ UINT16 tREFI;
+
+ ///
+ /// @brief
+ /// Refresh to Activate Delay.
+ /// @details
+ /// Refresh to Activate Delay or Refresh Cycle Time. The number of clocks from
+ /// a Refresh command to the first Activate command.
+ //
+ UINT16 nRFC;
+
+ ///
+ /// Frequency of DDR.
+ //
+ UINT16 ddrFreq;
+};
+
+typedef struct ReservedS193 {
+
+ UINT8 ReservedS69;
+
+ UINT8 ReservedS70;
+
+ UINT8 ReservedS68;
+
+ UINT8 ReservedS67;
+
+ UINT8 ReservedS71;
+
+ UINT8 ReservedS74[MAX_SOCKET * MAX_IMC];
+
+ UINT8 ReservedS194[MAX_SOCKET];
+
+ UINT8 ReservedS77;
+
+ UINT8 ReservedS48;
+
+ UINT32 ReservedS195;
+
+ UINT8 ReservedS196;
+
+ UINT8 ReservedS107;
+
+ UINT8 ReservedS105;
+
+ UINT8 ReservedS75;
+
+ UINT8 ReservedS108;
+
+ UINT8 ReservedS73;
+
+ UINT8 ReservedS197;
+
+
+ UINT8 ReservedS49;
+
+ UINT8 ReservedS50;
+
+ UINT8 ReservedS51;
+
+ UINT8 ReservedS52;
+
+ UINT16 ReservedS53;
+
+ UINT16 ReservedS54;
+
+ UINT16 ReservedS55;
+
+ UINT16 ReservedS56;
+
+ UINT16 ReservedS57;
+
+ UINT8 ReservedS58;
+
+ UINT16 ReservedS59;
+
+ UINT8 ReservedS60;
+
+ UINT16 ReservedS61;
+
+ UINT8 ReservedS62;
+
+ UINT8 ReservedS63;
+
+ UINT16 ReservedS64;
+
+ UINT16 ReservedS65;
+
+ UINT8 ReservedS66;
+
+ UINT8 ReservedS198 : 1,
+ ReservedS199 : 1,
+ ReservedS200 : 1,
+ ReservedS119 : 1,
+ ReservedS201 : 4;
+ UINT8 ReservedS120;
+
+ BOOLEAN ReservedS128; // Posted CSR access method is available when this is TRUE
+
+ BOOLEAN ReservedS130;
+
+ UINT16 ReservedS131;
+
+ BOOLEAN ReservedS111;
+
+ BOOLEAN ReservedS202;
+
+ UINT8 ReservedS203;
+
+ BOOLEAN ReservedS204;
+
+ BOOLEAN ReservedS205;
+
+ BOOLEAN ReservedS206;
+
+ UINT8 ReservedS121;
+
+ UINT8 ReservedS122;
+
+ UINT8 ReservedS123;
+
+ UINT8 ReservedS124;
+
+ UINT8 ReservedS125;
+
+ UINT8 ReservedS126;
+
+ UINT8 ReservedS127;
+
+ BOOLEAN ReservedS137;
+
+ UINT8 SenseAmpCalibHwSwOption;
+
+ BOOLEAN ReservedS129;
+
+ UINT8 ReservedS207 :4,
+ ReservedS208 :1,
+ ReservedS209 :1,
+ ReservedS210 :2;
+
+ UINT8 ReservedS143;
+
+ UINT8 ReservedS144;
+
+ UINT8 ReservedS145;
+
+ UINT8 ReservedS211 :4,
+ ReservedS212 :1,
+ ReservedS213 :3;
+
+ UINT8 ReservedS148;
+
+
+ UINT8 ReservedS149;
+
+} RESERVED_S193;
+
+///
+/// DIMM enable/disable information
+//
+struct ddrDimmSetup {
+
+ ///
+ /// Setting for each DIMM to be mapped out.
+ //
+ UINT8 mapOut[MAX_RANK_DIMM];
+};
+
+///
+/// Channel setup structure declaration
+//
+struct ddrChannelSetup {
+ UINT8 enabled; /// Channel enable switch.
+ UINT8 numDimmSlots; /// Number of DIMM slots per channel.
+ UINT8 batterybacked; /// ADR Battery backed or not.
+ UINT8 rankmask; /// Rank mask. 0 = disable; 1 = enable.
+ struct ddrDimmSetup dimmList[MAX_DIMM]; /// DIMM enable/disable information.
+};
+
+///
+/// PPR DRAM Address.
+//
+typedef struct {
+ UINT8 dimm;
+ UINT8 rank;
+ UINT8 subRank;
+ UINT32 nibbleMask;
+ UINT8 bank;
+ UINT32 row;
+} PPR_ADDR;
+
+///
+/// PPR Address, buffer to hold DRAM Address that need to be repaired.<BR>
+//
+typedef struct {
+ UINT8 pprAddrStatus;
+ UINT8 socket;
+ UINT8 mc;
+ UINT8 ch;
+ PPR_ADDR pprAddr;
+} PPR_ADDR_MRC_SETUP;
+
+
+///
+/// Socket setup structure declaration.
+//
+struct ddrSocketSetup {
+
+ ///
+ /// iMC enable/disable switch.
+ //
+ UINT8 enabled;
+
+ ///
+ /// Bit-mapped options per socket.
+ //
+ UINT8 options;
+
+ ///
+ /// Platform configuration for each channel.
+ //
+ struct ddrChannelSetup ddrCh[MAX_CH];
+
+ ///
+ /// Enable/Disable memory controller.
+ //
+ UINT8 imcEnabled[MAX_IMC];
+};
+
+///
+/// Define AdvMemTest Rank List item
+/// The input format is defined as follows:
+/// Rank number in bits[3:0]
+/// DIMM number in bits[7:4]
+/// Channel number in the MC in bits[11:8]
+/// MC number in bits[15:12]
+/// Socket number in bits [19:16]
+/// bits [31:20] are reserved
+/// For example:
+/// To test MC 0, CH 1, DIMM 0, RANK 0 on Socket 0, you need to enter a value of 0x100
+/// To test MC 1, CH 0, DIMM 0, RANK 0 on Socket 0, you need to enter a value of 0x1000
+//
+typedef union {
+ struct {
+ UINT32 Rank: 4;
+ UINT32 Dimm: 4;
+ UINT32 Channel: 4;
+ UINT32 Mc: 4;
+ UINT32 Socket: 4;
+ UINT32 rsvd: 12;
+ } Bits;
+ UINT32 Data;
+} AdvMemTestRankData;
+
+///
+/// Host memory setup structure declaration.
+//
+struct memSetup {
+
+ ///
+ /// @brief
+ /// Flags for enabling (1)/disabling(0) MRC features.<BR>
+ /// @details
+ /// TEMPHIGH_EN BIT0, enables support for 95 degree DIMMs.<BR>
+ /// ATTEMPT_FAST_BOOT_COLD BIT1.<BR>
+ /// PDWN_SR_CKE_MODE BIT2, enables CKE to be tri-stated during
+ /// register clock off power down self-refresh.<BR>
+ /// OPP_SELF_REF_EN BIT3, enables the opportunistic self refresh mechanism.<BR>
+ /// MDLL_SHUT_DOWN_EN BIT4, enables MDLL shutdown.<BR>
+ /// PAGE_POLICY BIT5, Clear for open page, set for closed page. Open page
+ /// has better performance and power usage in general.
+ /// Close page may benefit some applications with poor <BR>
+ /// locality.<BR>
+ /// ALLOW2XREF_EN BIT6, enables 2X refresh if needed for extended operating
+ /// temperature range (95degrees) If TEMPHIGH_EN is also
+ /// set, setting this bit will result in 2X refresh timing
+ /// for the IMC refresh control register. <BR>
+ /// MULTI_THREAD_MRC_EN BIT7, enables multithreaded MRC. This reduces boot time for
+ /// systems with multiple processor sockets.<BR>
+ /// ADAPTIVE_PAGE_EN BIT8, enables adaptive page mode. The memory controller will
+ /// dynamically determine how long to keep pages open<BR>
+ /// to improve performance.<BR>
+ /// CMD_CLK_TRAINING_EN BIT9, enables command to clock training step.<BR>
+ /// SCRAMBLE_EN BIT10, set to enable data scrambling. This should always be
+ /// enabled except for debug purposes.<BR>
+ /// SCRAMBLE_EN_DDRT BIT11, set to enable data scrambling. This should always be
+ /// enabled except for debug purposes.<BR>
+ /// DISPLAY_EYE_EN BIT12,<BR>
+ /// DDR_RESET_LOOP BIT13, enables infinite channel reset loop without retries
+ /// for gathering of margin data.<BR>
+ /// NUMA_AWARE BIT14, enables configuring memory interleaving appropriately
+ /// for NUMA aware OS.<BR>
+ /// DISABLE_WMM_OPP_READ BIT15, disables issuing read commands opportunistically during WMM.<BR>
+ /// RMT_COLD_FAST_BOOT BIT16. <BR>
+ /// ECC_CHECK_EN BIT17, enables ECC checking.<BR>
+ /// ECC_MIX_EN BIT18, enables ECC in a system with mixed ECC and non-ECC memory in a
+ /// channel by disabling ECC when this configuration is detected.<BR>
+ /// DISABLE_ECC_SUPPORT BIT19, disables ECC check.<BR>
+ /// CA_PARITY_EN BIT20, <BR>
+ /// PER_NIBBLE_EYE_EN BIT22.
+ /// RAS_TO_INDP_EN BIT23, switches from lockstep or mirror mode to independenct channel
+ /// mode when memory is present on channel 2 and this is enabled.<BR>
+ /// MARGIN_RANKS_EN BIT25, enables the rank margin tool.<BR>
+ /// MEM_OVERRIDE_EN BIT26, enables use of inputMemTime inputs as hard overrides.<BR>
+ /// DRAMDLL_OFF_PD_EN BIT27, <BR>
+ /// MEMORY_TEST_EN BIT28, enables execution of MemTest if on cold boot<BR>
+ /// MEMORY_TEST_COLD_FAST_BOOT_EN BIT29, enables the memory test when going through a cold fast boot
+ /// path<BR>
+ /// ATTEMPT_FAST_BOOT BIT30, attempts to take a fast boot path if the NVRAM structure is good
+ /// and the memory config hasn't changed. For example, on a warm boot,
+ /// this will take the "fast warm" path through MRC which attempts
+ /// to make it as close as possible to the S3 path.<BR>
+ /// SW_MEMORY_TEST_EN BIT31. <BR>
+ //
+ UINT32 options;
+
+ ///
+ /// @brief
+ /// Flags for enabling (1)/disabling(0) MRC features.<BR>
+ /// @details
+ /// PD_CRC_CHECK BIT0<BR>
+ /// SET_MEM_TESTED_EN BIT1<BR>
+ /// AVAILABLE BIT2<BR>
+ /// TURNAROUND_OPT_EN_DDRT BIT3<BR>
+ /// PDA_EN BIT5<BR>
+ /// TURNAROUND_OPT_EN BIT6<BR>
+ /// AVAILABLE BIT7<BR>
+ /// ALLOW_CORRECTABLE_ERROR BIT8<BR>
+ /// ALLOW_CORRECTABLE_MEM_TEST_ERROR BIT9<BR>
+ /// AVAILABLE BIT10<BR>
+ /// AVAILABLE BIT11<BR>
+ /// AVAILABLE BIT12<BR>
+ /// PER_BIT_MARGINS BIT13<BR>
+ /// DUTY_CYCLE_EN BIT14<BR>
+ /// LRDIMM_BACKSIDE_VREF_EN BIT15<BR>
+ /// AVAILABLE BIT16<BR>
+ /// DRAM_RX_EQ_EN BIT17<BR>
+ /// AVAILABLE BIT18<BR>
+ /// AVAILABLE BIT19<BR>
+ /// AVAILABLE BIT20<BR>
+ /// OPTIONS_EXT_RESERVED1 BIT21<BR>
+ /// AVAILABLE BIT22<BR>
+ /// WR_CRC BIT23<BR>
+ /// OPTIONS_EXT_RESERVED2 BIT24<BR>
+ /// AVAILABLE BIT25<BR>
+ /// AVAILABLE BIT26<BR>
+ /// AVAILABLE BIT27<BR>
+ /// AVAILABLE BIT28<BR>
+ /// DIMM_ISOLATION_EN BIT29<BR>
+ /// AVAILABLE BIT30<BR>
+ //
+ UINT32 optionsExt;
+
+ ///
+ /// @brief
+ /// NGN Flags.
+ /// @details
+ /// NGN_CMD_TIME BIT1<BR>
+ /// NGN_DEBUG_LOCK BIT6<BR>
+ /// NGN_ARS_ON_BOOT BIT7<BR>
+ /// NGN_ARS_PUBLISH BIT9<BR>
+ /// NGN_ECC_EXIT_CORR BIT10<BR>
+ /// NGN_ECC_CORR BIT11<BR>
+ /// NGN_ECC_WR_CHK BIT12<BR>
+ /// NGN_ECC_RD_CHK BIT13<BR>
+ //
+ UINT32 optionsNgn;
+
+
+ ///
+ /// @brief
+ /// PDA behavior for x16 devices.<BR>
+ /// @details
+ /// 0 - will disable PDA operation when a x16 device is detected.<BR>
+ /// 1 - will not modify PDA Mode.<BR>
+ //
+ UINT8 PdaModeX16;
+
+ ///
+ /// @brief
+ /// IMC BCLK frequency. <BR>
+ /// @details
+ /// 0 - Auto, MRC code determine the value.<BR>
+ /// 1 - 100MHz.<BR>
+ /// 2 - 133MHz.<BR>
+ //
+ UINT8 imcBclk;
+
+ ///
+ /// @brief
+ /// Enforce memory POR configurations.<BR>
+ /// @details
+ /// 0 (ENFORCE_POR_EN) - Enforce memory POR.<BR>
+ /// 1 (ENFORCE_STRETCH_EN) - Enforce memory frequency stretch goal.<BR>
+ /// 2 (ENFORCE_POR_DIS) - Do not enforce POR configurations.<BR>
+ //
+ UINT8 enforcePOR;
+
+ ///
+ /// @brief
+ /// DDR Frequency Limit.
+ /// @details
+ /// Forces a DDR frequency slower than the common tCK detected via SPD.<BR>
+ /// A DDR frequency faster than the common frequency is a config error.<BR>
+ /// Options are 0=AUTO, 1=DDR_800, 3=DDR_1066, 5=DDR_1333, 7=DDR_1600, <BR>
+ /// 9=DDR_1866, 11=DDR_2133, 13=DDR2400.<BR>
+ //
+ UINT8 ddrFreqLimit;
+
+ ///
+ /// @brief
+ /// Channels interleave setting.
+ /// @details
+ /// Valid options are 1, 2, or 3 way interleave. Other values defaults
+ /// to 3 ways interleave.<BR>
+ //
+ UINT8 chInter;
+
+ ///
+ /// @brief
+ /// DIMM types.<BR>
+ /// @details
+ /// 0=RDIMM, 1=UDIMM, 2 = RDIMMandUDIMM or SODIMM, 9=LRDIMM; 10=QRDIMM, 11=NVMDIMM.<BR>
+ //
+ UINT8 dimmTypeSupport;
+
+ ///
+ /// @brief
+ /// CKE Power managment mode.<BR>
+ /// @details
+ /// 0 = Disabled.<BR>
+ /// 1 = APD Enabled, PPD Disabled.<BR>
+ /// 2 = APD Disabled, PPDF Enabled.<BR>
+ /// 3 = APD Disabled, PPDS Enabled.<BR>
+ /// 4 = APD Enabled, PPDF Enabled.<BR>
+ /// 5 = APD Enabled, PPDS Enabled.<BR>
+ //
+ UINT8 ckeThrottling;
+
+ ///
+ /// @brief
+ /// Open Loop Thermal Throttling.
+ /// @details
+ /// (value/100) * 255 / max number of dimms per channel = DIMM_TEMP_THRT_LMT THRT_HI.<BR>
+ //
+ UINT8 olttPeakBWLIMITPercent;
+
+ ///
+ /// @brief
+ /// Bitmapped field for Thermal Throttling Modes.
+ /// @details
+ /// Defined in mem.thermalThrottlingOptions section.<BR>
+ //
+ UINT16 thermalThrottlingOptions;
+
+ ///
+ /// @brief
+ /// Option to manualy enter Temperature refresh value.
+ /// @details
+ /// Select Manual to use value from HalfxRefreshValue, TwoxRefreshValue and
+ /// FourxRefreshValue. Auto for default value in MRC code.<BR>
+ /// 0 = Auto.<BR>
+ /// 1 = Manual option select.<BR>
+ //
+ UINT8 TempRefreshOption;
+
+ ///
+ /// Half X temperature refresh value.
+ //
+ UINT8 HalfxRefreshValue;
+
+ ///
+ /// Two X temperature refresh value.
+ //
+ UINT8 TwoxRefreshValue;
+
+ ///
+ /// Four X temperature refresh value.
+ //
+ UINT8 FourxRefreshValue;
+
+ //
+ // Receive Enable Average Feature
+ //
+ BOOLEAN RecEnDelayAverage;
+
+ ///
+ /// @brief
+ /// Thermal Throttling O/P bits - (High | Mid | Low).<BR>
+ /// @details
+ /// 0= Memhot output disabled,<BR>
+ /// 1 = Memhot on High,<BR>
+ /// 2 = Memhot on High|Mid, <BR>
+ /// 3 = Memhot on High|Mid|Low.<BR>
+ //
+ UINT8 MemHotOuputAssertThreshold;
+
+ ///
+ /// @brief
+ /// Enable/Disable the initialization of THRTMID on TEMPLO.<BR>
+ /// @details
+ /// 0 = THRTMID on TEMPLO disabled,<BR>
+ /// 1 = THRTMID on TEMPLO enabled.<BR>
+ //
+ UINT8 ThrottlingMidOnTempLo;
+
+ ///
+ /// @brief
+ /// Enable/Disable DRAM RAPL.<BR>
+ /// @details
+ /// 0 - disable.<BR>
+ /// 1 - enable.<BR>
+ //
+ UINT8 DramRaplEnable;
+
+ ///
+ /// Multipler of BW_LIMIT_TF when DRAM RAPL is enabled.
+ //
+ UINT8 dramraplbwlimittf;
+
+ ///
+ /// @brief
+ /// Notify PCU to enable/disable DRAM PM of memory controller.<BR>
+ /// @details
+ /// 0 - Disable.<BR>
+ /// 1 - Enable.<BR>
+ //
+ UINT8 CmsEnableDramPm;
+
+ ///
+ /// @brief
+ /// DRAM RAPL Refresh Base.
+ /// @details
+ /// Allows custom tuning of Power scaling by Refresh rate in units of 0.1x
+ /// when DRAM RAPL is enabled.<BR>
+ //
+ UINT8 dramraplRefreshBase;
+
+ ///
+ /// Enable disable per Bit DeSkew Training.
+ //
+ UINT8 perBitDeSkew;
+
+ UINT8 ReservedS214;
+ UINT8 ReservedS215;
+ UINT8 ReservedS86;
+ UINT8 ReservedS216;
+ UINT8 ReservedS217;
+ UINT8 ReservedS218;
+ UINT8 ReservedS219;
+ UINT8 ReservedS220;
+ UINT8 ReservedS221;
+ UINT8 ReservedS222;
+ UINT8 ReservedS223;
+ UINT8 ReservedS224;
+ UINT8 ReservedS225;
+ UINT8 ReservedS226;
+ UINT8 ReservedS227;
+ UINT8 ReservedS228;
+ UINT8 ReservedS229;
+ UINT8 ReservedS230;
+ UINT8 ReservedS231;
+ UINT8 ReservedS232;
+ UINT8 ReservedS233;
+
+ ///
+ /// NVDIMM Factory Reset Clear
+ //
+ UINT8 FactoryResetClear;
+
+ ///
+ /// Enable Backside RMT.
+ //
+ UINT8 enableBacksideRMT;
+
+ ///
+ /// Enable Backside CMD RMT.
+ //
+ UINT8 enableBacksideCMDRMT;
+
+ ///
+ /// Enable NVMDIMM BCOM margining support.
+ //
+ UINT8 enableNgnBcomMargining;
+
+ ///
+ /// @brief
+ /// Training Result Offset function enable or disable.
+ /// @details
+ /// It controls whether to enable the function to offset the final training results or not.<BR>
+ /// Enable - Enables training results to be offset. <BR>
+ /// Disable - Disables this feature; current default is Enable disable<BR>
+
+ //
+ UINT8 trainingResultOffsetFunctionEnable;
+
+ ///
+ /// Platform value to offset the final memory training result of TxDq.
+ //
+ INT16 offsetTxDq;
+
+ ///
+ /// Platform value to offset the final memory training result of RxDq.
+ //
+ INT16 offsetRxDq;
+
+ ///
+ /// Platform value to offset the final memory training result of TxVref.
+ //
+ INT16 offsetTxVref;
+
+ ///
+ /// Platform value to offset the final memory training result of RxVref.
+ //
+ INT16 offsetRxVref;
+
+ ///
+ /// Platform value to offset the final memory training result of CmdAll.
+ //
+ INT16 offsetCmdAll;
+
+ ///
+ /// Platform value to offset the final memory training result of CmdVref.
+ //
+ INT16 offsetCmdVref;
+
+ ///
+ /// Platform value to offset the final memory training result of CtlAll.
+ //
+ INT16 offsetCtlAll;
+
+ ///
+ /// Platform value to offset the final memory training result of RecvEn.
+ //
+ INT16 OffsetRecEn;
+
+ ///
+ /// Rank Margin Test: patten length.
+ //
+ UINT32 rmtPatternLength;
+
+ ///
+ /// Rank Margin Test: patten length extension.
+ //
+ UINT32 rmtPatternLengthExt;
+
+ ///
+ /// Memory RAS: Specifies the number of hours it takes for patrol scrub to scrub all system memory
+ //
+ UINT32 patrolScrubDuration;
+
+ ///
+ /// Enable/Disable Memory RAS die sparing.
+ //
+ UINT8 DieSparing;
+
+ ///
+ /// Memory RAS: Address Range Scrubbing
+ //
+ UINT8 NgnAddressRangeScrub;
+
+ ///
+ /// Number of MemTests loops to execute for legacy MemTest (type 8 and 10), that
+ /// provides the ability of inverting the data pattern in every odd pass for detecting
+ /// opposite polarity faults
+ //
+ UINT16 memTestLoops;
+
+ ///
+ /// CPGC MemTest step bit fields to enable different advanced MemTest options
+ //
+ UINT32 AdvMemTestOptions;
+
+ ///
+ /// Enable/Disable PPR repair during Advanced Memtest
+ //
+ UINT8 AdvMemTestPpr;
+
+ ///
+ /// Retry the Advanced Memtest step after a PPR repair occurs
+ /// This option is useful for testing that the PPR repair was successful, but it adds some latency
+ //
+ UINT8 AdvMemTestRetry;
+
+ ///
+ /// Reset row fail list after executing each Advanced MemTest option
+ /// This option is useful for testing multiple options.
+ //
+ UINT8 AdvMemTestResetList;
+
+ ///
+ /// Set Test Conditions for Advanced Memtest algorithms
+ /// ADV_MEM_TEST_COND_DISABLE - Do not modify test conditions during Advanced Memtest
+ /// ADV_MEM_TEST_COND_AUTO - Modify test conditions automatically based on Advanced Memtest algorithm
+ /// ADV_MEM_TEST_COND_MANUAL - Modify test conditions manually based on AdvMemTestCond input options
+ //
+ UINT8 AdvMemTestCondition;
+
+ ///
+ /// Manually set Vdd level when AdvMemTestCondition = ADV_MEM_TEST_COND_MANUAL
+ /// Specify Vdd in units of mV
+ //
+ UINT16 AdvMemTestCondVdd;
+
+ ///
+ /// Manually set host Write Recovery time when AdvMemTestCondition = ADV_MEM_TEST_COND_MANUAL
+ /// Specify host tWR value in units of tCK. This timing is only applicable in Open Page mode.
+ //
+ UINT8 AdvMemTestCondTwr;
+
+ ///
+ /// Manually set host tREFI time when AdvMemTestCondition = ADV_MEM_TEST_COND_MANUAL
+ /// Specify host tREFI in units of usec. 7800 = 1x refresh rate; 15600 = 0.5x refresh rate
+ //
+ UINT16 AdvMemTestCondTrefi;
+
+ ///
+ /// Manually set Pause time without refresh when AdvMemTestCondition = ADV_MEM_TEST_COND_MANUAL
+ /// Specify the Pause time in units of msec. It is applied between write and read steps to test data retention.
+ //
+
+ UINT32 AdvMemTestCondPause;
+ ///
+ /// Indicate the number of Ranks that will be tested in the system. A value of 0 will test all Ranks
+ ///
+ //
+ UINT8 AdvMemTestRankListNumEntries;
+
+ ///
+ /// The list of Rank addresses in the sysem that will execute AdvMemTest
+ //
+ AdvMemTestRankData AdvMemTestRankList[ADV_MT_LIST_LIMIT];
+
+ UINT8 Reserved0;
+ UINT8 Reserved1;
+ UINT8 Reserved2;
+ UINT32 Reserved3;
+ UINT32 Reserved4;
+ UINT8 Reserved5;
+ UINT8 Reserved6;
+ ///
+ /// Low 16 bits of the data scrambling seed.
+ //
+ UINT16 scrambleSeedLow;
+
+ ///
+ /// High 16 bits of the data scrambling seed
+ //
+ UINT16 scrambleSeedHigh;
+
+ ///
+ /// @brief
+ /// ADR: Enable/Disable Async DRAM Refresh(ADR) feature<BR>
+ /// @details
+ /// 0 - Disable.<BR>
+ /// 1 - Enable.<BR>
+ //
+ UINT8 ADREn;
+
+ ///
+ /// @brief
+ /// ADR: Enable/Dsiable Legacy ADR Async DRAM Refresh(ADR) feature<BR>
+ /// @details
+ /// 0 - Disable.<BR>
+ /// 1 - Enable.<BR>
+ //
+ UINT8 LegacyADRModeEn;
+
+ ///
+ /// @brief
+ /// ADR: Minimum memory size assigned as system memory when only JEDEC NVDIMMs are present<BR>
+ /// @details
+ /// 2 - 2GB.<BR>
+ /// 4 - 4GB.<BR>
+ /// 6 - 6GB.<BR>
+ /// 8 - 8GB.<BR>
+ //
+ UINT8 MinNormalMemSize;
+
+ ///
+ /// @brief
+ /// ADR: Data Save Mode for ADR. <BR>
+ /// @details
+ /// 0=Disabled, <BR>
+ /// 1=Batterybacked, <BR>
+ /// 2=NVDIMM.<BR>
+ //
+ UINT8 ADRDataSaveMode;
+
+ ///
+ /// @brief
+ /// ADR: Use the PCH_PM_STS register as ADR recovery indicator.<BR>
+ /// @details
+ /// 0 - Disable.<BR>
+ /// 1 - Enable.<BR>
+ //
+ UINT8 check_pm_sts;
+
+ ///
+ /// @brief
+ /// ADR: Use the PlatformDetectADR OEM hook function as ADR recovery indicator.<BR>
+ /// @details
+ /// 0 - Disable.<BR>
+ /// 1 - Enable.<BR>
+ //
+ UINT8 check_platform_detect;
+
+ ///
+ /// @brief
+ /// Memory RAS: Normal operation duration within sparing interval.
+ //
+ UINT16 normOppIntvl;
+
+ ///
+ /// @brief
+ /// SM Bus Clock Frequency- see SMB_CLOCK_FREQUENCY.<BR>
+ /// @details
+ /// 0 - SMB_CLK_100K.<BR>
+ /// 1 - SMB_CLK_400K. <BR>
+ /// 2 - SMB_CLK_700K.<BR>
+ /// 3 - SMB_CLK_1M.<BR>
+ //
+ SMB_CLOCK_FREQUENCY SpdSmbSpeed;
+
+ ///
+ /// @brief
+ /// Enable(1)/Disable(0) SPD data Print.<BR>
+ /// @details
+ /// 0 - Disable.<BR>
+ /// 1 - Enable.<BR>
+ //
+ UINT8 SpdPrintEn;
+
+ ///
+ /// @brief
+ /// Pirnt length of SPD data.<BR>
+ /// @details
+ /// 0 - AUTO(512 for DDR4, 1024 for DDR5).<BR>
+ /// 256.<BR>
+ /// 512.<BR>
+ ///
+ UINT16 SpdPrintLength;
+
+ ///
+ /// Socket setup configuration.
+ //
+ struct ddrSocketSetup socket[MAX_SOCKET];
+
+ ///
+ /// Memory timing settings.
+ //
+ struct memTiming inputMemTime;
+
+ UINT32 XMPChecksum[MAX_SOCKET][MAX_CH][MAX_DIMM];
+
+ UINT32 Reserved7;
+
+ UINT32 Reserved8;
+
+ UINT32 Reserved9;
+
+ ///
+ /// @brief
+ /// Custom tuning multiplier of Refresh rate from 2.0x to 4.0x in units of 0.1x
+ //
+ UINT8 customRefreshRate;
+
+ ///
+ /// @brief
+ /// Enable Mirror on entire memory for TAD0.<BR>
+ /// @details
+ /// 0 - Disable.<BR>
+ /// 1 - Enable.<BR>
+ //
+ UINT8 partialmirrorsad0;
+
+ ///
+ /// Size of each partial mirror to be created in order.
+ //
+ UINT16 partialmirrorsize[MAX_PARTIAL_MIRROR];
+
+ ///
+ /// @brief
+ /// Imitate behavior of UEFI based Address Range Mirror with setup option.
+ /// @details
+ /// It controls whether to enable partial mirror in 1LM and 2LM or not.
+ //
+ UINT8 partialMirrorUEFI;
+
+ ///
+ /// @brief
+ /// Numerator of the mirror ratio.<BR>
+ /// @details
+ /// Given the Numerator (N) and Denominator (D) returned by this function, and<BR>
+ /// the total memory size (T), the mirror size (M) should be computed as follows:<BR>
+ /// M = (T * N) / D<BR>
+ /// MirroredAmountAbove4GB is the amount of available memory above 4GB that needs to be mirrored
+ /// measured in basis point (hundredths of percent e.g. 12.75% = 1275).
+ /// In a multi-socket system, platform is required to distribute the mirrored memory ranges such that the
+ /// amount mirrored is approximately proportional to the amount of memory on each NUMA node. E.g. on
+ /// a two node machine with 64GB on node 0 and 32GB on node 1, a request for 12GB of mirrored memory
+ /// should be allocated with 8GB of mirror on node 0 and 4GB on node 1.<BR>
+ UINT32 partialmirrorpercent;
+
+ ///
+ /// @brief
+ /// Partial mirror status.<BR>
+ /// @details
+ /// MIRROR_STATUS_SUCCESS 0<BR>
+ /// MIRROR_STATUS_MIRROR_INCAPABLE 1<BR>
+ /// MIRROR_STATUS_VERSION_MISMATCH 2<BR>
+ /// MIRROR_STATUS_INVALID_REQUEST 3<BR>
+ /// MIRROR_STATUS_UNSUPPORTED_CONFIG 4<BR>
+ /// MIRROR_STATUS_OEM_SPECIFIC_CONFIGURATION 5<BR>
+ //
+ UINT8 partialmirrorsts;
+
+ ///
+ /// Immediate failover enable or disable when mirror scrub reads a uncorrected error.
+ //
+ UINT8 ImmediateFailoverAction;
+
+ ///
+ /// Number of times to loop through RMT to test the DLL Reset.
+ //
+ UINT8 dllResetTestLoops;
+
+ ///
+ /// @brief
+ /// Flags to enable(1)/disable(0) memory training steps in MRC flow.
+ /// The following are bit to MRC training step map.<BR>
+ /// @details
+ /// MF_X_OVER_EN BIT0;<BR>
+ /// MF_SENSE_AMP_EN BIT1;<BR>
+ /// MF_E_CMDCLK_EN BIT2;<BR>
+ /// MF_REC_EN_EN BIT3;<BR>
+ /// MF_RD_DQS_EN BIT4;<BR>
+ /// MF_WR_LVL_EN BIT5;<BR>
+ /// MF_WR_FLYBY_EN BIT6;<BR>
+ /// MF_WR_DQ_EN BIT7;<BR>
+ /// MF_CMDCLK_EN BIT8;<BR>
+ /// MF_RD_ADV_EN BIT9;<BR>
+ /// MF_WR_ADV_EN BIT10;<BR>
+ /// MF_RD_VREF_EN BIT11;<BR>
+ /// MF_WR_VREF_EN BIT12;<BR>
+ /// MF_RT_OPT_EN BIT13;<BR>
+ /// MF_RX_DESKEW_EN BIT14;<BR>
+ /// MF_TX_DESKEW_EN BIT14;<BR>
+ /// MF_TX_EQ_EN BIT15;<BR>
+ /// MF_IMODE_EN BIT16;<BR>
+ /// MF_EARLY_RID_EN BIT17;<BR>
+ /// MF_DQ_SWIZ_EN BIT18;<BR>
+ /// MF_LRBUF_RD_EN BIT19;<BR>
+ /// MF_LRBUF_WR_EN BIT20;<BR>
+ /// MF_RANK_MARGIN_EN BIT21;<BR>
+ /// MF_E_WR_VREF_EN BIT22;<BR>
+ /// MF_E_RD_VREF_EN BIT23;<BR>
+ /// MF_L_RD_VREF_EN BIT24;<BR>
+ /// MF_MEMINIT_EN BIT25;<BR>
+ /// MF_NORMAL_MODE_EN BIT27;<BR>
+ /// MF_CMD_VREF_EN BIT28;<BR>
+ /// MF_L_WR_VREF_EN BIT29;<BR>
+ /// MF_MEMTEST_EN BIT30;<BR>
+ /// MF_E_CTLCLK_EN BIT31.<BR>
+ //
+ UINT32 memFlows;
+
+ ///
+ /// @brief
+ /// Extension of flags to enable(1)/disable(0) memory training steps in MRC flow.<BR>
+ /// @details
+ /// MF_EXT_RX_CTLE_EN BIT0<BR>
+ /// MF_EXT_PXC_EN BIT1<BR>
+ /// MF_EXT_CMD_NORM_EN BIT2<BR>
+ /// MF_EXT_LRDIMM_BKSIDE_EN BIT3<BR>
+ /// MF_EXT_CHECK_POR BIT6<BR>
+ /// MF_EXT_MMRC_RUN BIT7<BR>
+ /// MF_EXT_THROTTLING_EARLY BIT8<BR>
+ /// MF_EXT_THROTTLING BIT9<BR>
+ /// MF_EXT_POST_TRAINING BIT10<BR>
+ /// MF_EXT_E_CONFIG BIT11<BR>
+ /// MF_EXT_L_CONFIG BIT12<BR>
+ /// MF_EXT_MCODT_EN BIT14<BR>
+ /// MF_EXT_MCRON_EN BIT15<BR>
+ /// MF_EXT_DIMMRON_EN BIT16<BR>
+ /// MF_EXT_CACLK_BACKSIDE_EN BIT17<BR>
+ /// MF_DQ_SWIZ_X16_EN BIT18<BR>
+ /// MF_EXT_TCO_COMP_EN BIT19<BR>
+ /// MF_EXT_TX_SLEW_RATE_EN BIT20<BR>
+ /// MF_EXT_INIT_MEM_EN BIT21<BR>
+ /// MF_EXT_CMD_TX_EQ_EN BIT22<BR>
+ /// MF_EXT_RCOMP_STAT_LEG BIT23<BR>
+ /// MF_EXT_DDJC_EN BIT24<BR>
+ /// MF_EXT_RX_DFE_EN BIT25<BR>
+ /// MF_EXT_CSCLK_EN BIT26<BR>
+ /// MF_EXT_CSCLK_BACKSIDE_EN BIT27<BR>
+ /// MF_EXT_CACLK_EN BIT28<BR>
+ /// MF_X_OVER_HWFSM_EN BIT29<BR>
+ /// MF_EXT_INIT_CMI_EN BIT30<BR>
+ /// MF_EXT_QxCA_CLK_EN BIT31<BR>
+ //
+ UINT32 memFlowsExt;
+
+ //
+ // Addtional storage for memory flows
+ //
+
+ UINT32 memFlowsExt2;
+ UINT32 memFlowsExt3;
+
+ ///
+ /// @brief
+ /// Write Preamble timing.<BR>
+ /// @details
+ /// 0 = PREAMBLE_1TCLK;<BR>
+ /// 1 = PREAMBLE_2TCLK;<BR>
+ /// 2 = PREAMBLE_3TCLK;<BR>
+ /// 3 = PREAMBLE_4TCLK.<BR>
+ //
+ UINT8 writePreamble;
+
+ ///
+ /// @brief
+ /// Read Preamble timing.<BR>
+ /// @details
+ /// 0 = PREAMBLE_1TCLK;<BR>
+ /// 1 = PREAMBLE_2TCLK;<BR>
+ /// 2 = PREAMBLE_3TCLK;<BR>
+ /// 3 = PREAMBLE_4TCLK.<BR>
+ //
+ UINT8 readPreamble;
+
+ ///
+ /// Enable extended range for DRAM RAPL.
+ //
+ UINT8 DramRaplExtendedRange;
+
+ ///
+ /// @brief
+ /// Memory RAS: Threshold value for logging Correctable Errors(CE).
+ /// @details
+ /// Threshold of 10 logs 10th CE, "All" logs every CE, and "None"
+ /// means no CE logging. All and None are not valid with Rank Sparing.
+ //
+ UINT16 spareErrTh;
+
+ ///
+ /// Memory RAS: Enable/Disable New 48B SDDC.<BR>
+ //
+ UINT8 NsddcEn;
+
+
+ ///
+ /// Memory RAS: Enable/Disable enhanced sddc.<BR>
+ //
+ UINT8 EsddcEn;
+
+ ///
+ /// Disable - Turns ON Column Correction feature. Enable - Turns OFF Column Correction feature
+ //
+ UINT8 ColumnCorrectionDisable;
+
+ ///
+ /// Memory RAS: Enable/Disable leaky bucket time window based interface.<BR>
+ //
+ UINT8 leakyBktTimeWindow;
+
+ ///
+ /// Leaky bucket low mask position.
+ //
+ UINT8 leakyBktLo;
+
+ ///
+ /// Leaky bucket high mask position.
+ //
+ UINT8 leakyBktHi;
+
+ ///
+ /// Leaky bucket time window based interface Hour(0 - 3744).
+ //
+ UINT16 leakyBktHour;
+
+ ///
+ /// Leaky bucket time window based interface Minute" (0 - 60).
+ //
+ UINT8 leakyBktMinute;
+
+ ///
+ /// Number of spare ranks per channel.
+ //
+ UINT8 spareRanks;
+
+ ///
+ /// Controls if NVDIMMs are interleaved together or not.
+ //
+ UINT8 interNVDIMMS;
+
+ ///
+ /// Control if BIOS will perform NVDIMM Restore operation.
+ //
+ UINT8 restoreNVDIMMS;
+
+ ///
+ /// Control if BIOS will perform NVDIMM erase & ARM operations.
+ //
+ UINT8 eraseArmNVDIMMS;
+
+ ///
+ /// Cmd setup percent offset for late cmd traning result. The possible
+ /// values are from 0 to 100.
+ //
+ UINT8 cmdSetupPercentOffset;
+
+ ///
+ /// @brief
+ /// Memory RAS. Power-up DDR4 Post Package Repair (PPR) type.<BR>
+ /// @details
+ /// 0 - PPR disabled.<BR>
+ /// 1 - PPR type hard.<BR>
+ /// 2 - PPR type soft.<BR>
+ //
+ UINT8 pprType;
+
+ ///
+ /// @brief
+ /// PPR Address.
+ /// @details
+ /// Buffer to hold DRAM Address that need to be repaired by PPR (Post Package Repair).<BR>
+ /// Platform Sample Implementation: <BR>
+ /// RAS code uses pprAddrSetup to cause MRC to launch PPR (Post Package Repair) on
+ /// a subsequent boot. RAS code passes failed DRAM information into pprAddrSetup
+ /// via the UEFI variable PPR_ADDR_VARIABLE.
+ //
+ PPR_ADDR_MRC_SETUP pprAddrSetup[MAX_PPR_ADDR_ENTRIES];
+
+ ///
+ /// IMC interleave setting (within a socket). Valid options are 1 or 2 way interleave.
+ //
+ UINT8 imcInter;
+
+ ///
+ /// Enable/Disable support for JEDEC RCD v2.0+ One Rank Timing Mode.
+ //
+ UINT8 oneRankTimingModeEn;
+
+ struct ReservedS193 ReservedS193;
+
+ ///
+ /// @brief
+ /// Volatile Memory Mode
+ /// @details
+ /// 0 - 1LM;<BR>
+ /// 1 - 2LM;<BR>
+ //
+ UINT8 volMemMode;
+
+ ///
+ /// For 2LM, the caching type. Only valid if volMemMode is 2LM
+ /// 0 - DDR caching DDRT.
+ //
+ UINT8 CacheMemType;
+
+ ///
+ /// @brief
+ /// Size of channel DDR to use as 2LM cache.
+ /// @details
+ /// Size of channel DDR to use as 2LM cache when Volatile Memory Mode
+ /// under Crystal Ridge is 1LM+2LM.
+ //
+ UINT8 DdrCacheSize;
+
+ ///
+ /// Caching contorl for AppDirect.
+ //
+ UINT8 PmemCaching;
+
+ ///
+ /// eADR support.
+ //
+ UINT8 EadrSupport;
+ UINT8 EadrCacheFlushMode;
+
+ ///
+ /// Enable or disable fADR support.
+ //
+ UINT8 FadrSupport;
+
+ ///
+ /// Memory interleave mode for 1LM.
+ //
+ UINT8 memInterleaveGran1LM;
+
+ ///
+ /// Enable or disable biased 2-way near memory cache.
+ //
+ UINT8 EnableTwoWayNmCache;
+
+ ///
+ /// A 10-bit mask to control the bias counter ratio.
+ //
+ UINT16 NonPreferredWayMask;
+
+ ///
+ /// Reads are issued to the non-preferred or preferred way first.
+ //
+ UINT8 PreferredReadFirst;
+
+ ///
+ /// Enable or disable boot-time fast zero memory support.
+ //
+ UINT8 FastZeroMemSupport;
+
+ ///
+ /// Enable/Disable DDRT memory power saving.
+ //
+ UINT8 DdrtMemPwrSave;
+
+ ///
+ /// @brief
+ /// Memory RAS: Patrol Scrub Address Mode.<BR>
+ /// @details
+ /// Selects the address mode between System Physical Address (or) Reverse Address.<BR>
+ /// 0 - PATROL_SCRUB_REVERSE_ADDR,<BR>
+ /// 1 - PATROL_SCRUB_SPA, <BR>
+ //
+ UINT8 patrolScrubAddrMode;
+
+ ///
+ /// @brief
+ /// Self Refresh control programming.
+ /// @details
+ /// Memory power managment feature:<BR>
+ /// Select manual or auto programming Self Refresh controls at Load Line point
+ /// 0/1/2/3 registers.<BR>
+ /// 0 - auto - MRC determines the value;<BR>
+ /// 1 - manual - use value from user Setup.<BR>
+ //
+ UINT8 SrefProgramming;
+
+ ///
+ /// @brief
+ /// Opportunistic self-refresh setting.
+ /// @details
+ /// Memory power managment feature:<BR>
+ /// opportunistic self-refresh setting in Self Refresh controls at Load Line point
+ /// 0/1/2/3 registers.<BR>
+ /// 0 - disable;<BR>
+ /// 1 - enable.<BR>
+ //
+ UINT8 OppSrefEn;
+
+ ///
+ /// @brief
+ /// Master DLLs (MDLL) setting.
+ /// @details
+ /// Memory power managment feature:<BR>
+ /// Master DLLs (MDLL) setting in Self Refresh controls at Load Line point 0/1/2/3 registers.<BR>
+ /// When 0 - Master DLLs (MDLL) cannot be turned off in Self Refresh.<BR>
+ /// When 1 - Master DLLs (MDLL) can be turned off in Self Refresh.<BR>
+ //
+ UINT8 MdllOffEn;
+
+ ///
+ /// @brief
+ /// Enables or disables Self Refresh in PkgC flow.<BR>
+ /// @details
+ /// Memory power managment feature.<BR>
+ /// 0 - Didable.<BR>
+ /// 1 - Enable.<BR>
+ //
+ UINT8 PkgcSrefEn;
+
+ ///
+ /// @brief
+ /// Configures CK behavior during self-refresh.<BR>
+ /// @details
+ /// 0 - CK is driven during self refresh.<BR>
+ /// 2 - CK is pulled low during self refresh.<BR>
+ //
+ UINT8 CkMode;
+
+ ///
+ /// @brief
+ /// CKE Registers Programming Mode.
+ /// @details
+ /// Select manual or auto programming registers Control for CKE (DRAM powerdown modes).
+ /// at Load Line point 0/1/23.<BR>
+ /// 0 - auto - MRC determines the value.<BR>
+ /// 1 - manual - use value from user Setup.<BR>
+ //
+ UINT8 CkeProgramming;
+
+ ///
+ /// @brief
+ /// CKE Idle Timer.
+ /// @details
+ /// Set the number of rank idle cycles that causes CKE power-down entrance.
+ /// The number of idle cycles (in DCLKs) are based from command CS assertion.
+ /// It is important to program this parameter to be greater than roundtrip
+ /// latency parameter in order to avoid the CKE de-assertion sooner than data return.
+ //
+ UINT8 CkeIdleTimer;
+
+ ///
+ /// @brief
+ /// CKE Active Power Down Mode for DDR4 DIMMs.<BR>
+ /// @details
+ /// 0 = APD is disabled.<BR>
+ /// 1 = APD is enabled.<BR>
+ //
+ UINT8 ApdEn;
+
+ ///
+ /// @brief
+ /// CKE Precharge Power Down (PPD).<BR>
+ /// @details
+ /// 0 = PPD is disabled.<BR>
+ /// 1 = PPD is enabled.<BR>
+ //
+ UINT8 PpdEn;
+
+ ///
+ /// @brief
+ /// CKE Active Power Down Mode for DDR-T DIMMs.<BR>
+ /// @details
+ /// 0 = APD is disabled.<BR>
+ /// 1 = APD is enabled.<BR>
+ //
+ UINT8 DdrtCkeEn;
+
+ ///
+ /// @brief
+ /// Turn off DDRIO data DLL in CKE Power Down or OppSR low power mode.<BR>
+ /// @details
+ /// 0 = Do not turn off data DLL.<BR>
+ /// 1 = Turn off data DLL.<BR>
+ //
+ UINT8 DataDllOff;
+
+ ///
+ /// @brief
+ /// RAS: Enable/Disable Extended ADDDC sparing.<BR>
+ /// @details
+ /// 0 = Disabled.<BR>
+ /// 1 = Enabled.<BR>
+ //
+ UINT8 ExtendedADDDCEn;
+
+ ///
+ /// @brief
+ /// DDRT Defeature Enable/Disable BLOCK GNT2CMD1CYC.<BR>
+ /// @details
+ /// 0 = Disabled.<BR>
+ /// 1 = Enabled.<BR>
+ //
+ UINT8 Blockgnt2cmd1cyc;
+
+ ///
+ /// @brief
+ /// Enable/Disable NVMDIMM OPPRD.<BR>
+ /// @details
+ /// 0 = DDRT RPQ Reads will not be scheduled in DDR4 mode DDRT Underfill Reads
+ /// will not be scheduled in DDR4 mode.<BR>
+ /// 1 = DDRT RPQ Reads will be scheduled in DDR4 mode. GNTs continue to be blocked
+ /// in DDR4 mode. This should be set for DDRT 2N mode.DDRT Underfill Reads will
+ /// be scheduled in DDR4 mode. GNTs continue to be blocked in DDR4 mode This
+ /// bit should be set for DDRT 2N mod.<BR>
+ //
+ UINT8 Disddrtopprd;
+
+ UINT16 Reserved10;
+
+ ///
+ /// @brief
+ /// NGNVM DIMM Secure Erase Unit, Erases the persistent memory region of the selected DIMMs".<BR>
+ /// @details
+ /// 0 - Erase DIMMs according to setting of setSecureEraseSktCh.<BR>
+ // 1 - enable Erase All DIMMs, Erases the persistent memory region of all NVMDIMMs in the system".<BR>
+ UINT8 setSecureEraseAllDIMMs;
+
+ ///
+ /// @brief
+ /// Enable/Disable secure erase of persistent memory region of NVMDIMM.<BR>
+ /// @details
+ /// 0 = Disable erasing the persistent memory region of NVMDIMM in <Channel 0, Memory controller 0, Socket 0.<BR>
+ /// 1 = Enable erasing the persistent memory region of NVMDIMM in Channel 0, Memory controller 0, Socket 0.<BR>
+ //
+ UINT8 setSecureEraseSktCh[MAX_SOCKET][MAX_CH];
+
+ ///
+ /// @brief
+ /// Select Crystal Ridge FastGo QoS Configuration Profiles.<BR>
+ /// @details
+ /// CR_FASTGO_DEFAULT 0;<BR>
+ /// CR_FASTGO_DISABLE 1;<BR>
+ /// CR_FASTGO_DISABLE_MLC_SQ_THRESHOLD_5 2;<BR>
+ /// CR_FASTGO_DISABLE_MLC_SQ_THRESHOLD_6 3;<BR>
+ /// CR_FASTGO_DISABLE_MLC_SQ_THRESHOLD_8 4;<BR>
+ /// CR_FASTGO_DISABLE_MLC_SQ_THRESHOLD_10 5;<BR>
+ /// CR_FASTGO_AUTOMATIC 6;<BR>
+ /// CR_FASTGO_LAST_OPTION CR_FASTGO_AUTOMATIC;<BR>
+ /// CR_FASTGO_KNOB_DEFAULT CR_FASTGO_AUTOMATIC.<BR>
+ //
+ UINT8 FastGoConfig;
+
+ ///
+ /// @brief
+ /// Non-Volatile Memory DIMM baseline performance settings depending on the workload behavior.<BR>
+ /// @details
+ /// 0 = BW Optimized.<BR>
+ /// 1 = Latency Optimized.<BR>
+ //
+ UINT8 NvmdimmPerfConfig;
+
+ ///
+ /// @brief
+ /// Memory topology of each channel per socket.<BR>
+ /// @details
+ /// 0 = DaisyChainTopology.<BR>
+ /// 1 = InvSlotsDaisyChainTopology.<BR>
+ /// 2 = TTopology.<BR>
+ //
+ EFI_MEMORY_TOPOLOGY_TYPE MemoryTopology[MAX_SOCKET][MAX_CH];
+
+ ///
+ /// @brief
+ /// Memory connector type of each channel per socket.<BR>
+ /// @details
+ /// 0 = DimmConnectorPth.<BR>
+ /// 1 = DimmConnectorSmt.<BR>
+ /// 2 = DimmConnectorMemoryDown.<BR>
+ //
+ EFI_MEMORY_DIMM_CONNECTOR_TYPE MemoryConnectorType[MAX_SOCKET][MAX_CH];
+
+ ///
+ /// @brief
+ /// Enable/Disable the App Direct Memory Hole.<BR>
+ /// @details
+ /// 0 = disable.<BR>
+ /// 1 = enable.<BR>
+ //
+ UINT8 AppDirectMemoryHole;
+
+ ///
+ /// @brief
+ /// Enable/disable Latch System Shutdown (LSS) of all enabled NVDIMMs.<BR>
+ /// @details
+ /// LSS is supposed to be done by the persistent memory driver in OS using ACPI DSM function,
+ /// before any write to persistent memory is done. BIOS knob is implemented to enable Latch LSS
+ /// for operating systems that would not call DSM. Enabling latch twice is not a problem so the BIOS
+ /// action does not colide with OSes that use DSM to enable latch.<BR>
+ /// 0 = Disable.<BR>
+ /// 1 = Enable.<BR>
+ //
+ UINT8 LatchSystemShutdownState;
+
+ ///
+ /// @brief
+ /// Select snoopy mode for 2LM.
+ /// @details
+ /// Set to 0 to Enables new 2LM specific feature to
+ /// avoid directory updates to far-memory from non-NUMA optimized workloads.<BR>
+ /// 0 = Enable eliminating directory in far memory.<BR>
+ /// 1 = Disable eliminating directory in far memory.<BR>
+ //
+ UINT8 EliminateDirectoryInFarMemory;
+
+ ///
+ /// @brief
+ /// Power Cycle Policy on NVM Surprise Clock Stop.
+ /// @details
+ /// Enable/Disable power cycle policy when NVMDIMM receive surprise clock stop.
+ //
+ UINT8 NvmdimmPowerCyclePolicy;
+
+ ///
+ /// @brief
+ /// NV DIMM Energy Policy Management.<BR>
+ /// @details
+ /// 1 = Setting Energy Policy to Device Managed.<BR>
+ /// 2 = Setting Energy Policy to Host Managed.<BR>
+ //
+ UINT8 NvDimmEnergyPolicy;
+
+ ///
+ /// @brief
+ /// Option to force Rx DFE enabled or disabled.<BR>
+ /// @details
+ /// 0 = Disable Rx DFE.<BR>
+ /// 1 = Enable Rx DFE.<BR>
+ /// 2 = Auto. MRC code detemines if enable or disable.<BR>
+ //
+ UINT8 RxDfeEn;
+
+ ///
+ /// @brief
+ /// Enable/Disable TX Rise Fall Slew Rate Training. <BR>
+ /// @details
+ /// 0 = Dsiable.<BR>
+ /// 1 = Enable.<BR>
+ /// 2 = AUTO, will enable if DDR Freq >= 2933.<BR>
+ //
+ UINT8 TxRiseFallSlewRate;
+
+ ///
+ /// @brief
+ /// Forces PXC (Phase-based Crosstalk Cancellation) initialization.
+ /// @details
+ /// Forces PXC (Phase-based Crosstalk Cancellation) initialization even if
+ /// PXC training is not enabled.<BR>
+ /// 0 = Disable.<BR>
+ /// 1 = Enable.<BR>
+ //
+ UINT8 ForcePxcInit;
+
+ ///
+ /// @brief
+ /// CMI Initialize Option.<BR>
+ /// @details
+ /// 0 = Initialize with desired credit.<BR>
+ /// 1 = Inialize with default(Reset Value)credit.<BR>
+ //
+ UINT8 CmiInitOption;
+
+ ///
+ /// @brief
+ /// Snoopy mode for AD.
+ /// @details
+ /// Snoopy mode for AD: Disable/Enable new AD specific feature to avoid directory
+ /// updates to DDRT memory from non-NUMA optimized workloads.<BR>
+ /// 0 = Disable.<BR>
+ /// 1 = Enable.<BR>
+ //
+ UINT8 DisableDirForAppDirect;
+
+ ///
+ /// @brief
+ /// Enable/Disable Crystal Ridge MediaStatus Exception.<BR>
+ /// @details
+ /// 0 = Disable.<BR>
+ /// 1 = Enable.<BR>
+ //
+ UINT8 NvmMediaStatusException;
+
+ ///
+ /// @brief
+ /// Select Crystal Ridge QoS tuning recipes.<BR>
+ /// @details
+ /// 0 = Enables tuning recipe 1 for CR QoS knobs <BR>
+ /// (recommended for 2-2-2 memory configuration in AD);<BR>
+ /// 1 = Enables tuning recipe 2 for CR QoS knobs<BR>
+ /// (recommended for other memory configuration in AD);<BR>
+ /// 2 = Enables tuning recipe 3 for CR QoS knobs <BR>
+ /// (recommended for 1 DIMM per channel config);<BR>
+ /// 3 = Disable CR QoS feature.<BR>
+ //
+ UINT8 NvmQos;
+
+ ///
+ /// @brief
+ /// Disable/Enable using extended Type 17 SMBIOS Structures.<BR>
+ /// @details
+ /// 0 = Disable.<BR>
+ /// 1 = Enable .<BR>
+ //
+ UINT8 ExtendedType17;
+
+ ///
+ /// @brief
+ /// Gen 2 Intel Optane DC Persistent Memory (DCPMM) Average Power Limit (in mW)".
+ /// @details
+ /// Valid range for power limit starts from 10000mW and must be a multiple of 250mW."
+ //
+ UINT16 DcpmmAveragePowerLimit;
+
+ ///
+ /// @brief
+ /// Gen 2 DCPMM Average Power Time Constant for Turbo Mode support (in mSec).
+ /// @details
+ /// This value is used as a base time window for power usage measurements.
+ //
+ UINT8 DcpmmAveragePowerTimeConstant;
+
+
+ ///
+ /// @brief
+ /// Gen 2 DCPMM Average Power Time Constant for Memory Bandwidth Boost Feature support(in mSec).
+ /// @details
+ /// This value is used as a base time window for power usage measurements.
+ //
+ UINT32 DcpmmMbbAveragePowerTimeConstant;
+
+ ///
+ /// @brief
+ /// Gen 2 DCPMM Turbo Mode/Memory Bandwidth Boost Feature Enable.<BR>
+ /// @details
+ /// 0 = Disable.<BR>
+ /// 1 = Enable.<BR>
+ //
+ UINT8 DcpmmMbbFeature;
+
+ ///
+ /// @brief
+ /// DCPPM Power limit in mW for Turbo Mode/Memory Bandwidth Boost Feature.
+ /// @details
+ /// DCPPM Power limit in mW used for limiting the Turbo Mode/Memory Bandwidth Boost power consumption (Valid
+ /// range starts from 15000mW).
+ //
+ UINT16 DcpmmMbbMaxPowerLimit;
+
+ ///
+ /// @brief
+ /// Select LSx (LSI/LSR/LSW) ACPI method implementation.<BR>
+ /// @details
+ /// 0 = Software SMI.<BR>
+ /// 1 = ASL.<BR>
+ //
+ UINT8 LsxImplementation;
+
+ ///
+ /// @brief
+ /// Set Smbus maximum access time<BR>
+ /// @details
+ /// Maximum amount of time (ms) UEFI mgmt driver is allowed to use the SMBus.<BR>
+ //
+ UINT32 NvdimmSmbusMaxAccessTime;
+
+ ///
+ /// @brief
+ /// Set Smbus release delay.<BR>
+ /// @details
+ /// Delay time (ms) before releasing after UEFI mgmt driver requests SMBus release.<BR>
+ //
+ UINT32 NvdimmSmbusReleaseDelay;
+
+ ///
+ /// @brief
+ /// Controls Mailbox structures in the NFIT
+ /// @details
+ /// 0 - Publish Mailbox structures in the NFIT
+ /// 1 - Do not publish Mailbox structures in the NFIT
+ ///
+ UINT8 NfitPublishMailboxStructsDisable;
+
+ ///
+ /// @brief
+ /// Enforce memory population POR configurations.<BR>
+ /// @details
+ /// 0 (ENFORCE_POPULATION_POR_DIS) - Do not enforce memory population POR.<BR>
+ /// 1 (ENFORCE_POPULATION_POR_ENFORCE_SUPPORTED) - Enforce supported memory populations.<BR>
+ /// 2 (ENFORCE_POPULATION_POR_ENFORCE_VALIDATED) - Enforce validated memory populations.<BR>
+ //
+ UINT8 EnforcePopulationPor;
+
+ ///
+ /// Configure Stagger Host Refresh feature
+ ///
+ UINT8 TrefiPerChannel;
+ UINT8 TrefiNumofRank;
+ UINT16 TrefiDelay;
+
+ //
+ // DFE Path Finding
+ //
+ UINT8 EnableTapSweep;
+
+ INT8 DfeGainBias;
+
+ INT8 Tap1Start;
+ INT8 Tap1End;
+ UINT8 Tap1Size;
+
+ INT8 Tap2Start;
+ INT8 Tap2End;
+ UINT8 Tap2Size;
+
+ INT8 Tap3Start;
+ INT8 Tap3End;
+ UINT8 Tap3Size;
+
+ INT8 Tap4Start;
+ INT8 Tap4End;
+ UINT8 Tap4Size;
+
+ ///
+ /// @brief
+ /// Training Comp Options Values.
+ /// @details
+ /// Options for issuing a Comp. cycle (RCOMP) at specific points in training.<BR>
+ /// 0 - One RCOMP cycle only on PHY Init (MMRC Init);<BR>
+ /// 1 - One RCOMP cycle after every JEDEC Init;<BR>
+ /// 2 - One RCOMP cycle right before every training step;<BR>
+ //
+ UINT8 TrainingCompOptions;
+
+ ///
+ /// @brief
+ /// Periodic Rcomp Control.
+ /// @details
+ /// Enable/Disable memory periodic Rcomp with PCU.<BR>
+ /// 0 - Disable;<BR>
+ /// 1 - Enable;<BR>
+ /// 2 - Auto;<BR>
+ //
+ UINT8 PeriodicRcomp;
+
+ ///
+ /// @brief
+ /// Periodic Rcomp Interval.
+ /// @details
+ /// Interval of periodic Rcomp controlled by PCU.<BR>
+ //
+ UINT8 PeriodicRcompInterval;
+
+ ///
+ /// @brief
+ /// Use SMBUS for early MRW commands
+ /// @details
+ /// Option to require all MRW commands to be sent over SMBUS until QCA training is complete<BR>
+ //
+ BOOLEAN UseSmbusForMrwEarly;
+
+ ///
+ /// @brief
+ /// Enable/Disable AEP DIMM Not Supported Exception.<BR>
+ /// @details
+ /// 0 = Disable.<BR>
+ /// 1 = Enable.<BR>
+ //
+ UINT8 AepNotSupportedException;
+
+ //
+ // Memory Boot Health Check
+ //
+ MEM_BOOT_HEALTH_CONFIG MemBootHealthConfig;
+
+ /// @brief
+ /// Select between Panic/High Watermark of Auto or High or Low.<BR>
+ /// @details
+ /// 0 = Auto
+ /// 1 = High<BR>
+ /// 2 = Low<BR>
+ UINT8 PanicWm;
+
+ /// @brief
+ /// Enable/Disable LRDIMM DB DFE.<BR>
+ /// @details
+ /// 0 - Disable;<BR>
+ /// 1 - Pmem Only;<BR>
+ /// 2 - All LRDIMM;<BR>
+ UINT8 DataBufferDfe;
+
+ ///
+ /// @brief
+ /// Enable/Disable Virtual NUMA.<BR>
+ /// @details
+ /// 0 - disable.<BR>
+ /// 1 - enable.<BR>
+ //
+ UINT8 VirtualNumaEnable;
+
+ ///
+ /// @brief
+ /// Smart Test Key pattern.<BR>
+ /// @details
+ /// Option to enter the confidential key to be used<BR>
+ //
+ UINT32 smartTestKey;
+
+ ///
+ /// Enable RMT minimum margin check
+ //
+ BOOLEAN RmtMinimumMarginCheckEnable;
+}; // memSetup
+
+///
+/// Common Platform Settings of MRC.
+///
+struct commonSetup {
+ ///
+ /// @brief
+ /// Flags for common platform settings.<BR>
+ /// @details
+ /// PROMOTE_WARN_EN BIT0 Enables warnings to be treated as fatal error.<BR>
+ /// PROMOTE_MRC_WARN_EN BIT1 Enables MRC warnings to be treated as fatal error.<BR>
+ /// HALT_ON_ERROR_EN BIT2 Enables errors to loop forever.<BR>
+ /// HALT_ON_ERROR_AUTO BIT3 Auto reset with Maximum Serial port debug<BR>
+ /// message level when fatal error is encountered.<BR>
+ //
+ UINT32 options;
+
+ ///
+ /// @brief
+ /// MRC debug feature. It indicates if debug jumper is set. <BR>
+ /// @details
+ /// 0 - Debug jumper is not set.<BR>
+ /// 1 - Debug jumper is set.<BR>
+ //
+ UINT8 debugJumper;
+
+ ///
+ /// @brief
+ /// Specifies what level of debug messages will be sent to serial port.<BR>
+ /// @details
+ /// Available options are a bitfield where: <BR>
+ /// SDBG_MIN BIT0;<BR>
+ /// SDBG_MAX BIT1;<BR>
+ /// SDBG_TRACE BIT2;<BR>
+ /// SDBG_MEM_TRAIN BIT3 + SDBG_MAX;<BR>
+ /// SDBG_CPGC BIT5;<BR>
+ /// SDBG_MINMAX SDBG_MIN + SDBG_MAX.<BR>
+ //
+ UINT32 serialDebugMsgLvl;
+
+ ///
+ /// MRC debug feature: Enable/Disable serial port buffer.<BR>
+ //
+ UINT8 serialBufEnable;
+
+ ///
+ /// MRC debug feature: Enable/Disable serial port pipe.<BR>
+ //
+ UINT8 serialPipeEnable;
+
+ ///
+ /// MRC debug feature: Enable/Disable serial pipe compress.<BR>
+ //
+ UINT8 serialPipeCompress;
+
+ ///
+ /// @brief
+ /// Maximum addressable memory supported by the platform.
+ /// @details
+ /// Skylake Processor supports up to 46-bit addressing. This input should be the
+ /// total number of addressable bytes in 256MB units. (0x40000 for 46-bit
+ /// and 0x1000 for 40-bit).
+ //
+ UINT32 maxAddrMem;
+
+ ///
+ /// User configurable IO port for post code which is traditionally located at 0x80.
+ //
+ UINT16 debugPort;
+
+ ///
+ /// 32-bit pointer to an optional OEM NVRAM image to be copied into the host NVRAM structure.
+ ///
+ UINT32 nvramPtr;
+
+ ///
+ /// 32-bit pointer to an optional OEM provided Host structure.
+ //
+ UINT32 sysHostBufferPtr;
+
+ ///
+ /// @brief
+ /// Disable/Enable DDRT Transcator.<BR>
+ /// @details
+ /// 0 - Disable;<BR>
+ /// 1 - Enable;<BR>
+ //
+ UINT8 ddrtXactor;
+
+ UINT8 ReservedS3;
+
+ UINT8 ReservedS7[MAX_B2P_MAILBOX_GROUPS];
+
+ ///
+ /// @brief
+ /// Socktet configuration supported by platform
+ /// @details
+ /// 0 - SOCKET_UNDEFINED
+ /// 1 - SOCKET_4S
+ /// 2 - SOCKET_HEDT High End Desktop
+ /// 3 - SOCKET_1S
+ /// 4 - SOCKET_1SWS 1 Socket Work Station
+ /// 5 - SOCKET_8S
+ /// 6 - SOCKET_2S
+ //
+ UINT8 SocketConfig;
+};
+
+///
+/// Platform Setting for MRC.
+//
+typedef struct sysSetup {
+
+ ///
+ /// Memory technology related settings for MRC.
+ //
+ struct memSetup mem;
+
+ ///
+ /// Common platform settings not related to memory techology.
+ //
+ struct commonSetup common;
+
+ ///
+ /// @brief
+ /// WFR Uncore GV Rate Reduction.<BR>
+ /// @details
+ /// AUTO: Enable if WFR socket is detected in system.<BR>
+ /// Enabled: Always enables WFR Uncore GV Rate Reduction.<BR>
+ //
+ UINT8 WFRWAEnable;
+
+ ///
+ /// Enable/Disable Pmax through BIOS to Pcode Mailbox.
+ //
+ UINT8 PmaxDisable;
+
+ UINT8 Pci64BitResourceAllocation; // TODO - This is IIO related, they need to stop relying on MRC structures
+
+
+ ///
+ /// Whether of not we should recover from ADR.
+ //
+
+ UINT32 AdrEvent;
+
+} SYS_SETUP;
+
+#pragma pack(pop)
+
+///
+/// Revison of MEMORY_POLICY_PPI.
+//
+#define MEMORY_POLICY_PPI_REVISION 0x00000001
+
+///
+/// Memory Policy PPI Definition.
+//
+typedef struct _MEMORY_POLICY_PPI {
+
+ ///
+ /// Revision of this PPI.
+ //
+ UINT32 Revision;
+
+ ///
+ /// This data structure contanis all platform level configuration for MRC.
+ //
+ SYS_SETUP *SysSetup;
+} MEMORY_POLICY_PPI;
+
+extern EFI_GUID gMemoryPolicyPpiGuid;
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h
new file mode 100644
index 0000000000..82725bc84e
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h
@@ -0,0 +1,53 @@
+/** @file
+ RAS IMC S3 Data Load PPI
+
+ @copyright
+ Copyright 2021 Intel Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _RAS_IMC_S3_DATA_H_
+#define _RAS_IMC_S3_DATA_H_
+
+#include <Uefi/UefiBaseType.h>
+
+typedef struct _RAS_IMC_S3_DATA_PPI RAS_IMC_S3_DATA_PPI;
+
+/**
+ Retrieves data for S3 saved memory RAS features from non-volatile storage.
+
+ If the Data buffer is too small to hold the contents of the NVS data,
+ the error EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the
+ required buffer size to obtain the data.
+
+ @param[in] This A pointer to this instance of the RAS_IMC_S3_DATA_PPI.
+ @param[in, out] DataSize On entry, points to the size in bytes of the Data buffer.
+ On return, points to the size of the data returned in Data.
+ @param[out] Data Points to the buffer which will hold the returned data.
+
+ @retval EFI_SUCCESS The NVS data was read successfully.
+ @retval EFI_NOT_FOUND The NVS data does not exist.
+ @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the NVS data.
+ DataSize is updated with the size required for
+ the NVS data.
+ @retval EFI_INVALID_PARAMETER DataSize or Data is NULL.
+ @retval EFI_DEVICE_ERROR The NVS data could not be retrieved because of a device error.
+ @retval EFI_UNSUPPORTED This platform does not support the save/restore of S3 memory data
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *RAS_IMC_S3_DATA_PPI_GET_IMC_S3_RAS_DATA) (
+ IN CONST RAS_IMC_S3_DATA_PPI *This,
+ IN OUT UINT32 *DataSize,
+ OUT VOID *Data
+ );
+
+struct _RAS_IMC_S3_DATA_PPI {
+ RAS_IMC_S3_DATA_PPI_GET_IMC_S3_RAS_DATA GetImcS3RasData;
+};
+
+extern EFI_GUID gRasImcS3DataPpiGuid;
+
+#endif // _RAS_IMC_S3_DATA_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPpi.h b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPpi.h
new file mode 100644
index 0000000000..e355dcaba3
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPpi.h
@@ -0,0 +1,39 @@
+/** @file
+ Silicon Policy PPI is used for specifying platform
+ related Intel silicon information and policy setting.
+ This PPI is consumed by the silicon PEI modules and carried
+ over to silicon DXE modules.
+
+ @copyright
+ Copyright 2017 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _UPI_POLICY_PPI_H_
+#define _UPI_POLICY_PPI_H_
+
+#include <Upi/KtiHost.h>
+
+///
+/// PPI revision information
+/// This PPI will be extended in a backwards compatible manner over time
+/// Added interfaces should be documented here with the revisions added
+/// Revision 1: Initial revision
+#define UPI_POLICY_PPI_REVISION 0x1
+
+typedef struct _UPI_POLICY_PPI UPI_POLICY_PPI;
+
+struct _UPI_POLICY_PPI {
+ /**
+ This member specifies the revision of the UPI_POLICY_PPI. This field is used to
+ indicate backwards compatible changes to the INTERFACE. Platform code that produces
+ this INTERFACE must fill with the correct revision value for UPI code
+ to correctly interpret the content of the INTERFACE fields.
+ **/
+ UINT32 Revision;
+ KTI_HOST_IN Upi;
+};
+
+#endif // _UPI_POLICY_PPI_H_
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol.h
new file mode 100644
index 0000000000..df8317937f
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol.h
@@ -0,0 +1,252 @@
+/** @file
+ Dynamic link silicon library service access Protocol
+
+ This protocol abstracts silicon static library accesses via a protocol
+
+ @copyright
+ Copyright 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DYNAMIC_SI_LIBARY_PROTOCOL_H_
+#define _DYNAMIC_SI_LIBARY_PROTOCOL_H_
+
+#include <Library/CompressedVariableLib.h>
+#include <IioPlatformData.h>
+#include <Include/SystemInfoVar.h>
+#include <Guid/MemoryMapData.h>
+#include <Library/CpuEarlyDataLib.h>
+#include <UsraAccessType.h>
+#include <IioUniversalData.h>
+
+#define DYNAMIC_SI_LIBARY_PROTOCOL_GUID \
+ { 0xb235fbed, 0x3b25, 0x4cb3, { 0x98, 0x9c, 0x8c, 0xe7, 0xec, 0x49, 0x8b, 0x7e } }
+
+#define DYNAMIC_SI_LIBARY_PROTOCOL_SIGNATURE SIGNATURE_32('D', 'S', 'L', 'P')
+#define DYNAMIC_SI_LIBARY_PROTOCOL_VERSION 0x01
+
+//
+// Functions
+//
+
+typedef
+EFI_STATUS
+(EFIAPI *DXE_SET_GPIO_OUTPUT_VALUE) (
+ IN UINT32 GPioPad,
+ IN UINT32 Value
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_IsCpuAndRevision) (
+ IN UINT8 CpuType,
+ IN UINT16 Revision
+ );
+
+typedef
+CPU_VAR_DATA *
+(EFIAPI *DXE_GetCpuVarData) (
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_MaxSataControllerNum) (
+ VOID
+ );
+
+typedef
+UINTN
+(EFIAPI *DXE_MmPciBase) (
+ IN UINT32 Bus,
+ IN UINT32 Device,
+ IN UINT32 Function
+ );
+
+typedef
+CPU_CSR_ACCESS_VAR *
+(EFIAPI *DXE_GetSysCpuCsrAccessVar) (
+ VOID
+ );
+
+typedef
+VOID
+(EFIAPI *DXE_IioPciHookBeforeEnumeration) (
+ IN UINT8 Segment,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT32 DidVid
+ );
+
+typedef
+CHAR8*
+(EFIAPI *DXE_PchGetSeriesStr) (
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *DXE_PchGetSteppingStr) (
+ OUT CHAR8 *Buffer,
+ IN UINT32 BufferSize
+ );
+
+typedef
+CHAR8*
+(EFIAPI *DXE_PchGetSkuStr) (
+ VOID
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *DXE_SaveVariableFromHob) (
+ IN EFI_GUID HobGuid,
+ IN CHAR16 *VariableName,
+ IN EFI_GUID VariableGuid
+ );
+
+typedef
+VOID
+(EFIAPI *DXE_SetColdBootSlowRequired) (
+ IN BOOLEAN ColdBootSlowRequired
+ );
+
+typedef
+SYS_INFO_VAR_NVRAM *
+(EFIAPI *DXE_GetSysInfoVarNvramPtr) (
+ VOID
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_HybridSystemLevelEmulationEnabled) (
+ VOID
+ );
+
+typedef
+SYSTEM_MEMORY_MAP_HOB *
+(EFIAPI *DXE_GetSystemMemoryMapData) (
+ VOID
+ );
+
+typedef
+BOOLEAN
+(EFIAPI *DXE_X2ApicIdDetect) (
+ IN VOID *Host
+ );
+
+typedef
+RETURN_STATUS
+(EFIAPI *DXE_RegisterRead) (
+ IN USRA_ADDRESS *Address,
+ IN VOID *Buffer
+ );
+
+typedef
+RETURN_STATUS
+(EFIAPI *DXE_RegisterWrite) (
+ IN USRA_ADDRESS *Address,
+ IN VOID *Buffer
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_SataDevNumber) (
+ IN UINT32 SataCtrlIndex
+ );
+
+typedef
+UINT8
+(EFIAPI *DXE_SataFuncNumber) (
+ IN UINT32 SataCtrlIndex
+ );
+
+typedef
+UINT16
+(EFIAPI *DXE_PmcGetAcpiBase) (
+ VOID
+ );
+
+typedef
+UINTN
+(EFIAPI *DXE_PchGetPmcBaseByPchId) (
+ IN UINT8 PchId
+ );
+
+typedef
+VOID
+(EFIAPI *DXE_SetBiosInfoFlagWpe) (
+ VOID
+ );
+
+typedef
+VOID
+(EFIAPI *DXE_ProgramGenProtRangeRegs) (
+ IIO_UDS *IioUds
+ );
+
+typedef
+VOID
+(EFIAPI *DXE_ProgramImrRegs) (
+ IIO_UDS *IioUds
+ );
+
+typedef
+VOID
+(EFIAPI *DXE_ProgramImr2Regs) (
+ IIO_UDS *IioUds
+ );
+
+typedef
+VOID
+(EFIAPI *DXE_CheckAndPopulateIedTraceMemory) (
+ UINTN IedTraceSize,
+ IIO_UDS *IioUds
+ );
+
+typedef
+UINT32
+(EFIAPI *DXE_ReadScratchpad7) (
+ VOID
+ );
+
+//
+// UBA specific silicon abstraction protocol
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Version;
+
+ DXE_GetCpuVarData GetCpuVarData;
+ DXE_IsCpuAndRevision IsCpuAndRevision;
+ DXE_MaxSataControllerNum MaxSataControllerNum;
+ DXE_MmPciBase MmPciBase;
+ DXE_GetSysCpuCsrAccessVar GetSysCpuCsrAccessVar;
+ DXE_IioPciHookBeforeEnumeration IioPciHookBeforeEnumeration;
+ DXE_SET_GPIO_OUTPUT_VALUE GpioSetOutputValue;
+ DXE_PchGetSeriesStr PchGetSeriesStr;
+ DXE_PchGetSteppingStr PchGetSteppingStr;
+ DXE_PchGetSkuStr PchGetSkuStr;
+ DXE_SaveVariableFromHob SaveVariableFromHob;
+ DXE_SetColdBootSlowRequired SetColdBootSlowRequired;
+ DXE_GetSysInfoVarNvramPtr GetSysInfoVarNvramPtr;
+ DXE_X2ApicIdDetect X2ApicIdDetect;
+ DXE_GetSystemMemoryMapData GetSystemMemoryMapData;
+ DXE_RegisterRead RegisterRead;
+ DXE_RegisterWrite RegisterWrite;
+ DXE_HybridSystemLevelEmulationEnabled HybridSystemLevelEmulationEnabled;
+ DXE_SataDevNumber SataDevNumber;
+ DXE_SataFuncNumber SataFuncNumber;
+ DXE_PmcGetAcpiBase PmcGetAcpiBase;
+ DXE_PchGetPmcBaseByPchId PchGetPmcBaseByPchId;
+ DXE_SetBiosInfoFlagWpe SetBiosInfoFlagWpe;
+ DXE_ProgramGenProtRangeRegs ProgramGenProtRangeRegs;
+ DXE_ProgramImrRegs ProgramImrRegs;
+ DXE_ProgramImr2Regs ProgramImr2Regs;
+ DXE_CheckAndPopulateIedTraceMemory CheckAndPopulateIedTraceMemory;
+ DXE_ReadScratchpad7 ReadScratchpad7;
+} DYNAMIC_SI_LIBARY_PROTOCOL;
+
+extern EFI_GUID gDynamicSiLibraryProtocolGuid;
+
+#endif // _DYNAMIC_SI_LIBARY_PROTOCOL_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibrarySmmProtocol.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibrarySmmProtocol.h
new file mode 100644
index 0000000000..53bf977d31
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibrarySmmProtocol.h
@@ -0,0 +1,60 @@
+/** @file
+ Dynamic link silicon library service access Protocol
+
+ This protocol abstracts silicon static library accesses via an SMM protocol
+
+ @copyright
+ Copyright 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DYNAMIC_SI_LIBARY_SMM_PROTOCOL_H_
+#define _DYNAMIC_SI_LIBARY_SMM_PROTOCOL_H_
+
+
+#define DYNAMIC_SI_LIBARY_SMM_PROTOCOL_GUID \
+ { 0xb235fbed, 0x3b25, 0x4cb3, { 0x98, 0x9c, 0x8c, 0xe7, 0xec, 0x49, 0x8b, 0x7e } }
+
+#define DYNAMIC_SI_LIBARY_SMM_PROTOCOL_SIGNATURE SIGNATURE_32('D', 'S', 'L', 'S')
+#define DYNAMIC_SI_LIBARY_SMM_PROTOCOL_VERSION 0x01
+
+//
+// Functions
+//
+
+typedef
+UINTN
+(EFIAPI *SMM_MmPciBase) (
+ IN UINT32 Bus,
+ IN UINT32 Device,
+ IN UINT32 Function
+ );
+
+typedef
+UINT16
+(EFIAPI *SMM_PmcGetAcpiBase) (
+ VOID
+ );
+
+typedef
+UINTN
+(EFIAPI *SMM_PchGetPmcBaseByPchId) (
+ IN UINT8 PchId
+ );
+
+//
+// UBA specific silicon abstraction protocol
+//
+typedef struct {
+ UINT32 Signature;
+ UINT32 Version;
+
+ SMM_MmPciBase MmPciBase;
+ SMM_PmcGetAcpiBase PmcGetAcpiBase;
+ SMM_PchGetPmcBaseByPchId PchGetPmcBaseByPchId;
+} DYNAMIC_SI_LIBARY_SMM_PROTOCOL;
+
+extern EFI_GUID gDynamicSiLibrarySmmProtocolGuid;
+
+#endif // _DYNAMIC_SI_LIBARY_SMM_PROTOCOL_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/GlobalNvsArea.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/GlobalNvsArea.h
new file mode 100644
index 0000000000..b5b51d4799
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/GlobalNvsArea.h
@@ -0,0 +1,212 @@
+/** @file
+ Definition of the global NVS area protocol. This protocol
+ publishes the address and format of a global ACPI NVS buffer used as a communications
+ buffer between SMM code and ASL code.
+ Note: Data structures defined in this protocol are not naturally aligned.
+
+ @copyright
+ Copyright 2004 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _EFI_GLOBAL_NVS_AREA_H_
+#define _EFI_GLOBAL_NVS_AREA_H_
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID { 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
+//
+// Because of ASL constrains cannot use MAX_SOCKET and MAX_LOGIC_IIO_STACK to configure ACPI objects. The symbols
+// below are the largest values of MAX_SOCKET or MAX_LOGIC_IIO_STACK currently supported in BiosParameterRegion.asi.
+//
+#define NVS_MAX_SOCKETS 8
+#define NVS_MAX_LOGIC_IIO_STACKS 14
+
+#if NVS_MAX_SOCKETS < MAX_SOCKET
+#error "Must update NVS_MAX_SOCKETS and BiosParameterRegion.asi to handle so many sockets"
+#endif
+#if NVS_MAX_LOGIC_IIO_STACKS < MAX_LOGIC_IIO_STACK
+#error "Must update NVS_MAX_LOGIC_IIO_STACKS and BiosParameterRegion.asi to handle so many stacks"
+#endif
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+
+//
+// Global NVS Area definition
+// BIOS parameters region provided by POST code to ASL, defined as PSYS in BiosParametersRegion.asi
+//
+#pragma pack (1)
+
+typedef struct {
+ // IOAPIC Start
+ UINT32 PlatformId;
+ UINT64 IoApicEnable;
+ UINT8 ApicIdOverrided :1;
+ UINT8 PchIoApic_24_119 :1;
+ UINT8 Cpx4Detect :1;
+ UINT8 Reserved0 :5;
+ // IOAPIC End
+
+ // Power Management Start
+ UINT8 TpmEnable :1;
+ UINT8 CStateEnable :1;
+ UINT8 C3Enable :1;
+ UINT8 C6Enable :1;
+ UINT8 C7Enable :1;
+ UINT8 MonitorMwaitEnable :1;
+ UINT8 PStateEnable :1;
+ UINT8 EmcaEn :1;
+ UINT8 HWAllEnable :2;
+ UINT8 KBPresent :1;
+ UINT8 MousePresent :1;
+ UINT8 TStateEnable :1;
+ UINT8 TStateFineGrained :1;
+ UINT8 OSCX :1;
+ UINT8 Reserved1 :1;
+ // Power Management End
+
+ // RAS Start
+ UINT8 CpuChangeMask;
+ UINT8 IioChangeMask;
+ UINT16 IioPresentBitMask[NVS_MAX_SOCKETS];
+ UINT32 SocketBitMask; // make sure this is at 4byte boundary
+ UINT8 CpuCoreThreadsCount;
+ UINT32 ProcessorApicIdBase[NVS_MAX_SOCKETS];
+ UINT64 ProcessorBitMask[NVS_MAX_SOCKETS]; // cores 0-63 for each socket
+ UINT64 ProcessorBitMaskHi[NVS_MAX_SOCKETS]; // cores 64-127 for each socket
+ UINT32 MmCfg;
+ UINT32 TsegSize;
+ UINT32 SmiRequestParam[4];
+ UINT32 SciRequestParam[4];
+ UINT64 MigrationActionRegionAddress;
+ UINT8 Cpu0Uuid[16];
+ UINT8 Cpu1Uuid[16];
+ UINT8 Cpu2Uuid[16];
+ UINT8 Cpu3Uuid[16];
+ UINT8 Cpu4Uuid[16];
+ UINT8 Cpu5Uuid[16];
+ UINT8 Cpu6Uuid[16];
+ UINT8 Cpu7Uuid[16];
+ UINT8 CpuSpareMask;
+ UINT8 Mem0Uuid[16];
+ UINT8 Mem1Uuid[16];
+ UINT8 Mem2Uuid[16];
+ UINT8 Mem3Uuid[16];
+ UINT8 Mem4Uuid[16];
+ UINT8 Mem5Uuid[16];
+ UINT8 Mem6Uuid[16];
+ UINT8 Mem7Uuid[16];
+ UINT8 Mem8Uuid[16];
+ UINT8 Mem9Uuid[16];
+ UINT8 Mem10Uuid[16];
+ UINT8 Mem11Uuid[16];
+ UINT8 Mem12Uuid[16];
+ UINT8 Mem13Uuid[16];
+ UINT8 Mem14Uuid[16];
+ UINT8 Mem15Uuid[16];
+ UINT64 EmcaL1DirAddr;
+ UINT32 ProcessorId;
+ UINT8 PcieAcpiHotPlugEnable;
+ UINT8 WheaEnabled;
+ UINT8 WheaSci;
+ UINT8 PropagateSerrOption;
+ UINT8 PropagatePerrOption;
+ // RAS End
+
+ // VTD Start
+ UINT64 DrhdAddr[3];
+ UINT64 AtsrAddr[3];
+ UINT64 RhsaAddr[3];
+ // VTD End
+
+ // SR-IOV WA Start
+ UINT8 WmaaSICaseValue;
+ UINT16 WmaaSISeg;
+ UINT8 WmaaSIBus;
+ UINT8 WmaaSIDevice;
+ UINT8 WmaaSIFunction;
+ UINT8 WmaaSISts;
+ UINT8 WheaSupportEn;
+ // SR-IOV End
+
+ // BIOS Guard Start
+ UINT64 BiosGuardMemAddress;
+ UINT8 BiosGuardMemSize;
+ UINT16 BiosGuardIoTrapAddress;
+ UINT8 CpuSkuNumOfBitShift;
+ // BIOS Guard End
+
+ // USB3 Start
+ UINT8 XhciMode;
+ UINT8 HostAlertVector1;
+ UINT8 HostAlertVector2;
+ // USB3 End
+
+ // HWPM Start
+ UINT8 HWPMEnable :2; // HWPM
+ UINT8 Reserved3 :1; // reserved bit
+ UINT8 HwpInterrupt :1; // HWP Interrupt
+ UINT8 Reserved2 :4; // reserved bits
+ // HWPM End
+
+ // SGX Start
+ UINT8 SgxStatus;
+ UINT64 EpcLength[8]; // MAX_IMC * MAX_SOCKET
+ UINT64 EpcBaseAddress[8]; // MAX_IMC * MAX_SOCKET
+ // SGX End
+
+ // PCIe Multi-Seg Start
+ UINT8 BusBase[NVS_MAX_SOCKETS][NVS_MAX_LOGIC_IIO_STACKS]; // PCI bus base number for each stack
+ UINT8 PcieMultiSegSupport; // Enable /Disable switch
+ UINT8 PcieSegNum[NVS_MAX_SOCKETS]; // PCI segment number array for each socket
+ // PCIe Multi-seg end
+
+ UINT8 SncAnd2Cluster; // 0 - SNC disabled, 2 - SNC enabled (2 clusters), 4 - SNC enabled (4 clusters)
+
+ // XTU Start
+ UINT32 XTUBaseAddress; // 193 XTU Base Address
+ UINT32 XTUSize; // 197 XTU Entries Size
+ UINT32 XMPBaseAddress; // 201 XTU Base Address
+ UINT8 DDRReferenceFreq; // 205 DDR Reference Frequency
+ UINT8 Rtd3Support; // 206 Runtime D3 support.
+ UINT8 Rtd3P0dl; // 207 User selctable Delay for Device D0 transition.
+ UINT8 Rtd3P3dl; // 208 User selctable Delay for Device D0 transition.
+ // XTU End
+
+ // FPGA Root Port Bus
+ UINT8 FpgaBusBase[8];
+ UINT8 FpgaBusLimit[8];
+
+ // FPGA present bit
+ UINT8 FpgaPresent[8];
+
+ // FPGA Resource Allocation
+ UINT32 VFPBMemBase[8];
+ UINT32 VFPBMemLimit[8];
+
+ // FPGA KTI present bitmap
+ UINT32 FpgaKtiPresent;
+ // FPGA Bus for KTI
+ UINT8 FpgaKtiBase[8];
+
+ UINT16 PmBase; // ACPI IO Base Address
+ UINT8 DebugModeIndicator; // Debug Mode Indicator
+ UINT8 IioPcieRpCapOffset; // IIO PCIe root port PCIe Capability offset
+ UINT8 ArtTscLinkFlag; // Flag to indicate if TSC is linked to ART
+} BIOS_ACPI_PARAM;
+
+#pragma pack ()
+
+//
+// Global NVS Area Protocol
+//
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+ BIOS_ACPI_PARAM *Area;
+} EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/IioUds.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/IioUds.h
new file mode 100644
index 0000000000..9efb4466f1
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/IioUds.h
@@ -0,0 +1,47 @@
+/** @file
+ This protocol provides access to the Ioh Universal Data Structure
+ This protocol is EFI compatible.
+
+ @copyright
+ Copyright 2005 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _EFI_IIO_UDS_PROTOCOL_H_
+#define _EFI_IIO_UDS_PROTOCOL_H_
+
+#include <IioUniversalData.h>
+
+#define EFI_IIO_UDS_PROTOCOL_GUID \
+ { 0xa7ced760, 0xc71c, 0x4e1a, 0xac, 0xb1, 0x89, 0x60, 0x4d, 0x52, 0x16, 0xcb }
+
+typedef struct _EFI_IIO_UDS_PROTOCOL EFI_IIO_UDS_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *IIH_ENABLE_VC) (
+ IN EFI_IIO_UDS_PROTOCOL *This,
+ IN UINT32 VcCtrlData
+ );
+/**
+
+ Enables the requested VC in IIO
+
+ @param This Pointer to the EFI_IOH_UDS_PROTOCOL instance.
+ @param VcCtrlData Data read from VC resourse control reg.
+
+**/
+
+
+typedef struct _EFI_IIO_UDS_PROTOCOL {
+ IIO_UDS *IioUdsPtr;
+ IIH_ENABLE_VC EnableVc;
+} EFI_IIO_UDS_PROTOCOL;
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiIioUdsProtocolGuid;
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/PciCallback.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/PciCallback.h
new file mode 100644
index 0000000000..a782bc3a1e
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/PciCallback.h
@@ -0,0 +1,85 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _EFI_PCI_CALLBACK_H
+#define _EFI_PCI_CALLBACK_H
+
+#include <Include/IndustryStandard/Pci22.h>
+#include <Protocol/CpuIo2.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+
+//
+// Global Id for PCI callback
+//
+#define EFI_PCI_CALLBACK_PROTOCOL_GUID \
+ { \
+ 0x1ca0e202, 0xfe9e, 0x4776, 0x9f, 0xaa, 0x57, 0xc, 0x19, 0x61, 0x7a, 0x06 \
+ }
+
+typedef struct _EFI_PCI_CALLBACK_PROTOCOL EFI_PCI_CALLBACK_PROTOCOL;
+
+typedef enum {
+ EfiPciEnumerationDeviceScanning = 1,
+ EfiPciEnumerationBusNumberAssigned = 2,
+ EfiPciEnumerationResourceAssigned = 4,
+} EFI_PCI_ENUMERATION_PHASE;
+
+typedef struct {
+ PCI_TYPE00 PciHeader;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_CPU_IO2_PROTOCOL *CpuIo;
+} EFI_PCI_CALLBACK_CONTEXT;
+
+typedef
+VOID
+(EFIAPI *EFI_PCI_CALLBACK_FUNC) (
+ IN EFI_HANDLE RootBridgeHandle,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_ENUMERATION_PHASE Phase,
+ IN EFI_PCI_CALLBACK_CONTEXT *Context
+);
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_REGISTER_PCI_CALLBACK) (
+ IN EFI_PCI_CALLBACK_PROTOCOL *This,
+ IN EFI_PCI_CALLBACK_FUNC Function,
+ IN EFI_PCI_ENUMERATION_PHASE Phase
+)
+/*++
+
+Routine Description:
+
+ Register a callback during PCI bus enumeration
+
+Arguments:
+
+ This - Protocol instance pointer.
+ Function - Callback function pointer.
+ Phase - PCI enumeration phase.
+
+Returns:
+
+ EFI_SUCCESS - Function has registed successfully
+ EFI_UNSUPPORTED - The function has been regisered
+ EFI_InVALID_PARAMETER - The parameter is incorrect
+
+--*/
+;
+
+//
+// Protocol definition
+//
+typedef struct _EFI_PCI_CALLBACK_PROTOCOL {
+ EFI_REGISTER_PCI_CALLBACK RegisterPciCallback;
+} EFI_PCI_CALLBACK_PROTOCOL;
+
+extern EFI_GUID gEfiPciCallbackProtocolGuid;
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/RcVersion.h b/Silicon/Intel/WhitleySiliconPkg/Include/RcVersion.h
new file mode 100644
index 0000000000..f0b618a65f
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/RcVersion.h
@@ -0,0 +1,23 @@
+/** @file
+ RC Version header file.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _RC_VERSION_H_
+#define _RC_VERSION_H_
+
+///
+/// RC version number structure.
+///
+typedef struct {
+ UINT8 Major;
+ UINT8 Minor;
+ UINT8 Revision;
+ UINT16 BuildNumber;
+} RC_VERSION;
+
+#endif // _RC_VERSION_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/ScratchpadList.h b/Silicon/Intel/WhitleySiliconPkg/Include/ScratchpadList.h
new file mode 100644
index 0000000000..732a3c2be6
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/ScratchpadList.h
@@ -0,0 +1,49 @@
+/** @file
+
+ @copyright
+ Copyright 2017 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __SCRATCHPAD_LIST__
+#define __SCRATCHPAD_LIST__
+
+//
+// Sticky BIOS Scratchpad 7. This struct contains the bit definitions for this Scratchpad.
+//
+// Comments: Reserved for Intel use.
+//
+
+#define BIOS_SCRATCHPAD7_COMPLETION_DELAY_RESET_COUNT_SIZE 2
+
+typedef union {
+ struct {
+ UINT32 Available : 4; // Bits[3:0] - These bits are not reserved.
+ UINT32 EnteredColdResetFlow : 1; // Bits[4:4] - Entered cold reset flow.
+ UINT32 CompletedColdResetFlow : 1; // Bits[5:5] - Completed cold reset flow.
+ UINT32 CompletionDelayResetCount : BIOS_SCRATCHPAD7_COMPLETION_DELAY_RESET_COUNT_SIZE;
+ // Bits[7:6] - The number of resets requested because the calculated
+ // completion delay was out of bounds. Only the socket 0 instance of this is
+ // used. This bitfield is used with workaround S1409301288.
+ UINT32 Available1 : 7; // Bits[14:8] - These bits are not reserved.
+ UINT32 CompletedWarmResetWA : 1; // Bits[15:15] - Indicates if the Warm reset WA was done in sec.
+ UINT32 SbspSocketId : 4; // Bits[19:16] - SBSP socket id
+ UINT32 PrefetchFailRecovery : 1; // Bits[20:20] - Prefetch failure/recovery.
+ UINT32 UmaBasedClusteringDowngrade : 2; // Bits[22:21] - Indicate UMA based clusting downgrade
+ // 0:default; 1: Quad-> Hemi 2: Quad-> Disable 3: Hemi-> Disable
+ UINT32 MarginTestfailure : 1; // Bits[23:23] - This bit is set when Margin Test Fails
+ UINT32 DcuModeSelect : 1; // Bits [24:24] - DCU_MODE select 0/1: 32KB 8-way no-ECC (hardware default) /
+ // 16KB 4-way with ECC.
+ UINT32 DwrBiosStall : 1; // Bits[25:25] - BIOS Stall if enter DWR.
+ UINT32 InDwr : 1; // Bits[26:26] - In DWR.
+ UINT32 FailMemChkFastColdBoot : 1; // Bits[27:27] - Bit set when setup option "DEBUG INTERFACE" is enabled
+ UINT32 BistFrbEventLastBoot : 1; // Bits[28:28] - BIST/FRB event occured during the last boot.
+ UINT32 RemoteSocketReleased : 1; // Bits[29:29] - Remote socket released in LT enabled system.
+ UINT32 SncFailRecovery : 1; // Bits[30:30] - Snc failure/recovery.
+ UINT32 AepDimmPresent : 1; // Bits[31:31] - AEP Dimm Present
+ } Bits;
+ UINT32 Data;
+} BIOS_SCRATCHPAD7_STRUCT;
+
+#endif // #ifndef __SCRATCHPAD_LIST__
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/SiliconUpdUpdate.h b/Silicon/Intel/WhitleySiliconPkg/Include/SiliconUpdUpdate.h
new file mode 100644
index 0000000000..da5a879a03
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/SiliconUpdUpdate.h
@@ -0,0 +1,53 @@
+/** @file
+ Header file for the SiliconUpdUpdate.h Library.
+
+ @copyright
+ Copyright 2020 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SILICON_UPD_UPDATE_H_
+#define _SILICON_UPD_UPDATE_H_
+
+#pragma pack(1)
+typedef struct {
+ //For IioPcieConfig
+ UINT8 Socket;
+ UINT16 PortIndex;
+ UINT8 HidePort;
+ UINT8 DeEmphasis;
+ UINT8 PortLinkSpeed;
+ UINT8 MaxPayload;
+ UINT8 ReservedE;
+ UINT8 ReservedF;
+ UINT8 ReservedG;
+ UINT8 Sris;
+ UINT8 PcieCommonClock;
+ //For IIO Ntb
+ UINT8 NtbIndex;
+ UINT8 NtbPpd;
+ UINT8 NtbBarSizeOverride;
+ UINT8 NtbSplitBar;
+ UINT8 NtbBarSizeImBar1;
+ UINT8 NtbBarSizeImBar2;
+ UINT8 NtbBarSizeImBar2_0;
+ UINT8 NtbBarSizeImBar2_1;
+ UINT8 NtbBarSizeEmBarSZ1;
+ UINT8 NtbBarSizeEmBarSZ2;
+ UINT8 NtbBarSizeEmBarSZ2_0;
+ UINT8 NtbBarSizeEmBarSZ2_1;
+ UINT8 NtbXlinkCtlOverride;
+} UPD_IIO_PCIE_PORT_CONFIG;
+
+// IIO_PCIE_PORT_CONFIG:
+// PciePortConfiguration - Pointer to an array of PCIe port configuration structures as declared above
+// NumberOfEntries - Number of elements in the PciePortConfiguration Array
+
+typedef struct {
+ UPD_IIO_PCIE_PORT_CONFIG *ConfigurationTable;
+ UINT16 NumberOfEntries;
+} IIO_PCIE_PORT_CONFIG;
+#pragma pack()
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/SystemInfoVar.h b/Silicon/Intel/WhitleySiliconPkg/Include/SystemInfoVar.h
new file mode 100644
index 0000000000..3eff6110aa
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/SystemInfoVar.h
@@ -0,0 +1,93 @@
+/** @file
+ System Infor Var Hearder File
+
+ @copyright
+ Copyright 2017 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __SYSTEM_INFO_VAR_INCLUDES__
+#define __SYSTEM_INFO_VAR_INCLUDES__
+
+#include <MemCommon.h>
+#include <Upi/KtiSi.h>
+#include <Pi/PiBootMode.h>
+
+#define SYS_INFO_NVRAM_VAR_NAME L"InfoVarNvramData"
+
+#pragma pack (push,1)
+
+typedef enum BootMode {
+ NormalBoot = 0, // Normal path through RC with full init, mem detection, init, training, etc.
+ // Some of these MRC specific init routines can be skipped based on MRC input params
+ // in addition to the sub-boot type (WarmBoot, WarmBootFast, etc).
+ S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3
+ // init and be optimized for speed.
+} BootMode;
+
+//
+// This is used to determine what type of die is connected to a UPI link
+//
+typedef enum {
+ UpiConnectionTypeCpu,
+ UpiConnectionTypePcieGen4,
+ UpiConnectionTypeFpga,
+ UpiConnectionTypeMax
+} UPI_CONNECTION_TYPE;
+
+typedef struct {
+ UINT16 stackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket
+ UINT8 StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack
+ UINT32 StackMmiol[MAX_SOCKET][MAX_IIO_STACK]; ///< mmiol of each IIO stack, if it works as CXL, the mmiol base is RCRBBAR
+ UINT8 SocketFirstBus[MAX_SOCKET];
+ UINT8 Socket10nmUboxBus0[MAX_SOCKET]; //10nm CPU use only
+ UINT8 SocketLastBus[MAX_SOCKET];
+ UINT8 segmentSocket[MAX_SOCKET];
+ UINT8 KtiPortCnt;
+ UINT32 socketPresentBitMap;
+ UINT32 SecondaryDieBitMap;
+ UINT32 FpgaPresentBitMap;
+ UINT32 mmCfgBase;
+ UINT32 mmCfgBaseH[MAX_SOCKET];
+ UINT32 mmCfgBaseL[MAX_SOCKET];
+ UINT8 DdrMaxCh;
+ UINT8 DdrMaxImc;
+ UINT8 DdrNumChPerMc;
+ UINT8 imcEnabled[MAX_SOCKET][MAX_IMC];
+ UINT8 mcId[MAX_SOCKET][MAX_CH];
+ MRC_MST MemSsType[MAX_SOCKET];
+ UINT32 MmioBar[MAX_SOCKET][TYPE_MAX_MMIO_BAR];
+ UINT8 HbmMaxCh;
+ UINT8 HbmMaxIoInst;
+ UINT8 HbmNumChPerMc;
+ UINT8 HbmNumChPerIo;
+ UINT32 LastCsrAddress[2];
+ UINT32 LastCsrMmioAddr;
+ UINT8 CsrCachingEnable;
+ UINT32 LastCsrMcAddress[2];
+ UINT32 LastCsrMcMmioPhyAddr;
+ UINT8 CsrPciBarCachingEnable;
+ UINT32 LastCsrPciBarAddr[2];
+ UINT64 LastCsrPciBarPhyAddr;
+ UINT32 LastSBPortId[MAX_SOCKET];
+ UPI_CONNECTION_TYPE UpiConnectionType[MAX_SOCKET];
+ BOOLEAN PostedCsrAccessAllowed; // SW is allowed to use posted CSR writes method when TRUE
+ BOOLEAN PostedWritesEnabled; // All CSR writes use posted method when TRUE, non-posted when FALSE
+ BOOLEAN DataPopulated; // CPU_CSR_ACCESS_VAR is unavailable when FALSE
+ BOOLEAN HbmSku;
+ UINT8 SocketConfig;
+ UINT8 HcxType[MAX_SOCKET];
+} CPU_CSR_ACCESS_VAR;
+
+typedef struct {
+ UINT32 MeRequestedSizeNv;
+ UINT32 MeRequestedAlignmentNv;
+ UINT32 IeRequestedSizeNv;
+ UINT32 IeRequestedAlignmentNv;
+ UINT8 SbspSocketIdNv;
+} SYS_INFO_VAR_NVRAM;
+
+#pragma pack (pop)
+
+#endif //#ifndef __SYSTEM_INFO_VAR_INCLUDES__
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h b/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h
new file mode 100644
index 0000000000..0ea93e9a78
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h
@@ -0,0 +1,111 @@
+/** @file
+ This file defines common equates.
+
+ @copyright
+ Copyright 2011 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _UNCORE_COMMON_INCLUDES_H_
+#define _UNCORE_COMMON_INCLUDES_H_
+
+#include <MaxSocket.h>
+#include <MaxCore.h>
+#include <MaxThread.h>
+
+#ifndef V_INTEL_VID
+#define V_INTEL_VID 0x8086
+#endif
+
+#define MAX_PROCESSOR_TSEG 5
+
+// CPX CPU steppings/revisions
+#ifndef CPX_A0_CPU_STEP
+#define CPX_A0_CPU_STEP 0x0A
+#endif //#ifdef CPX_A0_CPU_STEP
+
+#ifndef CPX_A1_CPU_STEP
+#define CPX_A1_CPU_STEP 0x0B
+#endif //#ifdef CPX_A1_CPU_STEP
+
+//
+// ICX SP CPU steppings
+//
+#ifndef ICXSP_R0_CPU_STEP
+#define ICXSP_R0_CPU_STEP 0x00
+#endif
+#ifndef ICXSP_L0_CPU_STEP
+#define ICXSP_L0_CPU_STEP 0x04
+#endif
+#ifndef ICXSP_C0_CPU_STEP
+#define ICXSP_C0_CPU_STEP 0x05
+#endif
+#ifndef ICXSP_D0_CPU_STEP
+#define ICXSP_D0_CPU_STEP 0x06
+#endif
+
+#define MAX_DIE 1
+#define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_SOCKET)
+
+#ifndef MAX_HA
+#define MAX_HA 2
+#endif
+
+// If you change this, please also update MAX_IMC in Library\ProcMemInit\Include\MemHostChip.h
+// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h
+#ifndef MAX_IMC
+#define MAX_IMC 2 // Maximum memory controllers per socket
+#endif
+
+// If you change this, please also update MAX_MC_CH in Library\ProcMemInit\Include\MemHostChip.h
+// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h
+#ifndef MAX_MC_CH
+#define MAX_MC_CH 3 // Max number of channels per MC (3 for EP)
+#endif
+
+// If you change this, please also update MAX_CH in Library\ProcMemInit\Include\MemHostChip.h
+// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h
+#ifndef MAX_CH
+#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
+#endif
+
+// If you change this, please also update MAX_DIMM in Library\ProcMemInit\Include\MemHostChip.h
+#ifndef MAX_DIMM
+#define MAX_DIMM 2 // Max DIMM per channel
+#endif
+
+// If you change this, please also update MC_MAX_NODE in Library\ProcMemInit\Include\MemHostChip.h
+#ifndef MC_MAX_NODE
+#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes
+#endif
+
+#ifndef TOTAL_CB3_DEVICES
+#define TOTAL_CB3_DEVICES 64 // IOAT_TOTAL_FUNCS * MAX_SOCKET. Note: this covers up to 8S.
+#endif
+
+#ifndef MaxIIO
+#define MaxIIO MAX_SOCKET
+#endif
+
+#ifndef TOTAL_IIO_STACKS
+#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. Not reflect architecture but only sysHost structure!
+#endif
+
+#ifndef NUMBER_NTB_PORTS_PER_SOCKET
+#define NUMBER_NTB_PORTS_PER_SOCKET 5
+#endif // #ifndef NUMBER_NTB_PORTS_PER_SOCKET
+
+#ifndef MAX_DEVHIDE_REGS_PER_SYSTEM
+ #if MaxIIO > 4
+ #define MAX_DEVHIDE_REGS_PER_SYSTEM 512 // MAX_DEVHIDE_REGS_PER_SOCKET * MaxIIO
+ #else
+ #define MAX_DEVHIDE_REGS_PER_SYSTEM 256 // MAX_DEVHIDE_REGS_PER_SOCKET * MaxIIO
+ #endif
+#endif
+
+#ifndef MAX_B2P_MAILBOX_GROUPS
+#define MAX_B2P_MAILBOX_GROUPS 32
+#endif // !MAX_B2P_MAILBOX_GROUPS
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiDisc.h b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiDisc.h
new file mode 100644
index 0000000000..67e0acd2ca
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiDisc.h
@@ -0,0 +1,36 @@
+/** @file
+
+ @copyright
+ Copyright 2004 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _KTI_DISCOVERY_H_
+#define _KTI_DISCOVERY_H_
+
+#include "DataTypes.h"
+#include <Upi/KtiSi.h>
+
+#pragma pack(1)
+
+//
+// Generic Data structure to describe Link Exchange Parameter (LEP) info
+//
+typedef struct {
+ UINT32 Valid : 1; ///< TRUE, if the link is valid (i.e trained successfully for low speed, no validation override that disables it)
+ UINT32 PeerSocId : 3; ///< Socket ID
+ UINT32 PeerSocType : 2; ///< Socket Type
+ UINT32 PeerPort : 4; ///< Port of the peer socket
+ UINT32 DualLink : 1; ///< TRUE, if there is a second link to the same neighbor
+ UINT32 TwoSkt3Link : 1; ///< TRUE, if there is a second and third link to the same neighbor
+ UINT32 TwoSkt4Link : 1; ///< TRUE, if there are 4 links between 2 sockets
+ UINT32 DualLinkIndex : 3; ///< Index of the second link that is connected to the same immediate neighbor
+ UINT32 DisallowRouteThru : 1; ///< TRUE if the link is not allowed to configure as route through traffic
+ UINT32 SpokeOfPinwheel : 1; ///< TRUE if the link is chosen as spoke of pinwheel
+ UINT32 Rsvd1 : 14;
+} KTI_LINK_DATA;
+
+#pragma pack()
+
+#endif // _KTI_DISCOVERY_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h
new file mode 100644
index 0000000000..cf558b3d34
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h
@@ -0,0 +1,304 @@
+/** @file
+
+ @copyright
+ Copyright 2004 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+// Definition Flag:
+// 1. KTI_SW_SIMULATION -> run with KTIRC Simulation
+// 2. IA32 -> run with IA32 mode
+
+
+#ifndef _KTI_HOST_H_
+#define _KTI_HOST_H_
+
+#include "DataTypes.h"
+#include "PlatformHost.h"
+#include <Upi/KtiSi.h>
+#include <Upi/KtiDisc.h>
+#include "MemHostChipCommon.h"
+
+#pragma pack(1)
+
+/*********************************************************
+ KTIRC Host Structure Related
+*********************************************************/
+
+typedef enum {
+ KTI_LINK0 = 0x0,
+ KTI_LINK1,
+ KTI_LINK2,
+ KTI_LINK3,
+ KTI_LINK4,
+ KTI_LINK5
+} KTI_LOGIC_LINK;
+
+typedef struct {
+
+ UINT8 Reserved1;
+ UINT8 Reserved2;
+ UINT8 Reserved3;
+ UINT8 Reserved4;
+ UINT8 Reserved5;
+ UINT8 Reserved6;
+ UINT8 Reserved7;
+ UINT8 Reserved8;
+ UINT8 Reserved9;
+ UINT8 Reserved10;
+ UINT8 Reserved11;
+ UINT8 Reserved12;
+ UINT8 Reserved13;
+ UINT8 Reserved14;
+ UINT8 Reserved15;
+ UINT8 Reserved16;
+ UINT8 Reserved17;
+ UINT8 Reserved18;
+ UINT8 Reserved19;
+ UINT8 Reserved20;
+ UINT8 Reserved21;
+ UINT8 Reserved22;
+ UINT8 Reserved23;
+ UINT8 Reserved24;
+ UINT8 Reserved25;
+ UINT8 Reserved26;
+ UINT8 Reserved27;
+ UINT8 Reserved28;
+ UINT8 Reserved29;
+
+ UINT8 Reserved30;
+ UINT8 Reserved31;
+ UINT8 Reserved32;
+ UINT8 Reserved33;
+ UINT8 Reserved34;
+ UINT8 Reserved35;
+ UINT8 Reserved36;
+ UINT8 Reserved37;
+ UINT32 Reserved38;
+
+ UINT8 Reserved39;
+ UINT8 Reserved40;
+
+} KTI_RESERVED_3;
+
+typedef struct {
+ UINT32 Reserved1:2;
+ UINT32 Reserved2:2;
+ UINT32 Reserved3:2;
+ UINT32 Rsvd1 : 26;
+} KTI_RESERVED_1;
+
+typedef struct {
+ UINT8 Reserved4 : 2;
+ UINT8 Rsvd1 : 6;
+} KTI_RESERVED_2;
+
+typedef struct {
+ KTI_RESERVED_1 Link[MAX_FW_KTI_PORTS];
+ KTI_RESERVED_2 Phy[MAX_FW_KTI_PORTS];
+} KTI_RESERVED_4;
+
+//
+// PHY settings that are system dependent. Need 1 of these for each socket/link/freq.
+//
+
+typedef struct {
+ UINT8 SocketID;
+ UINT8 AllLanesUseSameTxeq;
+ UINT8 Freq;
+ UINT32 Link;
+ UINT32 TXEQL[20];
+ UINT32 CTLEPEAK[5];
+} PER_LANE_EPARAM_LINK_INFO;
+
+//
+// This is for full speed mode, all lanes have the same TXEQ setting
+//
+typedef struct {
+ UINT8 SocketID;
+ UINT8 Freq;
+ UINT32 Link;
+ UINT32 AllLanesTXEQ;
+ UINT8 CTLEPEAK;
+} ALL_LANES_EPARAM_LINK_INFO;
+
+#define ADAPTIVE_CTLE 0x3f
+
+typedef enum {
+ TYPE_UBOX = 0,
+ TYPE_UBOX_IIO,
+ TYPE_MCP,
+ TYPE_FPGA,
+ TYPE_HFI,
+ TYPE_NAC,
+ TYPE_GRAPHICS,
+ TYPE_DINO,
+ TYPE_RESERVED,
+ TYPE_DISABLED, // This item must be prior to stack specific disable types
+ TYPE_UBOX_IIO_DIS,
+ TYPE_MCP_DIS,
+ TYPE_FPGA_DIS,
+ TYPE_HFI_DIS,
+ TYPE_NAC_DIS,
+ TYPE_GRAPHICS_DIS,
+ TYPE_DINO_DIS,
+ TYPE_RESERVED_DIS,
+ TYPE_NONE
+} STACK_TYPE;
+
+//
+// Link layer settings, per link
+//
+typedef struct {
+ UINT8 KtiPortDisable:1; // TRUE - Port disabled; FALSE- Port enabled (default)
+ UINT8 KtiLinkVnaOverride:7; // Numeric value 0x00-0x7f
+ UINT8 Rsvd:8;
+} KTI_CPU_LINK_SETTING;
+
+
+//
+// Phy general setting, per link
+//
+typedef struct {
+ UINT32 KtiLinkSpeed:3;
+ UINT32 Rsvd:29;
+} KTI_CPU_PHY_SETTING;
+
+//
+// Per CPU setting
+//
+typedef struct {
+ KTI_CPU_LINK_SETTING Link[MAX_FW_KTI_PORTS];
+ KTI_CPU_PHY_SETTING Phy[MAX_FW_KTI_PORTS];
+} KTI_CPU_SETTING;
+
+//
+// KTIRC input structure
+//
+typedef struct {
+ //
+ // Protocol layer and other general options; note that "Auto" is provided only options whose value will change depending
+ // on the topology, not for all options.
+ //
+
+ //
+ // Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO.
+ // Value 0 indicates, that CPU is not relevant for the system. If resource is
+ // requested for an CPU that is not currently populated, KTIRC will assume
+ // that the ratio is 0 for that CPU and won't allocate any resources for it.
+ // If resource is not requested for an CPU that is populated, KTIRC will force
+ // the ratio for that CPU to 1.
+ //
+
+
+ UINT8 BusRatio[MAX_SOCKET];
+
+ UINT8 D2KCreditConfig; // 1 - Min, 2 - Med (Default), 3- Max
+ UINT8 SnoopThrottleConfig; // 0 - Disabled (Default), 1 - Min, 2 - Med, 3- Max
+ UINT8 SnoopAllCores; // 0 - Disabled, 1 - Enabled, 2 - Auto
+ UINT8 LegacyVgaSoc; // Socket that claims the legacy VGA range; valid values are 0-7; 0 is default.
+ UINT8 LegacyVgaStack; // Stack that claims the legacy VGA range; valid values are 0-3; 0 is default.
+ UINT8 ColdResetRequestStart;
+ UINT8 P2pRelaxedOrdering; // 0 - Disable(default) 1 - Enable
+ UINT8 DebugPrintLevel; // Bit 0 - Fatal, Bit1 - Warning, Bit2 - Info Summary; Bit 3 - Info detailed. 1 - Enable; 0 - Disable
+ UINT8 SncEn; // 0 - Disable, (default) 1 - Enable
+ UINT8 UmaClustering; // 0 - Disable, 2 - 2Clusters UMA, 4 - 4Clusters UMA
+ UINT8 IoDcMode; // 0 - Disable IODC, 1 - AUTO (default), 2 - IODC_EN_REM_INVITOM_PUSH, 3 - IODC_EN_REM_INVITOM_ALLOCFLOW
+ // 4 - IODC_EN_REM_INVITOM_ALLOC_NONALLOC, 5 - IODC_EN_REM_INVITOM_AND_WCILF
+ UINT8 DegradePrecedence; // Use DEGRADE_PRECEDENCE definition; TOPOLOGY_PRECEDENCE is default
+ UINT8 Degrade4SPreference;// 4S1LFullConnect topology is default; another option is 4S2LRing topology.
+ UINT8 DirectoryModeEn; // 0 - Disable; 1 - Enable (default)
+ UINT8 XptPrefetchEn; // Xpt Prefetch : 1 - Enable; 0 - Disable; 2 - Auto (default)
+ UINT8 KtiPrefetchEn; // Kti Prefetch : 1 - Enable; 0 - Disable; 2 - Auto (default)
+ UINT8 XptRemotePrefetchEn; // Xpt Remote Prefetch : 1 - Enable; 0 - Disable; 2 - Auto (default) (ICX only)
+ UINT8 RdCurForXptPrefetchEn; // RdCur for XPT Prefetch : 0 - Disable, 1 - Enable, 2- Auto (default)
+ UINT8 KtiFpgaEnable[MAX_SOCKET]; // Indicate if should enable Fpga device found in this socket : 0 - Disable, 1 - Enable, 2- Auto
+ UINT8 DdrtQosMode; // DDRT QoS Feature: 0 - Disable (default), 1 - M2M QoS Enable, Cha QoS Disable
+ // 2 - M2M QoS Enable, Cha QoS Enable
+
+ //
+ // Phy/Link Layer Options (System-wide and per socket)
+ //
+ UINT8 KtiLinkSpeedMode; // Link speed mode selection; 0 - Slow Speed; 1- Full Speed (default)
+ UINT8 KtiLinkSpeed; // Use KTI_LINKSPEED definition
+ UINT8 KtiAdaptationEn; // 0 - Disable, 1 - Enable
+ UINT8 KtiAdaptationSpeed; // Use KTI_LINK_SPEED definition; MAX_KTI_LINK_SPEED - Auto (i.e BIOS choosen speed)
+ UINT8 KtiLinkL0pEn; // 0 - Disable, 1 - Enable, 2- Auto (default)
+ UINT8 KtiLinkL1En; // 0 - Disable, 1 - Enable, 2- Auto (default)
+ UINT8 KtiFailoverEn; // 0 - Disable, 1 - Enable, 2- Auto (default)
+ UINT8 KtiLbEn; // 0 - Disable(default), 1 - Enable
+ UINT8 KtiCrcMode; // CRC_MODE_16BIT, CRC_MODE_ROLLING_32BIT, CRC_MODE_AUTO or CRC_MODE_PER_LINK
+
+ UINT8 KtiCpuSktHotPlugEn; // 0 - Disable (default), 1 - Enable
+ UINT8 KtiCpuSktHotPlugTopology; // 0 - 4S Topology (default), 1 - 8S Topology
+ UINT8 KtiSkuMismatchCheck; // 0 - No, 1 - Yes (default)
+ UINT8 IrqThreshold; // IRQ Threshold setting
+ UINT8 TorThresLoctoremNorm; // TOR threshold - Loctorem threshold normal
+ UINT8 TorThresLoctoremEmpty; // TOR threshold - Loctorem threshold empty
+ UINT8 MbeBwCal; // 0 - Linear, 1 - Biased, 2 - Legacy, 3 - AUTO (default = Linear)
+ UINT8 TscSyncEn; // TSC sync in sockets: 0 - Disable, 1 - Enable, 2 - AUTO (Default)
+ UINT8 StaleAtoSOptEn; // HA A to S directory optimization: 1 - Enable; 0 - Disable; 2 - Auto (Default)
+ UINT8 LLCDeadLineAlloc; // LLC dead line alloc: 1 - Enable(Default); 0 - Disable
+ UINT8 SplitLock;
+ UINT8 ColdResetRequestEnd;
+
+ //
+ // Phy/Link Layer Options (per Port)
+ //
+ KTI_CPU_SETTING PhyLinkPerPortSetting[MAX_SOCKET];
+
+
+ UINT8 mmCfgBase; ///< MMCFG Base address, must be 64MB (SKX, HSX, BDX) / 256MB (GROVEPORT) aligned. Options: {0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6: Auto}
+ UINT8 mmCfgSize; ///< MMCFG Size address, must be 64M, 128M or 256M. Options: {0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto}
+ UINT32 mmiolBase; ///< MMIOL Base address, must be 64MB aligned
+ UINT32 mmiolSize; ///< MMIOL Size address
+ UINT32 mmiohBase; ///< Address bits above 4GB, i,e, the hex value here is address Bit[45:32] for SKX family, Bit[51:32] for ICX-SP
+ UINT8 CpuPaLimit; ///< Limits the max address to 46bits. This will take precedence over mmiohBase
+ UINT8 lowGap;
+ UINT8 highGap;
+ UINT16 mmiohSize; ////<< Number of 1GB contiguous regions to be assigned for MMIOH space per CPU. Range 1-1024
+ UINT8 isocEn; ///< 1 - Enable; 0 - Disable (BIOS will force this for 4S)
+ UINT8 dcaEn; ///< 1 - Enable; 0 - Disable
+
+ /*
+ BoardTypeBitmask:
+ Bits[3:0] - Socket0
+ Bits[7:4] - Socket1
+ Bits[11:8] - Socket2
+ Bits[15:12] - Socket3
+ Bits[19:16] - Socket4
+ Bits[23:20] - Socket5
+ Bits[27:24] - Socket6
+ Bits[31:28] - Socket7
+
+ Within each Socket-specific field, bits mean:
+ Bit0 = CPU_TYPE_STD support; always 1 on Socket0
+ Bit1 = CPU_TYPE_F support
+ Bit2 = CPU_TYPE_P support
+ Bit3 = reserved
+ */
+ UINT32 BoardTypeBitmask;
+ UINT32 AllLanesPtr;
+ UINT32 PerLanePtr;
+ UINT32 AllLanesSizeOfTable;
+ UINT32 PerLaneSizeOfTable;
+ UINT32 WaitTimeForPSBP; // the wait time in units of 1000us for PBSP to check in.
+ BOOLEAN IsKtiNvramDataReady;
+ UINT32 OemHookPostTopologyDiscovery;
+ UINT32 OemGetResourceMapUpdate;
+ UINT32 OemGetAdaptedEqSettings;
+ UINT32 OemCheckCpuPartsChangeSwap;
+
+ BOOLEAN WaSerializationEn; // Enable BIOS serialization WA by PcdWaSerializationEn
+ KTI_RESERVED_3 Reserved166;
+ KTI_RESERVED_4 Reserved167[MAX_SOCKET];
+ UINT8 KtiInEnableMktme; // 0 - Disabled; 1 - Enabled; MkTme status decides D2Kti feature state
+ UINT32 CFRImagePtr;
+ UINT8 S3mCFRCommit; // 0 - Disable S3m CFR flow. 1 - Provision S3m CFR but not Commit. 2 - Provsion and Commit S3M CFR.
+ UINT8 PucodeCFRCommit; // 0 - Disable Pucode CFR flow. 1 - Provision Pucode CFR but not Commit. 2 - Provsion and Commit Pucode CFR.
+} KTI_HOST_IN;
+
+#pragma pack()
+
+#endif // _KTI_HOST_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiSi.h b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiSi.h
new file mode 100644
index 0000000000..c0653bfae0
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiSi.h
@@ -0,0 +1,32 @@
+/** @file
+
+ @copyright
+ Copyright 2004 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _KTI_SI_H_
+#define _KTI_SI_H_
+
+#include "DataTypes.h"
+
+#if (MAX_SOCKET == 1)
+ #define MAX_FW_KTI_PORTS 3 // Maximum KTI PORTS to be used in structure definition.
+#else
+ #define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in structure definition
+#endif //(MAX_SOCKET == 1)
+
+#define IIO_PSTACK0 1
+#define IIO_PSTACK1 2
+#define IIO_PSTACK2 3
+#define IIO_PSTACK3 4
+#define IIO_PSTACK4 5
+
+#define UBOX_STACK MAX_LOGIC_IIO_STACK - 1 //use stack 13 for ubox
+
+#define IIO_RESERVED_1 6
+
+#define MAX_CHA_MAP 4
+
+#endif // _KTI_SI_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/UsraAccessType.h b/Silicon/Intel/WhitleySiliconPkg/Include/UsraAccessType.h
new file mode 100644
index 0000000000..e53aeb285b
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/UsraAccessType.h
@@ -0,0 +1,291 @@
+/** @file
+ Unified Silicon Register Access Types
+
+ @copyright
+ Copyright 2011 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __USRA_ACCESS_TYPE_H__
+#define __USRA_ACCESS_TYPE_H__
+
+typedef enum {
+ AddrTypePCIE = 0,
+ AddrTypePCIEBLK,
+ AddrTypeCSR,
+ AddrTypePCIIO,
+ AddrTypeCSRMEM,
+ AddrTypeCSRCFG,
+ AddrTypeMaximum
+} USRA_ADDR_TYPE;
+
+typedef enum {
+ CsrBoxInst = 0,
+ CsrMcId,
+ CsrChId,
+ CsrIoId,
+ InstTypeMax
+} CSR_INSTANCE_TYPE;
+
+typedef enum {
+ UsraWidth8 = 0,
+ UsraWidth16,
+ UsraWidth32,
+ UsraWidth64,
+ UsraWidthFifo8,
+ UsraWidthFifo16,
+ UsraWidthFifo32,
+ UsraWidthFifo64,
+ UsraWidthFill8,
+ UsraWidthFill16,
+ UsraWidthFill32,
+ UsraWidthFill64,
+ UsraWidthMaximum
+} USRA_ACCESS_WIDTH;
+
+#define USRA_ENABLE 1;
+#define USRA_DISABLE 0;
+
+#define PCI_CONFIGURATION_ADDRESS_PORT 0xCF8
+#define PCI_CONFIGURATION_DATA_PORT 0xCFC
+
+#pragma pack (1)
+
+typedef struct {
+ UINT32 RawData32[2]; // RawData of two UINT32 type, place holder
+ UINT32 AddrType:8; // Address type: CSR, PCIE, MMIO, IO, SMBus ...
+ UINT32 AccessWidth:4; // The Access width for 8, 16,32,64 -bit access
+ UINT32 FastBootEn:1; // Fast Boot Flag, can be used to log register access trace for fast boot
+ UINT32 S3Enable:1; // S3 Enable bit, when enabled, it will save the write to script to support S3
+ UINT32 HptrType:1; // Host Pointer type, below or above 4GB
+ UINT32 ConvertedType:1; // The address type was from converted type, use this field for address migration support
+ UINT32 RFU3:16; // Reserved for User use or Future Use
+
+ UINT32 HostPtr:32; // The Host Pointer, to point to Attribute buffer etc.
+} ADDR_ATTRIBUTE_TYPE;
+
+typedef struct {
+ UINT32 Offset:12; // The PCIE Register Offset
+ UINT32 Func:3; // The PCIE Function
+ UINT32 Dev:5; // The PCIE Device
+ UINT32 Bus:8; // The PCIE Bus
+ UINT32 RFU1:4; // Reserved for User use or Future Use
+
+ UINT32 Seg:16; // The PCI Segment
+ UINT32 Count:16; // Access Count
+
+} USRA_PCIE_ADDR_TYPE;
+
+#define BUS_DEV_FUN_OFFSET_MASK 0x0FFFFFFF
+
+typedef struct {
+ UINT32 Offset; // This Offset occupies 32 bits. It's platform code's responsibilty to define the meaning of specific
+ // bits and use them accordingly.
+ UINT32 InstId:8; // The Box Instance, 0 based, Index/Port within the box, Set Index as 0 if the box has only one instances
+ UINT32 SocketId:8; // The Socket Id
+ UINT32 InstType:8; // The Instance Type
+ UINT32 RFU:8; // Reserved for User use or Future Ues
+} USRA_CSR_ADDR_TYPE;
+
+typedef struct {
+ UINT32 Offset:8; // The PCIIO Register Offset
+ UINT32 Func:3; // The PCIIO Function
+ UINT32 Dev:5; // The PCIIO Device
+ UINT32 Bus:8; // The PCIIO Bus
+ UINT32 RFU:7; // Reserved for User use or Future Use
+ UINT32 EnableBit:1; // The PCIIO Register Enable Bit
+} USRA_PCIIO_ADDR_TYPE;
+
+typedef struct {
+ UINT32 Offset:32; // The register offset
+ UINT32 SocketId:8; // The socket ID
+ UINT32 MemBarId:8; // The ID of the BAR
+ UINT32 High64Split:1; // Move address up to access top of 64 bit register
+ UINT32 Reserved:15; // Reserved for User use or Future Use
+} USRA_CSR_MEM_ADDR_TYPE;
+
+typedef struct {
+ UINT32 Offset:32; // The register offset
+ UINT32 SocketId:7; // The socket ID
+ UINT32 Bus:8; // Bus
+ UINT32 Device:8; // Device
+ UINT32 Function:8; // Function
+ UINT32 High64Split:1; // Move address up to access top of 64 bit register
+} USRA_CSR_CFG_ADDR_TYPE;
+
+#pragma pack()
+
+typedef union {
+ UINT32 dwRawData[4];
+ ADDR_ATTRIBUTE_TYPE Attribute; // The address attribute type.
+ USRA_PCIE_ADDR_TYPE Pcie;
+ USRA_PCIE_ADDR_TYPE PcieBlk;
+ USRA_CSR_ADDR_TYPE Csr;
+ USRA_PCIIO_ADDR_TYPE PciIo;
+ USRA_CSR_MEM_ADDR_TYPE CsrMem;
+ USRA_CSR_CFG_ADDR_TYPE CsrCfg;
+} USRA_ADDRESS;
+
+//
+// Assemble macro for USRA_PCIE_ADDR_TYPE
+//
+#define USRA_PCIE_SEG_ADDRESS(Address, WIDTH, SEG, BUS, DEV, FUNC, OFFSET) \
+ USRA_ZERO_ADDRESS(Address); \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIE; \
+ ((USRA_ADDRESS *)(&Address))->Pcie.Seg = (UINT32)(SEG); \
+ ((USRA_ADDRESS *)(&Address))->Pcie.Bus = (UINT32)(BUS) & 0xFF; \
+ ((USRA_ADDRESS *)(&Address))->Pcie.Dev = (UINT32)(DEV) & 0x1F; \
+ ((USRA_ADDRESS *)(&Address))->Pcie.Func = (UINT32)(FUNC) & 0x07; \
+ ((USRA_ADDRESS *)(&Address))->Pcie.Offset = (UINT32)(OFFSET) & 0x0FFF
+
+ //
+ // Assemble macro for USRA_BDFO_ADDR_TYPE
+ //
+#define USRA_PCIE_SEG_BDFO_ADDRESS(Address, WIDTH, SEG, BDFO) \
+ USRA_ZERO_ADDRESS(Address); \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIE; \
+ ((USRA_ADDRESS *)(&Address))->Pcie.Seg = (UINT32)(SEG); \
+ ((USRA_ADDRESS *)(&Address))->Pcie.Bus = (UINT32)(BDFO >> 20) & 0xFF; \
+ ((USRA_ADDRESS *)(&Address))->Pcie.Dev = (UINT32)(BDFO >> 15) & 0x1F; \
+ ((USRA_ADDRESS *)(&Address))->Pcie.Func = (UINT32)(BDFO >> 12) & 0x07; \
+ ((USRA_ADDRESS *)(&Address))->Pcie.Offset = (UINT32)(BDFO) & 0x0FFF
+
+ //
+ // Assemble macro for USRA_PCIE_SEG_LIB_ADDR_TYPE
+ //
+#define USRA_PCIE_SEG_LIB_ADDRESS(Address, PCISEGADDR, WIDTH) \
+ USRA_ZERO_ADDRESS(Address); \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIE; \
+ ((USRA_ADDRESS *)(&Address))->Pcie.Seg = (UINT32)((PCISEGADDR >> 32) & 0x0000FFFF); \
+ ((USRA_ADDRESS *)(&Address))->Attribute.RawData32[0] = (UINT32)(PCISEGADDR & BUS_DEV_FUN_OFFSET_MASK)
+
+ //
+ // Assemble macro for USRA_PCIE_BLK_ADDR_TYPE
+ //
+#define USRA_BLOCK_PCIE_ADDRESS(Address, WIDTH, COUNT, SEG, BUS, DEV, FUNC, OFFSET) \
+ USRA_ZERO_ADDRESS(Address); \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIEBLK; \
+ ((USRA_ADDRESS *)(&Address))->PcieBlk.Count = (UINT32)COUNT; \
+ ((USRA_ADDRESS *)(&Address))->PcieBlk.Seg = (UINT32)SEG; \
+ ((USRA_ADDRESS *)(&Address))->PcieBlk.Bus = (UINT32)(BUS) & 0xFF; \
+ ((USRA_ADDRESS *)(&Address))->PcieBlk.Dev = (UINT32)(DEV) & 0x1F; \
+ ((USRA_ADDRESS *)(&Address))->PcieBlk.Func = (UINT32)(FUNC) & 0x07; \
+ ((USRA_ADDRESS *)(&Address))->PcieBlk.Offset = (UINT32)(OFFSET) & 0x0FFF
+ //
+ // Assemble macro for USRA_PCIE_SEG_ADDR_TYPE
+ //
+#define USRA_PCIE_ADDRESS(Address, WIDTH, BUS, DEV, FUNC, OFFSET) \
+ USRA_PCIE_SEG_ADDRESS(Address, WIDTH, 0, BUS, DEV, FUNC, OFFSET)
+
+ //
+ // Assemble macro for USRA CSR common Address
+ //
+#define USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET) \
+ USRA_ZERO_ADDRESS(Address); \
+ ((USRA_ADDRESS *)(&Address))->Csr.SocketId = SOCKETID; \
+ ((USRA_ADDRESS *)(&Address))->Csr.InstId = INSTID; \
+ ((USRA_ADDRESS *)(&Address))->Csr.Offset = CSROFFSET
+
+ //
+ // Assemble macro for address type CSR
+ //
+#define USRA_CSR_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET) \
+ USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET); \
+ ((USRA_ADDRESS *)(&Address))->Csr.InstType = CsrBoxInst; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSR
+
+#define USRA_CSR_MCID_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET) \
+ USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET); \
+ ((USRA_ADDRESS *)(&Address))->Csr.InstType = CsrMcId; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSR
+
+#define USRA_CSR_CHID_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET) \
+ USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET); \
+ ((USRA_ADDRESS *)(&Address))->Csr.InstType = CsrChId; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSR
+
+#define USRA_CSR_IOID_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET) \
+ USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET); \
+ ((USRA_ADDRESS *)(&Address))->Csr.InstType = CsrIoId; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSR
+
+ //
+ // Assemble macro for USRA_PCIIO_ADDR_TYPE
+ //
+#define USRA_PCI_IO_ADDRESS(Address, WIDTH, BUS, DEV, FUNC, OFFSET) \
+ USRA_ZERO_ADDRESS(Address); \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIIO; \
+ ((USRA_ADDRESS *)(&Address))->PciIo.Bus = (UINT32)(BUS) & 0xFF; \
+ ((USRA_ADDRESS *)(&Address))->PciIo.Dev = (UINT32)(DEV) & 0x1F; \
+ ((USRA_ADDRESS *)(&Address))->PciIo.Func = (UINT32)(FUNC) & 0x07; \
+ ((USRA_ADDRESS *)(&Address))->PciIo.Offset = (UINT32)(OFFSET) & 0xFF; \
+ ((USRA_ADDRESS *)(&Address))->PciIo.EnableBit = 1
+
+ //
+ // Assemble macro for USRA_BDFO_PCIIO_ADDR_TYPE
+ //
+#define USRA_PCI_IO_BDFO_ADDRESS(Address, WIDTH, BDFO) \
+ USRA_ZERO_ADDRESS(Address); \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIIO; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.RawData32[0] = (UINT32)(BDFO) & 0xFFFFFF; \
+ ((USRA_ADDRESS *)(&Address))->PciIo.EnableBit = 1
+
+ //
+ // Assemble macro for USRA_CSR_MMIO_ADDR_TYPE
+ //
+#define USRA_CSR_MEM_ADDRESS(Address, SOCKETID, MEMBARID, OFFSET, WIDTH) \
+ USRA_ZERO_ADDRESS(Address); \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSRMEM; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
+ ((USRA_ADDRESS *)(&Address))->CsrMem.SocketId = SOCKETID; \
+ ((USRA_ADDRESS *)(&Address))->CsrMem.MemBarId = MEMBARID; \
+ ((USRA_ADDRESS *)(&Address))->CsrMem.Offset = OFFSET; \
+ ((USRA_ADDRESS *)(&Address))->CsrMem.High64Split = 0;
+
+ //
+ // Assemble macro for USRA_CSR_CFG_ADDR_TYPE
+ //
+#define USRA_CSR_CFG_ADDRESS(Address, SOCKETID, BUS, DEVICE, FUNCTION, OFFSET, WIDTH) \
+ USRA_ZERO_ADDRESS(Address); \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSRCFG; \
+ ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
+ ((USRA_ADDRESS *)(&Address))->CsrCfg.SocketId = SOCKETID; \
+ ((USRA_ADDRESS *)(&Address))->CsrCfg.Bus = BUS; \
+ ((USRA_ADDRESS *)(&Address))->CsrCfg.Device = DEVICE; \
+ ((USRA_ADDRESS *)(&Address))->CsrCfg.Function = Function; \
+ ((USRA_ADDRESS *)(&Address))->CsrCfg.Offset = OFFSET; \
+ ((USRA_ADDRESS *)(&Address))->CsrCfg.High64Split = 0;
+
+ //
+ // Assemble macro for ZERO_USRA ADDRESS
+ //
+#define USRA_ZERO_ADDRESS(Address) \
+ ((UINT32 *)&Address)[3] = (UINT32)0; \
+ ((UINT32 *)&Address)[2] = (UINT32)0; \
+ ((UINT32 *)&Address)[1] = (UINT32)0; \
+ ((UINT32 *)&Address)[0] = (UINT32)0
+
+ //
+ // Assemble macro for ZERO_ADDR_TYPE
+ //
+#define USRA_ZERO_ADDRESS_TYPE(Address, AddressType) \
+ ((UINT32 *)&Address)[3] = (UINT32)0; \
+ ((UINT32 *)&Address)[2] = (UINT32)((AddressType) & 0x0FF); \
+ ((UINT32 *)&Address)[1] = (UINT32)0; \
+ ((UINT32 *)&Address)[0] = (UINT32)0
+
+#define USRA_ADDRESS_COPY(DestAddrPtr, SourceAddrPtr) \
+ ((UINT32 *)DestAddrPtr)[3] = ((UINT32 *)SourceAddrPtr)[3]; \
+ ((UINT32 *)DestAddrPtr)[2] = ((UINT32 *)SourceAddrPtr)[2]; \
+ ((UINT32 *)DestAddrPtr)[1] = ((UINT32 *)SourceAddrPtr)[1]; \
+ ((UINT32 *)DestAddrPtr)[0] = ((UINT32 *)SourceAddrPtr)[0];
+
+#endif
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h
new file mode 100644
index 0000000000..eb4bd92a1d
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h
@@ -0,0 +1,36 @@
+/** @file
+ DataTypes.h
+
+ @copyright
+ Copyright 2006 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _datatypes_h
+#define _datatypes_h
+
+#include <Base.h>
+
+typedef struct u64_struct {
+ UINT32 lo;
+ UINT32 hi;
+} UINT64_STRUCT, *PUINT64_STRUCT;
+
+typedef union {
+ struct {
+ UINT32 Low;
+ UINT32 High;
+ } Data32;
+ UINT64 Data;
+} UINT64_DATA;
+
+
+typedef struct u128_struct {
+ UINT32 one;
+ UINT32 two;
+ UINT32 three;
+ UINT32 four;
+} UINT128;
+
+#endif // _datatypes_h
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h
new file mode 100644
index 0000000000..8eaea40f72
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h
@@ -0,0 +1,1051 @@
+/** @file
+ MemHost.h
+
+ @copyright
+ Copyright 2006 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _memhost_h
+#define _memhost_h
+
+#include <Ppi/MemoryPolicyPpi.h>
+#include "DataTypes.h"
+#include "PlatformHost.h"
+#include "MemRegs.h"
+#include "MemDefaults.h"
+#include "NGNDimmPlatformCfgData.h"
+#include "MrcCommonTypes.h"
+#include "MemHostChipCommon.h"
+#include <MemCommon.h>
+#include <PiPei.h>
+#include <Memory/Ddr4SpdRegisters.h>
+
+#define RESERVED_2 2
+
+typedef struct TrainingStepDoneStruct {
+ UINT8 DramRxEq : 1;
+ UINT8 HostFlyBy : 1;
+ UINT8 TxVref : 1;
+ UINT8 DqSwzDone : 1;
+ UINT8 Reserved : 4;
+} TRAINING_STEP_DONE_STRUCT;
+
+#define CADB_MUX_MAX 4
+
+#define MAX_BITS_IN_BYTE 8 // BITS per byte
+#define MAX_BITS_IN_DWORD 32 // BITS per dword
+#define BITS_PER_NIBBLE 4
+#define MAX_NIBBLES_PER_BYTE 2
+#define INDEX_NIBBLE0 0
+#define INDEX_NIBBLE1 1
+
+//
+// DDR4 DB has 4 DFE coeff taps
+//
+#define DB_DFE_TAP 4
+
+#pragma pack(push, 1)
+
+///
+/// Rand per channel information
+//
+typedef struct RankCh {
+ UINT8 dimm; ///< DIMM this rank belongs to
+ UINT8 rank; ///< Rank on the DIMM (0-3)
+ UINT8 Roundtrip;
+ UINT8 IOLatency;
+} CHANNEL_RANKS;
+
+typedef enum {
+INVALID_BUS,
+SMBUS,
+EMRS,
+CPGC,
+SAD,
+} BUS_TYPE;
+
+//
+// -----------------------------------------------------------------------------
+///
+/// Common DRAM timings
+///
+struct comTime {
+ UINT8 nCL;
+ UINT8 nWR;
+ UINT8 nRCD;
+ UINT8 nAL;
+ UINT8 nRP;
+ UINT8 nRC;
+ UINT8 nWTR;
+ UINT8 nWTR_L;
+ UINT8 nRAS;
+ UINT8 nRTP;
+ UINT8 nFAW;
+ UINT8 nRRD;
+ UINT8 nRRD_L;
+ UINT8 nWL;
+ UINT16 nRFC;
+ UINT32 tCL;
+ UINT16 tRCD;
+ UINT16 tRP;
+ UINT16 tRC;
+ UINT16 tRFC;
+ UINT16 tRRD;
+ UINT16 tRRD_L;
+ UINT16 tRAS;
+ UINT16 tCCD;
+ UINT16 tCCD_WR;
+ UINT16 tCCD_L;
+ UINT16 tCCD_WR_L;
+ UINT64 casSup;
+ UINT8 casSupRange;
+}; //struct comTime
+
+//
+// Only applicable for x16 devices where 2 strobes are within a single DRAM device
+//
+typedef struct _X16_MAPPING {
+ UINT8 PairLogical[MAX_STROBE/2]; ///< Identifies logical strobe within the same DRAM device
+ BOOLEAN IsLow[MAX_STROBE/2]; ///< TRUE: represents the current logical strobe is connected to DQSL
+ ///< FALSE: represents the current logical strobe is connected to DQSU
+} X16_MAPPING;
+
+//
+// Packed bit field structure for storing MR1 RX EQ bits
+//
+typedef struct {
+ UINT32 Strobe0 : 3; //bits 0...2
+ UINT32 Strobe1 : 3; //bits 3...5
+ UINT32 Strobe2 : 3; //bits 6...8
+ UINT32 Strobe3 : 3; //bits 9...11
+ UINT32 Strobe4 : 3; //bits 12..14
+ UINT32 Strobe5 : 3; //bits 15..17
+ UINT32 Strobe6 : 3; //bits 18..20
+ UINT32 Strobe7 : 3; //bits 21..23
+ UINT32 Strobe8 : 3; //bits 24..26
+ UINT32 Rsvd : 5; //bits 27..31
+} Mr1RxEqStruct;
+
+//
+// NVRAM structures for S3 state
+//
+
+///
+/// DIMM rank info
+/// List indexed by rank number
+///
+typedef struct ddrRank {
+ UINT8 enabled; ///< 0 = disabled, 1 = enabled
+ UINT8 rankIndex;
+ UINT8 phyRank; ///< Physical Rank #(3:0)
+ UINT8 logicalRank; ///< Logical Rank number (0 - 7)
+ UINT8 ckIndex; ///< Index to the clock for this rank
+ UINT8 ctlIndex; ///< Index to the control group for this rank
+ UINT8 CKEIndex;
+ UINT8 ODTIndex;
+ UINT8 CSIndex;
+ UINT8 devTagInfo;
+ UINT16 RttWr;
+ UINT16 RttPrk;
+ UINT16 RttNom;
+ UINT16 rankSize; ///< Units of 64 MB
+ UINT16 remSize; ///< Units of 64 MB
+ UINT16 NVrankSize; ///< Units of 64 MB
+
+ UINT8 cmdLeft;
+ UINT8 cmdRight;
+ UINT8 cmdLow;
+ UINT8 cmdHigh;
+
+ UINT8 rxDQLeftSt;
+ UINT8 rxDQRightSt;
+ UINT8 txDQLeftSt;
+ UINT8 txDQRightSt;
+ UINT16 OutDrvImpCtrl;
+ UINT8 DqSwzDdr5[SUB_CH][20];
+ UINT8 faultyParts[MAX_STROBE];
+#ifdef LRDIMM_SUPPORT
+ UINT8 lrbufRxVref[MAX_STROBE]; ///< Actual value of backside RxVref
+ UINT8 lrBuf_FxBC4x5x[MAX_STROBE];
+ UINT8 lrBuf_FxBC8x9x[MAX_STROBE];
+#endif
+ UINT8 lrBuf_FxBC2x3x[MAX_STROBE];
+ UINT8 lrBuf_FxBCAxBx[MAX_STROBE];
+ UINT8 lrBuf_FxBCCxEx[MAX_STROBE/2];
+ UINT8 lrBuf_FxBCDxFx[MAX_STROBE/2];
+ UINT32 lrbufTxVref[MAX_STROBE]; ///< Actual value of backside TxVref
+ //
+ // MR1 per strobe Rx Eq value structure with 9 elements per structure
+ // therefore you need MAX_STROBE/9 structures to store all elements
+ //
+ Mr1RxEqStruct Mr1RxEqSettings[MAX_STROBE/9];
+
+} DDR_RANK_STRUCT; //struct ddrRank
+
+typedef enum {
+ DIMM_RANK_MAP_OUT_UNKNOWN = 0,
+ DIMM_RANK_MAP_OUT_MEM_DECODE,
+ DIMM_RANK_MAP_OUT_POP_POR_VIOLATION,
+ DIMM_RANK_MAP_OUT_RANK_DISABLED,
+ DIMM_RANK_MAP_OUT_ADVMEMTEST_FAILURE,
+ DIMM_RANK_MAP_OUT_MAX
+} DIMM_RANK_MAP_OUT_REASON;
+
+///
+/// DIMM information stored in NVRAM
+//
+typedef struct dimmNvram {
+ UINT8 dimmPresent; ///< 1 = DIMM present in this slot
+ UINT8 mailboxReady;
+ UINT16 lrbufswizzle;
+ INT32 minTCK; ///< minimum tCK for this DIMM (SPD_MIN_TCK)
+ UINT8 ftbTCK; ///< fine offset for tCK
+ UINT32 tCL;
+ UINT16 tRCD;
+ UINT16 tRP;
+ UINT8 ftbTRP; ///< DDR4 fine offset for tRP
+ UINT8 ftbTRCD; ///< DDR4 fine offset for tRCD
+ UINT8 ftbTAA; ///< DDR4 fine offset for tAA
+ UINT8 mapOut[MAX_RANK_DIMM]; ///< 1 = User requested rank made non-Present
+ UINT8 numRanks; ///< Number of logical ranks on this DIMM
+ UINT8 numDramRanks; ///< Number of physical DRAM ranks on this DIMM
+ UINT8 techIndex; ///< Index into DIMM technology table
+ UINT8 aepTechIndex; ///< Index into NVM DIMM technology table
+ UINT8 fmcType; ///< Far Memory Controller Type
+ UINT8 fmcRev; ///< Far Memory Controller Rev Type
+ SPD_AEP_MOD_REVISION_STRUCT FmcModRev; ///< Far Memory Controller Module Rev and Type
+ UINT8 NvmStepping; ///< NVM Device Stepping
+ UINT8 NvmDevDensity; ///< NVM DEV DENSITY
+ UINT8 NvmDevType; ///< NVM DEV TYPE
+ UINT8 SPDRawCard; ///< Raw Card Number
+ UINT8 DimmRevType; ///< RCD Revision
+ UINT8 SPDOtherOptFeatures;///< SDRAM Other Optional features
+ UINT8 SPDAddrMapp; ///< Address Mapping from Edge connector to DRAM
+ UINT8 SPDRegRev; ///< Register Revision
+ UINT8 SPDODCtl; ///< Register Output Drive Strength for Control
+ UINT8 SPDODCk; ///< Register Output Drive Strength for Clock
+#ifdef LRDIMM_SUPPORT
+ UINT16 SPDLrbufVen; ///< LRDIMM Data Buffer Vendor ID
+ UINT8 SPDLrbufDramVrefdqR0; ///< DRAM VrefDQ for Package Rank 0
+ UINT8 SPDLrbufDramVrefdqR1; ///< DRAM VrefDQ for Package Rank 1
+ UINT8 SPDLrbufDramVrefdqR2; ///< DRAM VrefDQ for Package Rank 2
+ UINT8 SPDLrbufDramVrefdqR3; ///< DRAM VrefDQ for Package Rank 3
+ UINT8 SPDLrbufDbVrefdq; ///< LR Data Buffer VrefDQ for DRAM Interface
+ UINT8 SPDLrbufDbDsRttLe1866; ///< LR Data Buffer MDQ Drive Strength and RTT for data rate <= 1866
+ UINT8 SPDLrbufDbDsRttGt1866Le2400; ///< LR Data Buffer MDQ Drive Strength and RTT for data rate > 1866 and <= 2400
+ UINT8 SPDLrbufDbDsRttGt2400Le3200; ///< LR Data Buffer MDQ Drive Strength and RTT for data rate > 2400 and <= 3200
+ UINT8 SPDLrbufDramDs; ///< LR Buffer DRAM Drive Strength (for data rates <1866, 1866 < data rate < 2400, and 2400 < data rate < 3200)
+ UINT8 SPDLrbufDramOdtWrNomLe1866; ///< LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866
+ UINT8 SPDLrbufDramOdtWrNomGt1866Le2400; ///< LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 1866 and <= 2400
+ UINT8 SPDLrbufDramOdtWrNomGt2400Le3200; ///< LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 2400 and <= 3200
+ UINT8 SPDLrbufDramOdtParkLe1866; ///< LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866
+ UINT8 SPDLrbufDramOdtParkGt1866Le2400; ///< LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 1866 and <= 2400
+ UINT8 SPDLrbufDramOdtParkGt2400Le3200; ///< LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 2400 and <= 3200
+ UINT8 rcLrFunc;
+ UINT8 lrBuf_BC00;
+ UINT8 lrBuf_BC01;
+ UINT8 lrBuf_BC02;
+ UINT8 lrBuf_BC03;
+ UINT8 lrBuf_BC04;
+ UINT8 lrBuf_BC05;
+ UINT8 lrBuf_BC1x;
+ UINT8 LrBuf_DFECoef[MAX_BITS_IN_BYTE][DB_DFE_TAP][MAX_STROBE/2]; // JEDEC F3BCCx-Fx coeffcient. 8 DQ x 4 taps x 9 DB
+ UINT8 Dfe_F2BCEX; // JEDEC DB02DFE DQ selection and global enable
+#endif // LRDIMM_SUPPORT
+
+ UINT8 XMPOrg; ///< XMP organization and configuration
+ UINT8 XMPRev;
+ UINT32 XMPChecksum;
+
+ UINT8 x4Present; ///< Set if this is a x4 rank
+ UINT8 keyByte;
+ UINT8 keyByte2; ///< Logical module type (for MRC compat)
+ UINT8 DcpmmPresent; ///< Is an NVM DIMM present?
+ BOOLEAN NvmDimmDisable; ///< 1 = NVMDimm present but got disabled in this slot
+ UINT8 actKeyByte2; ///< Actual module type reported by SPD
+ UINT8 SPDModuleOrg; ///< Logical number of DRAM ranks and device width
+ UINT8 actSPDModuleOrg; ///< Actual number of DRAM ranks and device width
+ UINT8 dramIOWidth; ///< The encoded value of DRAM IO width
+ UINT8 dramIOWidthSecondary; ///< The encoded value of IO width for secondary SDRAM
+ BOOLEAN rankMix; ///< Used to indicate if the target DIMM is asymmetric
+ UINT8 SPDDeviceType; ///< Primary SDRAM Device Type
+ UINT8 SPDSecondaryDeviceType; ///< Secondary SDRAM Device Type
+ UINT8 numBankAddressBits; ///< Number of bank address bits per bank group
+ UINT8 numBankAddressBitsSecondary; ///< Number of bank address bits per bank group of Secondary SDRAM
+ UINT8 numBankGroupBits; ///< Number of bank group bits
+ UINT8 numBankGroupBitsSecondary; ///< Number of bank group bits of Secondary SDRAM
+ UINT8 sdramCapacity; ///< Encoded SDRAM capacity based on DDR4 format
+ UINT8 sdramCapacitySecondary; ///< Encoded SDRAM capacity based on DDR4 format for Secondary SDRAM
+ UINT8 numRowBits; ///< Number of row address bits
+ UINT8 numRowBitsSecondary; ///< Number of row address bits of Secondary SDRAM
+ UINT8 numColBits; ///< Number of column address bits
+ UINT8 numColBitsSecondary; ///< Number of column address bits of Secondary SDRAM
+ UINT8 dieCount; ///< Number of SDRAM dies per package for symmetric DIMMs or Primary SDRAM dies per package for asymmetric DIMMs
+ UINT8 dieCountSecondary; ///< Number of Secondary DRAM dies per package for asymmetric DIMMs
+ UINT8 cidBitMap; ///< SubRanks per chip select per dimm of DDR4 3DS and non3ds_lrdimm
+ UINT8 lrRankMult; ///< Rank multiplication factor
+ UINT8 SPDMemBusWidth; ///< Width of the Primary bus and extension
+ UINT8 dimmTs; ///< Module Thermal Sensor
+ UINT8 dimmAttrib; ///< Module attributes
+ UINT8 mtbDiv; ///< medium time base divisor (SPD_MTB_DIV)
+ UINT8 SPDftb; ///< fine time base (SPD_FTB)
+ UINT32 dimmMemTech; ///< Used to program DIMMMTR
+ UINT16 SPDRegVen; ///< Register Vendor ID
+ UINT16 SPDMMfgId; ///< Module Mfg Id from SPD
+ UINT8 SPDMMfLoc; ///< Module Mfg Location from SPD
+ UINT16 SPDModDate; ///< Module Manufacturing Date
+ UINT16 SPDDramMfgId; ///< DRAM Mfg Id
+ UINT8 SPDDramRev; ///< DRAM Rev Id
+ UINT8 SPDModSN[SPD_MODULE_SERIAL]; ///< Module Serial Number
+ UINT8 SPDModPartDDR4[SPD_MODULE_PART_DDR4]; ///< Module Part Number DDR4
+ UINT8 SPDOptionalFeature; ///< DDR4 optional feature
+ UINT8 AitDramPoll;
+ BOOLEAN NvDimmNPresent; ///< JEDEC NVDIMM-N Type Memory Present
+ UINT16 NvDimmStatus;
+ // Bit Description
+ // 0 NVDIMM controller failure
+ // 1 NVDIMM restore failed
+ // 2 NVDIMM restore retry
+ // 3 NVDIMM backup failed
+ // 4 NVDIMM erase failed
+ // 5 NVDIMM erase retry
+ // 6 NVDIMM arm failed
+ // 7 No backup energy source detected
+ // 8 Backup energy source charge failed
+ // 9 NVDIMM uncorrectable memory error
+ // 10 NVDIMM correctable memory memory error threshold
+ // 11-15 Reserved
+
+ UINT8 lrbufRid; ///< LR Buffer Revision ID (from buffer not SPD)
+ UINT8 lrbufGen; ///< LR Buffer Gen
+ UINT8 SPDIntelSN[5]; ///< Intel DIMM serial number
+ struct ddrRank rankList[MAX_RANK_DIMM];
+ UINT8 SPDmtb; ///< DDR4 medium time base (SPD_TB_DDR4)
+ UINT8 SPDSpecRev; ///< Revision of the SPD spec for this data
+ UINT8 SpdModuleType; ///< SPD Byte 2 (0x002): Key Byte / Host Bus Command Protocol Type
+ UINT8 rcCache[16]; /// DDR4 RCD cache
+ UINT8 rcxCache[16];
+ UINT8 lrDimmPresent;
+ UINT8 rcClk;
+ UINT8 rcCmd;
+ UINT8 rcCtl;
+ UINT16 rcVref;
+ INT16 QxCAClkOffset; ///< RCD QxCA Training Offset
+ UINT8 dqSwz[36];
+ UINT16 rawCap; ///< Raw Capacity
+ UINT16 VendorID; ///< Vendor ID for NVMDIMM Mgmt driver thru Nfit
+ UINT16 DeviceID; ///< Device ID for NVMDIMM Mgmt driver thru Nfit
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 DimmGnt2Erid; ///< DIMM-side Grant-to-ERID (produced by SPD and consumed by FMC; distinct from MC-programmed value)
+ X16_MAPPING LogicalX16Mapping;
+ UINT8 manufacturer[NGN_MAX_MANUFACTURER_STRLEN]; /* Manufacturer */
+ UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; /* Serial Number */
+ UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; /* Part Number */
+ UINT16 volCap; /* Volatile Capacity (2LM region) */
+ UINT16 nonVolCap; /* NonVolatile Capacity (PMEM/PMEM$ region + Blk region) */
+ UINT16 perCap; /* Persistent Capcity (PMEM/PMEM$). This size is not obtained from FNV. This is derived data. */
+ UINT16 WbCachePerCap; /* Persistent WB cache Capcity (AD-WB) This size is not obtained from FNV. This is derived data. */
+ UINT32 volRegionDPA; /* DPA start address of 2LM Region */
+ UINT32 perRegionDPA; /* DPA start address of PMEM Region */
+ struct firmwareRev firmwareRevision; /* Firmware Revision */
+ UINT8 dimmSku; /* Dimm SKU info Bit0:MemorymodeEnabled 1: StoragemodeEnabled 2:AppDirectmodeEnabled 3:DieSparingCapable 4:SoftProgrammableSKU 5:MemorymodeEncryptionEnabled 6:AppDirectmodeEncryptionEnabled 7:StoragemodeEncrytionEnabled */
+ UINT16 InterfaceFormatCode;
+ UINT16 VendorIDIdentifyDIMM;
+ UINT16 DeviceIDIdentifyDIMM;
+ UINT32 DdrtDimmBasicTiming;
+ UINT8 Uniqueid[NGN_MAX_UID_STRLEN]; /* Unique ID */
+ DIMM_RANK_MAP_OUT_REASON MapOutReason[MAX_RANK_DIMM];
+ UINT8 VlpRdimmPresent;
+ RDIMM_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION_STRUCT SpdThermalHeatSpreaderSolution; ///< Byte 132 (0x084) (Registered): RDIMM Thermal Heat Spreader Solution
+ UINT8 pad[1]; ///< padding added to eliminate: MemChipDdrio.c(5567): warning C4366: The result of the unary '&' operator may be unaligned. ie: &((*ChannelNvList)[Channel].ddrCRClkControls)
+} DIMM_NVRAM_STRUCT; //struct dimmNvram
+
+#define MAX_CMD_CSR 16
+#define MAX_SIDE 2
+
+///
+/// Channel information stored in NVRAM
+///
+typedef struct channelNvram {
+ UINT8 enabled; ///< 0 = channel disabled, 1 = channel enabled
+ UINT8 mb3trainingfailure;
+ UINT8 features; ///< Bit mask of features to enable or disable
+ UINT8 maxDimm; ///< Number of DIMM
+ UINT8 numRanks; ///< Number of ranks on this channel
+ UINT8 numQuadRanks; ///< Number of QR DIMMs on this channel
+ UINT8 timingMode; ///< Command timing mode(1N, 2N, or 3N) for normal operation
+ UINT8 trainTimingMode; ///< Command timing mode(1N, 2N, or 3N) for training
+ UINT8 ckeMask; ///< CKE signals to assert during IOSAV mode
+ UINT8 chFailed; ///< ddr4 memory in this channel had failed (MFO)
+ UINT8 ngnChFailed; ///< NGN memory in this channel had failed (MFO)
+ struct comTime common; ///< Common timings for this channel
+ struct dimmNvram dimmList[MAX_DIMM];
+ struct RankCh rankPerCh[MAX_RANK_CH];
+ UINT32 dimmVrefControlFnv1;
+ UINT32 dimmVrefControlFnv1Sa; // SA fub
+ UINT32 ddrCrCmdPiCodingFnv;
+ UINT32 ddrCrCmdPiCodingFnv2;
+ UINT8 encodedCSMode;
+ UINT8 cidBitMap;
+ UINT8 txVrefSafe[MAX_RANK_CH];
+ UINT8 dimmRevType;
+ UINT8 lrDimmPresent;
+#ifdef LRDIMM_SUPPORT
+ UINT8 chOneRankTimingModeEnable;
+#endif
+ UINT8 lrRankMultEnabled;
+ UINT8 v110NotSupported;
+ UINT8 v120NotSupported;
+ UINT32 rankErrCountStatus;
+ UINT32 rankErrCountInfo[(MAX_RANK_CH * SUB_CH)/2];
+ UINT32 rankErrThresholdInfo[(MAX_RANK_CH * SUB_CH)/2];
+ UINT8 ddrtEnabled;
+ UINT32 SmiSpareCtlMcMainExt;
+ UINT8 spareInUse;
+ UINT8 spareDimm[MAX_RANK_CH/2];
+ UINT8 spareRank[MAX_RANK_CH/2];
+ UINT16 spareRankSize[MAX_RANK_CH/2];
+ UINT8 spareLogicalRank[MAX_SPARE_RANK];
+ UINT8 sparePhysicalRank[MAX_SPARE_RANK];
+ UINT32 ioLatency1;
+ UINT32 tcrwp; ///< TCRWP_MCDDC_CTL_STRUCT
+ UINT32 tcothp; ///< TCOTHP_MCDDC_CTL_STRUCT
+ UINT32 tcothp2;
+ UINT32 TCMr0Shadow;
+ UINT32 TCMr2Shadow;
+ UINT32 TCMr4Shadow;
+ UINT32 TCMr5Shadow;
+ INT16 normalizationFactor;
+ UINT8 FmcWrCreditLimit;
+ UINT8 FmcRdCreditLimit;
+ UINT8 twoXRefreshSetPerCh; /* Saves the refreshRate value for each channel */
+ UINT8 tCCDAdder;
+ BUS_TYPE fnvAccessMode;
+ UINT32 ddrtDimm0BasicTiming;
+ UINT32 ddrtDimm1BasicTiming;
+ UINT32 cadbMuxPattern[CADB_MUX_MAX];
+ UINT8 EccModeMcMain[(MAX_RANK_CH * SUB_CH)];
+ UINT32 Plus1Failover[(MAX_RANK_CH * SUB_CH)];
+ UINT32 LinkRetryErrLimits;
+ UINT32 LinkLinkFail;
+ UINT32 mtCas2CasDr; /* CNX Change */
+ UINT32 mtCas2CasDd; /* CNX Change */
+ UINT32 mtCas2CasSr; /* CNX Change */
+ UINT32 mtCas2CasSg; /* CNX Change */
+ UINT32 mtCas2CasDs; /* CNX Change */
+ UINT32 tCke; /* CNX Change */
+ UINT32 MemoryTimingsAdj;
+ UINT8 T_rrdr_org; ///< Nvram Variable to store original tRRDR turnaround timing parameter
+ UINT8 T_rrdd_org; ///< Nvram Variable to store original tRRDD turnaround timing parameter
+ UINT8 T_rrdr; ///< Nvram Variable to store current tRRDR turnaround timing parameter
+ UINT8 T_rrdd; ///< Nvram Variable to store current tRRDD turnaround timing parameter
+#ifndef DDRIO_DATA_1S
+ UINT32 dataControl0;
+ UINT32 dataControl1[MAX_STROBE]; ///< need to save for each strobe
+ UINT32 dataControl2[MAX_STROBE];
+ UINT32 dataControl4[MAX_STROBE];
+ UINT32 dataControl3[MAX_STROBE];
+ UINT32 dataOffsetComp[MAX_STROBE];
+ UINT8 DrvStaticLegCfg[MAX_STROBE];
+ UINT8 OdtSegmentEnable[MAX_STROBE];
+ UINT8 DataSegmentEnable[MAX_STROBE];
+ UINT8 RcompCode[MAX_STROBE];
+ UINT32 LegacyRxDfeTxEcho[MAX_STROBE]; //Used to store Legacy RxDfe or TxEcho register values
+ UINT32 ddrCRClkControls;
+ UINT32 DdrCrCmdNControls;
+ UINT32 DdrCrCmdSControls;
+ UINT32 DdrCrCkeControls;
+ UINT32 DdrCrCtlControls;
+ UINT32 clkCsr;
+ INT16 TxDqsDelay[MAX_RANK_CH][MAX_STROBE];
+ UINT32 txGroup0[MAX_RANK_CH][MAX_STROBE];
+ UINT32 txGroup1[MAX_RANK_CH][MAX_STROBE];
+ UINT32 TxEqCoefTap2[MAX_RANK_CH][MAX_STROBE];
+ UINT16 XtalkDeltaN0[MAX_RANK_CH][MAX_STROBE];
+ UINT16 XtalkDeltaN1[MAX_RANK_CH][MAX_STROBE];
+ UINT32 txTco[MAX_RANK_CH][MAX_STROBE];
+ UINT32 rxGroup0[MAX_RANK_CH][MAX_STROBE];
+ UINT32 rxGroup1[MAX_RANK_CH][MAX_STROBE];
+ UINT32 RxDfeCoeff[MAX_STROBE];
+ UINT32 RxDfeControl[MAX_STROBE];
+ UINT32 rxOffset[MAX_RANK_CH][MAX_STROBE];
+ UINT32 rxVrefCtrl[MAX_STROBE];
+ UINT8 txVrefCache[MAX_RANK_CH][MAX_STROBE]; ///< Cached value of txVref (this might not be the programmed value)
+ UINT8 txVref[MAX_RANK_CH][MAX_STROBE]; ///< Actual current value of txVref
+ UINT32 ddrCRCmdTrainingCmdN;
+ UINT32 ddrCRCmdTrainingCmdS;
+ UINT32 ddrCRCtlTraining;
+ UINT32 ddrCRCkeTraining;
+ UINT32 ddrCRClkTraining;
+ UINT32 ddrCRClkRanksUsed;
+ UINT32 dataOffsetTrain[MAX_STROBE];
+ UINT32 DataTrainFeedbackMultiCast;
+ UINT32 ddrCRCmdControls3CmdN;
+ UINT32 ddrCRCmdControls3CmdS;
+ UINT32 ddrCRCmdControls3Ctl;
+ UINT32 ddrCRCmdControls3Cke;
+ UINT32 cmdCsr[MAX_CMD_CSR];
+ UINT32 rxGroup1n[MAX_RANK_CH][MAX_STROBE]; /* CNX Change */
+ UINT32 rxGroup1p[MAX_RANK_CH][MAX_STROBE]; /* CNX Change */
+ UINT32 DdrCrintfDataTiming0;
+ UINT32 TxDqBitClockDelta[MAX_RANK_CH][MAX_STROBE]; ///< Each unit represent 64 ticks
+ ///< [7:0] -> UIs for Bit 0
+ ///< [15:8] -> UIs for Bit 1
+ ///< [23:16] -> UIs for Bit 2
+ ///< [31:24] -> UIs for Bit 3
+ UINT32 EnableRidUnderfillOrg; ///< Nvram Variable to store original EnableRidUnderfill RDB entry
+ UINT32 EnableRidVc2Org; ///< Nvram Variable to store original EnableRidVc2 RDB entry
+ UINT32 EnableRidVc3Org; ///< Nvram Variable to store original EnableRidVC3 RDB entry
+#endif // !DDRIO_DATA_1S
+} CHANNEL_NVRAM_STRUCT, *PCHANNEL_NVRAM_STRUCT;
+
+///
+/// IMC information stored in NVRAM
+///
+typedef struct imcNvram {
+ UINT8 enabled; ///< 0 = imc disabled, 1 = imc enabled
+ UINT32 scrubMask; ///< Scrub mask
+ UINT32 scrubMask2; ///< Scrub mask2
+ UINT8 EmcaLtCtlMcMainExt;
+ UINT32 ExRasConfigHaCfg;
+ UINT32 SmiSpareCtlMcMainExt;
+ UINT8 AppDirectHoleSize;
+ UINT8 imcNodeId; /* System wide socket id for imc */
+ BOOLEAN LaneReversalEn;
+#ifndef DDRIO_DATA_1S
+ UINT32 ddrCRCompCtl0;
+ UINT32 ddrCRCompCtl3; // This is need for silicon workaround 'S1409370801'
+ UINT32 dimmVrefControl1;
+#endif // !DDRIO_DATA_1S
+} IMC_NVRAM_STRUCT; //struct imcNvram
+
+///
+/// Socket information stored in NVRAM
+///
+struct socketNvram {
+ UINT8 enabled;
+ INT32 minTCK; ///< minimum tCK for this DIMM
+ UINT8 ddrFreq; ///< DDR Frequency of this socket
+ UINT16 ddrFreqMHz; ///< DDR Frequency of this socket in MHz
+ UINT16 QCLKps; ///< Qclk period in pS
+ UINT8 cmdClkTrainingDone;
+ UINT8 ddrVoltage; ///< Voltage of this socket
+ UINT8 lrDimmPresent;
+ UINT8 DcpmmPresent;
+ BOOLEAN x16DimmPresent;
+ UINT8 maxDimmPop; ///< Maximum number of DIMM populated on a channel for a socket
+ UINT8 wa; ///< Bit field for workarounds
+ UINT8 ddr4SpdPageEn;
+ struct channelNvram channelList[MAX_CH];
+ struct imcNvram imc[MAX_IMC];
+ UINT64_STRUCT procPpin; ///< Processor PPIN number
+ UINT32 smiCtrlUboxMisc;
+ UINT8 refreshRate;
+ INT8 normalizationFactorEn;
+ UINT16 WdbCacheValidPerChannel; ///< Channel bitmask indicating whether the WDB cache is valid
+ TRAINING_STEP_DONE_STRUCT TrainingStepDone; ///< Indicators of whether a given training step is done
+ UINT8 ddrtFreq;
+ UINT8 cmdVrefTrainingDone;
+ UINT8 mcpPresent;
+ UINT32 FaultyPartsFlag[MAX_CH]; ///< Store faulty strobe info in a channel to NVRAM
+ UINT32 CsrWriteLatency[MAX_CH]; ///< CSR Write Latency from Core-Ubox-iMC[ch] roundtrip
+ UINT32 CsrReadLatency[MAX_CH]; ///< CSR Read Latency from Core-Ubox-iMC[ch] roundtrip
+}; //struct socketNvram
+typedef struct socketNvram SOCKET_NVRAM;
+
+typedef struct memNvram {
+ UINT8 DataGood; ///< Set to one if valid data is present in this structure
+ UINT8 RASmode; ///< RAS mode (lockstep, mirror, sparing)
+ UINT16 RASmodeEx; ///< Extended RAS mode (patrol scrub)
+ UINT8 ratioIndex; ///< Index into the DDR3 ratio table
+ UINT8 eccEn; ///< Set if ECC will be enabled
+ UINT8 dimmTypePresent; ///< Type of DIMMs populated (RDIMM,UDIMM,SODIMM)
+ UINT8 DcpmmPresent; ///< Is an DCPMM present in the system?
+ UINT16 dramType; ///< DDR3 or DDR4 (from keybyte in SPD)
+ UINT32 scrambleSeed; ///< Data scrambling seed
+ UINT32 socketBitMap; ///< CPU present mask
+ UINT8 ExtendedADDDCEn;
+ struct memSetup savedSetupData;
+ struct socketNvram socket[MAX_SOCKET];
+
+ UINT8 XMPProfilesSup;
+ UINT8 XMPProfilesRevision;
+ struct memTiming profileMemTime[2];
+
+ UINT16 Crc16;
+ BOOLEAN FmcCacheDone; ///< Variable to indicate FMC Register caching is finished
+ UINT8 threeDsModeDisabled; ///< Variable to track if 3DS mode is enabled/disabled for CPGC
+ UINT8 volMemMode;
+ UINT8 CacheMemType; ///< Only valid if volMemMode is 2LM
+#ifdef DDRIO_DATA_1S
+ UINT8 DdrioNvdata[DDRIO_DATA_1S * MAX_SOCKET];
+#endif // DDRIO_DATA_1S
+#ifdef DRAM_DATA_1S
+ UINT8 DramNvdata[DRAM_DATA_1S * MAX_SOCKET];
+#endif // DRAM_DATA_1S
+#ifdef RCD_DATA_1S
+ UINT8 RcdNvdata[RCD_DATA_1S * MAX_SOCKET];
+#endif // RCD_DATA_1S
+#ifdef LRDIMM_DB_DATA_1S
+ UINT8 DbNvdata[LRDIMM_DB_DATA_1S * MAX_SOCKET];
+#endif // LRDIMM_DB_DATA_1S
+
+} MEM_NVRAM_STRUCT;
+
+//
+// Max number for FMC cache register and structure
+//
+#define MAX_FMC_CACHE 2
+
+struct FmcCacheSt {
+ UINT8 Status; // Cache status
+ UINT32 Reg; // Register
+ UINT32 Data; // Data
+}; // struct FmcCacheSt
+
+
+///
+/// Rank info
+///
+struct rankDevice {
+ UINT16 MR0; ///< MR0 value for this rank
+ UINT16 MR1; ///< MR1 value for this rank
+ UINT16 MR2; ///< MR2 value for this rank
+ UINT16 MR3; ///< MR3 value for this rank
+ UINT16 MR4; ///< MR4 value for this rank
+ UINT16 MR5; ///< MR5 value for this rank
+ UINT16 MR6[MAX_STROBE]; ///< MR6 value for this rank/dram
+#ifdef LRDIMM_SUPPORT
+ UINT8 CurrentLrdimmTrainingMode;
+ UINT8 CurrentDramMode;
+ UINT16 CurrentMpr0Pattern;
+ UINT8 lrbufRxVrefCache[MAX_STROBE];
+ UINT8 cachedLrBuf_FxBC2x3x[MAX_STROBE];
+ UINT8 cachedLrBuf_FxBC4x5x[MAX_STROBE];
+ UINT8 cachedLrBuf_FxBC8x9x[MAX_STROBE];
+ UINT8 cachedLrBuf_FxBCAxBx[MAX_STROBE];
+ UINT8 cachedLrBuf_FxBCCxEx[MAX_STROBE/2];
+ UINT8 cachedLrBuf_FxBCDxFx[MAX_STROBE/2];
+#endif
+ UINT32 lrbufTxVrefCache[MAX_STROBE];
+}; //struct rankDevice
+
+///
+/// DIMM info
+/// List ordered by proximity to Host (far to near)
+///
+typedef struct dimmDevice {
+ INT32 minTCK; ///< minimum tCK for this DIMM (SPD_MIN_TCK)
+#ifdef DEBUG_CODE_BLOCK
+ UINT32 tCL;
+ UINT16 tRCD;
+ UINT16 tRP;
+#endif // DEBUG_CODE_BLOCK
+ UINT16 NVmemSize;
+ UINT16 memSize; ///< Memory size for this DIMM (64MB granularity)
+ UINT16 UnmappedMemSize;
+ struct rankDevice rankStruct[MAX_RANK_DIMM];
+ struct FmcCacheSt FmcCache[MAX_FMC_CACHE]; ///< FMC cache info/status
+ UINT8 SPDPartitionRatio[MAX_SOCKET * MAX_IMC]; ///< NVM DIMM partitionRatios
+ UINT8 CachedLrBuf_DFECoef[MAX_BITS_IN_BYTE][DB_DFE_TAP][MAX_STROBE/2]; // JEDEC F3BCCx-Fx coeffcient. 8 DQ x 4 taps x 9 DB
+ BOOLEAN FmcWdbFlushFailed; /// < 0 = WDB flush failed on previous boot, 1 = WDB flush completed w/o errors on previous boot
+ BOOLEAN EadrFlushFailed; /// < 0 = Extended ADR flush failed on previous boot, 1 = Extended ADR flush completed w/o errors on previous boot
+} DIMM_DEVICE_INFO_STRUCT; //struct dimmDevice
+
+///
+/// DDRT DIMM info
+///
+typedef struct {
+ UINT16 NgnLogSeqNum[NGN_LOG_TYPE_NUM][NGN_LOG_LEVEL_NUM];
+ UINT16 NgnMaxLogEntries[NGN_LOG_TYPE_NUM][NGN_LOG_LEVEL_NUM];
+ UINT8 NvdimmLinkFailOnPrevBoot : 1, /* Link failure was detected in this boot */
+ NvdimmMediaErrLogged : 1, /* Media error log was detected in this boot */
+ NvdimmTempErrLogged : 1, /* Fatal temperature error log was detected in this boot */
+ NvdimmUnmapped : 1, /* NVDIMM is not to be mapped per memory population POR enforcement or SKU Limit violation. */
+ NvdimmUnmappedReason : 1, /* Reason of NVDIMM is not to be mapped 0 - population POR enforcement, 1 - SKU Limit Violation */
+ NvdimmRemapped : 1, /* NVDIMM is not to be unmapped per memory population POR enforcement. */
+ NvdimmAdModeNotEnabled : 1, /* Indicates whether DIMM SKU reports AD mode enabled or not */
+ Reserved : 1;
+ UINT64_STRUCT NgnBsr; /* NGN NVDIMM Boot Status Register */
+} HOST_DDRT_DIMM_DEVICE_INFO_STRUCT;
+
+typedef struct {
+ UINT8 WdbLine[MRC_WDB_LINE_SIZE];
+} TWdbLine;
+
+///
+/// TT channel info
+///
+typedef struct ddrChannel {
+ UINT8 mcId; ///<Memory controller number
+ UINT8 numDimmSlots; ///<Number of DIMM slots per channel
+ UINT32 memSize; ///<Memory size for this channel (64MB granularity)
+ UINT32 ddr4RemSize; ///<Remaining DDR4 Memory size for this channel
+ UINT32 volSize; ///<Volatile size of the NVM dimms in this channel
+ UINT32 NonVolSize; ///<Non Volatile size of the NVM dimms in this channel
+ UINT32 volRemSize; ///<Remaining Volatile size of the NVM dimms in this channel
+ UINT32 perSize; ///<Pmem size of the NVM dimms in this channel
+ UINT32 perRemSize; ///<Remaining Pmem size of the NVM dimms in this channel
+ UINT32 WbCachePerSize; ///<Persistent WB cache (AD-WB) size of the NVM dimms in this channel
+ UINT32 WbCachePerRemSize; ///<Remaining Persistent WB cache (AD-WB) size of the NVM dimms in this channel
+ UINT32 ctrlSize; ///<Ctrl region size of the NVM dimms in this channel
+ UINT32 ctrlRemSize; ///<Remaining Ctrl region size of the NVM dimms in this channel
+ UINT32 NVmemSize; ///< NVDIMM channel memory size
+ UINT32 NVmemRemSize;
+ UINT32 remSize; ///< Size not yet mapped in units of 64 MB
+ UINT32 DdrCacheSize; ///< Size of DDR memory reserved for 2LM cache (64MB granularity)
+ DIMM_DEVICE_INFO_STRUCT dimmList[MAX_DIMM];
+ HOST_DDRT_DIMM_DEVICE_INFO_STRUCT DdrtDimmList[MAX_DDRT_DIMM_PER_CH];
+ UINT8 CsrUnlock; ///< Whether FMC CSRs are unlocked (accessible/writable)
+ UINT16 FisVersion[MAX_DIMM]; ///< Firmwre Interface Specification version
+} DDR_CHANNEL_STRUCT; //struct ddrChannel
+
+typedef union {
+ struct {
+ UINT8 TrainingPatternMode : 3; // Bits[2:0] - Training Pattern Mode
+ UINT8 QcaUcaTrainingDone : 1; // Bits[3] - QCA training or UDIMM CA training are done or not
+ UINT8 BitIndex : 2; // Bits[5:4] - Used to indicate which bit to test.
+ UINT8 CoarseRdDqDqsTrainingDone : 1; // Bits[6] - Coarse Read Dq/Dqs training are done or not
+ UINT8 Reserved : 1; // Bits[7] - Reserved for future use.
+ } Bits;
+ UINT8 Data;
+} TRAINING_STATUS_STRUCT;
+
+#define MAX_FAIL_RANGE 128
+
+typedef union {
+ struct {
+ UINT32 row : 18; // This field is used for < > comparisons; more significant bits are used for match comparison only
+ UINT32 bankPair : 4;
+ UINT32 logicalSubRank : 3;
+ UINT32 logicalRank : 3;
+ UINT32 upperBgMask : 2; // bit-0 = 1 means failure with upper BG bit = 0; bit-1 = 1 means failure with upper BG = 1
+ UINT32 rfu: 1;
+ UINT32 valid : 1;
+ } Bits;
+ UINT32 Data;
+} ROW_ADDR;
+
+typedef struct {
+ ROW_ADDR addr;
+ UINT32 size;
+ UINT32 mask[3];
+} ROW_FAIL_RANGE;
+
+///
+/// socket info
+///
+typedef struct Socket {
+ UINT8 SocketDieCount; ///< Number of cpu dies present in the socket
+ UINT32 NumMemSs;
+ MRC_MSM MemSsList[MAX_MEM_SS];
+ BOOLEAN ImcPresent[MAX_IMC]; ///< on multi-die, some iMCs might not exist
+ UINT8 imcEnabled[MAX_IMC];
+ UINT8 fatalError;
+ UINT8 majorCode;
+ UINT8 minorCode;
+ UINT8 maxRankDimm; ///< Maximum number or ranks supported per DIMM
+ UINT32 memSize; ///< DDR4 memory size for this socket (64MB granularity)
+ TRAINING_STATUS_STRUCT TrainingStatus;
+ struct ddrChannel channelList[MAX_CH];
+ UINT8 socketSubBootMode;
+ UINT8 hostRefreshStatus;
+ UINT8 firstJEDECDone; ///< Flag to indicate the first JEDEC Init has executed
+ UINT64_STRUCT procPpin;
+ UINT8 cadbMRSMode; ///< Mode of operation (LOAD / EXECUTE / NORMAL)
+ UINT8 cadbMRSIndex[MAX_CH];
+ UINT32 NVmemSize; ///< Memory size for this node
+ UINT32 TotalInterleavedMemSize; ///< DDR4 memory size for this socket (64MB granularity)
+ UINT32 TotalInterleavedNVMemSize;///< Actual NVMEM interleaved.
+ UINT32 volSize; ///< Volatile size of the NVM dimms for this socket (64MB granularity)
+ UINT32 perSize; ///< Persistent size of the NVM dimms for this socket (64MB granularity)
+ UINT32 WbCachePerSize; ///< Persistent WB cache (AD-WB) size of the NVM dimms for this socket (64MB granularity)
+ BOOLEAN TurnaroundInitDone; ///< Turnaround Initialization Done
+ MRC_TT CurrentTestType; ///< Training step currently being executed by this socket
+ SOCKET_CHIP ///< Chip hook to enable Socket fields
+} SOCKET_INFO_STRUCT; // struct Socket
+
+///
+/// Sub-boot state internal to MRC (8-15 are definable). The 2 main boot types and paths through KTI RC/MRC - NormalBoot and S3Resume.
+/// Within NormalBoot and S3Resume, the sub-boot type can be cold, warm, fast warm, fast cold, and ADR resume. These are populated
+/// at the beginning of MRC so they are not applicable for KTI RC.
+///
+typedef enum SubBootMode
+{
+ ColdBoot = 8, // Normal path through MRC with full mem detection, init, training, etc.
+ WarmBoot = 9, // Warm boot path through MRC. Some functionality can be skipped for speed.
+ WarmBootFast = 10, // Fast warm boot path uses the NVRAM structure to skip as much MRC
+ // code as possible to try to get through MRC fast. Should be as close
+ // as possible to the S3 flow.
+ ColdBootFast = 11, // Fast cold boot path uses the NVRAM structure to skip as much MRC
+ // code as possible on a cold boot.
+ AdrResume = 12, // ADR flow can skip most of MRC (i.e. take the S3 path) for DIMMs that
+ // are in self-refresh. But the DIMMs that are not in self-refresh
+ // must go through more of MRC.
+ NvDimmResume = 13 // NvDimm flow is similar to Adr Batterybackup, but the DIMMs need
+ // Rx & Mx registers initialized.
+} SUB_BOOT_MODE;
+
+///
+/// define the Training_Result_UP/DOWN CRs struct.
+///
+struct TrainingResults {
+ UINT32 results[4];
+};
+
+#ifdef LRDIMM_SUPPORT
+struct lrMrecTrainingResults {
+ UINT8 results;
+};
+#endif // LRDIMM_SUPPORT
+
+#define MEM_CHIP_POLICY_DEF(x) Host->var.mem.memChipPolicy.x
+#define MEM_CHIP_POLICY_VALUE(Host, x) Host->var.mem.memChipPolicy.x
+typedef struct {
+ UINT8 maxVrefSettings; // MAX_VREF_SETTINGS
+ UINT8 earlyVrefStepSize; // EARLY_VREF_STEP_SIZE
+ INT16 ctlPiGrp; // CTL_PI_GRP
+ UINT8 minIoLatency; // MIN_IO_LATENCY
+ UINT16 cas2DrvenMaxGap; // CAS2DRVEN_MAXGAP
+ UINT8 mrcRoundTripIoComp; // MRC_ROUND_TRIP_IO_COMPENSATION;
+ UINT8 mrcRoundTripIoCompStart; // MRC_ROUND_TRIP_IO_COMP_START;
+ UINT8 mrcRoundTripMax; // MRC_ROUND_TRIP_MAX_VALUE;
+ UINT32 SrPbspCheckinCsr; // SR_PBSP_CHECKIN_CSR (BIOSNONSTICKYSCRATCHPAD2_UBOX_MISC_REG) // UBOX scratchpad CSR02
+ UINT32 SrBiosSerialDebugCsr; // SR_BIOS_SERIAL_DEBUG_CSR(BIOSSCRATCHPAD6_UBOX_MISC_REG) // UBOX scratchpad CSR6
+ UINT32 SrPostCodeCsr; // SR_POST_CODE_CSR (BIOSNONSTICKYSCRATCHPAD7_UBOX_MISC_REG) // UBOX scratchpad CSR7
+ UINT32 SrErrorCodeCsr; // SR_ERROR_CODE_CSR (BIOSNONSTICKYSCRATCHPAD8_UBOX_MISC_REG) // UBOX scratchpad CSR8
+ UINT32 SrMemoryDataStorageDispatchPipeCsr; // #define SR_MEMORY_DATA_STORAGE_DISPATCH_PIPE_CSR (BIOSNONSTICKYSCRATCHPAD13_UBOX_MISC_REG) // UBOX scratchpad CSR13
+ UINT32 SrMemoryDataStorageCommandPipeCsr; // #define SR_MEMORY_DATA_STORAGE_COMMAND_PIPE_CSR (BIOSNONSTICKYSCRATCHPAD14_UBOX_MISC_REG) // UBOX scratchpad CSR14
+ UINT32 SrMemoryDataStorageDataPipeCsr; // #define SR_MEMORY_DATA_STORAGE_DATA_PIPE_CSR (BIOSNONSTICKYSCRATCHPAD15_UBOX_MISC_REG) // UBOX scratchpad CSR15
+ UINT32 SrBdatStructPtrCsr; // SR_BDAT_STRUCT_PTR_CSR
+ UINT32 BiosStickyScratchPad0; // BIOSSCRATCHPAD0_UBOX_MISC_REG
+ UINT8 PerBitMarginDefault; // PER_BIT_MARGIN_DEFAULT
+ UINT8 RxOdtDefault; // RX_ODT_DEFAULT
+ UINT8 CmdTxEqDefault; // CMD_TX_EQ_DEFAULT
+ UINT8 RxDfeDefault; // RX_DFE_DEFAULT
+ UINT8 TxRiseFallSlewRateDefault; // TX_RF_SLEW_RATE_DEFAULT
+ UINT8 RmtColdFastBootDefault; // RMT_COLD_FAST_BOOT_DEFAULT
+ UINT8 RxVrefTrainingMode; // RX_VREF_TRAINING_MODE
+ UINT8 TxVrefTrainingMode; // TX_VREF_TRAINING_MODE
+ UINT16 MaxPhaseInReadAdjustmentDq; // MAX_PHASE_IN_READ_ADJUSTMENT_DQ
+} MEM_CHIP_POLICY;
+
+struct DimmDeviceTraining {
+ UINT8 oneRankTimingModeLrbuf_FxBC2x3x[MAX_STROBE];
+ UINT8 oneRankTimingModeLrbuf_FxBC4x5x[MAX_STROBE];
+ UINT8 oneRankTimingModeLrbuf_FxBC8x9x[MAX_STROBE];
+ UINT8 oneRankTimingModeLrbuf_FxBCAxBx[MAX_STROBE];
+ UINT8 oneRankTimingModeLrbuf_FxBCCxEx[MAX_STROBE/2];
+ UINT8 oneRankTimingModeLrbuf_FxBCDxFx[MAX_STROBE/2];
+ UINT8 originalRank0Lrbuf_FxBC2x3x[MAX_RANK_DIMM][MAX_STROBE];
+ UINT8 originalRank0Lrbuf_FxBC4x5x[MAX_RANK_DIMM][MAX_STROBE];
+ UINT8 originalRank0Lrbuf_FxBC8x9x[MAX_RANK_DIMM][MAX_STROBE];
+ UINT8 originalRank0Lrbuf_FxBCAxBx[MAX_RANK_DIMM][MAX_STROBE];
+ UINT8 originalRank0Lrbuf_FxBCCxEx[MAX_RANK_DIMM][MAX_STROBE/2];
+ UINT8 originalRank0Lrbuf_FxBCDxFx[MAX_RANK_DIMM][MAX_STROBE/2];
+}; //struct DimmDeviceTraining
+
+/// TT channel info
+///
+struct DdrChannelTraining {
+ TWdbLine WdbLines[MRC_WDB_LINES];
+ struct DimmDeviceTraining dimmList[MAX_DIMM];
+}; //struct DdrChannelTraining
+
+struct TrainingVariable {
+ UINT8 rdVrefLo;
+ UINT8 rdVrefHi;
+ UINT8 wrVrefLo;
+ UINT8 wrVrefHi;
+ UINT8 cmdVrefLo;
+ UINT8 cmdVrefHi;
+ UINT8 DQPat; ///< Global Variables storing the current DQPat REUT Test
+ UINT8 DQPatLC; ///< Global Variables storing the current DQPat Loopcount
+ BOOLEAN EnDumRd; ///< Enable/Disable Logic Analizer
+
+ INT16 TxDqLeft[MAX_CH][MAX_RANK_CH][MAX_STROBE];
+ INT16 TxDqRight[MAX_CH][MAX_RANK_CH][MAX_STROBE];
+ INT16 TxVrefLow[MAX_CH][MAX_RANK_CH][MAX_STROBE];
+ INT16 TxVrefHigh[MAX_CH][MAX_RANK_CH][MAX_STROBE];
+ INT16 RxDqsLeft[MAX_CH][MAX_RANK_CH][MAX_STROBE];
+ INT16 RxDqsRight[MAX_CH][MAX_RANK_CH][MAX_STROBE];
+ INT16 RxVrefLow[MAX_CH][MAX_RANK_CH][MAX_STROBE];
+ INT16 RxVrefHigh[MAX_CH][MAX_RANK_CH][MAX_STROBE];
+
+ struct DdrChannelTraining channelList[MAX_CH];
+}; //struct TrainingVariable
+
+///
+/// Indicates how SPD data should be retrieved:
+/// SpdSmbus Data should be retrieved via SMBUS
+/// SpdInternal Data should be retrieved via internal SPD array
+/// SpdInternalTrace Data should be retrieved via internal SPD array, but the SMBUS transactions should still be
+/// carried out to generate register traces for debugging
+///
+typedef enum {
+ SpdSmbus,
+ SpdInternal,
+ SpdInternalTrace,
+ SpdMax
+} SPD_SOURCE;
+
+//
+// CMI Read and Write credit configuration register defaults
+//
+typedef struct {
+ UINT32 CmiRdCreditConfigN0;
+ UINT32 CmiRdCreditConfigN1;
+ UINT32 CmiWrCreditConfigN0;
+ UINT32 CmiWrCreditConfigN1;
+ BOOLEAN Valid; /// Set to TRUE when structure is updated
+} CMI_CREDIT_CONFIG_DEFAULT;
+
+///
+/// TT Host info
+///
+typedef struct memVar {
+ UINT8 currentSocket; ///< Current socket being initialized
+ UINT8 PostCodeMinor;
+ SUB_BOOT_MODE subBootMode; ///< WarmBoot, WarmBootFast, etc.
+ UINT8 wipeMemory; ///< Write 0 to all memory to clean secrets
+ UINT8 skipMemoryInit; ///< Skip memory init based on certain conditions.
+ UINT8 ddrFreqLimit; ///< Set to limit frequency by the user
+ UINT8 chInter; ///< Number of ways to interleave channels (1,2,3, or 4)
+ UINT8 callingTrngOffstCfgOnce; ///<to prevent looping inside RMT
+ UINT8 earlyCmdClkExecuted;
+ UINT8 checkMappedOutRanks;
+#ifdef DEBUG_CODE_BLOCK
+ UINT8 earlyCtlClkSerialDebugFlag;
+#endif // DEBUG_CODE_BLOCK
+ UINT32 memSize; ///< Total physical memory size
+ UINT32 NVmemSize; ///< Total physical memory size
+ UINT32 TotalInterleavedMemSize; ///< DDR4 memory size for this socket (64MB granularity)
+ UINT32 TotalInterleavedNVMemSize; /// < Actual NVMEM interleaved.
+ UINT32 QCLKPeriod; ///< QCLK Period in pico seconds
+ UINT32 lowMemBase; ///< Mem base in 64MB units for below 4GB mem.
+ UINT32 lowMemSize; ///< Mem size in 64MB units for below 4GB mem.
+ UINT32 highMemBase; ///< Mem base in 64MB units for above 4GB mem.
+ UINT32 highMemSize; ///< Mem size in 64MB units for above 4GB mem.
+ UINT32 initialLFSRSeed;
+ UINT32 piSettingStopFlag[MAX_CH];
+ UINT8 pxcEnabled;
+ struct Socket socket[MAX_SOCKET]; ///< Per socket structure
+ struct TrainingVariable TrainingVar; ///< Local variable for DDR training
+ UINT32 NumValidPprEntries;
+ PPR_ADDR_MRC_SETUP pprAddrSetup[MAX_PPR_ADDR_ENTRIES_SPPR];
+ UINT8 pprStatus[MAX_PPR_ADDR_ENTRIES_SPPR];
+ UINT8 softPprDone[MAX_SOCKET];
+ ///
+ /// Flag to skip RowTestPPR execution, so it wont return false error
+ ///
+ BOOLEAN SkipPprRowTest[MAX_SOCKET];
+ //
+ // Avanced Memtest Failure Range tracking
+ //
+ UINT8 FailRangeInitDone[MAX_SOCKET];
+ ROW_FAIL_RANGE FailRange[MAX_CH][MAX_FAIL_RANGE];
+ UINT32 FailMax[MAX_CH]; // This is initialized to 0 prior to any memtest, indicating no failures
+ INT32 FailIndex[MAX_CH];
+ UINT8 RetryState;
+ ROW_FAIL_RANGE LastFail[MAX_CH];
+ UINT8 PprResourceAvailable[MAX_CH][MAX_DIMM * MAX_RANK_DIMM_3DS * MAX_SUBRANK_3DS][MAX_STROBE]; // Max logical ranks = 16 (2DPC, 3DS 2R-4H), each BG is bit-mapped into UINT8
+ UINT64_STRUCT AdvMemtestErrInjMask;
+ UINT8 InjectErrorMATS[MAX_CH];
+ UINT8 AmtErrInjDone;
+ BOOLEAN IsDdrMemInitDone; ///< Flag indicates if DDR memory init is done.
+
+#ifdef LRDIMM_SUPPORT
+ struct TrainingResults lrTrainRes[MAX_CH][MAX_STROBE];
+ struct lrMrecTrainingResults lrMrecTrainRes[MAX_CH][MAX_STROBE];
+ struct TrainingResults lrMrdTrainRes[MAX_CH][MAX_STROBE];
+ struct TrainingResults lrDwlTrainRes[MAX_CH][MAX_STROBE];
+ struct lrMrecTrainingResults lrCwlTrainRes[MAX_CH][MAX_STROBE];
+ struct TrainingResults lrMwdTrainRes[MAX_CH][MAX_STROBE];
+ UINT8 InPbaWaMode;
+ UINT8 InOvrRttPrkMode;
+#endif // LRDIMM_SUPPORT
+
+ UINT8 maxSubRank;
+ UINT8 currentSubRank;
+ struct TrainingResults trainRes[MAX_CH][MAX_STROBE];
+ BOOLEAN PerformanceTrackerInitialized;
+ UINT8 firstPass;
+ UINT8 previousBootError;
+ UINT8 xoverModeVar; ///< xover mode (1 = xover2:2, 0 = native 1:1)
+ UINT32 Reserved6;
+ UINT8 Reserved7[RESERVED_2];
+ EFI_GUID Reserved8[RESERVED_2];
+ UINT8 Reserved9;
+
+ SPD_SOURCE SpdSource; ///< Determines SPD data source
+ UINT8 SmbMode[MAX_SOCKET][MAX_SMB_INSTANCE]; ///< Stores type of smbus mode: 0 - I2C mode, 1 - I3C mode
+ UINT8 rankInter; ///< 1, 2, 4, or 8 way interleave
+ UINT8 RasStatePrevBoot;
+ UINT32 mccpubusno;
+ UINT32 rtDefaultValue;
+ UINT8 channelEn;
+ UINT8 runningRmt; ///< Flag to check that the RankMarginTool is currently being running
+ UINT32 lastCheckpoint[MAX_SOCKET];
+ UINT8 notRunningFromCT; ///< PostPackageRepairMain called from the CallTable (CT)
+ UINT32 chBitMask;
+ UINT8 FmcMaxCached; ///< Record how many FMC register been cached
+ UINT32 FmcCachedReads; ///< Record the amount of total FMC cache read times
+ MEM_CHIP_POLICY memChipPolicy;
+ BOOLEAN secondPass[MAX_CH][MAX_STROBE];
+ UINT8 volMemMode; ///< 0: 1LM 1:2LM 2:Undefined
+ UINT8 CacheMemType; ///< 0: DDR$DDRT Only valid if volMemMode is 2LM
+
+ UINT8 PmemCaching; // caching contorl for AppDirect
+ UINT8 EadrSupport; // eADR support
+ UINT8 EadrCacheFlushMode;
+
+ UINT8 imcInter; // Number of ways to interleave imc (1 or 2)
+ UINT32 mmiohBase; // MMIOH base in 64MB granularity
+ UINT8 read2tckCL[MAX_CH]; // increases to CL or CWL based on TCLK preamble
+ UINT8 write2tckCWL[MAX_CH];
+ UINT8 memInterleaveGran1LM;
+ struct Reserved168 Reserved168;
+ UINT32 optionsNgn;
+ UINT8 setSecureEraseAllDIMMs;
+ UINT8 setSecureEraseSktCh[MAX_SOCKET][MAX_CH];
+ UINT8 SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH];
+ BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH]; // ADR state for Intel PMEM Modules
+ UINT8 AppDirectMemoryHole;
+ UINT8 LsxImplementation;
+ UINT32 NvdimmSmbusMaxAccessTime;
+ UINT32 NvdimmSmbusReleaseDelay;
+ MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // Block decoder data for memory map
+ UINT8 ExtendedType17;
+
+ BOOLEAN DdrtReadPendingQueueTimedOut[MAX_SOCKET][MAX_CH]; ///< Each element represents whether a given channel has had a DDRT Read Pending Queue (RPQ) timeout
+ BOOLEAN DdrtReadPendingQueueCreditLimitSet[MAX_SOCKET][MAX_CH]; ///< Each element represents whether a given channel has the DDRT Read Pending (RPQ) credit limit enabled
+ BOOLEAN DdrtSkipRpqDrainInCpgcPolling[MAX_SOCKET]; ///< Indicates whether to drain the DDRT RPQ when polling for CPGC done
+ BOOLEAN WrLvlDeNormalizeStatus[MAX_SOCKET][MAX_CH][MAX_DIMM];
+ BOOLEAN EkvPresent; ///< Set if EKV controller on system
+ BOOLEAN BwvPresent; ///< Set if BWV controller on system
+ BOOLEAN FastWarmBootDowngraded; ///On slow boot when FWR is downgrated to SWR NVDIMMS need to do a catastrophic save to prevent data loss
+ BOOLEAN DcpmmWaitMediaReady; ///< Set on Slow Warm boots to indicate that BIOS needs to poll for Media Ready on DCPMM DIMMs after CKE is asserted
+ BOOLEAN WarmBootRequested; ///< Set on Warm boots when is not possible to detect warm boot it via subBootMode (when BIOS internally promoted warm reset to cold reset/fast cold reset)
+ CMI_CREDIT_CONFIG_DEFAULT CmiCreditConfigDefault;
+ UINT16 BiosFisRevision;
+ UINT16 MaxAveragePowerLimit; ///< Max Power limit in mW used for averaged power ( Valid range ends at 15000mW)
+ UINT16 MinAveragePowerLimit; ///< Min Power limit in mW used for averaged power ( Valid range starts from 10000mW)
+ UINT16 CurrAveragePowerLimit; ///< Current Power limit in mW used for average power
+ UINT16 MaxMbbPowerLimit; ///< Max MBB power limit ( Valid range ends at 18000mW).
+ UINT16 MinMbbPowerLimit; ///< Min MBB power limit ( Valid range starts from 15000mW).
+ UINT16 CurrMbbPowerLimit; ///< Current Power limit in mW used for MBB power
+ UINT32 MaxMbbAveragePowerTimeConstant; ///< Max MBB Average Power Time Constant
+ UINT32 MinMbbAveragePowerTimeConstant; ///< Min MBB Average Power Time Constant
+ UINT32 CurrMbbAveragePowerTimeConstant; ///< Current MBB Average POwer Time Constant
+ BOOLEAN RmtMinimumMarginCheckEnable;
+} MEM_VAR_STRUCT; // struct memVar
+
+#pragma pack(pop)
+
+#endif // _memhost_h
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h
new file mode 100644
index 0000000000..aed571f4cd
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h
@@ -0,0 +1,190 @@
+/** @file
+
+ @copyright
+ Copyright 2006 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _memhostchipcommon_h
+#define _memhostchipcommon_h
+
+
+#include "SysHostChipCommon.h"
+#include "NGNDimmPlatformCfgData.h"
+#include <MemCommon.h>
+#include <Library/MemTypeLib.h>
+
+#define MAX_MEM_SS 8 // Max Memory Subsystems per socket
+#define MAX_CLUSTERS 4 // Maximum number of clusters supported
+
+#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes
+#define MAX_DIMM 2 // Max DIMM per channel
+#define MAX_DDRT_DIMM_PER_CH 1 // Max DDRT DIMM per channel
+#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM
+
+#define MAX_BITS 72 // Max number of data bits per rank
+#define MAX_TECH 19 // Number of entries in DRAM technology table
+#define MAX_TECH_DDRT 8
+
+#define TAD_RULES 8 // Number of near memory TAD rule registers
+#define FM_TAD_RULES 12 // Number of far memory TAD rule registers
+#define FM_TAD_RULES_10NM 4 // Number of far memory only TAD rule registers in 10nm
+#define MAX_TAD_RULES (TAD_RULES + FM_TAD_RULES) // Number of combined near and far TAD rules
+#define MAX_TAD_RULES_10NM (TAD_RULES + FM_TAD_RULES_10NM) // Number of combined near and far TAD rules in 10nm
+#define MAX_TAD_WAYS 3 // Number of interleave ways for TAD RULES
+#define MAX_RT_WAYS 8 // Max. interleave ways for DDR/DDRT RTs in 256B McChan granularity
+#define MAX_RT 2 // Number of RTs per route table type
+#define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform
+
+#define MAX_STROBE 18 // Number of strobe groups
+
+#define MAX_RANK_DIMM_3DS 2 // Max physical CS ranks per 3DS DIMM
+#define MAX_SUBRANK_3DS 4 // Max logical C[2:0] subranks per CS in 3DS DIMM
+#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
+#define MAX_SUBRANK 2 // Max subranks per logical rank
+#define SPD_MODULE_PART_DDR4 20 // Number of bytes of module part - DDR4
+#define SPD_MODULE_SERIAL 4 // Number of bytes of Module Serial Number
+#define MAX_PARTIAL_MIRROR 4 //Maximum number of partial mirror regions that can be created
+
+#define CONVERT_64MB_TO_4KB_GRAN 14
+#define CONVERT_4KB_TO_64MB_GRAN 14
+#define CONVERT_64MB_TO_GB_GRAN 4
+#define CONVERT_GB_TO_64MB_GRAN 4
+#define CONVERT_64MB_TO_MB_GRAN 6
+#define CONVERT_MB_TO_64MB_GRAN 6
+#define CONVERT_64MB_TO_4GB_GRAN 6
+#define CONVERT_4GB_TO_64MB_GRAN 6
+#define CONVERT_64MB_TO_32GB_GRAN 9
+#define CONVERT_64B_TO_64MB 20
+#define CONVERT_B_TO_MB 20
+#define CONVERT_MB_TO_B 20
+#define CONVERT_B_TO_64MB 26
+#define CONVERT_64MB_TO_B 26
+#define CONVERT_64MB_TO_128MB_GRAN 1
+#define CONVERT_256MB_TO_64MB_GRAN 2
+#define CONVERT_64MB_TO_256MB_GRAN 2
+#define CONVERT_B_TO_256MB_GRAN 28
+
+#define MEM_1GB_AT_64MB_GRAN 0x10
+#define MEM_1GB_AT_4KB_GRAN 0x40000
+
+#define GB_TO_MB_CONVERSION 1024
+
+#define BITMAP_CH0_CH1_CH2 ( ( BIT0 ) | (BIT1 ) | (BIT2) )
+#define BITMAP_CH0_CH1 ( ( BIT0 ) | (BIT1 ) )
+#define BITMAP_CH1_CH2 ( ( BIT1 ) | (BIT2 ) )
+#define BITMAP_CH0_CH2 ( ( BIT0 ) | (BIT2 ) )
+#define BITMAP_CH0 BIT0
+#define BITMAP_CH1 BIT1
+#define BITMAP_CH2 BIT2
+
+#define CONVERT_64MB_TO_BYTE 64 * 1024 * 1024
+
+//
+// Define the WDB line. The WDB line is like the cache line.
+//
+#define MRC_WDB_LINES 32
+#define MRC_WDB_LINE_SIZE 64
+
+#define MAX_PHASE_IN_FINE_ADJUSTMENT 64
+#define MAX_PHASE_IN_READ_ADJ_DQ_RX_DFE 152 // larger range for added DQ 1/16 PI adjustments
+
+#pragma pack(1)
+typedef struct TADTable {
+ UINT8 Enable; // Rule enable
+ UINT8 SADId; // SAD Index
+ UINT8 socketWays; // Socket Interleave ways for TAD
+ UINT8 NmTadIndex; // Index of near memory TAD
+ UINT8 FmTadIndex; // Index of far memory TAD
+ UINT32 Limit; // Limit of the current TAD entry
+ UINT8 TargetGran; // MC granularity of 1LM forward and 2LM forward/reverse address decoding.
+ UINT8 ChGran; // Channel granularity of 1LM forward and 2LM forward/reverse address decoding.
+} TAD_TABLE;
+
+typedef struct SADTable {
+ UINT8 Enable; // Rule enable
+ MEM_TYPE type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges.
+ UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
+ UINT32 Base; // Base of the current SAD entry
+ UINT32 Limit; // Limit of the current SAD entry
+ UINT8 ways; // Interleave ways for SAD
+ UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+ UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+ UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM.
+ UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT.
+ UINT8 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket.
+ UINT8 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM (10nm usage only).
+ BOOLEAN local; //0 - Remote 1- Local
+ UINT8 IotEnabled; // To indicate if IOT is enabled
+ UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring
+ UINT8 Attr;
+ UINT8 tgtGranularity; // Interleave mode for target list
+ UINT8 Cluster; // SNC cluster, hemisphere, or quadrant index.
+} SAD_TABLE;
+
+typedef struct IMC {
+ UINT8 imcEnabled[MAX_IMC];
+ UINT8 imcNum; // imc Number
+ UINT32 memSize; // DDR4 memory size for this imc (64MB granularity)
+ UINT32 NVmemSize; // NV Memory size of this ha
+ UINT32 volSize; // Volatile size of the NVM dimms for this imc (64MB granularity)
+ UINT32 NonVolSize; // Non-Volatile size of the NVM DIMMs for this iMC (64MB granularity)
+ UINT32 perSize; // Persistent size of the NVM dimms for this imc (64MB granularity)
+ UINT32 WbCachePerSize; // Persistent WB cache (AD-WB) size of the NVM dimms for this imc (64MB granularity)
+ UINT8 TADintList[MAX_TAD_RULES][MAX_TAD_WAYS]; // TAD interleave list for this socket
+ UINT8 TADChnIndex[MAX_TAD_RULES][MAX_TAD_WAYS]; // Corresponding TAD channel indexes (per channel)
+ INT32 TADOffset[MAX_TAD_RULES][MAX_TAD_WAYS]; // Corresponding TAD offsets (per channel)
+ TAD_TABLE TAD[MAX_TAD_RULES]; // TAD table
+ UINT8 imcChannelListStartIndex; // Index in channel list of first channel on this imc
+} IMC_INFO_STRUCT;
+
+typedef struct firmwareRev {
+ UINT8 majorVersion;
+ UINT8 minorVersion;
+ UINT8 hotfixVersion;
+ UINT16 buildVersion;
+} FIRMWARE_REV;
+
+typedef struct Reserved168 {
+ UINT8 Reserved79;
+ UINT8 Reserved80;
+ UINT8 Reserved83;
+ UINT8 Reserved86[MAX_SOCKET * MAX_IMC];
+ UINT8 Reserved89;
+ UINT8 Reserved87;
+ UINT8 Reserved148;
+} MEM_RESERVED_1;
+
+#pragma pack()
+
+#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number
+
+typedef struct {
+ UINT32 BlockDecoderBase; // 64MB unit
+ UINT32 BlockDecoderLimit;
+ UINT8 BlockSocketEnable;
+ UINT8 BlockMcChEn[MAX_SI_SOCKET][MAX_IMC][MAX_MC_CH];
+} MEMORY_MAP_BLOCK_DECODER_DATA;
+
+//
+// Chip specific section of struct Socket
+//
+#define SOCKET_CHIP \
+ struct SADTable SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; \
+ UINT8 DdrtChRouteTable[MAX_RT][MAX_RT_WAYS]; /* PMEM/BLK memory channel route table 2 for CR protocol */ \
+ UINT8 DdrtTgtRouteTable[MAX_RT][MAX_RT_WAYS]; /* PMEM/BLK memory target route table 2 for CR protocol */ \
+ struct IMC imc[MAX_IMC]; \
+ UINT8 ddrClkData; \
+ UINT8 ddrClkType; \
+ UINT8 ddrFreqCheckFlag; \
+ UINT8 SktSkuValid; \
+ UINT32 SktSkuLimit; \
+ UINT32 SktTotMemMapSPA; \
+ UINT32 SktPmemMapSpa; \
+ UINT32 SktMemSize2LM; \
+ UINT8 maxFreq; \
+ UINT8 clkSwapFixDis; \
+ UINT8 ioInitdone;
+
+#endif // _memhostchipcommon_h
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h
new file mode 100644
index 0000000000..3c8abe4dbb
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h
@@ -0,0 +1,25 @@
+/** @file
+ MemRegs.h
+
+ @copyright
+ Copyright 2006 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _memregs_h
+#define _memregs_h
+
+//
+// NVM DIMM Reg Structs
+//
+
+typedef union {
+ struct {
+ UINT8 module_type : 4;
+ UINT8 module_revision : 4;
+ } Bits;
+ UINT8 Data;
+} SPD_AEP_MOD_REVISION_STRUCT;
+
+#endif // _memregs_h
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h
new file mode 100644
index 0000000000..eba0a14354
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h
@@ -0,0 +1,28 @@
+/** @file
+ MrcCommonTypes.h
+
+ @copyright
+ Copyright 2015 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _MrcCommonTypes_h_
+#define _MrcCommonTypes_h_
+
+#include "DataTypes.h"
+#include <MemCommon.h>
+
+typedef struct {
+ MRC_MST MemSsType;
+ UINT32 NumDataCh; // Total number of physical data channels in the MemSS
+ UINT32 NumDataIoFubsPerCh; // Total number of IO fubs in a data channel
+ UINT32 NumDataIoFubsPerSubCh; // Total number of IO fubs in a data sub channel
+ UINT32 NumDqLanesPerCh; // Number of active DQ lanes in a data channel (bus width)
+} MRC_MSM;
+
+typedef enum {
+ MrcTtDelim = MAX_INT32
+} MRC_TT;
+
+#endif // _MrcCommonTypes_h_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/NGNDimmPlatformCfgData.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/NGNDimmPlatformCfgData.h
new file mode 100644
index 0000000000..81ea4fc373
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/NGNDimmPlatformCfgData.h
@@ -0,0 +1,22 @@
+/** @file
+ NGNDimmPlatformCfgData.h
+
+ @copyright
+ Copyright 2014 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _NGN_DIMM_PLATFORM_CONFIG_DATA_H_
+#define _NGN_DIMM_PLATFORM_CONFIG_DATA_H_
+
+#define NGN_MAX_MANUFACTURER_STRLEN 2
+#define NGN_MAX_SERIALNUMBER_STRLEN 4
+#define NGN_MAX_PARTNUMBER_STRLEN 20
+#define NGN_MAX_UID_STRLEN 9
+#define NGN_FW_VER_LEN 4
+
+#define NGN_LOG_TYPE_NUM 2
+#define NGN_LOG_LEVEL_NUM 2
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h
new file mode 100644
index 0000000000..d419edea4a
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h
@@ -0,0 +1,193 @@
+/** @file
+ SysHost.h
+
+ @copyright
+ Copyright 2006 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SYS_HOST_H_
+#define _SYS_HOST_H_
+
+#include "SysHostChipCommon.h"
+
+
+
+#define MAX_LINE 256
+
+#define RC_SIM_FASTCADB 0
+
+
+
+typedef struct sysHost SYSHOST, *PSYSHOST;
+
+#include "DataTypes.h"
+#include "SysHostChipCommon.h"
+#include "PlatformHost.h"
+#include "MemHost.h"
+#include <Ppi/MemoryPolicyPpi.h>
+
+///
+/// Enhanced Warning Log Header
+///
+typedef struct {
+ EFI_GUID EwlGuid; /// GUID that uniquely identifies the EWL revision
+ UINT32 Size; /// Total size in bytes including the header and buffer
+ UINT32 FreeOffset; /// Offset of the beginning of the free space from byte 0
+ /// of the buffer immediately following this structure
+ /// Can be used to determine if buffer has sufficient space for next entry
+ UINT32 Crc; /// 32-bit CRC generated over the whole size minus this crc field
+ /// Note: UEFI 32-bit CRC implementation (CalculateCrc32) (References [7])
+ /// Consumers can ignore CRC check if not needed.
+ UINT32 Reserved; /// Reserved for future use, must be initialized to 0
+} EWL_HEADER;
+
+///
+/// Enhanced Warning Log Spec defined data log structure
+///
+typedef struct {
+ EWL_HEADER Header; /// The size will vary by implementation and should not be assumed
+ UINT8 Buffer[4 * 1024]; /// The spec requirement is that the buffer follow the header
+} EWL_PUBLIC_DATA;
+
+///
+/// EWL private data structure. This is going to be implementation dependent
+/// When we separate OEM hooks via a PPI, we can remove this
+///
+typedef struct {
+ UINT32 bufSizeOverflow; // Number of bytes that could not be added to buffer
+ UINT32 numEntries; // Number of entries currently logged
+ EWL_PUBLIC_DATA status; // Spec defined EWL
+} EWL_PRIVATE_DATA;
+
+#pragma pack(1)
+
+///
+/// System NVRAM structure
+//
+struct sysNvram {
+ struct memNvram mem;
+ struct commonNvram common;
+}; //struct sysNvram
+
+#pragma pack()
+
+//
+// -----------------------------------------------------------------------------
+// Variable structures
+//
+
+typedef struct CpuidRegisterInfo {
+ UINT32 Eax;
+ UINT32 Ebx;
+ UINT32 Ecx;
+ UINT32 Edx;
+} CPUID_REGISTER_INFO;
+
+typedef struct processorCommon {
+ UINT32 capid0;
+ UINT32 capid1;
+ UINT32 capid2;
+ UINT32 capid3;
+ UINT32 capid4;
+ UINT32 capid5;
+ UINT32 capid6lo;
+ UINT32 capid6hi;
+ CPUID_REGISTER_INFO ExtCpuid7;
+ CPUID_REGISTER_INFO ExtCpuid1B;
+} PROCESSOR_COMMON;
+
+///
+/// Common variable structure
+///
+struct commonVar {
+ RC_VERSION RcVersion; ///< Version of the reference code last executed
+ UINT32 rcStatus; ///< Non-zero indicates fatal error
+ UINT8 chopType[MAX_SOCKET]; ///< HCC, MCC, LCC, MCC-DE, LCC-DE (HSX family only)
+ UINT8 sbsp; ///< Non-zero value indicates that the socket is System BSP
+ UINT16 pmBase; ///< Power Management Base Address
+ UINT32 tohmLimit;
+ UINT32 JumpBuffer;
+
+#ifdef COMPRESS_RC
+ UINT32 rcSrc; ///< Decompression source code pointer
+ UINT32 rcDest; ///< Decompression destination pointer
+ UINT32 rcDecompressSourceAddr; ///< Decompression routine address of type func(UINT8*Src, UINT8*Dest);
+#endif // #ifdef COMPRESS_RC
+
+ UINT32 heapBase;
+ UINT32 heapSize;
+
+ UINT32 oemVariable;
+ EWL_PRIVATE_DATA ewlPrivateData; // implementation data for EWL
+ struct processorCommon procCom[MAX_SOCKET];
+ UINT32 MicroCodeRev;
+
+#define MAX_PROMOTE_WARN_LIMIT 90
+ UINT32 promoteWarnLimit;
+ UINT16 promoteWarnList[MAX_PROMOTE_WARN_LIMIT];
+ UINT32 printfDepth; ///< handle nested calls to get/releasePrintFControl
+ UINT32 meRequestedSize; /// Size of the memory range requested by ME FW, in MB
+ UINT32 ieRequestedSize; /// Size of the memory range requested by IE FW, in MB
+}; //struct commonVar
+
+///
+/// System Variable structure
+///
+struct sysVar {
+ struct memVar mem;
+ struct commonVar common;
+}; //struct sysVar
+
+// Bit definitions for commonSetup.options
+// ; PROMOTE_WARN_EN enables warnings to be treated as fatal error
+// ; PROMOTE_MRC_WARN_EN enables MRC warnings to be treated as fatal error
+// ; HALT_ON_ERROR_EN enables errors to loop forever
+// ; HALT_ON_ERROR_AUTO auto reset with Maximum Serial port debug message level when fatal error is encountered.
+#define PROMOTE_WARN_EN BIT0
+#define PROMOTE_MRC_WARN_EN BIT1
+#define HALT_ON_ERROR_EN BIT2
+#define HALT_ON_ERROR_AUTO BIT3
+
+typedef union _RMT_FLAGS {
+ UINT8 Data;
+ struct {
+ UINT8 EnableShortFormat :1;
+ UINT8 SkipPerBitMargin :1;
+ UINT8 SkipDisplayPerBitEyes :1;
+ UINT8 SkipDisplayPerBitMargins :1;
+ UINT8 SkipRmtRxDqs :1;
+ UINT8 SkipRmtRxVref :1;
+ UINT8 SkipRmtTxDq :1;
+ UINT8 SkipRmtTxVref :1;
+ } Bits;
+} RMT_FLAGS;
+
+///
+/// System Host (root structure)
+///
+struct sysHost {
+ struct sysVar var; ///< variable, volatile data
+ struct sysNvram nvram; ///< variable, non-volatile data for S3 and fast path
+ UINT8 ChannelModeOperation;
+ UINT32 cpuFlows; ///< Which flows to take
+ UINT32 ktiFlows;
+ UINT32 qpiFlows;
+ UINT32 opioFlows;
+ UINT32 memFlows;
+ UINT32 memFlowsExt;
+ UINT32 memFlowsExt2;
+ UINT32 memFlowsExt3;
+
+
+ UINT32 MrcHooksServicesPpi;
+ UINT32 MrcHooksChipServicesPpi;
+
+ BOOLEAN PrintCsr; // Enable / disable printing CSR
+ BOOLEAN MtrrCheck; // Check number of used MTRR's
+ INT32 DdrioUltSupport;
+ RMT_FLAGS RmtFlags;
+};
+
+#endif // #ifndef _SYS_HOST_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h
new file mode 100644
index 0000000000..a507c4fe23
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h
@@ -0,0 +1,101 @@
+/** @file
+ SysHostChipCommon.h
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SYSHOST_CHIP_COMMON_H_
+#define _SYSHOST_CHIP_COMMON_H_
+
+#include <DataTypes.h>
+#include <RcVersion.h>
+
+//
+// CpuPciAccess
+//
+#define READ_ACCESS 0
+#define WRITE_ACCESS 1
+
+//
+// -----------------------------------------------------------------------------
+// Nvram structures
+//
+#pragma pack(1)
+
+typedef union {
+ struct {
+ UINT32 Bit0:1;
+ UINT32 Bit1:1;
+ UINT32 Bit2:1;
+ UINT32 Bit3:1;
+ UINT32 Bit4:1;
+ UINT32 Bit5:1;
+ UINT32 Bit6:1;
+ UINT32 Bit7:1;
+ UINT32 Bit8:1;
+ UINT32 Bit9:1;
+ UINT32 Bit10:1;
+ UINT32 Bit11:1;
+ UINT32 Bit12:1;
+ UINT32 Bit13:1;
+ UINT32 Bit14:1;
+ UINT32 Bit15:1;
+ UINT32 Bit16:1;
+ UINT32 Bit17:1;
+ UINT32 Bit18:1;
+ UINT32 Bit19:1;
+ UINT32 Bit20:1;
+ UINT32 Bit21:1;
+ UINT32 Bit22:1;
+ UINT32 Bit23:1;
+ UINT32 Bit24:1;
+ UINT32 Bit25:1;
+ UINT32 Bit26:1;
+ UINT32 Bit27:1;
+ UINT32 Bit28:1;
+ UINT32 Bit29:1;
+ UINT32 Bit30:1;
+ UINT32 Bit31:1;
+ } Bits;
+ UINT32 Data;
+} DUMMY_REG;
+
+//
+// -----------------------------------------------------------------------------
+// Nvram structures
+//
+
+struct commonNvram {
+ UINT64_STRUCT cpuFreq;
+ RC_VERSION RcVersion; // Version of the reference code last executed
+ UINT8 platformType;
+ DUMMY_REG TsegBase;
+ DUMMY_REG TsegLimit;
+ DUMMY_REG MeMemLowBaseAddr;
+ DUMMY_REG MeMemHighBaseAddr;
+ DUMMY_REG MeMemLowLimit;
+ DUMMY_REG MeMemHighLimit;
+ DUMMY_REG MeNcMemLowBaseAddr;
+ DUMMY_REG MeNcMemHighBaseAddr;
+ DUMMY_REG MeNcMemLowLimit;
+ DUMMY_REG MeNcMemHighLimit;
+ DUMMY_REG MeNcMemLowRac;
+ DUMMY_REG MeNcMemLowWac;
+ UINT32 IeRequestedSize;
+ DUMMY_REG IeMemLowBaseAddr;
+ DUMMY_REG IeMemHighBaseAddr;
+ DUMMY_REG IeMemLowLimit;
+ DUMMY_REG IeMemHighLimit;
+ DUMMY_REG IeNcMemLowBaseAddr;
+ DUMMY_REG IeNcMemHighBaseAddr;
+ DUMMY_REG IeNcMemLowLimit;
+ DUMMY_REG IeNcMemHighLimit;
+ DUMMY_REG IeNcMemHighRac;
+ DUMMY_REG IeNcMemHighWac;
+};
+#pragma pack()
+
+#endif // _SYSHOST_CHIP_COMMON_H_
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/MemDefaults.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/MemDefaults.h
new file mode 100644
index 0000000000..68c2f447c9
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/MemDefaults.h
@@ -0,0 +1,28 @@
+/** @file
+
+ @copyright
+ Copyright 2006 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _mem_defaults_h
+#define _mem_defaults_h
+
+//
+// SMBUS Clk Period default set by PcdMrcSmbusSpeedDefault
+//
+#define SMB_CLK_100K 0
+#define SMB_CLK_400K 1
+#define SMB_CLK_700K 2
+#define SMB_CLK_1M 3
+
+#define MAX_PARTIAL_MIRROR 4 //Maximum number of partial mirror regions that can be created
+
+//
+// Limit of channels to be tested by AdvMemTest
+//
+#define ADV_MT_LIST_LIMIT 8
+#define ADV_MT_EMPTY_MASK 0xFFFFFFFF
+
+#endif // _mem_defaults_h
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h
new file mode 100644
index 0000000000..aa9b570f63
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h
@@ -0,0 +1,35 @@
+/** @file
+
+ @copyright
+ Copyright 2006 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _platformhost_h
+#define _platformhost_h
+
+#include <PlatformInfoTypes.h>
+
+//
+// Maximum number of processor sockets and cores per socket supported by platform.
+//
+#include <MaxSocket.h>
+#include <MaxCore.h>
+
+//
+// Post Package Repair
+//
+
+#define MAX_PPR_ADDR_ENTRIES 20
+#define MAX_PPR_ADDR_ENTRIES_SPPR 40
+
+#if !defined(SILENT_MODE)
+#define DEBUG_CODE_BLOCK 1
+#endif
+
+#define UBIOS_GENERATION_EN BIT22 // flag to enable DfxUbiosGeneration from Simics
+#define HYBRID_SYSTEM_LEVEL_EMULATION_EN BIT23 // flag to enable DfxHybridSystemLevelEmulation from Simics
+
+#endif // _platformhost_h
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c
new file mode 100644
index 0000000000..453e409523
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c
@@ -0,0 +1,243 @@
+/** @file
+ Sample to provide FSP wrapper related function.
+
+ @copyright
+ Copyright 2014 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <FspmUpd.h>
+#include <Ppi/UpiPolicyPpi.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/HobLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/MemoryAllocationLib.h>
+
+VOID *
+GetPlatformNvs(
+)
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable;
+ VOID *DataBuffer;
+ UINT32 DataBufferSize;
+ UINTN VarAttrib;
+ CHAR16 EfiMemoryConfigVariable[] = L"MemoryConfig";
+
+ DEBUG ((EFI_D_INFO, "Start PlatformGetNvs\n"));
+
+ Status = PeiServicesLocatePpi (
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiVariable
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "PlatformGetNvs: PeiServicesLocatePpi not found\n"));
+ ASSERT (FALSE);
+ return NULL;
+ }
+
+ VarAttrib = EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS;
+ DataBufferSize = 0;
+ DataBuffer = NULL;
+
+ Status = PeiVariable->GetVariable (
+ PeiVariable,
+ EfiMemoryConfigVariable,
+ &gFspNonVolatileStorageHobGuid,
+ (UINT32*)&VarAttrib,
+ &DataBufferSize,
+ NULL
+ );
+ if (Status == EFI_NOT_FOUND) {
+ DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Variable not found\n"));
+ return NULL;
+ }
+
+ if (Status != EFI_BUFFER_TOO_SMALL) {
+ DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Get Error %r\n", Status));
+ ASSERT (FALSE);
+ }
+
+ DataBuffer = AllocateZeroPool(DataBufferSize);
+ Status = PeiVariable->GetVariable (
+ PeiVariable,
+ EfiMemoryConfigVariable,
+ &gFspNonVolatileStorageHobGuid,
+ (UINT32*)&VarAttrib,
+ &DataBufferSize,
+ DataBuffer
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Variable Error %r\n", Status));
+ return NULL;
+ }
+ DEBUG ((EFI_D_INFO, "PlatformGetNvs: GetNVS %x %x\n", DataBuffer, DataBufferSize));
+ return DataBuffer;
+}
+
+VOID
+EFIAPI
+UpdateFspmUpdData (
+ IN OUT VOID *FspUpdRgnPtr
+ )
+{
+ FSPM_UPD *FspmUpd;
+ EFI_STATUS Status;
+ UPI_POLICY_PPI *UpiPolicyPpi;
+ KTI_HOST_IN *Upi;
+ UINTN Index;
+ VOID *FSPTempMem;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
+
+ Status = PeiServicesLocatePpi (&gUpiSiPolicyPpiGuid, 0, NULL, &UpiPolicyPpi);
+ ASSERT_EFI_ERROR(Status);
+
+ Upi = &UpiPolicyPpi->Upi;
+ FspmUpd = (FSPM_UPD*)FspUpdRgnPtr;
+
+ FSPTempMem = (VOID *)(UINTN)(PcdGet32(PcdTemporaryRamBase) + PcdGet32(PcdPeiTemporaryRamRcHeapSize));;
+ if (FSPTempMem != NULL) {
+ FspmUpd->FspmArchUpd.StackBase = (VOID*)(((UINTN)FSPTempMem) & (~0xFFF));
+ FspmUpd->FspmArchUpd.StackSize = PcdGet32(PcdFspTemporaryRamSize);
+ }
+
+ for (Index = 0; Index < MAX_SOCKET; Index ++) {
+ FspmUpd->FspmConfig.BusRatio[Index] = Upi->BusRatio[Index];
+ FspmUpd->FspmConfig.KtiFpgaEnable[Index] = Upi->KtiFpgaEnable[Index];
+ }
+
+ FspmUpd->FspmConfig.D2KCreditConfig = Upi->D2KCreditConfig;
+ FspmUpd->FspmConfig.SnoopThrottleConfig = Upi->SnoopThrottleConfig;
+ FspmUpd->FspmConfig.LegacyVgaSoc = Upi->LegacyVgaSoc;
+ FspmUpd->FspmConfig.LegacyVgaStack = Upi->LegacyVgaStack;
+ FspmUpd->FspmConfig.P2pRelaxedOrdering = Upi->P2pRelaxedOrdering;
+ FspmUpd->FspmConfig.SncEn = Upi->SncEn;
+ FspmUpd->FspmConfig.UmaClustering = Upi->UmaClustering;
+ FspmUpd->FspmConfig.IoDcMode = Upi->IoDcMode;
+ FspmUpd->FspmConfig.DegradePrecedence = Upi->DegradePrecedence;
+ FspmUpd->FspmConfig.Degrade4SPreference = Upi->Degrade4SPreference;
+ FspmUpd->FspmConfig.DirectoryModeEn = Upi->DirectoryModeEn;
+ FspmUpd->FspmConfig.XptPrefetchEn = Upi->XptPrefetchEn;
+ FspmUpd->FspmConfig.KtiPrefetchEn = Upi->KtiPrefetchEn;
+ FspmUpd->FspmConfig.XptRemotePrefetchEn = Upi->XptRemotePrefetchEn;
+ FspmUpd->FspmConfig.DdrtQosMode = Upi->DdrtQosMode;
+ FspmUpd->FspmConfig.KtiLinkSpeedMode = Upi->KtiLinkSpeedMode;
+ FspmUpd->FspmConfig.KtiLinkSpeed = Upi->KtiLinkSpeed;
+ FspmUpd->FspmConfig.KtiLinkL0pEn = Upi->KtiLinkL0pEn;
+ FspmUpd->FspmConfig.KtiLinkL1En = Upi->KtiLinkL1En;
+ FspmUpd->FspmConfig.KtiFailoverEn = Upi->KtiFailoverEn;
+ FspmUpd->FspmConfig.KtiLbEn = Upi->KtiLbEn;
+ FspmUpd->FspmConfig.KtiCrcMode = Upi->KtiCrcMode;
+ FspmUpd->FspmConfig.KtiCpuSktHotPlugEn = Upi->KtiCpuSktHotPlugEn;
+ FspmUpd->FspmConfig.KtiCpuSktHotPlugTopology = Upi->KtiCpuSktHotPlugTopology;
+ FspmUpd->FspmConfig.KtiSkuMismatchCheck = Upi->KtiSkuMismatchCheck;
+ FspmUpd->FspmConfig.IrqThreshold = Upi->IrqThreshold;
+ FspmUpd->FspmConfig.TorThresLoctoremNorm = Upi->TorThresLoctoremNorm;
+ FspmUpd->FspmConfig.TorThresLoctoremEmpty = Upi->TorThresLoctoremEmpty;
+ FspmUpd->FspmConfig.MbeBwCal = Upi->MbeBwCal;
+ FspmUpd->FspmConfig.TscSyncEn = Upi->TscSyncEn;
+ FspmUpd->FspmConfig.StaleAtoSOptEn = Upi->StaleAtoSOptEn;
+ FspmUpd->FspmConfig.LLCDeadLineAlloc = Upi->LLCDeadLineAlloc;
+ FspmUpd->FspmConfig.SplitLock = Upi->SplitLock;
+ FspmUpd->FspmConfig.mmCfgBase = Upi->mmCfgBase;
+ FspmUpd->FspmConfig.mmCfgSize = Upi->mmCfgSize;
+ FspmUpd->FspmConfig.mmiohBase = Upi->mmiohBase;
+ FspmUpd->FspmConfig.CpuPaLimit = Upi->CpuPaLimit;
+ FspmUpd->FspmConfig.highGap = Upi->highGap;
+ FspmUpd->FspmConfig.mmiohSize = Upi->mmiohSize;
+ FspmUpd->FspmConfig.isocEn = Upi->isocEn;
+ FspmUpd->FspmConfig.dcaEn = Upi->dcaEn;
+ FspmUpd->FspmConfig.BoardTypeBitmask = Upi->BoardTypeBitmask;
+ FspmUpd->FspmConfig.AllLanesPtr = Upi->AllLanesPtr;
+ FspmUpd->FspmConfig.PerLanePtr = Upi->PerLanePtr;
+ FspmUpd->FspmConfig.AllLanesSizeOfTable = Upi->AllLanesSizeOfTable;
+ FspmUpd->FspmConfig.PerLaneSizeOfTable = Upi->PerLaneSizeOfTable;
+ FspmUpd->FspmConfig.WaitTimeForPSBP = Upi->WaitTimeForPSBP;
+ FspmUpd->FspmConfig.IsKtiNvramDataReady = Upi->IsKtiNvramDataReady;
+ FspmUpd->FspmConfig.WaSerializationEn = Upi->WaSerializationEn;
+ FspmUpd->FspmConfig.KtiInEnableMktme = Upi->KtiInEnableMktme;
+ FspmUpd->FspmConfig.BoardId = PlatformInfo->BoardId;
+ FspmUpd->FspmArchUpd.NvsBufferPtr = GetPlatformNvs();
+}
+
+/**
+ This function overrides the default configurations in the FSP-S UPD data region.
+
+ @param[in,out] FspUpdRgnPtr A pointer to the UPD data region data strcture.
+
+**/
+VOID
+EFIAPI
+UpdateFspsUpdData (
+ IN OUT VOID *FspUpdRgnPtr
+ )
+{
+}
+
+/**
+ Update TempRamExit parameter.
+
+ @note At this point, memory is ready, PeiServices are available to use.
+
+ @return TempRamExit parameter.
+**/
+VOID *
+EFIAPI
+UpdateTempRamExitParam (
+ VOID
+ )
+{
+ return NULL;
+}
+
+/**
+ Get S3 PEI memory information.
+
+ @note At this point, memory is ready, and PeiServices are available to use.
+ Platform can get some data from SMRAM directly.
+
+ @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.
+ @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.
+
+ @return If S3 PEI memory information is got successfully.
+**/
+EFI_STATUS
+EFIAPI
+GetS3MemoryInfo (
+ OUT UINT64 *S3PeiMemSize,
+ OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Perform platform related reset in FSP wrapper.
+
+ This function will reset the system with requested ResetType.
+
+ @param[in] FspStatusResetType The type of reset the platform has to perform.
+**/
+VOID
+EFIAPI
+CallFspWrapperResetSystem (
+ IN UINT32 FspStatusResetType
+ )
+{
+ //
+ // Perform reset according to the type.
+ //
+
+ CpuDeadLoop();
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf
new file mode 100644
index 0000000000..625337c453
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf
@@ -0,0 +1,71 @@
+## @file
+# Sample to provide FSP wrapper platform related function.
+#
+# @copyright
+# Copyright 2014 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseFspWrapperPlatformLibSample
+ FILE_GUID = 12F38E73-B34D-4559-99E5-AE2DCD002156
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FspWrapperPlatformLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+ FspWrapperPlatformLib.c
+
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ CedarIslandFspBinPkg/CedarIslandFspBinPkg.dec
+
+[Ppis]
+ gUpiSiPolicyPpiGuid
+ gEfiPeiReadOnlyVariable2PpiGuid
+
+[Guids]
+ gEfiPlatformInfoGuid
+ gFspNonVolatileStorageHobGuid
+
+[LibraryClasses]
+ PeiServicesLib
+
+[Pcd]
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
+ gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize ## CONSUMES
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.c b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.c
new file mode 100644
index 0000000000..b06342c12a
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.c
@@ -0,0 +1,259 @@
+/** @file
+ Library functions for SetupLib.
+ This library instance provides methods to access Setup option.
+
+ @copyright
+ Copyright 2019 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <SetupLibInternal.h>
+#include <Library/IoLib.h>
+
+/**
+ Gets the data and size of a variable.
+
+ Read the EFI variable (VendorGuid/Name) and return a dynamically allocated
+ buffer, and the size of the buffer. If failure return NULL.
+
+ @param Name String part of EFI variable name
+ @param VendorGuid GUID part of EFI variable name
+ @param VariableSize Returns the size of the EFI variable that was
+ read
+
+ @return Dynamically allocated memory that contains a copy of the EFI variable.
+ Caller is responsible freeing the buffer via FreePages.
+
+ @retval NULL Variable was not read
+
+**/
+VOID *
+EFIAPI
+GetVariableAndSize (
+ IN CHAR16 *Name,
+ IN EFI_GUID *Guid,
+ IN UINTN BufferSize
+ )
+{
+ EFI_STATUS Status;
+ VOID *Buffer = NULL;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable;
+ CONST EFI_PEI_SERVICES **PeiServices;
+
+ PeiServices = GetPeiServicesTablePointer ();
+ (**PeiServices).LocatePpi (
+ PeiServices,
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ &PeiVariable
+ );
+
+ Buffer = AllocatePages (EFI_SIZE_TO_PAGES (BufferSize));
+ if (Buffer == NULL) {
+ return NULL;
+ }
+ //
+ // Read variable into the allocated buffer.
+ //
+ Status = PeiVariable->GetVariable (PeiVariable, Name, Guid, NULL, &BufferSize, Buffer);
+ ASSERT_EFI_ERROR (Status);
+
+ return Buffer;
+}
+
+/**
+ Retrieves the specified group space.
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates which namespace
+ to set a value from.
+ @reture GroupInfo The found group space. NULL will return if not found.
+**/
+UINTN
+InternalGetGroupInfo (
+ IN EFI_GUID *Guid
+ )
+{
+ UINTN Index;
+
+ if (Guid == NULL) {
+ return MAX_ADDRESS;
+ }
+
+ //
+ // Find the matched GUID space.
+ //
+ for (Index = 0; mSetupInfo[Index].GuidValue != NULL; Index ++) {
+ if (CompareGuid (mSetupInfo[Index].GuidValue, Guid)) {
+ break;
+ }
+ }
+
+ //
+ // No matched GUID space
+ //
+ if (mSetupInfo[Index].GuidValue == NULL) {
+ return MAX_ADDRESS;
+ }
+
+ return Index;
+}
+
+/**
+ This function provides a means by which to retrieve a value for a given option.
+
+ Returns the data, data type and data size specified by OptionNumber and Guid.
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] OptionNumber The option number to retrieve a current value for.
+ @param[out] DataType A pointer to basic data type of the retrieved data.
+ It is optional. It could be NULL.
+ @param[in, out] Data A pointer to the buffer to be retrieved.
+ @param[in, out] DataSize The size, in bytes, of Buffer.
+
+ @retval EFI_SUCCESS Data is successfully reterieved.
+ @retval EFI_INVALID_PARAMETER Guid is NULL or DataSize is NULL or OptionNumber is invalid.
+ @retval EFI_BUFFER_TOO_SMALL Input data buffer is not enough.
+ @retval EFI_NOT_FOUND The given option is not found.
+
+**/
+EFI_STATUS
+EFIAPI
+GetOptionData (
+ IN EFI_GUID *Guid,
+ IN UINTN OptionNumber,
+ IN OUT VOID *Data,
+ IN UINTN DataSize
+ )
+{
+ UINTN GroupIndex;
+ VOID *Variable = NULL;
+
+ if (Guid == NULL || DataSize == 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GroupIndex = InternalGetGroupInfo (Guid);
+ if (GroupIndex == MAX_ADDRESS) {
+ return EFI_NOT_FOUND;
+ }
+
+ Variable = GetVariableAndSize (
+ mSetupInfo[GroupIndex].SetupName,
+ Guid,
+ mSetupInfo[GroupIndex].VariableSize
+ );
+ if (Variable == NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ CopyMem (Data, (UINT8 *)Variable + OptionNumber, DataSize);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Get all data in the setup
+
+ @retval EFI_SUCCESS Data is committed successfully.
+ @retval EFI_INVALID_PARAMETER Guid is NULL.
+ @retval EFI_NOT_FOUND Guid is not found.
+ @retval EFI_DEVICE_ERROR Data can't be committed.
+**/
+EFI_STATUS
+EFIAPI
+GetEntireConfig (
+ IN OUT SETUP_DATA *SetupData
+ )
+{
+ VOID *Variable;
+ UINTN Index;
+ UINT8 *SetupDataPtr;
+
+ if (SetupData == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ SetupDataPtr = (UINT8 *)SetupData;
+ ZeroMem (SetupDataPtr, sizeof (SETUP_DATA));
+
+ for (Index = 0; mSetupInfo[Index].GuidValue != NULL; Index ++) {
+
+ Variable = NULL;
+ Variable = GetVariableAndSize (
+ mSetupInfo[Index].SetupName,
+ mSetupInfo[Index].GuidValue,
+ mSetupInfo[Index].VariableSize
+ );
+ ASSERT (Variable != NULL);
+ if (Variable == NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ CopyMem (SetupDataPtr, Variable, mSetupInfo[Index].VariableSize);
+ SetupDataPtr = SetupDataPtr + mSetupInfo[Index].VariableSize;
+
+ FreePages (Variable, EFI_SIZE_TO_PAGES (mSetupInfo[Index].VariableSize));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function provides a means by which to retrieve a value for a given option.
+
+ Returns the data, data type and data size specified by OptionNumber and Guid.
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] Variable Pointer to data location where variable is stored.
+
+ @retval EFI_SUCCESS Data is successfully reterieved.
+ @retval EFI_INVALID_PARAMETER Guid is NULL or DataSize is NULL or OptionNumber is invalid.
+ @retval EFI_BUFFER_TOO_SMALL Input data buffer is not enough.
+ @retval EFI_NOT_FOUND The given option is not found.
+
+**/
+EFI_STATUS
+EFIAPI
+GetSpecificConfigGuid (
+ IN EFI_GUID *Guid,
+ OUT VOID *Variable
+ )
+{
+ EFI_STATUS Status;
+ UINTN GroupIndex;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable;
+ CONST EFI_PEI_SERVICES **PeiServices;
+
+ if ((Guid == NULL) || (Variable == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+ GroupIndex = InternalGetGroupInfo (Guid);
+ if (GroupIndex == MAX_ADDRESS) {
+ return EFI_NOT_FOUND;
+ }
+ PeiServices = GetPeiServicesTablePointer ();
+ (**PeiServices).LocatePpi (
+ PeiServices,
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ &PeiVariable
+ );
+
+ Status = PeiVariable->GetVariable (PeiVariable, mSetupInfo[GroupIndex].SetupName, mSetupInfo[GroupIndex].GuidValue, NULL, &mSetupInfo[GroupIndex].VariableSize, Variable);
+
+ return Status;
+}
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.inf b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.inf
new file mode 100644
index 0000000000..b9d96f66fe
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.inf
@@ -0,0 +1,55 @@
+## @file
+#
+# @copyright
+# Copyright 2009 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiSetupLib
+ FILE_GUID = C27D6383-F718-490c-8959-CB8370263329
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SetupLib | PEIM
+
+
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources.common]
+ PeiSetupLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ ServerPlatformPkg/PlatformPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+
+[Guids]
+ gEfiSocketIioVariableGuid
+ gEfiSocketCommonRcVariableGuid
+ gEfiSocketMpLinkVariableGuid
+ gEfiSocketMemoryVariableGuid
+ gEfiSocketPowermanagementVarGuid
+ gEfiSocketProcessorCoreVarGuid
+ gEfiSetupVariableGuid
+ gPchSetupVariableGuid
+ gEfiMeRcVariableGuid
+ gEfiIeRcVariableGuid
+ gFpgaSocketVariableGuid
+ gMemBootHealthGuid
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid
+
+[Pcd.common]
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.c b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.c
new file mode 100644
index 0000000000..ba7f86732d
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.c
@@ -0,0 +1,253 @@
+/** @file
+ Library functions for SetupLib.
+ This library instance provides methods to access Setup option.
+
+ @copyright
+ Copyright 2020 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi/UefiBaseType.h>
+#include <SetupTable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ This function provides a means by which to retrieve a value for a given option.
+
+ Returns the data, data type and data size specified by OptionNumber and Guid.
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] OptionNumber The option number to retrieve a current value for.
+ @param[in, out] Data A pointer to the buffer to be retrieved.
+ @param[in, out] DataSize The size, in bytes, of Buffer.
+
+ @retval EFI_SUCCESS Data is successfully reterieved.
+ @retval EFI_INVALID_PARAMETER Guid is NULL or DataSize is NULL or OptionNumber is invalid.
+ @retval EFI_BUFFER_TOO_SMALL Input data buffer is not enough.
+ @retval EFI_NOT_FOUND The given option is not found.
+
+**/
+EFI_STATUS
+EFIAPI
+GetOptionData (
+ IN EFI_GUID *Guid,
+ IN UINTN OptionNumber,
+ IN OUT VOID *Data,
+ IN UINTN DataSize
+ )
+{
+ SETUP_DATA *SetupData = NULL;
+
+ if (Guid == NULL || DataSize == 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Retrieve the variable from PCD
+ //
+ if (CompareGuid (&gEfiSocketIioVariableGuid, Guid)) {
+ SetupData = (SETUP_DATA*) PcdGetPtr (PcdSocketIioConfig);
+ } else if (CompareGuid (&gEfiSocketCommonRcVariableGuid, Guid)) {
+ SetupData = (SETUP_DATA*) PcdGetPtr (PcdSocketCommonRcConfig);
+ } else if (CompareGuid (&gEfiSocketMpLinkVariableGuid, Guid)) {
+ SetupData = (SETUP_DATA*) PcdGetPtr (PcdSocketMpLinkConfig);
+ } else if (CompareGuid (&gEfiSocketMemoryVariableGuid, Guid)) {
+ SetupData = (SETUP_DATA*) PcdGetPtr (PcdSocketMemoryConfig);
+ } else if (CompareGuid (&gEfiSocketPowermanagementVarGuid, Guid)) {
+ SetupData = (SETUP_DATA*) PcdGetPtr (PcdSocketPowerManagementConfig);
+ } else if (CompareGuid (&gEfiSocketProcessorCoreVarGuid, Guid)) {
+ SetupData = (SETUP_DATA*) PcdGetPtr (PcdSocketProcessorCoreConfig);
+ } else if (CompareGuid (&gEfiSetupVariableGuid, Guid)) {
+ SetupData = (SETUP_DATA*) PcdGetPtr (PcdSetup);
+ } else if (CompareGuid (&gPchSetupVariableGuid, Guid)) {
+ SetupData = (SETUP_DATA*) PcdGetPtr (PcdPchSetup);
+ } else if (CompareGuid (&gMemBootHealthGuid, Guid)) {
+ SetupData = (SETUP_DATA*) PcdGetPtr (PcdMemBootHealthConfig);
+ }
+
+ //
+ // Grab the data from the offset
+ //
+ if (SetupData != NULL) {
+ CopyMem (Data, (UINT8*) SetupData + OptionNumber, DataSize);
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((DEBUG_ERROR, "ERROR: Unknown GetOptionData requested\n"));
+ ASSERT_EFI_ERROR (EFI_NOT_FOUND);
+ return EFI_NOT_FOUND;
+}
+
+/**
+ This function provides a means by which to set a value for a given option number.
+
+ Sets a buffer for the token specified by OptionNumber to the value specified by
+ Data and DataSize.
+ If DataSize is greater than the maximum size support by OptionNumber,
+ then set DataSize to the maximum size supported by OptionNumber.
+
+ @param[in] Guid Pointer to a 128-bit unique value that
+ designates which namespace to set a value from.
+ @param[in] OptionNumber The option number to set a current value for.
+ @param[in] Data A pointer to the buffer to set.
+ @param[in, out] DataSize The size, in bytes, of Buffer.
+
+ @retval EFI_SUCCESS Data is successfully updated.
+ @retval EFI_INVALID_PARAMETER OptionNumber is invalid, Guid is NULL, or Data is NULL, or DataSize is NULL.
+ @retval EFI_NOT_FOUND The given option is not found.
+ @retval EFI_UNSUPPORTED Set action is not supported.
+**/
+EFI_STATUS
+EFIAPI
+SetOptionData (
+ IN EFI_GUID *Guid,
+ IN UINTN OptionNumber,
+ IN VOID *Data,
+ IN UINTN DataSize
+ )
+{
+ DEBUG ((DEBUG_ERROR, "ERROR: SetOptionData not implemented\n"));
+ ASSERT_EFI_ERROR (EFI_NOT_FOUND);
+ return EFI_NOT_FOUND;
+}
+
+/**
+ Get all data in the setup
+
+ @retval EFI_SUCCESS Data is committed successfully.
+ @retval EFI_INVALID_PARAMETER Guid is NULL.
+ @retval EFI_NOT_FOUND Guid is not found.
+ @retval EFI_DEVICE_ERROR Data can't be committed.
+**/
+EFI_STATUS
+EFIAPI
+GetEntireConfig (
+ OUT SETUP_DATA *SetupData
+ )
+{
+ ZeroMem(SetupData, sizeof(SETUP_DATA) );
+
+ CopyMem (&SetupData->SocketConfig.IioConfig, PcdGetPtr (PcdSocketIioConfig), sizeof(SOCKET_IIO_CONFIGURATION));
+ CopyMem (&SetupData->SocketConfig.CommonRcConfig, PcdGetPtr (PcdSocketCommonRcConfig), sizeof(SOCKET_COMMONRC_CONFIGURATION));
+ CopyMem (&SetupData->SocketConfig.UpiConfig, PcdGetPtr (PcdSocketMpLinkConfig), sizeof(SOCKET_MP_LINK_CONFIGURATION));
+ CopyMem (&SetupData->SocketConfig.MemoryConfig, PcdGetPtr (PcdSocketMemoryConfig), sizeof(SOCKET_MEMORY_CONFIGURATION));
+ CopyMem (&SetupData->SocketConfig.PowerManagementConfig, PcdGetPtr (PcdSocketPowerManagementConfig), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION));
+ CopyMem (&SetupData->SocketConfig.SocketProcessorCoreConfiguration, PcdGetPtr (PcdSocketProcessorCoreConfig), sizeof(SOCKET_PROCESSORCORE_CONFIGURATION));
+ CopyMem (&SetupData->SystemConfig, PcdGetPtr (PcdSetup), sizeof(SYSTEM_CONFIGURATION));
+ CopyMem (&SetupData->PchSetup, PcdGetPtr (PcdPchSetup), sizeof(PCH_SETUP));
+ CopyMem (&SetupData->MemBootHealthConfig, PcdGetPtr (PcdMemBootHealthConfig), sizeof(MEM_BOOT_HEALTH_CONFIG));
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Set all data in the setup
+
+ @retval EFI_SUCCESS Data is committed successfully.
+ @retval EFI_INVALID_PARAMETER Guid is NULL.
+ @retval EFI_NOT_FOUND Guid is not found.
+ @retval EFI_DEVICE_ERROR Data can't be committed.
+**/
+EFI_STATUS
+EFIAPI
+SetEntireConfig (
+ IN SETUP_DATA *SetupData
+ )
+{
+ DEBUG ((DEBUG_ERROR, "ERROR: SetEntireConfig not implemented\n"));
+ ASSERT_EFI_ERROR (EFI_NOT_FOUND);
+ return EFI_NOT_FOUND;
+}
+
+/**
+ This function provides a means by which to retrieve a value for a given option.
+
+ Returns the data, data type and data size specified by OptionNumber and Guid.
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] Variable Pointer to data location where variable is stored.
+
+ @retval EFI_SUCCESS Data is successfully retrieved.
+ @retval EFI_INVALID_PARAMETER Guid or Variable is null.
+ @retval EFI_NOT_FOUND The given option is not found.
+
+**/
+EFI_STATUS
+EFIAPI
+GetSpecificConfigGuid (
+ IN EFI_GUID *Guid,
+ OUT VOID *Variable
+ )
+{
+ if ((Guid == NULL) || (Variable == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (CompareGuid (&gEfiSocketIioVariableGuid, Guid)) {
+ CopyMem (Variable, PcdGetPtr (PcdSocketIioConfig), sizeof(SOCKET_IIO_CONFIGURATION));
+ return EFI_SUCCESS;
+ } else if (CompareGuid (&gEfiSocketCommonRcVariableGuid, Guid)) {
+ CopyMem (Variable, PcdGetPtr (PcdSocketCommonRcConfig), sizeof(SOCKET_COMMONRC_CONFIGURATION));
+ return EFI_SUCCESS;
+ } else if (CompareGuid (&gEfiSocketMpLinkVariableGuid, Guid)) {
+ CopyMem (Variable, PcdGetPtr (PcdSocketMpLinkConfig), sizeof(SOCKET_MP_LINK_CONFIGURATION));
+ return EFI_SUCCESS;
+ } else if (CompareGuid (&gEfiSocketMemoryVariableGuid, Guid)) {
+ CopyMem (Variable, PcdGetPtr (PcdSocketMemoryConfig), sizeof(SOCKET_MEMORY_CONFIGURATION));
+ return EFI_SUCCESS;
+ } else if (CompareGuid (&gEfiSocketPowermanagementVarGuid, Guid)) {
+ CopyMem (Variable, PcdGetPtr (PcdSocketPowerManagementConfig), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION));
+ return EFI_SUCCESS;
+ } else if (CompareGuid (&gEfiSocketProcessorCoreVarGuid, Guid)) {
+ CopyMem (Variable, PcdGetPtr (PcdSocketProcessorCoreConfig), sizeof(SOCKET_PROCESSORCORE_CONFIGURATION));
+ return EFI_SUCCESS;
+ } else if (CompareGuid (&gEfiSetupVariableGuid, Guid)) {
+ CopyMem (Variable, PcdGetPtr (PcdSetup), sizeof(SYSTEM_CONFIGURATION));
+ return EFI_SUCCESS;
+ } else if (CompareGuid (&gPchSetupVariableGuid, Guid)) {
+ CopyMem (Variable, PcdGetPtr (PcdPchSetup), sizeof(PCH_SETUP));
+ return EFI_SUCCESS;
+ } else if (CompareGuid (&gMemBootHealthGuid, Guid)) {
+ CopyMem (Variable, PcdGetPtr (PcdMemBootHealthConfig), sizeof(MEM_BOOT_HEALTH_CONFIG));
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((DEBUG_ERROR, "ERROR: Unknown GetSpecificConfigGuid requested\n"));
+ ASSERT_EFI_ERROR (EFI_NOT_FOUND);
+ return EFI_NOT_FOUND;
+}
+
+/**
+ This function provides a means by which to set a value for a given option number.
+
+ Sets a buffer for the token specified by OptionNumber to the value specified by
+ Data and DataSize.
+ If DataSize is greater than the maximum size support by OptionNumber,
+ then set DataSize to the maximum size supported by OptionNumber.
+
+ @param[in] Guid Pointer to a 128-bit unique value that
+ designates which namespace to set a value from.
+ @param[in] Variable Pointer to data location where variable is stored.
+
+ @retval EFI_SUCCESS Data is successfully updated.
+ @retval EFI_INVALID_PARAMETER OptionNumber is invalid, Guid is NULL, or Data is NULL, or DataSize is NULL.
+ @retval EFI_NOT_FOUND The given option is not found.
+ @retval EFI_UNSUPPORTED Set action is not supported.
+**/
+EFI_STATUS
+EFIAPI
+SetSpecificConfigGuid (
+ IN EFI_GUID *Guid,
+ IN VOID *Variable
+ )
+{
+ DEBUG ((DEBUG_ERROR, "ERROR: SetSpecificConfigGuid not implemented\n"));
+ ASSERT_EFI_ERROR (EFI_NOT_FOUND);
+ return EFI_NOT_FOUND;
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.inf b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.inf
new file mode 100644
index 0000000000..c66eb07629
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.inf
@@ -0,0 +1,59 @@
+## @file
+# Status Code Handler Driver which produces general handlers and hook them
+# onto the status code router.
+#
+# @copyright
+# Copyright 2020 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SetupLib
+ FILE_GUID = 699ECE4C-8146-4C44-97D9-D1FFC5BCDC11
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SetupLib | PEIM DXE_DRIVER DXE_SMM_DRIVER DXE_RUNTIME_DRIVER UEFI_DRIVER
+
+[Sources]
+ SetupLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[LibraryClasses]
+ DebugLib
+
+[Guids]
+ gEfiSocketIioVariableGuid # CONSUMES
+ gEfiSocketCommonRcVariableGuid # CONSUMES
+ gEfiSocketMpLinkVariableGuid # CONSUMES
+ gEfiSocketMemoryVariableGuid # CONSUMES
+ gEfiSocketPowermanagementVarGuid # CONSUMES
+ gEfiSocketProcessorCoreVarGuid # CONSUMES
+ gEfiSetupVariableGuid # CONSUMES
+ gPchSetupVariableGuid # CONSUMES
+ gMemBootHealthGuid # CONSUMES
+
+[Pcd]
+ gStructPcdTokenSpaceGuid.PcdSocketIioConfig
+ gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig
+ gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig
+ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig
+ gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig
+ gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig
+ gStructPcdTokenSpaceGuid.PcdSetup
+ gStructPcdTokenSpaceGuid.PcdPchSetup
+ gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig
+ gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig
+
+[FixedPcd]
+
+
+[Depex]
+ TRUE
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.c b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.c
new file mode 100644
index 0000000000..f55657ff67
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.c
@@ -0,0 +1,159 @@
+/** @file
+ Library functions for SetupLib.
+ This library instance provides methods to access Setup option.
+
+ @copyright
+ Copyright 2012 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi/UefiBaseType.h>
+#include <SetupTable.h>
+
+/**
+ This function provides a means by which to retrieve a value for a given option.
+
+ Returns the data, data type and data size specified by OptionNumber and Guid.
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] OptionNumber The option number to retrieve a current value for.
+ @param[in, out] Data A pointer to the buffer to be retrieved.
+ @param[in, out] DataSize The size, in bytes, of Buffer.
+
+ @retval EFI_SUCCESS Data is successfully reterieved.
+ @retval EFI_INVALID_PARAMETER Guid is NULL or DataSize is NULL or OptionNumber is invalid.
+ @retval EFI_BUFFER_TOO_SMALL Input data buffer is not enough.
+ @retval EFI_NOT_FOUND The given option is not found.
+
+**/
+EFI_STATUS
+EFIAPI
+GetOptionData (
+ IN EFI_GUID *Guid,
+ IN UINTN OptionNumber,
+ IN OUT VOID *Data,
+ IN UINTN DataSize
+ )
+{
+ return EFI_NOT_FOUND;
+}
+
+/**
+ This function provides a means by which to set a value for a given option number.
+
+ Sets a buffer for the token specified by OptionNumber to the value specified by
+ Data and DataSize.
+ If DataSize is greater than the maximum size support by OptionNumber,
+ then set DataSize to the maximum size supported by OptionNumber.
+
+ @param[in] Guid Pointer to a 128-bit unique value that
+ designates which namespace to set a value from.
+ @param[in] OptionNumber The option number to set a current value for.
+ @param[in] Data A pointer to the buffer to set.
+ @param[in, out] DataSize The size, in bytes, of Buffer.
+
+ @retval EFI_SUCCESS Data is successfully updated.
+ @retval EFI_INVALID_PARAMETER OptionNumber is invalid, Guid is NULL, or Data is NULL, or DataSize is NULL.
+ @retval EFI_NOT_FOUND The given option is not found.
+ @retval EFI_UNSUPPORTED Set action is not supported.
+**/
+EFI_STATUS
+EFIAPI
+SetOptionData (
+ IN EFI_GUID *Guid,
+ IN UINTN OptionNumber,
+ IN VOID *Data,
+ IN UINTN DataSize
+ )
+{
+ return EFI_NOT_FOUND;
+}
+
+/**
+ Get all data in the setup
+
+ @retval EFI_SUCCESS Data is committed successfully.
+ @retval EFI_INVALID_PARAMETER Guid is NULL.
+ @retval EFI_NOT_FOUND Guid is not found.
+ @retval EFI_DEVICE_ERROR Data can't be committed.
+**/
+EFI_STATUS
+EFIAPI
+GetEntireConfig (
+ OUT SETUP_DATA *SetupData
+ )
+{
+ return EFI_NOT_FOUND;
+}
+
+
+/**
+ Set all data in the setup
+
+ @retval EFI_SUCCESS Data is committed successfully.
+ @retval EFI_INVALID_PARAMETER Guid is NULL.
+ @retval EFI_NOT_FOUND Guid is not found.
+ @retval EFI_DEVICE_ERROR Data can't be committed.
+**/
+EFI_STATUS
+EFIAPI
+SetEntireConfig (
+ IN SETUP_DATA *SetupData
+ )
+{
+ return EFI_NOT_FOUND;
+}
+
+/**
+ This function provides a means by which to retrieve a value for a given option.
+
+ Returns the data, data type and data size specified by OptionNumber and Guid.
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] Variable Pointer to data location where variable is stored.
+
+ @retval EFI_SUCCESS Data is successfully reterieved.
+ @retval EFI_INVALID_PARAMETER Guid or Variable is null.
+ @retval EFI_NOT_FOUND The given option is not found.
+
+**/
+EFI_STATUS
+EFIAPI
+GetSpecificConfigGuid (
+ IN EFI_GUID *Guid,
+ OUT VOID *Variable
+ )
+{
+ return EFI_NOT_FOUND;
+}
+
+/**
+ This function provides a means by which to set a value for a given option number.
+
+ Sets a buffer for the token specified by OptionNumber to the value specified by
+ Data and DataSize.
+ If DataSize is greater than the maximum size support by OptionNumber,
+ then set DataSize to the maximum size supported by OptionNumber.
+
+ @param[in] Guid Pointer to a 128-bit unique value that
+ designates which namespace to set a value from.
+ @param[in] Variable Pointer to data location where variable is stored.
+
+ @retval EFI_SUCCESS Data is successfully updated.
+ @retval EFI_INVALID_PARAMETER OptionNumber is invalid, Guid is NULL, or Data is NULL, or DataSize is NULL.
+ @retval EFI_NOT_FOUND The given option is not found.
+ @retval EFI_UNSUPPORTED Set action is not supported.
+**/
+EFI_STATUS
+EFIAPI
+SetSpecificConfigGuid (
+ IN EFI_GUID *Guid,
+ IN VOID *Variable
+ )
+{
+ return EFI_NOT_FOUND;
+}
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.inf b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.inf
new file mode 100644
index 0000000000..45792c88cc
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.inf
@@ -0,0 +1,46 @@
+## @file
+# Status Code Handler Driver which produces general handlers and hook them
+# onto the status code router.
+#
+# @copyright
+# Copyright 2006 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SetupLibNull
+ FILE_GUID = E92E7B25-7CE3-489e-B985-DC9ED7BF2091
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SetupLib | PEIM DXE_DRIVER DXE_SMM_DRIVER DXE_RUNTIME_DRIVER UEFI_DRIVER
+
+[Sources]
+ SetupLibNull.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+
+[LibraryClasses]
+ DebugLib
+
+
+[Protocols]
+
+
+[Guids]
+
+
+[Pcd]
+
+[FixedPcd]
+
+
+[Depex]
+ TRUE
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.c b/Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.c
new file mode 100644
index 0000000000..a1c7fb0f67
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.c
@@ -0,0 +1,104 @@
+/** @file
+
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SiliconPolicyInitLib.h>
+#include <Guid/SiliconPolicyInitLibInterface.h>
+
+VOID *
+EFIAPI
+SiliconPolicyInitPreMem (
+ IN VOID *Policy
+ )
+{
+ RETURN_STATUS Status = RETURN_SUCCESS;
+ SILICON_POLICY_INIT_LIB_PPI *SiliconPolicyInitLibPpi = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiliconPolicyInitLibInterfaceGuid, 0, NULL, &SiliconPolicyInitLibPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return NULL;
+ }
+
+ return SiliconPolicyInitLibPpi->SiliconPolicyInitPreMem (Policy);
+}
+
+RETURN_STATUS
+EFIAPI
+SiliconPolicyDonePreMem (
+ IN VOID *Policy
+ )
+{
+ RETURN_STATUS Status = RETURN_SUCCESS;
+ SILICON_POLICY_INIT_LIB_PPI *SiliconPolicyInitLibPpi = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiliconPolicyInitLibInterfaceGuid, 0, NULL, &SiliconPolicyInitLibPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ return SiliconPolicyInitLibPpi->SiliconPolicyDonePreMem (Policy);
+}
+
+VOID *
+EFIAPI
+SiliconPolicyInitPostMem (
+ IN VOID *Policy
+ )
+{
+ RETURN_STATUS Status = RETURN_SUCCESS;
+ SILICON_POLICY_INIT_LIB_PPI *SiliconPolicyInitLibPpi = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiliconPolicyInitLibInterfaceGuid, 0, NULL, &SiliconPolicyInitLibPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return NULL;
+ }
+
+ return SiliconPolicyInitLibPpi->SiliconPolicyInitPostMem (Policy);
+}
+
+RETURN_STATUS
+EFIAPI
+SiliconPolicyDonePostMem (
+ IN VOID *Policy
+ )
+{
+ RETURN_STATUS Status = RETURN_SUCCESS;
+ SILICON_POLICY_INIT_LIB_PPI *SiliconPolicyInitLibPpi = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiliconPolicyInitLibInterfaceGuid, 0, NULL, &SiliconPolicyInitLibPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ return SiliconPolicyInitLibPpi->SiliconPolicyDonePostMem (Policy);
+}
+
+VOID *
+EFIAPI
+SiliconPolicyInitLate (
+ IN VOID *Policy
+ )
+{
+ ASSERT_EFI_ERROR (RETURN_UNSUPPORTED);
+ return NULL;
+}
+
+RETURN_STATUS
+EFIAPI
+SiliconPolicyDoneLate (
+ IN VOID *Policy
+ )
+{
+ ASSERT_EFI_ERROR (RETURN_UNSUPPORTED);
+ return RETURN_SUCCESS;
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.inf b/Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.inf
new file mode 100644
index 0000000000..3579cc5922
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.inf
@@ -0,0 +1,38 @@
+## @file
+# Component information file for Silicon Init Library Shim instance
+#
+# This library provides a "shim" between the library and PPI or protocols implementing the library services.
+# This allows the silicon initialization specifics to be abstracted behind binaries.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SiliconPolicyInitLibShim
+ FILE_GUID = 3af20aaa-ed5d-4d82-bfd4-db7cc85d4188
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconPolicyInitLib | PEIM DXE_DRIVER
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ PeiServicesLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+
+[Sources]
+ SiliconPolicyInitLibShim.c
+
+[Guids]
+ gSiliconPolicyInitLibInterfaceGuid ## ALWAYS CONSUMES
+
+[Depex]
+ gSiliconPolicyInitLibInterfaceGuid
\ No newline at end of file
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.c b/Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.c
new file mode 100644
index 0000000000..9602cb2ac0
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.c
@@ -0,0 +1,38 @@
+/** @file
+ Silicon workaround library.
+
+ @copyright
+ Copyright 2006 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include <Library/SiliconWorkaroundLib.h>
+#include <Library/BaseLib.h>
+
+
+/**
+ Return whether the workaround is enabled.
+
+ This function returns a boolean that determines whether the workaround is enabled
+ given a workaround name.
+
+ @param[in] WorkaroundName An ASCII string that represents the workaround name.
+ This workaround name should correspond to an entry
+ in the silicon workarounds table(s).
+
+ @retval TRUE The workaround is enabled.
+ @retval FALSE The workaround is not found in the table(s) and therefore disabled.
+
+**/
+BOOLEAN
+EFIAPI
+IsSiliconWorkaroundEnabled (
+ IN CONST CHAR8 *WorkaroundName
+ )
+{
+ return FALSE;
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.inf b/Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.inf
new file mode 100644
index 0000000000..a5b8151f6e
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.inf
@@ -0,0 +1,50 @@
+## @file
+#
+# @copyright
+# Copyright 2008 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SiliconWorkaroundLib
+ FILE_GUID = 85650F6E-9B35-40C0-9F84-B6C8285D1837
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconWorkaroundLib
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+ SiliconWorkaroundLibNull.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ EmulationConfigurationLib
+ PreSiliconEnvDetectLib
+ CpuAndRevisionLib
+ SiliconWorkaroundHelperLib
+
--
2.27.0.windows.1
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