[edk2-devel] [edk2-platforms] [PATCH V1 05/17] WhitleySiliconPkg: Add PCH Register Includes
Nate DeSimone
nathaniel.l.desimone at intel.com
Tue Jul 13 00:41:19 UTC 2021
Signed-off-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
Co-authored-by: Isaac Oram <isaac.w.oram at intel.com>
Co-authored-by: Mohamed Abbas <mohamed.abbas at intel.com>
Cc: Chasel Chiu <chasel.chiu at intel.com>
Cc: Michael D Kinney <michael.d.kinney at intel.com>
Cc: Isaac Oram <isaac.w.oram at intel.com>
Cc: Mohamed Abbas <mohamed.abbas at intel.com>
Cc: Liming Gao <gaoliming at byosoft.com.cn>
Cc: Eric Dong <eric.dong at intel.com>
Cc: Michael Kubacki <Michael.Kubacki at microsoft.com>
---
.../Include/Register/PchRegsDci.h | 44 ++
.../Include/Register/PchRegsDmi.h | 302 ++++++++
.../Include/Register/PchRegsEva.h | 124 +++
.../Include/Register/PchRegsFia.h | 106 +++
.../Include/Register/PchRegsGpio.h | 531 +++++++++++++
.../Include/Register/PchRegsHda.h | 271 +++++++
.../Include/Register/PchRegsHsio.h | 190 +++++
.../Include/Register/PchRegsItss.h | 90 +++
.../Include/Register/PchRegsLan.h | 156 ++++
.../Include/Register/PchRegsLpc.h | 490 ++++++++++++
.../Include/Register/PchRegsP2sb.h | 132 ++++
.../Include/Register/PchRegsPcie.h | 620 +++++++++++++++
.../Include/Register/PchRegsPcr.h | 177 +++++
.../Include/Register/PchRegsPmc.h | 731 ++++++++++++++++++
.../Include/Register/PchRegsPsf.h | 304 ++++++++
.../Include/Register/PchRegsPsth.h | 66 ++
.../Include/Register/PchRegsSata.h | 713 +++++++++++++++++
.../Include/Register/PchRegsSmbus.h | 157 ++++
.../Include/Register/PchRegsSpi.h | 354 +++++++++
.../Include/Register/PchRegsThermal.h | 113 +++
.../Include/Register/PchRegsTraceHub.h | 147 ++++
.../Include/Register/PchRegsUsb.h | 529 +++++++++++++
22 files changed, 6347 insertions(+)
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsDci.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsDmi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsEva.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsFia.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsGpio.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsHda.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsHsio.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsItss.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsLan.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsLpc.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsP2sb.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPcie.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPcr.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPmc.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPsf.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPsth.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSata.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSmbus.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSpi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsThermal.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsTraceHub.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsUsb.h
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsDci.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsDci.h
new file mode 100644
index 0000000000..c2ced719cc
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsDci.h
@@ -0,0 +1,44 @@
+/** @file
+ Register names for PCH DCI device
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_DCI_H_
+#define _PCH_REGS_DCI_H_
+
+//
+// DCI PCR Registers
+//
+#define R_PCH_PCR_DCI_ECTRL 0x04 ///< DCI Control Register
+#define B_PCH_PCR_DCI_ECTRL_HDCILOCK BIT0 ///< Host DCI lock
+#define B_PCH_PCR_DCI_ECTRL_HDCIEN BIT4 ///< Host DCI enable
+#define R_PCH_PCR_DCI_ECKPWRCTL 0x08 ///< DCI Power Control
+#define R_PCH_PCR_DCI_PCE 0x30 ///< DCI Power Control Enable Register
+#define B_PCH_PCR_DCI_PCE_HAE BIT5 ///< Hardware Autonomous Enable
+#define B_PCH_PCR_DCI_PCE_D3HE BIT2 ///< D3-Hot Enable
+#define B_PCH_PCR_DCI_PCE_I3E BIT1 ///< I3 Enable
+#define B_PCH_PCR_DCI_PCE_PMCRE BIT0 ///< PMC Request Enable
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsDmi.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsDmi.h
new file mode 100644
index 0000000000..4f42debf91
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsDmi.h
@@ -0,0 +1,302 @@
+/** @file
+ Register names for DMI and OP-DMI
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 2014 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_DMI_H_
+#define _PCH_REGS_DMI_H_
+
+//
+// DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// VC Configuration (Common)
+//
+#define R_PCH_DMI_PCR_V0CTL 0x2014 ///< Virtual channel 0 resource control
+#define B_PCH_DMI_PCR_V0CTL_EN BIT31
+#define B_PCH_DMI_PCR_V0CTL_ID (7 << 24) ///< Bit[26:24]
+#define N_PCH_DMI_PCR_V0CTL_ID 24
+#define V_PCH_DMI_PCR_V0CTL_ETVM_MASK 0xFC00
+#define V_PCH_DMI_PCR_V0CTL_TVM_MASK 0x7E
+#define R_PCH_DMI_PCR_V0STS 0x201A ///< Virtual channel 0 status
+#define B_PCH_DMI_PCR_V0STS_NP BIT1
+#define R_PCH_DMI_PCR_V1CTL 0x2020 ///< Virtual channel 1 resource control
+#define B_PCH_DMI_PCR_V1CTL_EN BIT31
+#define B_PCH_DMI_PCR_V1CTL_ID (0x0F << 24) ///< Bit[27:24]
+#define N_PCH_DMI_PCR_V1CTL_ID 24
+#define V_PCH_DMI_PCR_V1CTL_ETVM_MASK 0xFC00
+#define V_PCH_DMI_PCR_V1CTL_TVM_MASK 0xFE
+#define R_PCH_DMI_PCR_V1STS 0x2026 ///< Virtual channel 1 status
+#define B_PCH_DMI_PCR_V1STS_NP BIT1
+#define R_PCH_DMI_PCR_VMCTL 0x2040 ///< ME Virtual Channel (VCm) resource control
+#define R_PCH_DMI_PCR_VMSTS 0x2046 ///< ME Virtual Channel Resource Status
+#define R_PCH_DMI_PCR_IOSFC1TC 0x2054 ///< Offset of credits for VC1 register
+#define R_PCH_DMI_PCR_IOSFC2TC 0x2058 ///< Offset of credits for VCm register
+#define V_PCH_DMI_PCR_IOSFC1TC_ICX 0x00021002 ///< Credits for VC1 - values for ICX
+#define V_PCH_DMI_PCR_IOSFC2TC_ICX 0x00082005 ///< Credits for VCm - values for ICX
+#define R_PCH_DMI_PCR_UEM 0x2088 ///< Uncorrectable Error Mask
+#define R_PCH_DMI_PCR_REC 0x20AC ///< Root Error Command
+
+//
+// DMI Error Reporting
+//
+#define R_PCH_DMI_PCR_UES 0x2084 ///< Uncorrectable Error Status
+#define R_PCH_DMI_PCR_UEM 0x2088 ///< Uncorrectable Error Mask
+#define B_PCH_DMI_UE_DLPE BIT4 // Data Link Protocol Error
+#define B_PCH_DMI_UE_PT BIT12 // Poisoned TLP
+#define B_PCH_DMI_UE_CA BIT15 // Completer Abort
+#define B_PCH_DMI_UE_RO BIT17 // Receiver Overflow
+#define B_PCH_DMI_UE_MT BIT18 // Malformed TLP
+#define R_PCH_DMI_PCR_CES 0x2090 ///< Correctable Error Status
+#define R_PCH_DMI_PCR_CEM 0x2094 ///< Correctable Error Mask
+#define B_PCH_DMI_CE_RE BIT0 // Indicates a receiver error
+#define B_PCH_DMI_CE_BT BIT6 // Bad TLP
+#define B_PCH_DMI_CE_BD BIT7 // Bad DLLP
+#define B_PCH_DMI_CE_RNR BIT8 // Replay Number Rollover
+#define R_PCH_DMI_PCR_RES 0x20B0 ///< Root Error Status
+#define B_PCH_DMI_RES_CR BIT0 // correctable error message is received or an internal correctable error is detected
+#define B_PCH_DMI_RES_ENR BIT2 // either afatal or a non-fatal error message is received or an internal fatal error is detected
+
+//
+// Internal Link Configuration (DMI Only)
+//
+#define R_PCH_DMI_PCR_LCAP 0x21A4 ///< Link Capabilities
+#define B_PCH_DMI_PCR_LCAP_EL1 (BIT17 | BIT16 | BIT15)
+#define B_PCH_DMI_PCR_LCAP_EL0 (BIT14 | BIT13 | BIT12)
+#define B_PCH_DMI_PCR_LCAP_APMS (BIT11 | BIT10) ///< L0 is supported on DMI
+#define B_PCH_DMI_PCR_LCAP_MLW 0x000003F0
+#define B_PCH_DMI_PCR_LCAP_MLS 0x0000000F
+
+#define R_PCH_DMI_PCR_LCTL 0x21A8 ///< Link Control
+#define B_PCH_DMI_PCR_LCTL_ES BIT7
+#define B_PCH_DMI_PCR_LCTL_ASPM (BIT1 | BIT0) ///< Link ASPM
+#define R_PCH_DMI_PCR_LSTS 0x21AA ///< Link Status
+
+#define R_PCH_DMI_PCR_LCAP2 0x21AC ///< Link Control 2
+typedef union {
+ UINT32 Dword;
+ struct {
+ UINT32 Rsrvd0 : 1,
+ SLSV : 7, // Supported Link Speed Vector
+ CS : 1, // Crosslink Supported
+ LSOSGSSV : 7, // Lower SKP OS Generation Supported Speeds Vector
+ LSOSRSS : 7, // Lower SKP OS Reception Supported Speeds Vector
+ Rsrvd1 : 9;
+ } Bits;
+} PCH_DMI_PCR_LCAP2;
+
+#define R_PCH_DMI_PCR_LCTL2 0x21B0 ///< Link Control 2
+typedef union {
+ UINT32 Dword;
+ struct {
+ UINT32 TLS : 4, // 0:3 Target Link Speed
+ EC : 1, // 4 Enter Compliance
+ HASD : 1, // 5 Hardware Autonomous Speed Disable
+ SD : 1, // 6 Selectable De-emphasis
+ TM : 3, // 9:7 Transmit Margin
+ EMC : 1, // 10 Enter Modified Compliance
+ CSOS : 1, // 11 Compliance SOS
+ CD : 4, // 15:12 Compliance Preset/De-emphasis
+ CDL : 1, // 16 Current De-emphasis Level
+ EqC : 1, // 17 Equalization Complete
+ EQP1S : 1, // 18 Equalization Phase 1 Successful
+ EQP2S : 1, // 19 Equalization Phase 2 Successful
+ EQP3S : 1, // 20 Equalization Phase 3 Successful
+ LER : 1, // 21 Link Equalization Request
+ Rsrvd0 :10; // 31:22
+ } Bits;
+} PCH_DMI_PCR_LCTL2;
+
+#define R_PCH_DMI_PCR_LSTS2 0x21B2 ///< Link Status 2
+#define R_PCH_PCR_DMI_L01EC 0x21BC ///< Lane 0 and Lane 1 Equalization Control
+#define R_PCH_PCR_DMI_L23EC 0x21C0 ///< Lane 2 and Lane 3 Equalization Control
+#define B_PCH_PCR_DMI_UPL13RPH 0x0F000000 ///< Upstream Port Lane 1/3 Transmitter Preset Hint mask
+#define N_PCH_PCR_DMI_UPL13RPH 24 ///< Upstream Port Lane 1/3 Transmitter Preset Hint value offset
+#define B_PCH_PCR_DMI_UPL02RPH 0x000000F0 ///< Upstream Port Lane 0/2 Transmitter Preset Hint mask
+#define N_PCH_PCR_DMI_UPL02RPH 8 ///< Upstream Port Lane 0/2 Transmitter Preset Hint value offset
+#define V_PCH_PCR_DMI_UPL0RPH 7 ///< Upstream Port Lane 0 Transmitter Preset Hint value
+#define V_PCH_PCR_DMI_UPL1RPH 7 ///< Upstream Port Lane 1 Transmitter Preset Hint value
+#define V_PCH_PCR_DMI_UPL2RPH 7 ///< Upstream Port Lane 2 Transmitter Preset Hint value
+#define V_PCH_PCR_DMI_UPL3RPH 7 ///< Upstream Port Lane 3 Transmitter Preset Hint value
+
+
+//
+// North Port Error Injection Configuration (DMI Only)
+//
+#define R_PCH_DMI_PCR_DMIEN 0x2230 ///< DMI Error Injection Enable
+
+//
+// DMI Control
+//
+#define R_PCH_DMI_PCR_DMIC 0x2234 ///< DMI Control
+#define B_PCH_DMI_PCR_DMIC_SRL BIT31 ///< Secured register lock
+#define B_PCH_DMI_PCR_DMIC_ORCE (BIT25 | BIT24) ///< Offset Re-Calibration Enable
+#define N_PCH_DMI_PCR_DMIC_ORCE 24
+#define V_PCH_DMI_PCR_DMIC_ORCE_EN_GEN2_GEN3 1 ///< Enable offset re-calibration for Gen 2 and Gen 3 data rate only.
+#define B_PCH_DMI_PCR_DMIC_DMICGEN (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) ///< DMI Clock Gate Enable
+#define R_PCH_DMI_PCR_DMIHWAWC 0x2238 ///< DMI HW Autonomus Width Control
+#define R_PCH_DMI_PCR_IOSFSBCS 0x223E ///< IOSF Sideband Control and Status
+#define B_PCH_DMI_PCR_IOSFSBCS_DMICGEN (BIT6 | BIT5 | BIT3 | BIT2) ///< DMI Clock Gate Enable
+#define B_PCH_PCR_DMI_DMIC_DNPRL BIT19
+
+#define R_PCH_DMI_PCR_2300 0x2300
+#define R_PCH_DMI_PCR_2304 0x2304
+#define R_PCH_DMI_PCR_2310 0x2310
+#define B_PCH_PCR_DMI_2310_HALEP BIT22
+#define R_PCH_DMI_PCR_2314 0x2314
+#define R_PCH_DMI_PCR_2320 0x2320
+#define R_PCH_DMI_PCR_2324 0x2324
+#define R_PCH_DMI_PCR_232C 0x232C
+#define R_PCH_DMI_PCR_2334 0x2334
+#define R_PCH_DMI_PCR_2338 0x2338
+#define R_PCH_DMI_PCR_2340 0x2340
+#define R_PCH_DMI_PCR_2344 0x2344
+#define R_PCH_DMI_PCR_2348 0x2348
+#define R_PCH_PCR_DMI_234C 0x234C
+
+//
+// Port Configuration Extension(DMI Only)
+//
+#define R_PCH_DMI_PCR_EQCFG1 0x2450
+#define B_PCH_DMI_PCR_EQCFG1_RTLEPCEB BIT16
+#define B_PCH_PCR_DMI_EQCFG1_RTPCOE BIT15 ///< Remote Transmitter Preset Coefficient Override Enable
+
+#define R_PCH_PCR_DMI_RTPCL1 0x2454 ///< Remote Transmitter Preset Coefficient List 1
+
+#define N_PCH_PCR_DMI_RTPCL1_RTPRECL2PL4 24
+#define N_PCH_PCR_DMI_RTPCL1_RTPOSTCL1PL3 18
+#define N_PCH_PCR_DMI_RTPCL1_RTPRECL1PL2 12
+#define N_PCH_PCR_DMI_RTPCL1_RTPOSTCL0PL1 6
+#define N_PCH_PCR_DMI_RTPCL1_RTPRECL0PL0 0
+
+#define B_PCH_PCR_DMI_RTPCL1_PCM BIT31
+#define B_PCH_PCR_DMI_RTPCL1_RTPRECL2PL4 (0X3F << N_PCH_PCR_DMI_RTPCL1_RTPRECL2PL4)
+#define B_PCH_PCR_DMI_RTPCL1_RTPOSTCL1PL3 (0X3F << N_PCH_PCR_DMI_RTPCL1_RTPOSTCL1PL3)
+#define B_PCH_PCR_DMI_RTPCL1_RTPRECL1PL2 (0X3F << N_PCH_PCR_DMI_RTPCL1_RTPRECL1PL2)
+#define B_PCH_PCR_DMI_RTPCL1_RTPOSTCL0PL1 (0X3F << N_PCH_PCR_DMI_RTPCL1_RTPOSTCL0PL1)
+#define B_PCH_PCR_DMI_RTPCL1_RTPRECL0PL0 (0X3F << N_PCH_PCR_DMI_RTPCL1_RTPRECL0PL0)
+#define R_PCH_PCR_DMI_RTPCL2 0x2458 ///< Remote Transmitter Preset Coefficient List 2
+
+#define N_PCH_PCR_DMI_RTPCL2_RTPOSTCL4PL9 24
+#define N_PCH_PCR_DMI_RTPCL2_RTPRECL4PL8 18
+#define N_PCH_PCR_DMI_RTPCL2_RTPOSTCL3PL7 12
+#define N_PCH_PCR_DMI_RTPCL2_RTPRECL3PL6 6
+#define N_PCH_PCR_DMI_RTPCL2_RTPOSTCL2PL5 0
+
+#define B_PCH_PCR_DMI_RTPCL2_RTPOSTCL4PL9 (0X3F << N_PCH_PCR_DMI_RTPCL2_RTPOSTCL4PL9)
+#define B_PCH_PCR_DMI_RTPCL2_RTPRECL4PL8 (0X3F << N_PCH_PCR_DMI_RTPCL2_RTPRECL4PL8)
+#define B_PCH_PCR_DMI_RTPCL2_RTPOSTCL3PL7 (0X3F << N_PCH_PCR_DMI_RTPCL2_RTPOSTCL3PL7)
+#define B_PCH_PCR_DMI_RTPCL2_RTPRECL3PL6 (0X3F << N_PCH_PCR_DMI_RTPCL2_RTPRECL3PL6)
+#define B_PCH_PCR_DMI_RTPCL2_RTPOSTCL2PL5 (0X3F << N_PCH_PCR_DMI_RTPCL2_RTPOSTCL2PL5)
+
+
+#define R_PCH_DMI_PCR_LTCO1 0x2470 ///< Local Transmitter Coefficient Override 1
+#define R_PCH_DMI_PCR_LTCO2 0x2474 ///< Local Transmitter Coefficient Override 2
+#define B_PCH_DMI_PCR_L13TCOE BIT25 ///< Lane 1/3 Transmitter Coefficient Override Enable
+#define B_PCH_DMI_PCR_L02TCOE BIT24 ///< Lane 0/2 Transmitter Coefficient Override Enable
+#define B_PCH_DMI_PCR_L13TPOSTCO 0x00fc0000 ///< Lane 1/3 Transmitter Post-Cursor Coefficient Override mask
+#define N_PCH_DMI_PCR_L13TPOSTCO 18 ///< Lane 1/3 Transmitter Post-Cursor Coefficient Override value offset
+#define B_PCH_DMI_PCR_L13TPRECO 0x0003f000 ///< Lane 1/3 Transmitter Pre-Cursor Coefficient Override mask
+#define N_PCH_DMI_PCR_L13TPRECO 12 ///< Lane 1/3 Transmitter Pre-Cursor Coefficient Override value offset
+#define B_PCH_DMI_PCR_L02TPOSTCO 0x00000fc0 ///< Lane 0/2 Transmitter Post-Cursor Coefficient Override mask
+#define N_PCH_DMI_PCR_L02TPOSTCO 6 ///< Lane 0/2 Transmitter Post-Cursor Coefficient Override value offset
+#define B_PCH_DMI_PCR_L02TPRECO 0x0000003f ///< Lane 0/2 Transmitter Pre-Cursor Coefficient Override mask
+#define N_PCH_DMI_PCR_L02TPRECO 0 ///< Lane 0/2 Transmitter Pre-Cursor Coefficient Override value offset
+#define R_PCH_DMI_PCR_G3L0SCTL 0x2478 ///< GEN3 L0s Control
+
+//
+// OP-DMI Specific Registers (OP-DMI Only)
+//
+#define R_PCH_OPDMI_PCR_LCTL 0x2600 ///< Link Control
+#define R_PCH_OPDMI_PCR_STC 0x260C ///< Sideband Timing Control
+#define R_PCH_OPDMI_PCR_LPMC 0x2614 ///< Link Power Management Control
+#define R_PCH_OPDMI_PCR_LCFG 0x2618 ///< Link Configuration
+
+//
+// DMI Source Decode PCRs (Common)
+//
+#define R_PCH_DMI_PCR_PCIEPAR1E 0x2700 ///< PCIE Port IOxAPIC Range 1 Enable
+#define R_PCH_DMI_PCR_PCIEPAR2E 0x2704 ///< PCIE Port IOxAPIC Range 2 Enable
+#define R_PCH_DMI_PCR_PCIEPAR3E 0x2708 ///< PCIE Port IOxAPIC Range 3 Enable
+#define R_PCH_DMI_PCR_PCIEPAR4E 0x270C ///< PCIE Port IOxAPIC Range 4 Enable
+#define R_PCH_DMI_PCR_PCIEPAR1DID 0x2710 ///< PCIE Port IOxAPIC Range 1 Destination ID
+#define R_PCH_DMI_PCR_PCIEPAR2DID 0x2714 ///< PCIE Port IOxAPIC Range 2 Destination ID
+#define R_PCH_DMI_PCR_PCIEPAR3DID 0x2718 ///< PCIE Port IOxAPIC Range 3 Destination ID
+#define R_PCH_DMI_PCR_PCIEPAR4DID 0x271C ///< PCIE Port IOxAPIC Range 4 Destination ID
+#define R_PCH_DMI_PCR_P2SBIOR 0x2720 ///< P2SB IO Range
+#define R_PCH_DMI_PCR_TTTBARB 0x2724 ///< Thermal Throttling BIOS Assigned Thermal Base Address
+#define R_PCH_DMI_PCR_TTTBARBH 0x2728 ///< Thermal Throttling BIOS Assigned Thermal Base High Address
+#define R_PCH_DMI_PCR_LPCLGIR1 0x2730 ///< LPC Generic I/O Range 1
+#define R_PCH_DMI_PCR_LPCLGIR2 0x2734 ///< LPC Generic I/O Range 2
+#define R_PCH_DMI_PCR_LPCLGIR3 0x2738 ///< LPC Generic I/O Range 3
+#define R_PCH_DMI_PCR_LPCLGIR4 0x273C ///< LPC Generic I/O Range 4
+#define R_PCH_DMI_PCR_LPCGMR 0x2740 ///< LPC Generic Memory Range
+#define R_PCH_DMI_PCR_LPCBDE 0x2744 ///< LPC BIOS Decode Enable
+#define R_PCH_DMI_PCR_UCPR 0x2748 ///< uCode Patch Region
+#define B_PCH_DMI_PCR_UCPR_UPRE BIT0 ///< uCode Patch Region Enable
+#define R_PCH_DMI_PCR_GCS 0x274C ///< Generic Control and Status
+#define B_PCH_DMI_PCR_RPRDID 0xFFFF0000 ///< RPR Destination ID
+#define B_PCH_DMI_PCR_BBS BIT10 ///< Boot BIOS Strap
+#define B_PCH_DMI_PCR_RPR BIT11 ///< Reserved Page Route
+#define B_PCH_DMI_PCR_BILD BIT0 ///< BIOS Interface Lock-Down
+#define R_PCH_DMI_PCR_IOT1 0x2750 ///< I/O Trap Register 1
+#define R_PCH_DMI_PCR_IOT2 0x2758 ///< I/O Trap Register 2
+#define R_PCH_DMI_PCR_IOT3 0x2760 ///< I/O Trap Register 3
+#define R_PCH_DMI_PCR_IOT4 0x2768 ///< I/O Trap Register 4
+#define R_PCH_DMI_PCR_LPCIOD 0x2770 ///< LPC I/O Decode Ranges
+#define R_PCH_DMI_PCR_LPCIOE 0x2774 ///< LPC I/O Enables
+#define R_PCH_DMI_PCR_TCOBASE 0x2778 ///< TCO Base Address
+#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 ///< TCO Base Address Mask
+#define R_PCH_DMI_PCR_GPMR1 0x277C ///< General Purpose Memory Range 1
+#define R_PCH_DMI_PCR_GPMR1DID 0x2780 ///< General Purpose Memory Range 1 Destination ID
+#define R_PCH_DMI_PCR_GPMR2 0x2784 ///< General Purpose Memory Range 2
+#define R_PCH_DMI_PCR_GPMR2DID 0x2788 ///< General Purpose Memory Range 2 Destination ID
+#define R_PCH_DMI_PCR_GPMR3 0x278C ///< General Purpose Memory Range 3
+#define R_PCH_DMI_PCR_GPMR3DID 0x2790 ///< General Purpose Memory Range 3 Destination ID
+#define R_PCH_DMI_PCR_GPIOR1 0x2794 ///< General Purpose I/O Range 1
+#define R_PCH_DMI_PCR_GPIOR1DID 0x2798 ///< General Purpose I/O Range 1 Destination ID
+#define R_PCH_DMI_PCR_GPIOR2 0x279C ///< General Purpose I/O Range 2
+#define R_PCH_DMI_PCR_GPIOR2DID 0x27A0 ///< General Purpose I/O Range 2 Destination ID
+#define R_PCH_DMI_PCR_GPIOR3 0x27A4 ///< General Purpose I/O Range 3
+#define R_PCH_DMI_PCR_GPIOR3DID 0x27A8 ///< General Purpose I/O Range 3 Destination ID
+#define R_PCH_PCR_DMI_PMBASEA 0x27AC ///< PM Base Address
+#define R_PCH_PCR_DMI_PMBASEC 0x27B0 ///< PM Base Control
+#define R_PCH_PCR_DMI_ACPIBA 0x27B4 ///< ACPI Base Address
+#define R_PCH_PCR_DMI_ACPIBDID 0x27B8 ///< ACPI Base Destination ID
+#define R_PCH_DMI_PCR_SEGMR 0x27C0 ///< Second eSPI Generic Memory Range
+#define R_PCH_DMI_PCR_SEGIR 0x27BC ///< Second eSPI Generic I/O Range
+
+//
+// Opi PHY registers
+//
+#define R_PCH_OPIPHY_PCR_0110 0x0110
+#define R_PCH_OPIPHY_PCR_0118 0x0118
+#define R_PCH_OPIPHY_PCR_011C 0x011C
+#define R_PCH_OPIPHY_PCR_0354 0x0354
+#define R_PCH_OPIPHY_PCR_B104 0xB104
+#define R_PCH_OPIPHY_PCR_B10C 0xB10C
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsEva.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsEva.h
new file mode 100644
index 0000000000..77ec6284a5
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsEva.h
@@ -0,0 +1,124 @@
+/** @file
+ Register names for PCH Eva devices.
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_<generation_name>_" in register/bit names. e.g., "_PCH_LPT_"
+ Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without <generation_name> inserted.
+
+ @copyright
+ Copyright 2014 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_EVA_H_
+#define _PCH_REGS_EVA_H_
+
+#define PCI_DEVICE_NUMBER_EVA 17
+#define PCI_FUNCTION_NUMBER_EVA_MROM0 0
+#define PCI_FUNCTION_NUMBER_EVA_MROM1 1
+#define PCI_FUNCTION_NUMBER_EVA_SSATA 5
+
+///
+/// Lewisburg SKUs
+///
+#define LBG_SKU_G 1
+#define LBG_SKU_X 2
+#define LBG_SKU_A 3
+
+#define PCI_DEVICE_NUMBER_PCH_SSATA 17
+#define PCI_FUNCTION_NUMBER_PCH_SSATA 5
+
+#define R_PCH_LBG_SSATA_DEVICE_ID 0x02
+
+///
+/// LBG Production sSATA Controller DID definition
+///
+#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_AHCI 0xA1D2 // LBG Production Server Secondary AHCI Mode (Ports 0-4)
+#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID 0xA1D4 // LBG Production Server RAID 0/1/5/10 - NOT premium
+#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID_PREMIUM 0xA1D6 // LBG Production Server RAID 0/1/5/10 - premium
+#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID1 0xA1DE // LBG Production Server RAID 1/RRT
+
+///
+/// LBG Production (PRQ) MSUint SMBUS DID definition
+///
+#define V_PCH_LBG_PROD_MROM_DEVICE_ID_0 0xA1F0 // LBG MS Unit MROM 0 PRQ DID
+#define V_PCH_LBG_PROD_MROM_DEVICE_ID_1 0xA1F1 // LBG MS Unit MROM 1 PRQ DID
+
+
+///
+/// LBG SSX (Super SKUs and Pre Production) sSATA Controller DID definition
+///
+#define V_PCH_LBG_SSATA_DEVICE_ID_D_AHCI 0xA252 // LBG SSX Server Secondary AHCI Mode (Ports 0-4)
+#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID 0xA254 // LBG SSX Server RAID 0/1/5/10 - NOT premium
+#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM 0xA256 // LBG SSX Server RAID 0/1/5/10 - premium
+#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID1 0xA25E // LBG SSX Server RAID 1/RRT
+
+#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0 0x2823 // Server RAID 0/1/5/10 - premium - Alternate ID for RST
+#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1 0x2827 // Server RAID 0/1/5/10 - premium - Alternate ID for RSTe
+
+///
+/// LBG Super SKU (SSX) MSUint DID definition
+///
+#define V_PCH_LBG_MROM_DEVICE_ID_0 0xA270 // LBG NS MS Unit MROM 0 Super SKU DID
+#define V_PCH_LBG_MROM_DEVICE_ID_1 0xA271 // LBG NS MS Unit MROM 1 Super SKU DID
+
+#define R_PCH_LBG_MROM_DEVCLKGCTL 0xE4
+
+#define R_PCH_LBG_MROM_PLKCTL 0xE8
+#define B_PCH_LBG_MROM_PLKCTL_CL BIT0
+
+#define ADR_TMR_HELD_OFF_SETUP_OPTION 2
+#define R_PCH_LBG_MROM_ADRTIMERCTRL 0x180
+#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_MASK (BIT27|BIT26|BIT25|BIT24)
+#define N_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT 24
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_1 0x0
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_8 0x1
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_24 0x2
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_40 0x3
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_56 0x4
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_64 0x5
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_72 0x6
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_80 0x7
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_88 0x8
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_96 0x9
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_MAX (V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_96)
+#define ADR_MULT_SETUP_DEFAULT_POR 99
+#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_DBG_DIS BIT28
+#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_DIS BIT29
+#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_MASK (BIT30|BIT31)
+#define N_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR 30
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_25US 0x0
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_50US 0x1
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_100US 0x2
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_0US 0x3
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_MAX (V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_0US)
+#define ADR_TMR_SETUP_DEFAULT_POR 4
+
+///
+/// MS Unit Hide Control Register
+///
+#define PCH_LBG_MSUINT_FUNCS 3
+#define R_PCH_LBG_MSUINT_MSDEVFUNCHIDE 0xD4
+#define B_PCH_LBG_MSUINT_MSDEVFUNCHIDE_RSVD (BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|\
+ BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|\
+ BIT16|BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|\
+ BIT9|BIT8|BIT7|BIT6|BIT4|BIT3|BIT2)
+
+#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_SSATA (BIT5)
+
+#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_MROM1 BIT1
+#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_MROM0 BIT0
+#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_REGLOCK BIT31
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsFia.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsFia.h
new file mode 100644
index 0000000000..c66de3404b
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsFia.h
@@ -0,0 +1,106 @@
+/** @file
+ Register definition for FIA component
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 2014 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_FIA_H_
+#define _PCH_REGS_FIA_H_
+
+
+//
+// Private chipset regsiter (Memory space) offset definition
+// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well.
+//
+
+//
+// PID:FIA
+//
+#define PCH_MAX_PCI_SATA_COMBO_PORT 14
+#define PCH_MAX_FIA_DRCRM 3
+#define R_PCH_PCR_FIA_CC 0
+#define B_PCH_PCR_FIA_CC_SRL BIT31
+#define B_PCH_PCR_FIA_CC_PTOCGE BIT17
+#define B_PCH_PCR_FIA_CC_OSCDCGE BIT16
+#define B_PCH_PCR_FIA_CC_SCPTCGE BIT15
+
+#define R_PCH_PCR_FIA_PLLCTL 0x20
+#define R_PCH_PCR_FIA_DRCRM1 0x100
+#define R_PCH_PCR_FIA_DRCRM2 0x104
+#define R_PCH_PCR_FIA_DRCRM3 0x108
+#define N_PCH_PCR_FIA_DRCRM3_GBEPCKRQM 28
+#define S_PCH_PCR_FIA_DRCRM 4
+#define R_PCH_PCR_FIA_STRPFUSECFG1_REG_BASE 0x200
+#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIE_PEN BIT31
+#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL (BIT30 | BIT29 | BIT28)
+#define N_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL 28
+#define R_PCH_PCR_FIA_PCIESATA_FUSECFG_REG_BASE 0x204
+#define R_PCH_PCR_FIA_PCIESATA_STRPCFG_REG_BASE 0x208
+#define R_PCH_PCR_FIA_PCIEUSB3_STRPFUSECFG_REG_BASE 0x20C
+#define R_PCH_PCR_FIA_EXP_FUSECFG_REG_BASE 0x210
+#define R_PCH_PCR_FIA_USB3SSIC_STRPFUSECFG_REG_BASE 0x214
+#define R_PCH_PCR_FIA_CSI3_STRPFUSECFG_REG_BASE 0x218
+#define R_PCH_PCR_FIA_USB3SATA_STRPFUSECFG_REG_BASE 0x21C
+#define R_PCH_PCR_FIA_UFS_STRPFUSECFG_REG_BASE 0x220
+#define R_PCH_PCR_FIA_PCIEUDL_STRPFUSECFG_REG_BASE 0x224
+#define R_PCH_PCR_FIA_LOS1_REG_BASE 0x250
+#define R_PCH_PCR_FIA_LOS2_REG_BASE 0x254
+#define R_PCH_PCR_FIA_LOS3_REG_BASE 0x258
+#define R_PCH_PCR_FIA_LOS4_REG_BASE 0x25C
+#define V_PCH_PCR_FIA_LANE_OWN_PCIEDMI 0x0
+#define V_PCH_PCR_FIA_LANE_OWN_USB3 0x1
+#define V_PCH_PCR_FIA_LANE_OWN_SATA 0x2
+#define V_PCH_PCR_FIA_LANE_OWN_GBE 0x3
+#define V_PCH_PCR_FIA_LANE_OWN_SSIC 0x5
+
+#define V_PCH_PCR_FIA_LANE_OWN_UX8 0x8
+
+#define B_PCH_PCR_FIA_L0O (BIT3 | BIT2 | BIT1 | BIT0)
+#define B_PCH_PCR_FIA_L1O (BIT7 | BIT6 | BIT5 | BIT4)
+#define B_PCH_PCR_FIA_L2O (BIT11 | BIT10 | BIT9 | BIT8)
+#define B_PCH_PCR_FIA_L3O (BIT15 | BIT14 | BIT13 | BIT12)
+#define B_PCH_PCR_FIA_L4O (BIT19 | BIT18 | BIT17 | BIT16)
+#define B_PCH_PCR_FIA_L5O (BIT23 | BIT22 | BIT21 | BIT20)
+#define B_PCH_PCR_FIA_L6O (BIT27 | BIT26 | BIT25 | BIT24)
+#define B_PCH_PCR_FIA_L7O (BIT31 | BIT30 | BIT29 | BIT28)
+#define B_PCH_PCR_FIA_L8O (BIT3 | BIT2 | BIT1 | BIT0)
+#define B_PCH_PCR_FIA_L9O (BIT7 | BIT6 | BIT5 | BIT4)
+#define B_PCH_PCR_FIA_L10O (BIT11 | BIT10 | BIT9 | BIT8)
+#define B_PCH_PCR_FIA_L11O (BIT15 | BIT14 | BIT13 | BIT12)
+#define B_PCH_PCR_FIA_L12O (BIT19 | BIT18 | BIT17 | BIT16)
+#define B_PCH_PCR_FIA_L13O (BIT23 | BIT22 | BIT21 | BIT20)
+#define B_PCH_PCR_FIA_L14O (BIT27 | BIT26 | BIT25 | BIT24)
+#define B_PCH_PCR_FIA_L15O (BIT31 | BIT30 | BIT29 | BIT28)
+#define B_PCH_PCR_FIA_L16O (BIT3 | BIT2 | BIT1 | BIT0)
+#define B_PCH_PCR_FIA_L17O (BIT7 | BIT6 | BIT5 | BIT4)
+#define B_PCH_PCR_FIA_L18O (BIT11 | BIT10 | BIT9 | BIT8)
+#define B_PCH_PCR_FIA_L19O (BIT15 | BIT14 | BIT13 | BIT12)
+#define B_PCH_PCR_FIA_L20O (BIT19 | BIT18 | BIT17 | BIT16)
+#define B_PCH_PCR_FIA_L21O (BIT23 | BIT22 | BIT21 | BIT20)
+#define B_PCH_PCR_FIA_L22O (BIT27 | BIT26 | BIT25 | BIT24)
+#define B_PCH_PCR_FIA_L23O (BIT31 | BIT30 | BIT29 | BIT28)
+#define B_PCH_PCR_FIA_L24O (BIT3 | BIT2 | BIT1 | BIT0)
+#define B_PCH_PCR_FIA_L25O (BIT7 | BIT6 | BIT5 | BIT4)
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsGpio.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsGpio.h
new file mode 100644
index 0000000000..bbf4df90ae
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsGpio.h
@@ -0,0 +1,531 @@
+/** @file
+ Register names for PCH GPIO
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 2013 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_GPIO_H_
+#define _PCH_REGS_GPIO_H_
+
+#define V_PCH_GPIO_GPP_A_PAD_MAX 24
+#define V_PCH_GPIO_GPP_B_PAD_MAX 24
+#define V_PCH_GPIO_GPP_C_PAD_MAX 24
+#define V_PCH_GPIO_GPP_D_PAD_MAX 24
+#define V_PCH_LP_GPIO_GPP_E_PAD_MAX 24
+#define V_PCH_H_GPIO_GPP_E_PAD_MAX 13
+#define V_PCH_GPIO_GPP_F_PAD_MAX 24
+#define V_PCH_LP_GPIO_GPP_G_PAD_MAX 8
+#define V_PCH_H_GPIO_GPP_G_PAD_MAX 24
+#define V_PCH_H_GPIO_GPP_H_PAD_MAX 24
+#define V_PCH_H_GPIO_GPP_J_PAD_MAX 24
+#define V_PCH_H_GPIO_GPP_K_PAD_MAX 11
+#define V_PCH_H_GPIO_GPP_L_PAD_MAX 20
+#define V_PCH_H_GPIO_GPP_I_PAD_MAX 11
+
+#define V_PCH_GPIO_GPD_PAD_MAX 12
+
+#define V_PCH_GPIO_GROUP_MAX 13
+#define V_PCH_H_GPIO_GROUP_MAX V_PCH_GPIO_GROUP_MAX
+#define V_PCH_LP_GPIO_GROUP_MAX 8
+#define PCH_GPIO_NUM_SUPPORTED_GPIS 261
+#define S_GPIO_PCR_GP_SMI_EN 4
+#define S_GPIO_PCR_GP_SMI_STS 4
+
+///
+/// Groups mapped to 2-tier General Purpose Event will all be under
+/// one master GPE_111 (0x6F)
+///
+#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F
+
+
+//
+// GPIO Common Private Configuration Registers
+//
+#define R_GPIO_PCR_REV_ID 0x00
+#define R_GPIO_PCR_CAP_LIST 0x04
+#define R_GPIO_PCR_FAMBAR 0x08
+#define R_GPIO_PCR_PADBAR 0x0C
+#define B_GPIO_PCR_PADBAR 0x0000FFFF
+#define R_GPIO_PCR_MISCCFG 0x10
+#define B_GPIO_PCR_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16)
+#define N_GPIO_PCR_MISCCFG_GPE0_DW2 16
+#define B_GPIO_PCR_MISCCFG_GPE0_DW1 (BIT15 | BIT14 | BIT13 | BIT12)
+#define N_GPIO_PCR_MISCCFG_GPE0_DW1 12
+#define B_GPIO_PCR_MISCCFG_GPE0_DW0 (BIT11 | BIT10 | BIT9 | BIT8)
+#define N_GPIO_PCR_MISCCFG_GPE0_DW0 8
+#define B_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE BIT3
+#define N_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE 3
+#define B_GPIO_PCR_MISCCFG_GPDPCGEN BIT1
+#define B_GPIO_PCR_MISCCFG_GPDLCGEN BIT0
+// SKL PCH-H:
+#define R_PCH_H_PCR_GPIO_MISCSECCFG 0x14
+
+//
+// GPIO Community 0 Private Configuration Registers
+//
+// SKL PCH-LP
+#define R_PCH_LP_PCR_GPIO_GPP_A_PAD_OWN 0x20
+#define R_PCH_LP_PCR_GPIO_GPP_B_PAD_OWN 0x30
+#define R_PCH_LP_PCR_GPIO_GPP_A_GPI_VWM_EN 0x80
+#define R_PCH_LP_PCR_GPIO_GPP_B_GPI_VWM_EN 0x84
+#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCK 0xA0
+#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCKTX 0xA4
+#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCK 0xA8
+#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCKTX 0xAC
+// SKX Server PCH
+#define R_PCH_H_PCR_GPIO_GPP_A_PAD_OWN 0x20
+#define R_PCH_H_PCR_GPIO_GPP_B_PAD_OWN 0x2C
+#define R_PCH_H_PCR_GPIO_GPP_F_PAD_OWN 0x38
+#define R_PCH_H_PCR_GPIO_GPP_A_GPI_VWM_EN 0x50
+#define R_PCH_H_PCR_GPIO_GPP_B_GPI_VWM_EN 0x54
+#define R_PCH_H_PCR_GPIO_GPP_F_GPI_VWM_EN 0x58
+#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCK 0x60
+#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCKTX 0x64
+#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCK 0x68
+#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCKTX 0x6C
+#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCK 0x70
+#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCKTX 0x74
+#define R_PCH_H_PCR_GPIO_GPP_F_HOSTSW_OWN 0x88
+#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IS 0x0108
+#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IE 0x0118
+#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0128
+#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0138
+#define R_PCH_H_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x580
+
+// Common
+#define R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN 0x80
+#define R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN 0x84
+#define R_PCH_PCR_GPIO_GPP_A_GPI_IS 0x0100
+#define R_PCH_PCR_GPIO_GPP_B_GPI_IS 0x0104
+#define R_PCH_PCR_GPIO_GPP_A_GPI_IE 0x0110
+#define R_PCH_PCR_GPIO_GPP_B_GPI_IE 0x0114
+#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS 0x0120
+#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS 0x0124
+#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_EN 0x0130
+#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_EN 0x0134
+#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0144
+#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x0154
+#define R_PCH_PCR_GPIO_GPP_B_NMI_STS 0x0164
+#define R_PCH_PCR_GPIO_GPP_B_NMI_EN 0x0174
+#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400
+#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0
+
+//
+// GPIO Community 1 Private Configuration Registers
+//
+//SKL PCH-LP:
+#define R_PCH_LP_PCR_GPIO_GPP_C_PAD_OWN 0x20
+#define R_PCH_LP_PCR_GPIO_GPP_D_PAD_OWN 0x30
+#define R_PCH_LP_PCR_GPIO_GPP_E_PAD_OWN 0x40
+#define R_PCH_LP_PCR_GPIO_GPP_C_GPI_VWM_EN 0x80
+#define R_PCH_LP_PCR_GPIO_GPP_D_GPI_VWM_EN 0x84
+#define R_PCH_LP_PCR_GPIO_GPP_E_GPI_VWM_EN 0x88
+#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCK 0xA0
+#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCKTX 0xA4
+#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCK 0xA8
+#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCKTX 0xAC
+#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCK 0xB0
+#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCKTX 0xB4
+//SKL PCH-H:
+#define R_PCH_H_PCR_GPIO_GPP_C_PAD_OWN 0x20
+#define R_PCH_H_PCR_GPIO_GPP_D_PAD_OWN 0x2C
+#define R_PCH_H_PCR_GPIO_GPP_E_PAD_OWN 0x38
+// Server SKX PCH
+#define R_PCH_H_PCR_GPIO_GPP_C_GPI_VWM_EN 0x50
+#define R_PCH_H_PCR_GPIO_GPP_D_GPI_VWM_EN 0x54
+#define R_PCH_H_PCR_GPIO_GPP_E_GPI_VWM_EN 0x58
+#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCK 0x60
+#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCKTX 0x64
+#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCK 0x68
+#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCKTX 0x6C
+#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCK 0x70
+#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCKTX 0x74
+// Common
+#define R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN 0x80
+#define R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN 0x84
+#define R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN 0x88
+#define R_PCH_PCR_GPIO_GPP_C_GPI_IS 0x0100
+#define R_PCH_PCR_GPIO_GPP_D_GPI_IS 0x0104
+#define R_PCH_PCR_GPIO_GPP_E_GPI_IS 0x0108
+#define R_PCH_PCR_GPIO_GPP_C_GPI_IE 0x0110
+#define R_PCH_PCR_GPIO_GPP_D_GPI_IE 0x0114
+#define R_PCH_PCR_GPIO_GPP_E_GPI_IE 0x0114
+#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS 0x0120
+#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS 0x0124
+#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS 0x0128
+#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_EN 0x0130
+#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_EN 0x0134
+#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_EN 0x0138
+#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0140
+#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0144
+#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0148
+#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x0150
+#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x0154
+#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x0158
+#define R_PCH_PCR_GPIO_GPP_C_NMI_STS 0x0160
+#define R_PCH_PCR_GPIO_GPP_D_NMI_STS 0x0164
+#define R_PCH_PCR_GPIO_GPP_E_NMI_STS 0x0168
+#define R_PCH_PCR_GPIO_GPP_C_NMI_EN 0x0170
+#define R_PCH_PCR_GPIO_GPP_D_NMI_EN 0x0174
+#define R_PCH_PCR_GPIO_GPP_E_NMI_EN 0x0178
+
+
+// Common:
+#define R_GPIO_PCR_CAP_LIST_1_PWM 0x0200
+#define R_GPIO_PCR_PWMC 0x0204
+#define R_GPIO_PCR_CAP_LIST_2_SER_BLINK 0x0208
+#define R_GPIO_PCR_GP_SER_BLINK 0x020C
+#define B_GPIO_PCR_GP_SER_BLINK 0x1F
+#define R_GPIO_PCR_GP_SER_CMDSTS 0x0210
+#define B_GPIO_PCR_GP_SER_CMDSTS_DLS (BIT23 | BIT22)
+#define N_GPIO_PCR_GP_SER_CMDSTS_DLS 22
+#define B_GPIO_PCR_GP_SER_CMDSTS_DRS 0x003F0000
+#define N_GPIO_PCR_GP_SER_CMDSTS_DRS 16
+#define B_GPIO_PCR_GP_SER_CMDSTS_BUSY BIT8
+#define B_GPIO_PCR_GP_SER_CMDSTS_GO BIT0
+#define R_GPIO_PCR_GP_SER_DATA 0x0210
+// Common:
+#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400
+#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0
+#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580
+
+//
+// GPIO Community 2 Private Configuration Registers
+//
+// SKL PCH-LP
+#define R_PCH_LP_PCR_GPIO_GPD_PAD_OWN 0x20
+#define R_PCH_LP_PCR_GPIO_GPD_GPI_VWM_EN 0x80
+#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCK 0xA0
+#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCKTX 0xA4
+// SKX Server PCH
+#define R_PCH_H_PCR_GPIO_GPD_PAD_OWN 0x20
+#define R_PCH_H_PCR_GPIO_GPD_GPI_VWM_EN 0x50
+#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCK 0x60
+#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCKTX 0x64
+// Common
+#define R_PCH_PCR_GPIO_GPD_HOSTSW_OWN 0x80
+#define R_PCH_PCR_GPIO_GPD_GPI_IS 0x0100
+#define R_PCH_PCR_GPIO_GPD_GPI_IE 0x0110
+#define R_PCH_PCR_GPIO_GPD_GPI_GPE_STS 0x0120
+#define R_PCH_PCR_GPIO_GPD_GPI_GPE_EN 0x0130
+#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400
+
+//
+// GPIO Community 3 Private Configuration Registers
+//
+// SKL PCH-LP:
+#define R_PCH_LP_PCR_GPIO_GPP_F_PAD_OWN 0x20
+#define R_PCH_LP_PCR_GPIO_GPP_G_PAD_OWN 0x30
+#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_VWM_EN 0x80
+#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_VWM_EN 0x84
+#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCK 0xA0
+#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCKTX 0xA4
+#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCK 0xA8
+#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCKTX 0xAC
+#define R_PCH_LP_PCR_GPIO_GPP_F_HOSTSW_OWN 0xD0
+#define R_PCH_LP_PCR_GPIO_GPP_G_HOSTSW_OWN 0xD4
+#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IS 0x0100
+#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IS 0x0104
+#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IE 0x0120
+#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IE 0x0124
+#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0140
+#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0144
+#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0160
+#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0164
+#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400
+#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0
+
+// SKX Server PCH
+#define R_PCH_H_PCR_GPIO_GPP_I_PAD_OWN 0x20
+#define R_PCH_H_PCR_GPIO_GPP_I_GPI_VWM_EN 0x50
+#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCK 0x60
+#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCKTX 0x64
+#define R_PCH_H_PCR_GPIO_GPP_I_HOSTSW_OWN 0x80
+#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IS 0x0100
+#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IE 0x0110
+#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_STS 0x0120
+#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_EN 0x0130
+#define R_PCH_H_PCR_GPIO_GPP_I_SMI_STS 0x0140
+#define R_PCH_H_PCR_GPIO_GPP_I_SMI_EN 0x0150
+#define R_PCH_H_PCR_GPIO_GPP_I_NMI_STS 0x0160
+#define R_PCH_H_PCR_GPIO_GPP_I_NMI_EN 0x0170
+#define R_PCH_H_PCR_GPIO_GPP_I_PADCFG_OFFSET 0x400
+
+//
+// GPIO Community 4 Private Configuration Registers
+//
+
+// SKX Server PCH
+#define R_PCH_H_PCR_GPIO_GPP_J_PAD_OWN 0x20
+#define R_PCH_H_PCR_GPIO_GPP_K_PAD_OWN 0x2C
+#define R_PCH_H_PCR_GPIO_GPP_J_GPI_VWM_EN 0x50
+#define R_PCH_H_PCR_GPIO_GPP_K_GPI_VWM_EN 0x54
+#define R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCK 0x60
+#define R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCKTX 0x64
+#define R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCK 0x68
+#define R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCKTX 0x6C
+#define R_PCH_H_PCR_GPIO_GPP_J_HOSTSW_OWN 0x80
+#define R_PCH_H_PCR_GPIO_GPP_K_HOSTSW_OWN 0x84
+#define R_PCH_H_PCR_GPIO_GPP_J_GPI_IS 0x0100
+#define R_PCH_H_PCR_GPIO_GPP_K_GPI_IS 0x0104
+#define R_PCH_H_PCR_GPIO_GPP_J_GPI_IE 0x0110
+#define R_PCH_H_PCR_GPIO_GPP_K_GPI_IE 0x0114
+#define R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_STS 0x0120
+#define R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_STS 0x0124
+#define R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_EN 0x0130
+#define R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_EN 0x0134
+#define R_PCH_H_PCR_GPIO_GPP_J_PADCFG_OFFSET 0x400
+#define R_PCH_H_PCR_GPIO_GPP_K_PADCFG_OFFSET 0x4C0
+
+//
+// GPIO Community 5 Private Configuration Registers
+//
+
+// SKX Server PCH
+#define R_PCH_H_PCR_GPIO_GPP_G_PAD_OWN 0x20
+#define R_PCH_H_PCR_GPIO_GPP_H_PAD_OWN 0x2C
+#define R_PCH_H_PCR_GPIO_GPP_L_PAD_OWN 0x38
+#define R_PCH_H_PCR_GPIO_GPP_G_GPI_VWM_EN 0x50
+#define R_PCH_H_PCR_GPIO_GPP_H_GPI_VWM_EN 0x54
+#define R_PCH_H_PCR_GPIO_GPP_L_GPI_VWM_EN 0x58
+#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCK 0x60
+#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCKTX 0x64
+#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCK 0x68
+#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCKTX 0x6C
+#define R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCK 0x70
+#define R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCKTX 0x74
+#define R_PCH_H_PCR_GPIO_GPP_G_HOSTSW_OWN 0x80
+#define R_PCH_H_PCR_GPIO_GPP_H_HOSTSW_OWN 0x84
+#define R_PCH_H_PCR_GPIO_GPP_L_HOSTSW_OWN 0x88
+#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IS 0x0100
+#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IS 0x0104
+#define R_PCH_H_PCR_GPIO_GPP_L_GPI_IS 0x0108
+#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IE 0x0110
+#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IE 0x0114
+#define R_PCH_H_PCR_GPIO_GPP_L_GPI_IE 0x0118
+#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0120
+#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_STS 0x0124
+#define R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_STS 0x0128
+#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0130
+#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_EN 0x0134
+#define R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_EN 0x0138
+#define R_PCH_H_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x400
+#define R_PCH_H_PCR_GPIO_GPP_H_PADCFG_OFFSET 0x4C0
+#define R_PCH_H_PCR_GPIO_GPP_L_PADCFG_OFFSET 0x580
+
+
+
+
+//
+// Define Pad Number
+//
+#define V_GPIO_PAD0 0
+#define V_GPIO_PAD1 1
+#define V_GPIO_PAD2 2
+#define V_GPIO_PAD3 3
+#define V_GPIO_PAD4 4
+#define V_GPIO_PAD5 5
+#define V_GPIO_PAD6 6
+#define V_GPIO_PAD7 7
+#define V_GPIO_PAD8 8
+#define V_GPIO_PAD9 9
+#define V_GPIO_PAD10 10
+#define V_GPIO_PAD11 11
+#define V_GPIO_PAD12 12
+#define V_GPIO_PAD13 13
+#define V_GPIO_PAD14 14
+#define V_GPIO_PAD15 15
+#define V_GPIO_PAD16 16
+#define V_GPIO_PAD17 17
+#define V_GPIO_PAD18 18
+#define V_GPIO_PAD19 19
+#define V_GPIO_PAD20 20
+#define V_GPIO_PAD21 21
+#define V_GPIO_PAD22 22
+#define V_GPIO_PAD23 23
+
+//
+// Host Software Pad Ownership modes
+//
+#define V_GPIO_PCR_HOSTSW_OWN_ACPI 0x00
+#define V_GPIO_PCR_HOSTSW_OWN_GPIO 0x01
+
+//
+// Pad Ownership modes
+//
+#define V_GPIO_PCR_PAD_OWN_HOST 0x00
+#define V_GPIO_PCR_PAD_OWN_CSME 0x01
+#define V_GPIO_PCR_PAD_OWN_ISH 0x02
+
+//
+// Pad Configuration Register DW0
+//
+
+//Pad Reset Config
+#define B_GPIO_PCR_RST_CONF (BIT31 | BIT30)
+#define N_GPIO_PCR_RST_CONF 30
+#define V_GPIO_PCR_RST_CONF_POW_GOOD 0x00
+#define V_GPIO_PCR_RST_CONF_DEEP_RST 0x01
+#define V_GPIO_PCR_RST_CONF_GPIO_RST 0x02
+#define V_GPIO_PCR_RST_CONF_RESUME_RST 0x03 // Only for GPD Group
+
+//RX Pad State Select
+#define B_GPIO_PCR_RX_PAD_STATE BIT29
+#define N_GPIO_PCR_RX_PAD_STATE 29
+#define V_GPIO_PCR_RX_PAD_STATE_RAW 0x00
+#define V_GPIO_PCR_RX_PAD_STATE_INT 0x01
+
+//RX Raw Overrride to 1
+#define B_GPIO_PCR_RX_RAW1 BIT28
+#define N_GPIO_PCR_RX_RAW1 28
+#define V_GPIO_PCR_RX_RAW1_DIS 0x00
+#define V_GPIO_PCR_RX_RAW1_EN 0x01
+
+//RX Level/Edge Configuration
+#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25)
+#define N_GPIO_PCR_RX_LVL_EDG 25
+#define V_GPIO_PCR_RX_LVL_EDG_LVL 0x00
+#define V_GPIO_PCR_RX_LVL_EDG_EDG 0x01
+#define V_GPIO_PCR_RX_LVL_EDG_0 0x02
+#define V_GPIO_PCR_RX_LVL_EDG_RIS_FAL 0x03
+
+//RX Invert
+#define B_GPIO_PCR_RXINV BIT23
+#define N_GPIO_PCR_RXINV 23
+#define V_GPIO_PCR_RXINV_NO 0x00
+#define V_GPIO_PCR_RXINV_YES 0x01
+
+//GPIO Input Route IOxAPIC
+#define B_GPIO_PCR_RX_APIC_ROUTE BIT20
+#define N_GPIO_PCR_RX_APIC_ROUTE 20
+#define V_GPIO_PCR_RX_APIC_ROUTE_DIS 0x00
+#define V_GPIO_PCR_RX_APIC_ROUTE_EN 0x01
+
+//GPIO Input Route SCI
+#define B_GPIO_PCR_RX_SCI_ROUTE BIT19
+#define N_GPIO_PCR_RX_SCI_ROUTE 19
+#define V_GPIO_PCR_RX_SCI_ROUTE_DIS 0x00
+#define V_GPIO_PCR_RX_SCI_ROUTE_EN 0x01
+
+//GPIO Input Route SMI
+#define B_GPIO_PCR_RX_SMI_ROUTE BIT18
+#define N_GPIO_PCR_RX_SMI_ROUTE 18
+#define V_GPIO_PCR_RX_SMI_ROUTE_DIS 0x00
+#define V_GPIO_PCR_RX_SMI_ROUTE_EN 0x01
+
+//GPIO Input Route NMI
+#define B_GPIO_PCR_RX_NMI_ROUTE BIT17
+#define N_GPIO_PCR_RX_NMI_ROUTE 17
+#define V_GPIO_PCR_RX_NMI_ROUTE_DIS 0x00
+#define V_GPIO_PCR_RX_NMI_ROUTE_EN 0x01
+
+//GPIO Pad Mode
+#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_PAD_MODE 10
+#define V_GPIO_PCR_PAD_MODE_GPIO 0
+#define V_GPIO_PCR_PAD_MODE_NAT_1 1
+#define V_GPIO_PCR_PAD_MODE_NAT_2 2
+#define V_GPIO_PCR_PAD_MODE_NAT_3 3
+#define V_GPIO_PCR_PAD_MODE_NAT_4 4 // SPT-H only
+
+//GPIO RX Disable
+#define B_GPIO_PCR_RXDIS BIT9
+#define N_GPIO_PCR_RXDIS 9
+#define V_GPIO_PCR_RXDIS_EN 0x00
+#define V_GPIO_PCR_RXDIS_DIS 0x01
+
+//GPIO TX Disable
+#define B_GPIO_PCR_TXDIS BIT8
+#define N_GPIO_PCR_TXDIS 8
+#define V_GPIO_PCR_TXDIS_EN 0x00
+#define V_GPIO_PCR_TXDIS_DIS 0x01
+
+//GPIO RX State
+#define B_GPIO_PCR_RX_STATE BIT1
+#define N_GPIO_PCR_RX_STATE 1
+#define V_GPIO_PCR_RX_STATE_LOW 0x00
+#define V_GPIO_PCR_RX_STATE_HIGH 0x01
+
+//GPIO TX State
+#define B_GPIO_PCR_TX_STATE BIT0
+#define N_GPIO_PCR_TX_STATE 0
+#define V_GPIO_PCR_TX_STATE_LOW 0x00
+#define V_GPIO_PCR_TX_STATE_HIGH 0x01
+
+//
+// Pad Configuration Register DW1
+//
+
+//Padtol
+#define B_GPIO_PCR_PADTOL BIT25
+#define N_GPIO_PCR_PADTOL 25
+#define V_GPIO_PCR_PADTOL_NONE 0x00
+#define V_GPIO_PCR_PADTOL_CLEAR 0x00
+#define V_GPIO_PCR_PADTOL_SET 0x01
+
+//Termination
+#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_TERM 10
+#define V_GPIO_PCR_TERM_WPD_NONE 0x00
+#define V_GPIO_PCR_TERM_WPD_5K 0x02
+#define V_GPIO_PCR_TERM_WPD_20K 0x04
+#define V_GPIO_PCR_TERM_WPU_NONE 0x08
+#define V_GPIO_PCR_TERM_WPU_1K 0x09
+#define V_GPIO_PCR_TERM_WPU_2K 0x0B
+#define V_GPIO_PCR_TERM_WPU_5K 0x0A
+#define V_GPIO_PCR_TERM_WPU_20K 0x0C
+#define V_GPIO_PCR_TERM_WPU_1K_2K 0x0D
+#define V_GPIO_PCR_TERM_NATIVE 0x0F
+
+//Interrupt number
+#define B_GPIO_PCR_INTSEL 0x7F
+#define N_GPIO_PCR_INTSEL 0
+
+//
+// Ownership
+//
+#define V_GPIO_PCR_OWN_GPIO 0x01
+#define V_GPIO_PCR_OWN_ACPI 0x00
+
+//
+// GPE
+//
+#define V_GPIO_PCR_GPE_EN 0x01
+#define V_GPIO_PCR_GPE_DIS 0x00
+//
+// SMI
+//
+#define V_GPIO_PCR_SMI_EN 0x01
+#define V_GPIO_PCR_SMI_DIS 0x00
+//
+// NMI
+//
+#define V_GPIO_PCR_NMI_EN 0x01
+#define V_GPIO_PCR_NMI_DIS 0x00
+//
+// Reserved: RSVD1
+//
+#define V_PCH_GPIO_RSVD1 0x00
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsHda.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsHda.h
new file mode 100644
index 0000000000..b7c737be42
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsHda.h
@@ -0,0 +1,271 @@
+/** @file
+ Register names for PCH High Definition Audio device.
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_HDA_H_
+#define _PCH_REGS_HDA_H_
+
+//
+// HD-A Controller Registers (D31:F3)
+//
+// PCI Configuration Space Registers
+//
+#define PCI_DEVICE_NUMBER_PCH_HDA 31
+#define PCI_FUNCTION_NUMBER_PCH_HDA 3
+
+#define V_PCH_HDA_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_LP_HDA_DEVICE_ID_0 0x9D70
+#define V_PCH_LP_HDA_DEVICE_ID_1 0x9D71
+#define V_PCH_LP_HDA_DEVICE_ID_2 0x9D72
+#define V_PCH_LP_HDA_DEVICE_ID_3 0x9D73
+#define V_PCH_LP_HDA_DEVICE_ID_4 0x9D74
+#define V_PCH_LP_HDA_DEVICE_ID_5 0x9D75
+#define V_PCH_LP_HDA_DEVICE_ID_6 0x9D76
+#define V_PCH_LP_HDA_DEVICE_ID_7 0x9D77
+#define V_PCH_H_HDA_DEVICE_ID_0 0xA170
+#define V_PCH_H_HDA_DEVICE_ID_1 0xA171
+#define V_PCH_H_HDA_DEVICE_ID_2 0xA172
+#define V_PCH_H_HDA_DEVICE_ID_3 0xA173
+#define V_PCH_H_HDA_DEVICE_ID_4 0xA174
+#define V_PCH_H_HDA_DEVICE_ID_5 0xA175
+#define V_PCH_H_HDA_DEVICE_ID_6 0xA176
+#define V_PCH_H_HDA_DEVICE_ID_7 0xA177
+//
+// LBG SSX (Super SKU) DIDs
+//
+#define V_PCH_LBG_HDA_DEVICE_ID_0 0xA270
+#define V_PCH_LBG_HDA_DEVICE_ID_1 0xA271
+#define V_PCH_LBG_HDA_DEVICE_ID_2 0xA272
+#define V_PCH_LBG_HDA_DEVICE_ID_3 0xA273
+#define V_PCH_LBG_HDA_DEVICE_ID_4 0xA274
+#define V_PCH_LBG_HDA_DEVICE_ID_5 0xA275
+#define V_PCH_LBG_HDA_DEVICE_ID_6 0xA276
+#define V_PCH_LBG_HDA_DEVICE_ID_7 0xA277
+//
+// LBG PRODUCTION (PRQ) DIDs
+//
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_0 0xA1F0
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_1 0xA1F1
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_2 0xA1F2
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_3 0xA1F3
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_4 0xA1F4
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_5 0xA1F5
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_6 0xA1F6
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_7 0xA1F7
+
+
+#define R_PCH_HDA_PI 0x09
+#define V_PCH_HDA_PI_ADSP_UAA 0x80
+#define R_PCH_HDA_SCC 0x0A
+#define V_PCH_HDA_SCC_ADSP 0x01
+#define R_PCH_HDA_HDALBA 0x10
+#define B_PCH_HDA_HDALBA_LBA 0xFFFFC000
+#define V_PCH_HDA_HDBAR_SIZE (1 << 14)
+#define R_PCH_HDA_HDAUBA 0x14
+#define B_PCH_HDA_HDAUBA_UBA 0xFFFFFFFF
+#define R_PCH_HDA_CGCTL 0x48
+#define B_PCH_HDA_CGCTL_MEMDCGE BIT0
+#define B_PCH_HDA_CGCTL_ADSPDCGE BIT1
+#define B_PCH_HDA_CGCTL_GPDMADCGE BIT2
+#define B_PCH_HDA_CGCTL_HDALDCGE BIT3
+#define B_PCH_HDA_CGCTL_MISCBDCGE BIT6
+#define B_PCH_HDA_CGCTL_ODMABDCGE BIT4
+#define B_PCH_HDA_CGCTL_IDMABDCGE BIT5
+#define B_PCH_HDA_CGCTL_IOSFBDCGE BIT7
+#define B_PCH_HDA_CGCTL_IOSFSDCGE BIT8
+#define B_PCH_HDA_CGCTL_DMICDCGE BIT10
+#define B_PCH_HDA_CGCTL_I2SDCGE BIT11
+#define B_PCH_HDA_CGCTL_APTCGE BIT16
+#define B_PCH_HDA_CGCTL_XOTCGE BIT17
+#define B_PCH_HDA_CGCTL_SROTCGE BIT18
+#define B_PCH_HDA_CGCTL_IOSFBTCGE BIT19
+#define B_PCH_HDA_CGCTL_IOSFSTCGE BIT20
+#define B_PCH_HDA_CGCTL_FROTCGE BIT21
+#define B_PCH_HDA_CGCTL_APLLSE BIT31
+#define V_PCH_HDA_CGCTL_CGEN (B_PCH_HDA_CGCTL_MEMDCGE | \
+ B_PCH_HDA_CGCTL_ADSPDCGE | \
+ B_PCH_HDA_CGCTL_GPDMADCGE | \
+ B_PCH_HDA_CGCTL_HDALDCGE | \
+ B_PCH_HDA_CGCTL_MISCBDCGE | \
+ B_PCH_HDA_CGCTL_ODMABDCGE | \
+ B_PCH_HDA_CGCTL_IDMABDCGE | \
+ B_PCH_HDA_CGCTL_IOSFBDCGE | \
+ B_PCH_HDA_CGCTL_IOSFSDCGE | \
+ B_PCH_HDA_CGCTL_DMICDCGE | \
+ B_PCH_HDA_CGCTL_I2SDCGE | \
+ B_PCH_HDA_CGCTL_APTCGE | \
+ B_PCH_HDA_CGCTL_XOTCGE | \
+ B_PCH_HDA_CGCTL_SROTCGE | \
+ B_PCH_HDA_CGCTL_IOSFBTCGE | \
+ B_PCH_HDA_CGCTL_IOSFSTCGE | \
+ B_PCH_HDA_CGCTL_FROTCGE | \
+ B_PCH_HDA_CGCTL_APLLSE )
+#define R_PCH_HDA_CGCTL 0x48
+#define B_PCH_HDA_CGCTL_MISCBDCGE BIT6
+#define R_PCH_HDA_PC 0x52
+#define V_PCH_HDA_PC_PMES 0x18
+#define N_PCH_HDA_PC_PMES 11
+#define R_PCH_HDA_PCS 0x54
+#define B_PCH_HDA_PCS_PMES BIT15
+#define B_PCH_HDA_PCS_PMEE BIT8
+#define B_PCH_HDA_PCS_PS (BIT1 | BIT0)
+#define R_PCH_HDA_MMC 0x62
+#define B_PCH_HDA_MMC_ME BIT0
+#define R_PCH_HDA_DEVC 0x78
+#define B_PCH_HDA_DEVC_NSNPEN BIT11
+#define R_PCH_HDA_SEM1 0xC0
+#define B_PCH_HDA_SEM1_LFLCS BIT24
+#define B_PCH_HDA_SEM1_BLKC3DIS BIT17
+#define B_PCH_HDA_SEM1_TMODE BIT12
+#define B_PCH_HDA_SEM1_FIFORDYSEL (BIT10 | BIT9)
+#define R_PCH_HDA_SEM2 0xC4
+#define B_PCH_HDA_SEM2_BSMT (BIT27 | BIT26)
+#define V_PCH_HDA_SEM2_BSMT 0x1
+#define N_PCH_HDA_SEM2_BSMT 26
+#define B_PCH_HDA_SEM2_VC0PSNR BIT24
+#define R_PCH_HDA_SEM3L 0xC8
+#define B_PCH_HDA_SEM3L_ISL1EXT2 (BIT21 | BIT20)
+#define V_PCH_HDA_SEM3L_ISL1EXT2 0x2
+#define N_PCH_HDA_SEM3L_ISL1EXT2 20
+#define R_PCH_HDA_SEM4L 0xD0
+#define B_PCH_HDA_SEM4L_OSL1EXT2 (BIT21 | BIT20)
+#define V_PCH_HDA_SEM4L_OSL1EXT2 0x3
+#define N_PCH_HDA_SEM4L_OSL1EXT2 20
+
+//
+// Memory Space Registers
+//
+//
+// Resides in 'HD Audio Global Registers' (0000h)
+//
+#define R_PCH_HDABA_GCAP 0x00
+#define R_PCH_HDABA_GCTL 0x08
+#define B_PCH_HDABA_GCTL_CRST BIT0
+
+#define R_PCH_HDABA_OUTPAY 0x04
+#define R_PCH_HDABA_INPAY 0x06
+#define V_PCH_HDABA_INPAY_DEFAULT 0x1C
+
+#define R_PCH_HDABA_WAKEEN 0x0C
+#define B_PCH_HDABA_WAKEEN_SDI_3 BIT3
+#define B_PCH_HDABA_WAKEEN_SDI_2 BIT2
+#define B_PCH_HDABA_WAKEEN_SDI_1 BIT1
+#define B_PCH_HDABA_WAKEEN_SDI_0 BIT0
+
+#define R_PCH_HDABA_WAKESTS 0x0E
+#define B_PCH_HDABA_WAKESTS_SDIN3 BIT3
+#define B_PCH_HDABA_WAKESTS_SDIN2 BIT2
+#define B_PCH_HDABA_WAKESTS_SDIN1 BIT1
+#define B_PCH_HDABA_WAKESTS_SDIN0 BIT0
+
+//
+// Resides in 'HD Audio Controller Registers' (0030h)
+//
+#define R_PCH_HDABA_IC 0x60
+#define R_PCH_HDABA_IR 0x64
+#define R_PCH_HDABA_ICS 0x68
+#define B_PCH_HDABA_ICS_IRV BIT1
+#define B_PCH_HDABA_ICS_ICB BIT0
+
+//
+// Resides in 'HD Audio Processing Pipe Capability Structure' (0800h)
+//
+#define R_PCH_HDABA_PPC 0x0800 // Processing Pipe Capability Structure (Memory Space, offset 0800h)
+#define R_PCH_HDABA_PPCTL (R_PCH_HDABA_PPC + 0x04)
+#define B_PCH_HDABA_PPCTL_GPROCEN BIT30
+
+//
+// Resides in 'HD Audio Multiple Links Capability Structure' (0C00h)
+//
+#define V_PCH_HDA_HDALINK_INDEX 0
+#define V_PCH_HDA_IDISPLINK_INDEX 1
+
+#define R_PCH_HDABA_MLC 0x0C00 // Multiple Links Capability Structure (Memory Space, offset 0C00h)
+#define R_PCH_HDABA_LCTLX(x) (R_PCH_HDABA_MLC + (0x40 + (0x40 * (x)) + 0x04)) // x - Link index: 0 - HDA Link, 1 - iDisp Link
+#define B_PCH_HDABA_LCTLX_CPA BIT23
+#define B_PCH_HDABA_LCTLX_SPA BIT16
+#define N_PCH_HDABA_LCTLX_SCF 0
+#define V_PCH_HDABA_LCTLX_SCF_6MHZ 0x0
+#define V_PCH_HDABA_LCTLX_SCF_12MHZ 0x1
+#define V_PCH_HDABA_LCTLX_SCF_24MHZ 0x2
+#define V_PCH_HDABA_LCTLX_SCF_48MHZ 0x3
+#define V_PCH_HDABA_LCTLX_SCF_96MHZ 0x4
+
+//
+// Resides in 'HD Audio Vendor Specific Registers' (1000h)
+//
+#define R_PCH_HDABA_LTRC 0x1048
+#define V_PCH_HDABA_LTRC_GB 0x29
+#define N_PCH_HDABA_LTRC_GB 0
+#define R_PCH_HDABA_PCE 0x104B
+#define B_PCH_HDABA_PCE_D3HE BIT2
+
+//
+// Private Configuration Space Registers
+//
+//
+// Resides in IOSF & Fabric Configuration Registers (000h)
+//
+#define R_PCH_PCR_HDA_TTCCFG 0xE4
+#define B_PCH_PCR_HDA_TTCCFG_HCDT BIT1
+
+//
+// Resides in PCI & Codec Configuration Registers (500h)
+//
+#define R_PCH_PCR_HDA_PCICDCCFG 0x500 // PCI & Codec Configuration Registers (PCR, offset 500h)
+#define B_PCH_PCR_HDA_PCICDCCFG_ACPIIN 0x0000FF00
+#define N_PCH_PCR_HDA_PCICDCCFG_ACPIIN 8
+#define R_PCH_PCR_HDA_FNCFG (R_PCH_PCR_HDA_PCICDCCFG + 0x30)
+#define B_PCH_PCR_HDA_FNCFG_PGD BIT5
+#define B_PCH_PCR_HDA_FNCFG_BCLD BIT4
+#define B_PCH_PCR_HDA_FNCFG_CGD BIT3
+#define B_PCH_PCR_HDA_FNCFG_ADSPD BIT2
+
+#define B_PCH_PCR_HDA_FNCFG_HDASPCID BIT1
+
+#define B_PCH_PCR_HDA_FNCFG_HDASD BIT0
+#define R_PCH_PCR_HDA_CDCCFG (R_PCH_PCR_HDA_PCICDCCFG + 0x34)
+#define B_PCH_PCR_HDA_CDCCFG_DIS_SDIN2 BIT2
+
+//
+// Resides in Power Management & EBB Configuration Registers (600h)
+//
+#define R_PCH_PCR_HDA_PWRMANCFG 0x600 // Power Management & EBB Configuration Registers (PCR, offset 600h)
+#define R_PCH_PCR_HDA_APLLP0 (R_PCH_PCR_HDA_PWRMANCFG + 0x10)
+#define V_PCH_PCR_HDA_APLLP0 0xFC1E0000
+#define R_PCH_PCR_HDA_APLLP1 (R_PCH_PCR_HDA_PWRMANCFG + 0x14)
+#define V_PCH_PCR_HDA_APLLP1 0x00003F00
+#define R_PCH_PCR_HDA_APLLP2 (R_PCH_PCR_HDA_PWRMANCFG + 0x18)
+#define V_PCH_PCR_HDA_APLLP2 0x0000011D
+#define R_PCH_PCR_HDA_IOBCTL (R_PCH_PCR_HDA_PWRMANCFG + 0x1C)
+#define B_PCH_PCR_HDA_IOBCTL_OSEL (BIT9 | BIT8)
+#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK 0
+#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK_I2S 1
+#define V_PCH_PCR_HDA_IOBCTL_OSEL_I2S 3
+#define N_PCH_PCR_HDA_IOBCTL_OSEL 8
+#define B_PCH_PCR_HDA_IOBCTL_VSEL BIT1
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsHsio.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsHsio.h
new file mode 100644
index 0000000000..52a27fccf5
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsHsio.h
@@ -0,0 +1,190 @@
+/** @file
+ Register definition for HSIO
+
+ @copyright
+ Copyright 2014 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_HSIO_H_
+#define _PCH_REGS_HSIO_H_
+
+#define B_HSIO_PCR_ACCESS_TYPE (BIT15 | BIT14)
+#define N_HSIO_PCR_ACCESS_TYPE 14
+#define V_HSIO_PCR_ACCESS_TYPE_BDCAST (BIT15 | BIT14)
+#define V_HSIO_PCR_ACCESS_TYPE_MULCAST BIT15
+#define B_HSIO_PCR_LANE_GROUP_NO (BIT13 | BIT12 | BIT11 | BIT10 | BIT9)
+#define B_HSIO_PCR_FUNCTION_NO (BIT8 | BIT7)
+#define N_HSIO_PCR_FUNCTION_NO 7
+#define B_HSIO_PCR_REG_OFFSET (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
+
+#define V_HSIO_PCR_ACCESS_TYPE_BCAST 0x03
+#define V_HSIO_PCR_ACCESS_TYPE_MCAST 0x02
+#define V_HSIO_PCR_ACCESS_TYPE_UCAST 0x00
+
+#define V_HSIO_PCR_LANE_GROUP_NO_CMN_LANE 0x00
+
+#define V_HSIO_PCR_FUNCTION_NO_PCS 0x00
+#define V_HSIO_PCR_FUNCTION_NO_TX 0x01
+#define V_HSIO_PCR_FUNCTION_NO_RX 0x02
+
+#define V_HSIO_PCR_FUNCTION_NO_CMNDIG 0x00
+#define V_HSIO_PCR_FUNCTION_NO_CMNANA 0x01
+#define V_HSIO_PCR_FUNCTION_NO_PLL 0x02
+
+#define R_HSIO_PCR_PCS_DWORD4 0x10
+
+#define R_HSIO_PCR_PCS_DWORD8 0x20
+#define B_HSIO_PCR_PCS_DWORD8_CRI_RXEB_PTR_INIT_4_0 0x1F000000
+#define B_HSIO_PCR_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 0x001F0000
+#define N_HSIO_PCR_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 16
+#define B_HSIO_PCR_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 0x00001F00
+#define N_HSIO_PCR_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 8
+
+#define R_HSIO_PCR_PCS_DWORD9 0x24
+#define B_HSIO_PCR_PCS_DWORD9_REG_ENABLE_PWR_GATING BIT29
+
+#define R_HSIO_PCR_RX_DWORD8 0x120
+#define B_HSIO_PCR_RX_DWORD8_ICFGDFETAP3_EN BIT10
+
+#define R_HSIO_PCR_RX_DWORD9 0x124
+#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP4_OVERRIDE_EN BIT24
+#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP3_OVERRIDE_EN BIT26
+#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP2_OVERRIDE_EN BIT28
+#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP1_OVERRIDE_EN BIT30
+
+#define R_HSIO_PCR_RX_DWORD12 0x130
+#define B_HSIO_PCR_RX_DWORD12_O_CFGEWMARGINSEL BIT14
+
+#define R_HSIO_PCR_RX_DWORD20 0x150
+#define B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24)
+#define N_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 24
+
+#define R_HSIO_PCR_RX_DWORD21 0x154
+#define B_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
+#define N_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 8
+#define B_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
+#define N_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 0
+
+#define R_HSIO_PCR_RX_DWORD23 0x15C
+#define B_HSIO_PCR_RX_DWORD23_ICFGVGABLWTAP_OVERRIDE_EN BIT2
+#define B_HSIO_PCR_RX_DWORD23_CFGVGATAP_ADAPT_OVERRIDE_EN BIT4
+
+#define R_HSIO_PCR_RX_DWORD25 0x164
+#define B_HSIO_PCR_RX_DWORD25_RX_TAP_CFG_CTRL BIT3
+#define B_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 0x1F0000
+#define N_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 16
+
+#define R_HSIO_PCR_RX_DWORD26 0x168
+#define B_HSIO_PCR_RX_DWORD26_SATA_EQ_DIS BIT16
+
+#define R_HSIO_PCR_RX_DWORD34 0x188
+#define B_HSIO_PCR_RX_DWORD34_MM_PH_OFC_SCALE_2_0 (BIT14 | BIT13 | BIT12)
+#define N_HSIO_PCR_RX_DWORD34_MM_PH_OFC_SCALE_2_0 12
+
+#define R_HSIO_PCR_RX_DWORD44 0x1B0
+#define B_HSIO_PCR_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 0xFF0000
+#define N_HSIO_PCR_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 16
+
+#define R_HSIO_PCR_RX_DWORD39 0x19C
+#define B_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0 0x7C0000
+#define N_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0 18
+
+#define R_HSIO_PCR_RX_DWORD40 0x1A0
+#define B_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP 0xFF000000
+#define N_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP 24
+
+#define R_HSIO_PCR_RX_DWORD41 0x1A4
+#define B_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS 0xFFFFFF
+#define N_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS 0
+
+#define R_HSIO_PCR_RX_DWORD7 0x11C
+#define B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL 0xF8000000
+#define N_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL 27
+
+
+#define R_HSIO_PCR_RX_DWORD56 0x1E0
+#define B_HSIO_PCR_RX_DWORD56_ICFGPIDACCFGVALID BIT16
+
+#define R_HSIO_PCR_RX_DWORD57 0x1E4
+#define B_HSIO_PCR_RX_DWORD57_JIM_COURSE BIT30
+#define B_HSIO_PCR_RX_DWORD57_JIM_ENABLE BIT29
+#define B_HSIO_PCR_RX_DWORD57_JIMMODE BIT28
+#define B_HSIO_PCR_RX_DWORD57_JIMNUMCYCLES_3_0 0x0F000000
+#define N_HSIO_PCR_RX_DWORD57_JIMNUMCYCLES_3_0 24
+#define B_HSIO_PCR_RX_DWORD57_ICFGMARGINEN BIT0
+
+#define R_HSIO_PCR_RX_DWORD59 0x1EC
+#define R_HSIO_PCR_RX_DWORD60 0x1F0
+
+#define R_HSIO_PCR_TX_DWORD5 0x94
+#define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
+#define N_HSIO_PCR_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 16
+#define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
+#define N_HSIO_PCR_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 8
+
+#define R_HSIO_PCR_TX_DWORD6 0x98
+#define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
+#define N_HSIO_PCR_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 16
+#define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
+#define N_HSIO_PCR_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 8
+#define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN1DEEMPH6P0_5_0 (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
+
+#define R_HSIO_PCR_TX_DWORD8 0xA0
+#define B_HSIO_PCR_TX_DWORD8_ORATE10MARGIN_5_0 (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24)
+#define N_HSIO_PCR_TX_DWORD8_ORATE10MARGIN_5_0 24
+#define B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
+#define N_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0 16
+#define B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
+#define N_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0 8
+
+#define R_HSIO_PCR_TX_DWORD19 0xCC
+
+#define R_PCH_LP_HSIO_LANE10_PCS_DWORD8 0x020
+#define R_PCH_LP_HSIO_LANE11_PCS_DWORD8 0x220
+#define R_PCH_LP_HSIO_LANE14_PCS_DWORD8 0x820
+#define R_PCH_LP_HSIO_LANE15_PCS_DWORD8 0xA20
+#define R_PCH_H_HSIO_LANE18_PCS_DWORD8 0x820
+#define R_PCH_H_HSIO_LANE19_PCS_DWORD8 0xA20
+#define R_PCH_H_HSIO_LANE22_PCS_DWORD8 0x020
+#define R_PCH_H_HSIO_LANE23_PCS_DWORD8 0x220
+#define R_PCH_H_HSIO_LANE24_PCS_DWORD8 0x420
+#define R_PCH_H_HSIO_LANE25_PCS_DWORD8 0x620
+#define R_PCH_H_HSIO_LANE26_PCS_DWORD8 0x820
+#define R_PCH_H_HSIO_LANE27_PCS_DWORD8 0xA20
+#define R_PCH_H_HSIO_LANE28_PCS_DWORD8 0xC20
+#define R_PCH_H_HSIO_LANE29_PCS_DWORD8 0xE20
+
+#define R_HSIO_PCR_CLANE0_CMN_ANA_DWORD2 0x8088
+#define B_HSIO_PCR_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_PLLEN_H_OVRDEN BIT5
+#define B_HSIO_PCR_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_FULLCALRESET_L_OVERDEN BIT3
+
+#define R_HSIO_PCR_PLL_SSC_DWORD2 0x8108
+#define B_HSIO_PCR_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
+#define N_HSIO_PCR_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 16
+#define B_HSIO_PCR_PLL_SSC_DWORD2_SSCSEN BIT10
+#define N_HSIO_PCR_PLL_SSC_DWORD2_SSCSEN 10
+
+#define R_HSIO_PCR_PLL_SSC_DWORD3 0x810C
+#define B_HSIO_PCR_PLL_SSC_DWORD3_SSC_PROPAGATE BIT0
+
+#define R_PCH_PCR_MODPHY0_COM0_CMN_DIG_DWORD12 0x8030
+#define B_PCH_PCR_MODPHY0_COM0_CMN_DIG_DWORD12_O_CFG_PWR_GATING_CTRL BIT0
+
+//
+// xHCI SSIC Private Configuration Register, but with opcode 4/5 for read/write access
+//
+#define R_PCH_PCR_MMP0_LANE_0_OFFSET 0x0
+#define R_PCH_PCR_MMP0_LANE_1_OFFSET 0x2000
+#define R_PCH_PCR_MMP0_IMPREG21 0x1050
+#define R_PCH_PCR_MMP0_IMPREG22 0x1054
+#define R_PCH_PCR_MMP0_IMPREG23 0x1058
+#define R_PCH_PCR_MMP0_IMPREG24 0x105C
+#define R_PCH_PCR_MMP0_IMPREG25 0x1060
+#define R_PCH_PCR_MMP0_CMNREG4 0xF00C
+#define R_PCH_PCR_MMP0_CMNREG15 0xF038
+#define R_PCH_PCR_MMP0_CMNREG16 0xF03C
+
+#endif //_PCH_REGS_HSIO_H_
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsItss.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsItss.h
new file mode 100644
index 0000000000..fecfe22c5c
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsItss.h
@@ -0,0 +1,90 @@
+/** @file
+ Register names for ITSS
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 2014 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_ITSS_H_
+#define _PCH_REGS_ITSS_H_
+
+//
+// ITSS PCRs (PID:ITSS)
+//
+#define R_ITSS_PCR_PIRQA_ROUT 0x3100 ///< PIRQA Routing Control register
+#define R_ITSS_PCR_PIRQB_ROUT 0x3101 ///< PIRQB Routing Control register
+#define R_ITSS_PCR_PIRQC_ROUT 0x3102 ///< PIRQC Routing Control register
+#define R_ITSS_PCR_PIRQD_ROUT 0x3103 ///< PIRQD Routing Control register
+#define R_ITSS_PCR_PIRQE_ROUT 0x3104 ///< PIRQE Routing Control register
+#define R_ITSS_PCR_PIRQF_ROUT 0x3105 ///< PIRQF Routing Control register
+#define R_ITSS_PCR_PIRQG_ROUT 0x3106 ///< PIRQG Routing Control register
+#define R_ITSS_PCR_PIRQH_ROUT 0x3107 ///< PIRQH Routing Control register
+#define B_ITSS_PCR_PIRQX_ROUT_REN 0x80 ///< Interrupt Routing Enable
+#define B_ITSS_PCR_PIRQX_ROUT_IR 0x0F ///< IRQ Routng
+#define V_ITSS_PCR_PIRQX_ROUT_IRQ_3 0x03 ///< Route PIRQx to IRQ3
+#define V_ITSS_PCR_PIRQX_ROUT_IRQ_4 0x04 ///< Route PIRQx to IRQ4
+#define V_ITSS_PCR_PIRQX_ROUT_IRQ_5 0x05 ///< Route PIRQx to IRQ5
+#define V_ITSS_PCR_PIRQX_ROUT_IRQ_6 0x06 ///< Route PIRQx to IRQ6
+#define V_ITSS_PCR_PIRQX_ROUT_IRQ_7 0x07 ///< Route PIRQx to IRQ7
+#define V_ITSS_PCR_PIRQX_ROUT_IRQ_9 0x09 ///< Route PIRQx to IRQ9
+#define V_ITSS_PCR_PIRQX_ROUT_IRQ_10 0x0A ///< Route PIRQx to IRQ10
+#define V_ITSS_PCR_PIRQX_ROUT_IRQ_11 0x0B ///< Route PIRQx to IRQ11
+#define V_ITSS_PCR_PIRQX_ROUT_IRQ_12 0x0C ///< Route PIRQx to IRQ12
+#define V_ITSS_PCR_PIRQX_ROUT_IRQ_14 0x0E ///< Route PIRQx to IRQ14
+#define V_ITSS_PCR_PIRQX_ROUT_IRQ_15 0x0F ///< Route PIRQx to IRQ15
+
+#define R_ITSS_PCR_PIR0 0x3140 ///< PCI Interrupt Route 0
+#define R_ITSS_PCR_PIR1 0x3142 ///< PCI Interrupt Route 1
+#define R_ITSS_PCR_PIR2 0x3144 ///< PCI Interrupt Route 2
+#define R_ITSS_PCR_PIR3 0x3146 ///< PCI Interrupt Route 3
+#define R_ITSS_PCR_PIR4 0x3148 ///< PCI Interrupt Route 4
+#define R_ITSS_PCR_PIR5 0x314A ///< PCI Interrupt Route 5
+#define R_ITSS_PCR_PIR6 0x314C ///< PCI Interrupt Route 6
+#define R_ITSS_PCR_PIR7 0x314E ///< PCI Interrupt Route 7
+#define R_ITSS_PCR_PIR8 0x3150 ///< PCI Interrupt Route 8
+#define R_ITSS_PCR_PIR9 0x3152 ///< PCI Interrupt Route 9
+#define R_ITSS_PCR_PIR10 0x3154 ///< PCI Interrupt Route 10
+#define R_ITSS_PCR_PIR11 0x3156 ///< PCI Interrupt Route 11
+#define R_ITSS_PCR_PIR12 0x3158 ///< PCI Interrupt Route 12
+
+#define R_ITSS_PCR_GIC 0x31FC ///< General Interrupt Control
+#define B_ITSS_PCR_GIC_MAX_IRQ_24 BIT9 ///< Max IRQ entry size, 1 = 24 entry size, 0 = 120 entry size
+#define B_ITSS_PCR_GIC_SERM BIT8 ///< Server Error Reporting Mode
+#define B_ITSS_PCR_GIC_AME BIT17 ///< Alternate Access Mode Enable
+#define B_ITSS_PCR_GIC_SPS BIT16 ///< Shutdown Policy Select
+#define N_ITSS_PCR_GIC_SPS 16 ///< Shutdown Policy Select bit shift
+#define R_ITSS_PCR_IPC0 0x3200 ///< Interrupt Polarity Control 0
+#define R_ITSS_PCR_IPC1 0x3204 ///< Interrupt Polarity Control 1
+#define R_ITSS_PCR_IPC2 0x3208 ///< Interrupt Polarity Control 2
+#define R_ITSS_PCR_IPC3 0x320C ///< Interrupt Polarity Control 3
+#define R_ITSS_PCR_ITSSPRC 0x3300 ///< ITSS Power Reduction Control
+#define B_ITSS_PCR_ITSSPRC_PGCBDCGE BIT4 ///< PGCB Dynamic Clock Gating Enable
+#define B_ITSS_PCR_ITSSPRC_HPETDCGE BIT3 ///< HPET Dynamic Clock Gating Enable
+#define B_ITSS_PCR_ITSSPRC_8254CGE BIT2 ///< 8254 Static Clock Gating Enable
+#define B_ITSS_PCR_ITSSPRC_IOSFICGE BIT1 ///< IOSF-Sideband Interface Clock Gating Enable
+#define B_ITSS_PCR_ITSSPRC_ITSSCGE BIT0 ///< ITSS Clock Gate Enable
+
+#define R_ITSS_PCR_MMC 0x3334 ///< Master Message Control
+#define B_ITSS_PCR_MMC_MSTRMSG_EN BIT0 ///< Master Message Enable
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsLan.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsLan.h
new file mode 100644
index 0000000000..d298e2ad66
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsLan.h
@@ -0,0 +1,156 @@
+/** @file
+ Register names for PCH LAN device
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_LAN_H_
+#define _PCH_REGS_LAN_H_
+
+//
+// Gigabit LAN Controller configuration registers (D31:F6)
+//
+#define PCI_DEVICE_NUMBER_PCH_LAN 31
+#define PCI_FUNCTION_NUMBER_PCH_LAN 6
+
+#define V_PCH_LAN_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_LAN_DEVICE_ID 0x156F
+
+//
+// LBG Production Gigabit LAN Controller Device ID
+//
+#define V_PCH_LBG_PROD_LAN_DEVICE_ID 0xA1A5
+//
+// LBG SSX (Super SKU) Gigabit LAN Controller Device ID
+//
+#define V_PCH_LBG_LAN_DEVICE_ID 0xA225
+
+#define V_PCH_LP_LAN_DEVICE_ID 0x156F
+#define R_PCH_LAN_MBARA 0x10
+#define B_PCH_LAN_MBARA_BA 0xFFFE0000
+#define N_PCH_LAN_MBARA_ALIGN 17
+#define R_PCH_LAN_LTR_CAP 0xA8
+#define R_PCH_LAN_CLIST1 0xC8
+#define B_PCH_LAN_CLIST1_NEXT 0xFF00
+#define B_PCH_LAN_CLIST1_CID 0x00FF
+#define R_PCH_LAN_PMC 0xCA
+#define B_PCH_LAN_PMC_PMES 0xF800
+#define B_PCH_LAN_PMC_D2S BIT10
+#define B_PCH_LAN_PMC_D1S BIT9
+#define B_PCH_LAN_PMC_AC (BIT8 | BIT7 | BIT6)
+#define B_PCH_LAN_PMC_DSI BIT5
+#define B_PCH_LAN_PMC_PMEC BIT3
+#define B_PCH_LAN_PMC_VS (BIT2 | BIT1 | BIT0)
+#define R_PCH_LAN_PMCS 0xCC
+#define B_PCH_LAN_PMCS_PMES BIT15
+#define B_PCH_LAN_PMCS_DSC (BIT14 | BIT13)
+#define B_PCH_LAN_PMCS_DSL 0x1E00
+#define V_PCH_LAN_PMCS_DSL0 0x0000
+#define V_PCH_LAN_PMCS_DSL3 0x0600
+#define V_PCH_LAN_PMCS_DSL4 0x0800
+#define V_PCH_LAN_PMCS_DSL7 0x0E00
+#define V_PCH_LAN_PMCS_DSL8 0x1000
+#define B_PCH_LAN_PMCS_PMEE BIT8
+#define B_PCH_LAN_PMCS_PS (BIT1 | BIT0)
+#define V_PCH_LAN_PMCS_PS0 0x00
+#define V_PCH_LAN_PMCS_PS3 0x03
+#define R_PCH_LAN_DR 0xCF
+#define B_PCH_LAN_DR 0xFF
+#define R_PCH_LAN_CLIST2 0xD0
+#define B_PCH_LAN_CLIST2_NEXT 0xFF00
+#define B_PCH_LAN_CLIST2_CID 0x00FF
+#define R_PCH_LAN_MCTL 0xD2
+#define B_PCH_LAN_MCTL_CID BIT7
+#define B_PCH_LAN_MCTL_MME (BIT6 | BIT5 | BIT4)
+#define B_PCH_LAN_MCTL_MMC (BIT3 | BIT2 | BIT1)
+#define B_PCH_LAN_MCTL_MSIE BIT0
+#define R_PCH_LAN_MADDL 0xD4
+#define B_PCH_LAN_MADDL 0xFFFFFFFF
+#define R_PCH_LAN_MADDH 0xD8
+#define B_PCH_LAN_MADDH 0xFFFFFFFF
+#define R_PCH_LAN_MDAT 0xDC
+#define B_PCH_LAN_MDAT 0xFFFFFFFF
+#define R_PCH_LAN_FLRCAP 0xE0
+#define B_PCH_LAN_FLRCAP_NEXT 0xFF00
+#define B_PCH_LAN_FLRCAP_CID 0x00FF
+#define V_PCH_LAN_FLRCAP_CID_SSEL0 0x13
+#define V_PCH_LAN_FLRCAP_CID_SSEL1 0x09
+#define R_PCH_LAN_FLRCLV 0xE2
+#define B_PCH_LAN_FLRCLV_FLRC_SSEL0 BIT9
+#define B_PCH_LAN_FLRCLV_TXP_SSEL0 BIT8
+#define B_PCH_LAN_FLRCLV_VSCID_SSEL1 0xF000
+#define B_PCH_LAN_FLRCLV_CAPVER_SSEL1 0x0F00
+#define B_PCH_LAN_FLRCLV_CAPLNG 0x00FF
+#define R_PCH_LAN_DEVCTRL 0xE4
+#define B_PCH_LAN_DEVCTRL BIT0
+#define R_PCH_LAN_CPCE 0x80
+#define B_PCH_LAN_CPCE_HAE BIT5
+#define B_PCH_LAN_CPCE_SE BIT3
+#define B_PCH_LAN_CPCE_D3HE BIT2
+#define B_PCH_LAN_CPCE_I3E BIT1
+#define B_PCH_LAN_CPCE_PCMCRE BIT0
+#define R_PCH_LAN_CD0I3 0x84
+#define B_PCH_LAN_CD0I3_RR BIT3
+#define B_PCH_LAN_CD0I3_D0I3 BIT2
+#define R_PCH_LAN_CLCTL 0x94
+#define R_PCH_LAN_LANDISCTRL 0xA0
+#define B_PCH_LAN_LANDISCTRL_DISABLE BIT0
+#define R_PCH_LAN_LOCKLANDIS 0xA4
+#define B_PCH_LAN_LOCKLANDIS_LOCK BIT0
+//
+// Gigabit LAN Capabilities and Status Registers (Memory space)
+//
+#define R_PCH_LAN_CSR_CTRL 0
+#define B_PCH_LAN_CSR_CTRL_MEHE BIT19
+#define R_PCH_LAN_CSR_STRAP 0x000C
+#define B_PCH_LAN_CSR_STRAP_NVM_VALID BIT11
+#define R_PCH_LAN_CSR_FEXTNVM6 0x0010
+#define R_PCH_LAN_CSR_CTRL_EXT 0x0018
+#define B_PCH_LAN_CSR_CTRL_EXT_CGEN BIT19
+#define B_PCH_LAN_CSR_CTRL_EXT_FORCE_SMB BIT11
+#define R_PCH_LAN_CSR_MDIC 0x0020
+#define B_PCH_LAN_CSR_MDIC_RB BIT28
+#define B_PCH_LAN_CSR_MDIC_DATA 0xFFFF
+#define R_PCH_LAN_CSR_FEXT 0x002C
+#define B_PCH_LAN_CSR_FEXT_WOL BIT30
+#define B_PCH_LAN_CSR_FEXT_WOL_VALID BIT31
+#define R_PCH_LAN_CSR_EXTCNF_CTRL 0x0F00
+#define B_PCH_LAN_CSR_EXTCNF_CTRL_SWFLAG BIT5
+#define B_PCH_LAN_CSR_EXTCNF_K1OFF_EN BIT8
+#define R_PCH_LAN_CSR_PHY_CTRL 0x0F10
+#define B_PCH_LAN_CSR_PHY_CTRL_GGD BIT6
+#define B_PCH_LAN_CSR_PHY_CTRL_GBEDIS BIT3
+#define B_PCH_LAN_CSR_PHY_CTRL_LPLUND BIT2
+#define B_PCH_LAN_CSR_PHY_CTRL_LPLUD BIT1
+#define R_PCH_LAN_CSR_F18 0x0F18
+#define B_PCH_LAN_CSR_F18_K1OFF_EN BIT31
+#define R_PCH_LAN_CSR_PBECCSTS 0x100C
+#define B_PCH_LAN_CSR_PBECCSTS_ECC_EN BIT16
+#define R_PCH_LAN_CSR_RAL 0x5400
+#define R_PCH_LAN_CSR_RAH 0x5404
+#define B_PCH_LAN_CSR_RAH_RAH 0x0000FFFF
+#define R_PCH_LAN_CSR_WUC 0x5800
+#define B_PCH_LAN_CSR_WUC_APME BIT0
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsLpc.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsLpc.h
new file mode 100644
index 0000000000..356cc05f96
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsLpc.h
@@ -0,0 +1,490 @@
+/** @file
+ Register names for PCH LPC/eSPI device
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_LPC_H_
+#define _PCH_REGS_LPC_H_
+
+#include <PchLimits.h>
+//
+// PCI to LPC Bridge Registers (D31:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_LPC 31
+#define PCI_FUNCTION_NUMBER_PCH_LPC 0
+
+typedef enum {
+ PchHA0 = 0x00,
+ PchHB0 = 0x01,
+ PchHC0,
+ PchHD0,
+ PchHD1,
+#ifdef SIMICS_FLAG
+ PchLpA0 = 0x20,
+#endif
+ PchLpB0 = 0x23,
+ PchLpB1,
+ PchLpC0,
+ PchLpC1,
+ LbgA0 = LBG_A0,
+ LbgB0,
+ LbgB1,
+ LbgB2,
+ LbgB3,
+ LbgS0,
+ LbgS1,
+ LbgS2,
+ PchMiniA0,
+ PchSteppingMax
+} PCH_STEPPING;
+
+#define PCH_H_MIN_SUPPORTED_STEPPING PchHA0
+#define PCH_LP_MIN_SUPPORTED_STEPPING PchLpB0
+
+#define PCH_LBG_MIN_SUPPORTED_STEPPING LbgA0
+#define R_PCH_LPC_VENDOR_ID 0x00
+#define R_PCH_LPC_DEVICE_ID 0x02
+
+//
+//
+// SKL PCH Server/WS LPC Device IDs
+//
+#define V_PCH_H_LPC_DEVICE_ID_SVR_0 0xA149 ///< Server SKU Intel C236 Chipset
+#define V_PCH_H_LPC_DEVICE_ID_SVR_1 0xA14A ///< Server SKU Intel C232 Chipset
+#define V_PCH_H_LPC_DEVICE_ID_SVR_2 0xA150 ///< Server SKU Intel CM236 Chipset
+#define V_PCH_H_LPC_DEVICE_ID_A14B 0xA14B ///< Super SKU Unlocked
+
+//
+// SKL PCH-H Desktop LPC Device IDs
+//
+#define V_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU 0xA141 ///< PCH H Desktop Super SKU unlocked
+#define V_PCH_H_LPC_DEVICE_ID_DT_0 0xA142 ///< PCH H Desktop Super SKU locked
+#define V_PCH_H_LPC_DEVICE_ID_DT_1 0xA143 ///< PCH H Desktop H110
+#define V_PCH_H_LPC_DEVICE_ID_DT_2 0xA144 ///< PCH H Desktop H170
+#define V_PCH_H_LPC_DEVICE_ID_DT_3 0xA145 ///< PCH H Desktop Z170
+#define V_PCH_H_LPC_DEVICE_ID_DT_4 0xA146 ///< PCH H Desktop Q170
+#define V_PCH_H_LPC_DEVICE_ID_DT_5 0xA147 ///< PCH H Desktop Q150
+#define V_PCH_H_LPC_DEVICE_ID_DT_6 0xA148 ///< PCH H Desktop B150
+#define V_PCH_H_LPC_DEVICE_ID_UNFUSE 0xA140 ///< PCH-H Unfuse
+//
+// PCH-H Mobile LPC Device IDs
+//
+#define V_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU 0xA141 ///< PCH H Mobile Super SKU unlocked
+#define V_PCH_H_LPC_DEVICE_ID_MB_0 0xA14D ///< PCH H Mobile QM170
+#define V_PCH_H_LPC_DEVICE_ID_MB_1 0xA14E ///< PCH H Mobile HM170
+#define V_PCH_H_LPC_DEVICE_ID_MB_2 0xA14F ///< PCH H Mobile QMS170 (SFF)
+//
+// PCH-LP LPC Device IDs
+//
+#define V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU 0x9D41 ///< PCH LP Mobile Super SKU unlocked
+#define V_PCH_LP_LPC_DEVICE_ID_MB_0 0x9D42 ///< PCH LP Mobile Super SKU locked
+#define V_PCH_LP_LPC_DEVICE_ID_MB_1 0x9D43 ///< PCH LP Mobile (U) Base SKU
+#define V_PCH_LP_LPC_DEVICE_ID_MB_2 0x9D46 ///< PCH LP Mobile (Y) Premium SKU
+#define V_PCH_LP_LPC_DEVICE_ID_MB_3 0x9D48 ///< PCH LP Mobile (U) Premium SKU
+#define V_PCH_LP_LPC_DEVICE_ID_UNFUSE 0x9D40 ///< PCH LP Unfuse
+
+//
+// Lewisburg Production LPC Device ID's
+//
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_0 0xA1C0 ///< LBG PRQ Unfused LBG 0 SKU
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_1G 0xA1C1 ///< LBG PRQ Fused LBG 1G
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_2 0xA1C2 ///< LBG PRQ Fused LBG 2
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_4 0xA1C3 ///< LBG PRQ Fused LBG 4
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_E 0xA1C4 ///< LBG PRQ Fused LBG E
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_M 0xA1C5 ///< LBG PRQ Fused LBG M
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_T 0xA1C6 ///< LBG PRQ Fused LBG T (both uplinks SKU - NS)
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_LP 0xA1C7 ///< LBG PRQ Fused LBG LP
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_C 0xA1CA ///< LBG PRQ Fused LBG C
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_C621A 0xA1CB ///< LBG-R PRQ Fused LBG C621A
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_C627A 0xA1CC ///< LBG-R PRQ Fused LBG C627A
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_C629A 0xA1CD ///< LBG-R PRQ Fused LBG C629A
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_ADG 0xA1CE ///< LBG-R PRQ Fused LBG ADG
+
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_RESERVED_MAX 0xA1CF ///< 0xA1CF reserved for future QS/PRQ SKUs
+
+//
+// Lewisburg SSX (Super SKUs and pre production) LPC Device ID's
+//
+#define V_PCH_LBG_LPC_DEVICE_ID_UNFUSED 0xA240 ///< LBG SSX Unfused SKU
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_0 0xA241 ///< LBG SSX Super SKU 0
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_4_SD 0xA242 ///< LBG SSX Super SKU 4/SD
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_T80_NS 0xA243 ///< LBG SSX Super SKU T80/NS
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_1G 0xA244 ///< LBG SSX Super SKU 1G
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_T 0xA245 ///< LBG Super SKU - T
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_L 0xA246 ///< LBG Super SKU - L
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_C621A 0xA24A ///< LBG-R Super SKU - C621A
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_C627A 0xA24B ///< LBG-R Super SKU - C627A
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_C629A 0xA24C ///< LBG-R Super SKU - C629A
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_ADG 0xA24E ///< LBG-R Super SKU - ADG
+
+#define V_PCH_LBG_LPC_DEVICE_ID_RESERVED_SS_MAX 0xA24F ///< 0xA24D, 0xA24F Super SKU reserved
+
+
+#define V_PCH_LBG_LPC_RID_0 0x00 ///< A0 stepping
+#define V_PCH_LBG_LPC_RID_1 0x01 ///< A1 stepping
+#define V_PCH_LBG_LPC_RID_2 0x02 ///< B0 stepping
+#define V_PCH_LBG_LPC_RID_3 0x03 ///< B1 stepping
+#define V_PCH_LBG_LPC_RID_4 0x04 ///< B2 stepping
+#define V_PCH_LBG_LPC_RID_5 0x05 ///< C0 stepping
+#define V_PCH_LBG_LPC_RID_8 0x08 ///< S0 stepping
+#define V_PCH_LBG_LPC_RID_9 0x09 ///< S1 stepping
+#define V_PCH_LBG_LPC_RID_A 0x0A ///< T0 stepping
+
+#define V_PCH_MINI_LPC_RID_0 0xC0 ///< FPGA PCH stepping
+
+#define V_LPC_CFG_RID_0 0x00
+#define V_LPC_CFG_RID_1 0x01
+#define V_LPC_CFG_RID_9 0x09
+#define V_LPC_CFG_RID_10 0x10
+#define V_LPC_CFG_RID_11 0x11
+#define V_LPC_CFG_RID_20 0x20
+#define V_LPC_CFG_RID_21 0x21
+#define V_LPC_CFG_RID_30 0x30
+#define V_LPC_CFG_RID_31 0x31
+#define R_LPC_CFG_SERIRQ_CNT 0x64
+#define B_LPC_CFG_SERIRQ_CNT_SIRQEN 0x80
+#define B_LPC_CFG_SERIRQ_CNT_SIRQMD 0x40
+#define B_LPC_CFG_SERIRQ_CNT_SIRQSZ 0x3C
+#define N_LPC_CFG_SERIRQ_CNT_SIRQSZ 2
+#define B_LPC_CFG_SERIRQ_CNT_SFPW 0x03
+#define N_LPC_CFG_SERIRQ_CNT_SFPW 0
+#define V_LPC_CFG_SERIRQ_CNT_SFPW_4CLK 0x00
+#define V_LPC_CFG_SERIRQ_CNT_SFPW_6CLK 0x01
+#define V_LPC_CFG_SERIRQ_CNT_SFPW_8CLK 0x02
+#define R_LPC_CFG_IOD 0x80
+#define B_LPC_CFG_IOD_FDD 0x1000
+#define N_LPC_CFG_IOD_FDD 12
+#define V_LPC_CFG_IOD_FDD_3F0 0
+#define V_LPC_CFG_IOD_FDD_370 1
+#define B_LPC_CFG_IOD_LPT 0x0300
+#define N_LPC_CFG_IOD_LPT 8
+#define V_LPC_CFG_IOD_LPT_378 0
+#define V_LPC_CFG_IOD_LPT_278 1
+#define V_LPC_CFG_IOD_LPT_3BC 2
+#define B_LPC_CFG_IOD_COMB 0x0070
+#define N_LPC_CFG_IOD_COMB 4
+#define V_LPC_CFG_IOD_COMB_3F8 0
+#define V_LPC_CFG_IOD_COMB_2F8 1
+#define V_LPC_CFG_IOD_COMB_220 2
+#define V_LPC_CFG_IOD_COMB_228 3
+#define V_LPC_CFG_IOD_COMB_238 4
+#define V_LPC_CFG_IOD_COMB_2E8 5
+#define V_LPC_CFG_IOD_COMB_338 6
+#define V_LPC_CFG_IOD_COMB_3E8 7
+#define B_LPC_CFG_IOD_COMA 0x0007
+#define N_LPC_CFG_IOD_COMA 0
+#define V_LPC_CFG_IOD_COMA_3F8 0
+#define V_LPC_CFG_IOD_COMA_2F8 1
+#define V_LPC_CFG_IOD_COMA_220 2
+#define V_LPC_CFG_IOD_COMA_228 3
+#define V_LPC_CFG_IOD_COMA_238 4
+#define V_LPC_CFG_IOD_COMA_2E8 5
+#define V_LPC_CFG_IOD_COMA_338 6
+#define V_LPC_CFG_IOD_COMA_3E8 7
+#define R_LPC_CFG_IOE 0x82
+#define B_LPC_CFG_IOE_ME2 BIT13 ///< Microcontroller Enable #2, Enables decoding of I/O locations 4Eh and 4Fh to LPC
+#define B_LPC_CFG_IOE_SE BIT12 ///< Super I/O Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC.
+#define B_LPC_CFG_IOE_ME1 BIT11 ///< Microcontroller Enable #1, Enables decoding of I/O locations 62h and 66h to LPC.
+#define B_LPC_CFG_IOE_KE BIT10 ///< Keyboard Enable, Enables decoding of the keyboard I/O locations 60h and 64h to LPC.
+#define B_LPC_CFG_IOE_HGE BIT9 ///< High Gameport Enable, Enables decoding of the I/O locations 208h to 20Fh to LPC.
+#define B_LPC_CFG_IOE_LGE BIT8 ///< Low Gameport Enable, Enables decoding of the I/O locations 200h to 207h to LPC.
+#define B_LPC_CFG_IOE_FDE BIT3 ///< Floppy Drive Enable, Enables decoding of the FDD range to LPC. Range is selected by LIOD.FDE
+#define B_LPC_CFG_IOE_PPE BIT2 ///< Parallel Port Enable, Enables decoding of the LPT range to LPC. Range is selected by LIOD.LPT.
+#define B_LPC_CFG_IOE_CBE BIT1 ///< Com Port B Enable, Enables decoding of the COMB range to LPC. Range is selected LIOD.CB.
+#define B_LPC_CFG_IOE_CAE BIT0 ///< Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA.
+#define R_LPC_CFG_GEN1_DEC 0x84
+#define R_LPC_CFG_GEN2_DEC 0x88
+#define R_LPC_CFG_GEN3_DEC 0x8C
+#define R_LPC_CFG_GEN4_DEC 0x90
+#define B_LPC_CFG_GENX_DEC_IODRA 0x00FC0000
+#define B_LPC_CFG_GENX_DEC_IOBAR 0x0000FFFC
+#define B_LPC_CFG_GENX_DEC_EN 0x00000001
+#define R_LPC_CFG_ULKMC 0x94
+#define B_LPC_CFG_ULKMC_SMIBYENDPS BIT15
+#define B_LPC_CFG_ULKMC_TRAPBY64W BIT11
+#define B_LPC_CFG_ULKMC_TRAPBY64R BIT10
+#define B_LPC_CFG_ULKMC_TRAPBY60W BIT9
+#define B_LPC_CFG_ULKMC_TRAPBY60R BIT8
+#define B_LPC_CFG_ULKMC_SMIATENDPS BIT7
+#define B_LPC_CFG_ULKMC_PSTATE BIT6
+#define B_LPC_CFG_ULKMC_A20PASSEN BIT5
+#define B_LPC_CFG_ULKMC_USBSMIEN BIT4
+#define B_LPC_CFG_ULKMC_64WEN BIT3
+#define B_LPC_CFG_ULKMC_64REN BIT2
+#define B_LPC_CFG_ULKMC_60WEN BIT1
+#define B_LPC_CFG_ULKMC_60REN BIT0
+#define R_LPC_CFG_LGMR 0x98
+#define B_LPC_CFG_LGMR_MA 0xFFFF0000
+#define B_LPC_CFG_LGMR_LMRD_EN BIT0
+#define R_LPC_CFG_PCCS1IORE 0xA0
+#define R_LPC_CFG_PCCS1GIR1 0xA4
+#define R_LPC_CFG_PCCS1GMR1 0xA8
+#define R_ESPI_CFG_CS1IORE 0xA0
+#define R_ESPI_CFG_CS1IORE_DPCS1RE BIT14
+#define R_ESPI_CFG_CS1GIR1 0xA4
+#define R_ESPI_CFG_CS1GMR1 0xA8
+
+#define R_LPC_CFG_FWH_BIOS_SEL 0xD0
+#define B_LPC_CFG_FWH_BIOS_SEL_F8 0xF0000000
+#define B_LPC_CFG_FWH_BIOS_SEL_F0 0x0F000000
+#define B_LPC_CFG_FWH_BIOS_SEL_E8 0x00F00000
+#define B_LPC_CFG_FWH_BIOS_SEL_E0 0x000F0000
+#define B_LPC_CFG_FWH_BIOS_SEL_D8 0x0000F000
+#define B_LPC_CFG_FWH_BIOS_SEL_D0 0x00000F00
+#define B_LPC_CFG_FWH_BIOS_SEL_C8 0x000000F0
+#define B_LPC_CFG_FWH_BIOS_SEL_C0 0x0000000F
+#define R_LPC_CFG_FWH_BIOS_SEL2 0xD4
+#define B_LPC_CFG_FWH_BIOS_SEL2_70 0xF000
+#define B_LPC_CFG_FWH_BIOS_SEL2_60 0x0F00
+#define B_LPC_CFG_FWH_BIOS_SEL2_50 0x00F0
+#define B_LPC_CFG_FWH_BIOS_SEL2_40 0x000F
+#define R_LPC_CFG_BDE 0xD8 ///< BIOS decode enable
+#define B_LPC_CFG_BDE_F8 0x8000
+#define B_LPC_CFG_BDE_F0 0x4000
+#define B_LPC_CFG_BDE_E8 0x2000
+#define B_LPC_CFG_BDE_E0 0x1000
+#define B_LPC_CFG_BDE_D8 0x0800
+#define B_LPC_CFG_BDE_D0 0x0400
+#define B_LPC_CFG_BDE_C8 0x0200
+#define B_LPC_CFG_BDE_C0 0x0100
+#define B_LPC_CFG_BDE_LEG_F 0x0080
+#define B_LPC_CFG_BDE_LEG_E 0x0040
+#define B_LPC_CFG_BDE_70 0x0008
+#define B_LPC_CFG_BDE_60 0x0004
+#define B_LPC_CFG_BDE_50 0x0002
+#define B_LPC_CFG_BDE_40 0x0001
+#define R_LPC_CFG_PCC 0xE0
+#define B_LPC_CFG_PCC_CLKRUN_EN 0x0001
+#define B_LPC_CFG_FVEC0_USB_PORT_CAP 0x00000C00
+#define V_LPC_CFG_FVEC0_USB_14_PORT 0x00000000
+#define V_LPC_CFG_FVEC0_USB_12_PORT 0x00000400
+#define V_LPC_CFG_FVEC0_USB_10_PORT 0x00000800
+#define B_LPC_CFG_FVEC0_SATA_RAID_CAP 0x00000080
+#define B_LPC_CFG_FVEC0_SATA_PORT23_CAP 0x00000040
+#define B_LPC_CFG_FVEC0_SATA_PORT1_6GB_CAP 0x00000008
+#define B_LPC_CFG_FVEC0_SATA_PORT0_6GB_CAP 0x00000004
+#define B_LPC_CFG_FVEC0_PCI_CAP 0x00000002
+#define R_LPC_CFG_FVEC1 0x01
+#define B_LPC_CFG_FVEC1_USB_R_CAP 0x00400000
+#define R_LPC_CFG_FVEC2 0x02
+#define B_PCH_LPC_FVEC2_IATT_CAP 0x00400000 ///< Intel Anti-Theft Technology Capability
+#define V_LPC_CFG_FVEC2_PCIE_PORT78_CAP 0x00200000
+#define V_LPC_CFG_FVEC2_PCH_IG_SUPPORT_CAP 0x00020000 ///< PCH Integrated Graphics Support Capability
+#define R_LPC_CFG_FVEC3 0x03
+#define B_LPC_CFG_FVEC3_DCMI_CAP 0x00002000 ///< Data Center Manageability Interface (DCMI) Capability
+#define B_LPC_CFG_FVEC3_NM_CAP 0x00001000 ///< Node Manager Capability
+
+#define R_LPC_CFG_MDAP 0xC0
+#define B_LPC_CFG_MDAP_POLICY_EN BIT31
+#define B_LPC_CFG_MDAP_PDMA_EN BIT30
+#define B_LPC_CFG_MDAP_VALUE 0x0001FFFF
+
+//
+// APM Registers
+//
+#define R_PCH_IO_APM_CNT 0xB2
+#define R_PCH_IO_APM_STS 0xB3
+
+#define R_LPC_CFG_BC 0xDC ///< Bios Control
+#define S_LPC_CFG_BC 1
+#define B_LPC_CFG_BC_BILD BIT7 ///< BIOS Interface Lock-Down
+#define B_LPC_CFG_BC_BBS BIT6 ///< Boot BIOS strap
+#define N_LPC_CFG_BC_BBS 6
+#define V_LPC_CFG_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI
+#define V_LPC_CFG_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC
+#define B_LPC_CFG_BC_EISS BIT5 ///< Enable InSMM.STS
+#define B_LPC_CFG_BC_TS BIT4 ///< Top Swap
+#define B_LPC_CFG_BC_LE BIT1 ///< Lock Enable
+#define N_LPC_CFG_BC_LE 1
+#define B_LPC_CFG_BC_WPD BIT0 ///< Write Protect Disable
+
+#define R_ESPI_CFG_PCBC 0xDC ///< Peripheral Channel BIOS Control
+#define S_ESPI_CFG_PCBC 4 ///< Peripheral Channel BIOS Control register size
+#define B_ESPI_CFG_PCBC_BWRE BIT11 ///< BIOS Write Report Enable
+#define N_ESPI_CFG_PCBC_BWRE 11 ///< BIOS Write Report Enable bit position
+#define B_ESPI_CFG_PCBC_BWRS BIT10 ///< BIOS Write Report Status
+#define N_ESPI_CFG_PCBC_BWRS 10 ///< BIOS Write Report Status bit position
+#define B_ESPI_CFG_PCBC_BWPDS BIT8 ///< BIOS Write Protect Disable Status
+#define N_ESPI_CFG_PCBC_BWPDS 8 ///< BIOS Write Protect Disable Status bit position
+#define B_ESPI_CFG_PCBC_ESPI_EN BIT2 ///< eSPI Enable Pin Strap
+#define B_ESPI_CFG_PCBC_LE BIT1 ///< Lock Enable
+
+//
+// Processor interface registers
+//
+#define R_PCH_IO_NMI_SC 0x61
+#define B_PCH_IO_NMI_SC_SERR_NMI_STS BIT7
+#define B_PCH_IO_NMI_SC_IOCHK_NMI_STS BIT6
+#define B_PCH_IO_NMI_SC_TMR2_OUT_STS BIT5
+#define B_PCH_IO_NMI_SC_REF_TOGGLE BIT4
+#define B_PCH_IO_NMI_SC_IOCHK_NMI_EN BIT3
+#define B_PCH_IO_NMI_SC_PCI_SERR_EN BIT2
+#define B_PCH_IO_NMI_SC_SPKR_DAT_EN BIT1
+#define B_PCH_IO_NMI_SC_TIM_CNT2_EN BIT0
+#define R_PCH_IO_NMI_EN 0x70
+#define B_PCH_IO_NMI_EN_NMI_EN BIT7
+
+//
+// Reset Generator I/O Port
+//
+#define R_PCH_IO_RST_CNT 0xCF9
+#define B_PCH_IO_RST_CNT_FULL_RST BIT3
+#define B_PCH_IO_RST_CNT_RST_CPU BIT2
+#define B_PCH_IO_RST_CNT_SYS_RST BIT1
+#define V_PCH_IO_RST_CNT_FULLRESET 0x0E
+#define V_PCH_IO_RST_CNT_HARDRESET 0x06
+#define V_PCH_IO_RST_CNT_SOFTRESET 0x04
+#define V_PCH_IO_RST_CNT_HARDSTARTSTATE 0x02
+#define V_PCH_IO_RST_CNT_SOFTSTARTSTATE 0x00
+
+//
+// RTC register
+//
+#define R_RTC_IO_INDEX 0x70
+#define R_RTC_IO_TARGET 0x71
+#define R_RTC_IO_EXT_INDEX 0x72
+#define R_RTC_IO_EXT_TARGET 0x73
+#define R_RTC_IO_INDEX_ALT 0x74
+#define R_RTC_IO_TARGET_ALT 0x75
+#define R_RTC_IO_EXT_INDEX_ALT 0x76
+#define R_RTC_IO_EXT_TARGET_ALT 0x77
+#define R_RTC_IO_REGA 0x0A
+#define B_RTC_IO_REGA_UIP 0x80
+#define R_RTC_IO_REGB 0x0B
+#define B_RTC_IO_REGB_SET 0x80
+#define B_RTC_IO_REGB_PIE 0x40
+#define B_RTC_IO_REGB_AIE 0x20
+#define B_RTC_IO_REGB_UIE 0x10
+#define B_RTC_IO_REGB_DM 0x04
+#define B_RTC_IO_REGB_HOURFORM 0x02
+#define R_RTC_IO_REGC 0x0C
+#define R_RTC_IO_REGD 0x0D
+
+//
+// Private Configuration Register
+// RTC PCRs (PID:RTC)
+//
+#define R_RTC_PCR_CONF 0x3400 ///< RTC Configuration register
+#define S_PCH_PCR_RTC_CONF 4
+#define B_RTC_PCR_CONF_UCMOS_LOCK BIT4
+#define B_RTC_PCR_CONF_LCMOS_LOCK BIT3
+#define B_PCH_PCR_RTC_CONF_RESERVED BIT31
+#define B_RTC_PCR_CONF_UCMOS_EN BIT2 ///< Upper CMOS bank enable
+#define R_RTC_PCR_BUC 0x3414 ///< Backed Up Control
+#define B_RTC_PCR_BUC_TS BIT0 ///< Top Swap
+#define B_RTC_PCR_BUC_NMFLUSH BIT3
+#define R_RTC_PCR_RTCDCG 0x3418 ///< RTC Dynamic Clock Gating Control
+#define R_RTC_PCR_RTCDCG_RTCPCICLKDCGEN BIT1 ///< ipciclk_clk (24 MHz) Dynamic Clock Gate Enable
+#define R_RTC_PCR_RTCDCG_RTCROSIDEDCGEN BIT0 ///< rosc_side_clk (120 MHz) Dynamic Clock Gate Enable
+#define R_RTC_PCR_3F00 0x3F00
+#define R_RTC_PCR_UIPSMI 0x3F04 ///< RTC Update In Progress SMI Control
+
+//
+// LPC PCR Registers
+//
+#define R_LPC_PCR_HVMTCTL 0x3410
+#define R_LPC_PCR_GCFD 0x3418
+#define R_PCH_PCR_LPC_CCE 0x341C
+#define B_PCH_PCR_LPC_CCE_LCG BIT0
+#define B_PCH_PCR_LPC_CCE_ISBICGEN BIT1
+#define B_PCH_PCR_LPC_CCE_IPICGEN BIT2
+#define B_PCH_PCR_LPC_CCE_PGCBCGEN BIT3
+#define V_PCH_PCR_LPC_CCE_CGEN (B_PCH_PCR_LPC_CCE_LCG | \
+ B_PCH_PCR_LPC_CCE_ISBICGEN | \
+ B_PCH_PCR_LPC_CCE_IPICGEN | \
+ B_PCH_PCR_LPC_CCE_PGCBCGEN )
+#define R_LPC_PCR_PCT 0x3420
+#define R_LPC_PCR_SCT 0x3424
+#define R_LPC_PCR_LPCCT 0x3428
+#define R_LPC_PCR_ULTOR 0x3500
+
+//
+// eSPI PCR Registers
+//
+#define R_ESPI_PCR_SLV_CFG_REG_CTL 0x4000 ///< Slave Configuration Register and Link Control
+#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE BIT31 ///< Slave Configuration Register Access Enable
+#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28) ///< Slave Configuration Register Access Status
+#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS 28 ///< Slave Configuration Register Access Status bit position
+#define B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL BIT27 ///< IOSF-SB eSPI Link Configuration Lock
+#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR 7 ///< No errors (transaction completed successfully)
+#define B_ESPI_PCR_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) ///< Slave ID
+#define N_ESPI_PCR_SLV_CFG_REG_CTL_SID 19 ///< Slave ID bit position
+#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) ///< Slave Configuration Register Access Type
+#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT 16 ///< Slave Configuration Register Access Type bit position
+#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RD 0 ///< Slave Configuration register read from address SCRA[11:0]
+#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_WR 1 ///< Slave Configuration register write to address SCRA[11:0]
+#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_STS 2 ///< Slave Status register read
+#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RS 3 ///< In-Band reset
+#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA 0x00000FFF ///< Slave Configuration Register Address
+#define R_ESPI_PCR_SLV_CFG_REG_DATA 0x4004 ///< Slave Configuration Register Data
+
+#define R_ESPI_PCR_PCERR_SLV0 0x4020 ///< Peripheral Channel Error for Slave 0
+#define S_ESPI_PCR_PCERR_SLV0 4 ///< Peripheral Channel Error register size
+#define B_ESPI_PCR_PCERR_PCFES BIT4 ///< Peripheral Channel Error Fatal Error Status bit
+#define R_ESPI_PCR_PCERR_SLV1 0x4024 ///< Peripheral Channel Error for Slave 1
+#define R_ESPI_PCR_VWERR_SLV0 0x4030 ///< Virtual Wire Channel Error for Slave 0
+#define S_ESPI_PCR_VWERR_SLV0 4 ///< Virtual Wire Channel Error register size
+#define B_ESPI_PCR_VWERR_VWFES BIT4 ///< Virtual Wire Channel Error Fatal Error status bit
+#define R_ESPI_PCR_VWERR_SLV1 0x4034 ///< Virtual Wire Channel Error for Slave 1
+#define R_ESPI_PCR_FCERR_SLV0 0x4040 ///< Flash Access Channel Error for Slave 0
+#define B_ESPI_PCR_FCERR_FCNFES BIT12 ///< Flash Access Channel Non-Fatal Error Status
+#define B_ESPI_PCR_PCERR_FCNFEC (BIT11 | BIT10 | BIT9 | BIT8) ///< Non-Fatal Error Cause bits
+#define N_ESPI_PCR_PCERR_FCNFEC 8 ///< Flash Access Channel Error for Slave 0 bit position
+#define V_ESPI_PCR_PCERR_FCNFEC_SRC_NFE 1 ///< Slave Response Code: NONFATAL_ERROR
+#define V_ESPI_PCR_PCERR_FCNFEC_SCR_UC 2 ///< Slave Response Code: Unsuccessful Completion
+#define V_ESPI_PCR_PCERR_FCNFEC_UCT 4 ///< Unsupported Cycle Type
+#define V_ESPI_PCR_PCERR_FCNFEC_UA 6 ///< Unsupported Address
+#define B_ESPI_PCR_FCERR_FCFES BIT4 ///< Flash Access Channel Fatal Error status bit
+#define B_ESPI_PCR_XERR_XNFEE (BIT14 | BIT13) ///< Non-Fatal Error Reporting Enable bits
+#define N_ESPI_PCR_XERR_XNFEE 13 ///< Non-Fatal Error Reporting Enable bit position
+#define V_ESPI_PCR_XERR_XNFEE_SMI 3 ///< Enable Non-Fatal Error Reporting as SMI
+#define B_ESPI_PCR_XERR_XNFES BIT12 ///< Fatal Error Status
+#define B_ESPI_PCR_XERR_XFEE (BIT6 | BIT5) ///< Fatal Error Reporting Enable bits
+#define N_ESPI_PCR_XERR_XFEE 5 ///< Fatal Error Reporting Enable bit position
+#define V_ESPI_PCR_XERR_XFEE_SMI 3 ///< Enable Fatal Error Reporting as SMI
+#define B_ESPI_PCR_XERR_XFES BIT4 ///< Fatal Error Status
+#define B_ESPI_PCR_PCERR_SLV0_PCURD BIT24 ///< Peripheral Channel Unsupported Request Detected
+#define R_ESPI_PCR_LNKERR_SLV0 0x4050 ///< Link Error for Slave 0
+#define S_ESPI_PCR_LNKERR_SLV0 4 ///< Link Error for Slave 0 register size
+#define B_ESPI_PCR_LNKERR_SLV0_SLCRR BIT31 ///< eSPI Link and Slave Channel Recovery Required
+#define B_ESPI_PCR_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fatal Error Type 1 Reporting Enable
+#define N_ESPI_PCR_LNKERR_SLV0_LFET1E 21 ///< Fatal Error Type 1 Reporting Enable bit position
+#define V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI 3 ///< Enable Fatal Error Type 1 Reporting as SMI
+#define B_ESPI_PCR_LNKERR_SLV0_LFET1S BIT20 ///< Link Fatal Error Type 1 Status
+#define R_ESPI_PCR_LNKERR_SLV1 0x4054 ///< Link Error for Slave 1
+
+#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI Sofstraps Register 0
+#define R_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# Enable
+
+//
+// eSPI Slave registers
+//
+#define R_ESPI_PCR_SLAVE_PCREG 0x10 ///< Slave Channel 1 Capabilities and Configurations register (Peripheral Channel)
+#define R_ESPI_PCR_SLAVE_VWREG 0x20 ///< Slave Channel 2 Capabilities and Configurations register (Virtual Wire Channel)
+#define R_ESPI_PCR_SLAVE_FCREG 0x40 ///< Slave Channel 4 Capabilities and Configurations register (Flash Access Channel)
+#define B_ESPI_PCR_SLAVE_CHEN BIT0 ///< Slave Channel enable bit
+#define B_ESPI_PCR_SLAVE_CHRDY BIT1 ///< Slave Channel ready bit
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsP2sb.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsP2sb.h
new file mode 100644
index 0000000000..f74fd5800b
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsP2sb.h
@@ -0,0 +1,132 @@
+/** @file
+ Register names for PCH P2SB device
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 2013 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_P2SB_H_
+#define _PCH_REGS_P2SB_H_
+
+//
+// PCI to P2SB Bridge Registers (D31:F1)
+//
+#define PCI_DEVICE_NUMBER_PCH_P2SB 31
+#define PCI_FUNCTION_NUMBER_PCH_P2SB 1
+
+#define V_PCH_P2SB_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define R_P2SB_CFG_SBREG_BAR 0x10
+#define B_PCH_P2SB_SBREG_RBA 0xFF000000
+#define R_PCH_P2SB_SBREG_BARH 0x14
+#define B_PCH_P2SB_SBREG_RBAH 0xFFFFFFFF
+#define R_PCH_P2SB_VBDF 0x50
+#define B_PCH_P2SB_VBDF_BUF 0xFF00
+#define B_PCH_P2SB_VBDF_DEV 0x00F8
+#define B_PCH_P2SB_VBDF_FUNC 0x0007
+#define R_PCH_P2SB_ESMBDF 0x52
+#define B_PCH_P2SB_ESMBDF_BUF 0xFF00
+#define B_PCH_P2SB_ESMBDF_DEV 0x00F8
+#define B_PCH_P2SB_ESMBDF_FUNC 0x0007
+#define R_PCH_P2SB_RCFG 0x54
+#define B_PCH_P2SB_RCFG_RPRID 0x0000FF00
+#define B_PCH_P2SB_RCFG_RSE BIT0
+#define R_PCH_P2SB_HPTC 0x60
+#define B_PCH_P2SB_HPTC_AE BIT7
+#define B_PCH_P2SB_HPTC_AS 0x0003
+#define N_PCH_HPET_ADDR_ASEL 12
+#define V_PCH_HPET_BASE0 0xFED00000
+#define V_PCH_HPET_BASE1 0xFED01000
+#define V_PCH_HPET_BASE2 0xFED02000
+#define V_PCH_HPET_BASE3 0xFED03000
+#define R_PCH_P2SB_IOAC 0x64
+#define B_PCH_P2SB_IOAC_AE BIT8
+#define B_PCH_P2SB_IOAC_ASEL 0x00FF
+#define N_PCH_IO_APIC_ASEL 12
+#define R_PCH_IO_APIC_INDEX 0xFEC00000
+#define R_PCH_IO_APIC_DATA 0xFEC00010
+#define R_PCH_IO_APIC_EOI 0xFEC00040
+#define R_PCH_P2SB_IBDF 0x6C
+#define B_PCH_P2SB_IBDF_BUF 0xFF00
+#define B_PCH_P2SB_IBDF_DEV 0x00F8
+#define B_PCH_P2SB_IBDF_FUNC 0x0007
+#define R_PCH_P2SB_HBDF 0x70
+#define B_PCH_P2SB_HBDF_BUF 0xFF00
+#define B_PCH_P2SB_HBDF_DEV 0x00F8
+#define B_PCH_P2SB_HBDF_FUNC 0x0007
+#define R_PCH_P2SB_80 0x80
+#define R_PCH_P2SB_84 0x84
+#define R_PCH_P2SB_88 0x88
+#define R_PCH_P2SB_8C 0x8C
+#define R_PCH_P2SB_90 0x90
+#define R_PCH_P2SB_94 0x94
+#define R_PCH_P2SB_98 0x98
+#define R_PCH_P2SB_9C 0x9C
+#define R_PCH_P2SB_DISPBDF 0xA0
+#define B_PCH_P2SB_DISPBDF_DTBLK 0x00070000
+#define B_PCH_P2SB_DISPBDF_BUF 0x0000FF00
+#define B_PCH_P2SB_DISPBDF_DEV 0x000000F8
+#define B_PCH_P2SB_DISPBDF_FUNC 0x00000007
+#define R_PCH_P2SB_ICCOS 0xA4
+#define B_PCH_P2SB_ICCOS_MODBASE 0xFF00
+#define B_PCH_P2SB_ICCOS_BUFBASE 0x00FF
+#define R_PCH_P2SB_EPMASK0 0x220
+#define R_PCH_P2SB_EPMASK1 0x224
+#define R_PCH_P2SB_EPMASK2 0x228
+#define R_PCH_P2SB_EPMASK3 0x22C
+#define R_PCH_P2SB_EPMASK4 0x230
+#define R_PCH_P2SB_EPMASK5 0x234
+#define R_PCH_P2SB_EPMASK6 0x238
+#define R_PCH_P2SB_EPMASK7 0x23C
+#define B_PCH_P2SB_MASKLOCK BIT17
+//
+// Definition for SBI
+//
+#define R_PCH_P2SB_SBIADDR 0xD0
+#define B_PCH_P2SB_SBIADDR_DESTID 0xFF000000
+#define B_PCH_P2SB_SBIADDR_RS 0x000F0000
+#define B_PCH_P2SB_SBIADDR_OFFSET 0x0000FFFF
+#define R_PCH_P2SB_SBIDATA 0xD4
+#define B_PCH_P2SB_SBIDATA_DATA 0xFFFFFFFF
+#define R_PCH_P2SB_SBISTAT 0xD8
+#define B_PCH_P2SB_SBISTAT_OPCODE 0xFF00
+#define B_PCH_P2SB_SBISTAT_POSTED BIT7
+#define B_PCH_P2SB_SBISTAT_RESPONSE 0x0006
+#define N_PCH_P2SB_SBISTAT_RESPONSE 1
+#define B_PCH_P2SB_SBISTAT_INITRDY BIT0
+#define R_PCH_P2SB_SBIRID 0xDA
+#define B_PCH_P2SB_SBIRID_FBE 0xF000
+#define B_PCH_P2SB_SBIRID_BAR 0x0700
+#define B_PCH_P2SB_SBIRID_FID 0x00FF
+#define R_PCH_P2SB_SBIEXTADDR 0xDC
+#define B_PCH_P2SB_SBIEXTADDR_ADDR 0xFFFFFFFF
+
+//
+// Others
+//
+#define R_PCH_P2SB_E0 0xE0
+#define R_PCH_P2SB_PCE 0xE4
+#define R_PCH_P2SB_PCE_HAE BIT5
+#define R_PCH_P2SB_PCE_PMCRE BIT0
+
+#define R_PCH_P2SB_F4 0xF4
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPcie.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPcie.h
new file mode 100644
index 0000000000..0d10c9dbeb
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPcie.h
@@ -0,0 +1,620 @@
+/** @file
+ Register names for PCH PCI-E root port devices
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_PCIE_H_
+#define _PCH_REGS_PCIE_H_
+
+#define PCI_INVALID_VALUE_16BIT 0xFFFF
+#define PCI_INVALID_VALUE_32BIT 0xFFFFFFFF
+
+//
+// PCH PCI Express Root Ports (D28:F0~7 & D29:F0~3)
+//
+#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5 4
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6 5
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7 6
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8 7
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9 0
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10 1
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11 2
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12 3
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13 4
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14 5
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15 6
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16 7
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17 0
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18 1
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19 2
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20 3
+
+#define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+
+#define V_PCH_H_PCIE_DEVICE_ID_PORT1 0xA110 ///< PCI Express Root Port #1, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT2 0xA111 ///< PCI Express Root Port #2, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT3 0xA112 ///< PCI Express Root Port #3, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT4 0xA113 ///< PCI Express Root Port #4, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT5 0xA114 ///< PCI Express Root Port #5, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT6 0xA115 ///< PCI Express Root Port #6, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT7 0xA116 ///< PCI Express Root Port #7, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT8 0xA117 ///< PCI Express Root Port #8, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT9 0xA118 ///< PCI Express Root Port #9, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT10 0xA119 ///< PCI Express Root Port #10, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT11 0xA11A ///< PCI Express Root Port #11, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT12 0xA11B ///< PCI Express Root Port #12, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT13 0xA11C ///< PCI Express Root Port #13, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT14 0xA11D ///< PCI Express Root Port #14, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT15 0xA11E ///< PCI Express Root Port #15, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT16 0xA11F ///< PCI Express Root Port #16, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT17 0xA167 ///< PCI Express Root Port #17, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT18 0xA168 ///< PCI Express Root Port #18, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT19 0xA169 ///< PCI Express Root Port #19, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT20 0xA16A ///< PCI Express Root Port #20, SKL PCH H
+
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT1 0x9D10 ///< PCI Express Root Port #1, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT2 0x9D11 ///< PCI Express Root Port #2, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT3 0x9D12 ///< PCI Express Root Port #3, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT4 0x9D13 ///< PCI Express Root Port #4, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT5 0x9D14 ///< PCI Express Root Port #5, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT6 0x9D15 ///< PCI Express Root Port #6, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT7 0x9D16 ///< PCI Express Root Port #7, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT8 0x9D17 ///< PCI Express Root Port #8, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT9 0x9D18 ///< PCI Express Root Port #9, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT10 0x9D19 ///< PCI Express Root Port #10, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT11 0x9D1A ///< PCI Express Root Port #11, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT12 0x9D1B ///< PCI Express Root Port #12, SKL PCH LP PCIe Device ID
+
+#define V_PCH_QAT_DEVICE_ID 0x37c8 ///< PCH QAT Device ID
+
+//
+// LBG Production (PRQ) PCI Express Root Ports Device ID's
+//
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT1 0xA190 ///< PCI Express Root Port #1, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT2 0xA191 ///< PCI Express Root Port #2, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT3 0xA192 ///< PCI Express Root Port #3, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT4 0xA193 ///< PCI Express Root Port #4, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT5 0xA194 ///< PCI Express Root Port #5, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT6 0xA195 ///< PCI Express Root Port #6, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT7 0xA196 ///< PCI Express Root Port #7, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT8 0xA197 ///< PCI Express Root Port #8, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT9 0xA198 ///< PCI Express Root Port #9, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT10 0xA199 ///< PCI Express Root Port #10, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT11 0xA19A ///< PCI Express Root Port #11, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT12 0xA19B ///< PCI Express Root Port #12, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT13 0xA19C ///< PCI Express Root Port #13, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT14 0xA19D ///< PCI Express Root Port #14, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT15 0xA19E ///< PCI Express Root Port #15, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT16 0xA19F ///< PCI Express Root Port #16, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT17 0xA1E7 ///< PCI Express Root Port #17, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT18 0xA1E8 ///< PCI Express Root Port #18, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT19 0xA1E9 ///< PCI Express Root Port #19, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT20 0xA1EA ///< PCI Express Root Port #20, LBG PRQ
+//
+// LBG Super SKU (SSX) PCI Express Root Ports Device ID's
+//
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT1 0xA210 ///< PCI Express Root Port #1, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT2 0xA211 ///< PCI Express Root Port #2, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT3 0xA212 ///< PCI Express Root Port #3, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT4 0xA213 ///< PCI Express Root Port #4, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT5 0xA214 ///< PCI Express Root Port #5, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT6 0xA215 ///< PCI Express Root Port #6, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT7 0xA216 ///< PCI Express Root Port #7, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT8 0xA217 ///< PCI Express Root Port #8, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT9 0xA218 ///< PCI Express Root Port #9, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT10 0xA219 ///< PCI Express Root Port #10, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT11 0xA21A ///< PCI Express Root Port #11, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT12 0xA21B ///< PCI Express Root Port #12, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT13 0xA21C ///< PCI Express Root Port #13, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT14 0xA21D ///< PCI Express Root Port #14, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT15 0xA21E ///< PCI Express Root Port #15, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT16 0xA21F ///< PCI Express Root Port #16, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT17 0xA267 ///< PCI Express Root Port #17, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT18 0xA268 ///< PCI Express Root Port #18, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT19 0xA269 ///< PCI Express Root Port #19, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT20 0xA26A ///< PCI Express Root Port #20, LBG SSKU
+typedef enum {
+ PCIE_SPA,
+ PCIE_SPB,
+ PCIE_SPC,
+ PCIE_SPD,
+ PCIE_SPE
+} PCIE_CONTROLLER_INDEX;
+
+#define R_PCH_PCIE_PCISTS 0x06
+#define B_PCH_PCIE_PCISTS_CAP_LST BIT4
+#define B_PCH_PCIE_XCAP_CV 0x000F
+#define B_PCH_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4)
+
+#define R_PCH_PCIE_CLIST 0x40
+#define R_PCH_PCIE_XCAP (R_PCH_PCIE_CLIST + R_PCIE_XCAP_OFFSET)
+#define R_PCH_PCIE_CFG_DEVCAP (R_PCH_PCIE_CLIST + R_PCIE_DCAP_OFFSET)
+#define R_PCH_PCIE_DCTL (R_PCH_PCIE_CLIST + R_PCIE_DCTL_OFFSET)
+#define R_PCH_PCIE_DSTS (R_PCH_PCIE_CLIST + R_PCIE_DSTS_OFFSET)
+#define R_PCH_PCIE_LCAP (R_PCH_PCIE_CLIST + R_PCIE_LCAP_OFFSET)
+#define B_PCH_PCIE_LCAP_PN 0xFF000000
+#define N_PCH_PCIE_LCAP_PN 24
+#define R_PCH_PCIE_LCTL (R_PCH_PCIE_CLIST + R_PCIE_LCTL_OFFSET)
+#define R_PCH_PCIE_LSTS (R_PCH_PCIE_CLIST + R_PCIE_LSTS_OFFSET)
+#define R_PCH_PCIE_CFG_LINKSTS (R_PCH_PCIE_CLIST + R_PCIE_LSTS_OFFSET)
+#define R_PCH_PCIE_SLCAP (R_PCH_PCIE_CLIST + R_PCIE_SLCAP_OFFSET)
+#define R_PCH_PCIE_SLCTL (R_PCH_PCIE_CLIST + R_PCIE_SLCTL_OFFSET)
+#define R_PCH_PCIE_SLSTS (R_PCH_PCIE_CLIST + R_PCIE_SLSTS_OFFSET)
+#define R_PCH_PCIE_CFG_ROOTCTL (R_PCH_PCIE_CLIST + R_PCIE_RCTL_OFFSET)
+#define R_PCH_PCIE_RSTS (R_PCH_PCIE_CLIST + R_PCIE_RSTS_OFFSET)
+#define R_PCH_PCIE_CFG_DCAP2 (R_PCH_PCIE_CLIST + R_PCIE_DCAP2_OFFSET)
+#define R_PCH_PCIE_DCTL2 (R_PCH_PCIE_CLIST + R_PCIE_DCTL2_OFFSET)
+#define R_PCH_PCIE_LCTL2 (R_PCH_PCIE_CLIST + R_PCIE_LCTL2_OFFSET)
+#define R_PCH_PCIE_LSTS2 (R_PCH_PCIE_CLIST + R_PCIE_LSTS2_OFFSET)
+
+
+#define R_PCH_PCIE_MID 0x80
+#define S_PCH_PCIE_MID 2
+#define R_PCH_PCIE_MC 0x82
+#define S_PCH_PCIE_MC 2
+#define R_PCH_PCIE_MA 0x84
+#define S_PCH_PCIE_MA 4
+#define R_PCH_PCIE_MD 0x88
+#define S_PCH_PCIE_MD 2
+
+#define R_PCH_PCIE_SVCAP 0x90
+#define S_PCH_PCIE_SVCAP 2
+#define R_PCH_PCIE_SSVID 0x94
+#define S_PCH_PCIE_SSVID 4
+
+#define R_PCH_PCIE_PMCAP 0xA0
+#define R_PCH_PCIE_PMCS (R_PCH_PCIE_PMCAP + R_PCIE_PMCS_OFFST)
+
+#define R_PCH_PCIE_CCFG 0xD0
+#define B_PCH_PCIE_CCFG_UPMWPD BIT25
+#define B_PCH_PCIE_CCFG_UPSD BIT24
+#define B_PCH_PCIE_CCFG_UNSD BIT23
+#define B_PCH_PCIE_CCFG_NPAP BIT16
+#define B_PCH_PCIE_CCFG_DCGEISMA BIT15
+#define B_PCH_PCIE_CCFG_UNRD (BIT13 | BIT12)
+#define N_PCH_PCIE_CCFG_UNRD 12
+#define B_PCH_PCIE_CCFG_UNRS (BIT6 | BIT5 | BIT4)
+#define N_PCH_PCIE_CCFG_UNRS 4
+#define V_PCH_PCIE_CCFG_UNRS_128B 0
+#define V_PCH_PCIE_CCFG_UNRS_256B 1
+#define B_PCH_PCIE_CCFG_UPRS (BIT2 | BIT1 | BIT0)
+#define N_PCH_PCIE_CCFG_UPRS 0
+#define V_PCH_PCIE_CCFG_UPRS_128B 0
+#define V_PCH_PCIE_CCFG_UPRS_256B 1
+
+#define R_PCH_PCIE_MPC2 0xD4
+#define S_PCH_PCIE_MPC2 4
+#define B_PCH_PCIE_MPC2_PTNFAE BIT12
+#define B_PCH_PCIE_MPC2_LSTP BIT6
+#define B_PCH_PCIE_MPC2_IEIME BIT5
+#define B_PCH_PCIE_MPC2_ASPMCOEN BIT4
+#define B_PCH_PCIE_MPC2_ASPMCO (BIT3 | BIT2)
+#define V_PCH_PCIE_MPC2_ASPMCO_DISABLED 0
+#define V_PCH_PCIE_MPC2_ASPMCO_L0S (1 << 2)
+#define V_PCH_PCIE_MPC2_ASPMCO_L1 (2 << 2)
+#define V_PCH_PCIE_MPC2_ASPMCO_L0S_L1 (3 << 2)
+#define B_PCH_PCIE_MPC2_EOIFD BIT1
+
+#define R_PCH_PCIE_MPC 0xD8
+#define S_PCH_PCIE_MPC 4
+#define B_PCH_PCIE_MPC_PMCE BIT31
+#define B_PCH_PCIE_MPC_HPCE BIT30
+#define B_PCH_PCIE_MPC_MMBNCE BIT27
+#define B_PCH_PCIE_MPC_P8XDE BIT26
+#define B_PCH_PCIE_MPC_IRRCE BIT25
+#define B_PCH_PCIE_MPC_SRL BIT23
+#define B_PCH_PCIE_MPC_UCEL (BIT20 | BIT19 | BIT18)
+#define N_PCH_PCIE_MPC_UCEL 18
+#define B_PCH_PCIE_MPC_CCEL (BIT17 | BIT16 | BIT15)
+#define N_PCH_PCIE_MPC_CCEL 15
+#define B_PCH_PCIE_MPC_PCIESD (BIT14 | BIT13)
+#define N_PCH_PCIE_MPC_PCIESD 13
+#define V_PCH_PCIE_MPC_PCIESD_GEN1 1
+#define V_PCH_PCIE_MPC_PCIESD_GEN2 2
+#define B_PCH_PCIE_MPC_MCTPSE BIT3
+#define B_PCH_PCIE_MPC_HPME BIT1
+#define N_PCH_PCIE_MPC_HPME 1
+#define B_PCH_PCIE_MPC_PMME BIT0
+
+#define R_PCH_PCIE_SMSCS 0xDC
+#define S_PCH_PCIE_SMSCS 4
+#define N_PCH_PCIE_SMSCS_LERSMIS 5
+#define N_PCH_PCIE_SMSCS_HPLAS 4
+#define N_PCH_PCIE_SMSCS_HPPDM 1
+
+#define R_PCH_PCIE_RPDCGEN 0xE1
+#define S_PCH_PCIE_RPDCGEN 1
+#define B_PCH_PCIE_RPDCGEN_RPSCGEN BIT7
+#define B_PCH_PCIE_RPDCGEN_PTOCGE BIT6
+#define B_PCH_PCIE_RPDCGEN_LCLKREQEN BIT5
+#define B_PCH_PCIE_RPDCGEN_BBCLKREQEN BIT4
+#define B_PCH_PCIE_RPDCGEN_SRDBCGEN BIT2
+#define B_PCH_PCIE_RPDCGEN_RPDLCGEN BIT1
+#define B_PCH_PCIE_RPDCGEN_RPDBCGEN BIT0
+
+#define R_PCH_PCIE_RPPGEN 0xE2
+#define B_PCH_PCIE_RPPGEN_PTOTOP BIT6
+#define B_PCH_PCIE_RPPGEN_SEOSCGE BIT4
+
+#define R_PCH_PCIE_PWRCTL 0xE8
+#define B_PCH_PCIE_PWRCTL_LTSSMRTC BIT20
+#define B_PCH_PCIE_PWRCTL_WPDMPGEP BIT17
+#define B_PCH_PCIE_PWRCTL_DBUPI BIT15
+#define B_PCH_PCIE_PWRCTL_TXSWING BIT13
+#define B_PCH_PCIE_PWRCTL_RPL1SQPOL BIT1
+#define B_PCH_PCIE_PWRCTL_RPDTSQPOL BIT0
+
+#define R_PCH_PCIE_DC 0xEC
+#define B_PCH_PCIE_DC_PCIBEM BIT2
+
+#define R_PCH_PCIE_PHYCTL2 0xF5
+#define B_PCH_PCIE_PHYCTL2_TDFT (BIT7 | BIT6)
+#define B_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4)
+#define N_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT 4
+#define B_PCH_PCIE_PHYCTL2_PXPG3PLLOFFEN BIT1
+#define B_PCH_PCIE_PHYCTL2_PXPG2PLLOFFEN BIT0
+
+#define R_PCH_PCIE_IOSFSBCS 0xF7
+#define B_PCH_PCIE_IOSFSBCS_SCPTCGE BIT6
+#define B_PCH_PCIE_IOSFSBCS_SIID (BIT3 | BIT2)
+
+#define R_PCH_PCIE_STRPFUSECFG 0xFC
+#define B_PCH_PCIE_STRPFUSECFG_SERM BIT29
+#define B_PCH_PCIE_STRPFUSECFG_PXIP (BIT27 | BIT26 | BIT25 | BIT24)
+#define N_PCH_PCIE_STRPFUSECFG_PXIP 24
+#define B_PCH_PCIE_STRPFUSECFG_RPC (BIT15 | BIT14)
+#define V_PCH_PCIE_STRPFUSECFG_RPC_1_1_1_1 0
+#define V_PCH_PCIE_STRPFUSECFG_RPC_2_1_1 1
+#define V_PCH_PCIE_STRPFUSECFG_RPC_2_2 2
+#define V_PCH_PCIE_STRPFUSECFG_RPC_4 3
+#define N_PCH_PCIE_STRPFUSECFG_RPC 14
+#define B_PCH_PCIE_STRPFUSECFG_MODPHYIOPMDIS BIT9
+#define B_PCH_PCIE_STRPFUSECFG_PLLSHTDWNDIS BIT8
+#define B_PCH_PCIE_STRPFUSECFG_STPGATEDIS BIT7
+#define B_PCH_PCIE_STRPFUSECFG_ASPMDIS BIT6
+#define B_PCH_PCIE_STRPFUSECFG_LDCGDIS BIT5
+#define B_PCH_PCIE_STRPFUSECFG_LTCGDIS BIT4
+#define B_PCH_PCIE_STRPFUSECFG_CDCGDIS BIT3
+#define B_PCH_PCIE_STRPFUSECFG_DESKTOPMOB BIT2
+
+//
+//PCI Express Extended Capability Registers
+//
+
+#define R_PCH_PCIE_EXCAP_OFFSET 0x100
+
+#define R_PCH_PCIE_CFG_ROOTERRSTS 0x130
+#define S_PCH_PCIE_CFG_ROOTERRSTS 4
+#define B_PCH_PCIE_CFG_ROOTERRSTS_AEMN 0xF8000000
+#define B_PCH_PCIE_CFG_ROOTERRSTS_FEMR BIT6
+#define B_PCH_PCIE_CFG_ROOTERRSTS_NFEMR BIT5
+#define B_PCH_PCIE_CFG_ROOTERRSTS_FUF BIT4
+#define B_PCH_PCIE_CFG_ROOTERRSTS_MEFR BIT3
+#define B_PCH_PCIE_CFG_ROOTERRSTS_EFR BIT2
+#define B_PCH_PCIE_CFG_ROOTERRSTS_MCER BIT1
+#define B_PCH_PCIE_CFG_ROOTERRSTS_CER BIT0
+
+#define R_PCH_PCIE_EX_AECH 0x100 ///< Advanced Error Reporting Capability Header
+#define V_PCH_PCIE_EX_AEC_CV 0x1
+#define R_PCH_PCIE_EX_UEM (R_PCH_PCIE_EX_AECH + R_PCIE_EX_UEM_OFFSET)
+#define R_PCH_PCIE_EX_REC 0x12C ///< Root Error Command
+#define B_PCH_PCIE_EX_REC_FERE BIT2 ///< Root Error Command Fatal Error Reporting Enable
+#define B_PCH_PCIE_EX_REC_NERE BIT1 ///< Root Error Command Non-fatal Error Reporting Enable
+#define B_PCH_PCIE_EX_REC_CERE BIT0 ///< Root Error Command Correctable Error Reporting Enable
+
+#define R_PCH_PCIE_EX_CES 0x110 ///< Correctable Error Status
+#define B_PCH_PCIE_EX_CES_BD BIT7 ///< Bad DLLP Status
+#define B_PCH_PCIE_EX_CES_BT BIT6 ///< Bad TLP Status
+#define B_PCH_PCIE_EX_CES_RE BIT0 ///< Receiver Error Status
+
+
+//CES.RE, CES.BT, CES.BD
+
+#define R_PCH_PCIE_EX_ACSECH 0x140 ///< ACS Extended Capability Header
+#define V_PCH_PCIE_EX_ACS_CV 0x1
+#define R_PCH_PCIE_EX_ACSCAPR (R_PCH_PCIE_EX_ACSECH + R_PCIE_EX_ACSCAPR_OFFSET)
+
+#define R_PCH_PCIE_EX_L1SECH 0x200 ///< L1 Sub-States Extended Capability Header
+#define V_PCH_PCIE_EX_L1S_CV 0x1
+#define R_PCH_PCIE_EX_L1SCAP (R_PCH_PCIE_EX_L1SECH + R_PCIE_EX_L1SCAP_OFFSET)
+#define R_PCH_PCIE_EX_L1SCTL1 (R_PCH_PCIE_EX_L1SECH + R_PCIE_EX_L1SCTL1_OFFSET)
+#define R_PCH_PCIE_EX_L1SCTL2 (R_PCH_PCIE_EX_L1SECH + R_PCIE_EX_L1SCTL2_OFFSET)
+
+#define R_PCH_PCIE_EX_SPEECH 0x220 ///< Secondary PCI Express Extended Capability Header
+#define V_PCH_PCIE_EX_SPEECH_CV 0x1
+
+#define R_PCH_PCIE_EX_LCTL3 (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_LCTL3_OFFSET)
+#define R_PCH_PCIE_EX_LES (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_LES_OFFSET)
+#define R_PCH_PCIE_EX_LECTL (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L01EC_OFFSET)
+#define B_PCH_PCIE_EX_LECTL_UPTPH (BIT14 | BIT13 | BIT12)
+#define N_PCH_PCIE_EX_LECTL_UPTPH 12
+#define B_PCH_PCIE_EX_LECTL_UPTP 0x0F00
+#define N_PCH_PCIE_EX_LECTL_UPTP 8
+#define B_PCH_PCIE_EX_LECTL_DPTPH (BIT6 | BIT5 | BIT4)
+#define N_PCH_PCIE_EX_LECTL_DPTPH 4
+#define B_PCH_PCIE_EX_LECTL_DPTP 0x000F
+#define N_PCH_PCIE_EX_LECTL_DPTP 0
+
+#define R_PCH_PCIE_EX_L01EC (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L01EC_OFFSET)
+#define R_PCH_PCIE_EX_L23EC (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L23EC_OFFSET)
+
+#define R_PCH_PCIE_PCIERTP1 0x300
+#define R_PCH_PCIE_PCIERTP2 0x304
+#define R_PCH_PCIE_PCIENFTS 0x314
+#define R_PCH_PCIE_PCIEL0SC 0x318
+
+#define R_PCH_PCIE_PCIECFG2 0x320
+#define B_PCH_PCIE_PCIECFG2_LBWSSTE BIT30
+#define B_PCH_PCIE_PCIECFG2_RLLG3R BIT27
+#define B_PCH_PCIE_PCIECFG2_CROAOV BIT24
+#define B_PCH_PCIE_PCIECFG2_CROAOE BIT23
+#define B_PCH_PCIE_PCIECFG2_CRSREN BIT22
+#define B_PCH_PCIE_PCIECFG2_PMET (BIT21 | BIT20)
+#define V_PCH_PCIE_PCIECFG2_PMET 1
+#define N_PCH_PCIE_PCIECFG2_PMET 20
+
+#define R_PCH_PCIE_PCIEDBG 0x324
+#define B_PCH_PCIE_PCIEDBG_USSP (BIT27 | BIT26)
+#define B_PCH_PCIE_PCIEDBG_LGCLKSQEXITDBTIMERS (BIT25 | BIT24)
+#define B_PCH_PCIE_PCIEDBG_CTONFAE BIT14
+#define B_PCH_PCIE_PCIEDBG_SQOL0 BIT7
+#define B_PCH_PCIE_PCIEDBG_SPCE BIT5
+#define B_PCH_PCIE_PCIEDBG_LR BIT4
+#define B_PCH_PCIE_DMIL1EDM BIT3
+
+#define R_PCH_PCIE_PCIESTS1 0x328
+#define B_PCH_PCIE_PCIESTS1_LTSMSTATE 0xFF000000
+#define N_PCH_PCIE_PCIESTS1_LTSMSTATE 24
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDY 0x01
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDYECINP1CG 0x0E
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_L0 0x33
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DISWAIT 0x5E
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DISWAITPG 0x60
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_RECOVERYSPEEDREADY 0x6C
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_RECOVERYLNK2DETECT 0x6F
+
+
+#define B_PCH_PCIE_PCIESTS1_LNKSTAT (BIT22 | BIT21 | BIT20 | BIT19)
+#define N_PCH_PCIE_PCIESTS1_LNKSTAT 19
+#define V_PCH_PCIE_PCIESTS1_LNKSTAT_L0 0x7
+
+#define R_PCH_PCIE_PCIESTS2 0x32C
+#define B_PCH_PCIE_PCIESTS2_P4PNCCWSSCMES BIT31
+#define B_PCH_PCIE_PCIESTS2_P3PNCCWSSCMES BIT30
+#define B_PCH_PCIE_PCIESTS2_P2PNCCWSSCMES BIT29
+#define B_PCH_PCIE_PCIESTS2_P1PNCCWSSCMES BIT28
+#define B_PCH_PCIE_PCIESTS2_CLRE 0x0000F000
+#define N_PCH_PCIE_PCIESTS2_CLRE 12
+
+#define R_PCH_PCIE_PCIEALC 0x338
+#define B_PCH_PCIE_PCIEALC_ITLRCLD BIT29
+#define B_PCH_PCIE_PCIEALC_ILLRCLD BIT28
+#define B_PCH_PCIE_PCIEALC_BLKDQDA BIT26
+
+#define R_PCH_PCIE_LTROVR 0x400
+
+#define R_PCH_PCIE_LTROVR2 0x404
+
+#define R_PCH_PCIE_PHYCTL4 0x408
+#define B_PCH_PCIE_PHYCTL4_SQDIS BIT27
+
+
+#define R_PCH_PCIE_PCIEPMECTL 0x420
+#define B_PCH_PCIE_PCIEPMECTL_FDPPGE BIT31
+#define B_PCH_PCIE_PCIEPMECTL_DLSULPPGE BIT30
+#define B_PCH_PCIE_PCIEPMECTL_DLSULDLSD BIT29
+#define B_PCH_PCIE_PCIEPMECTL_L1LE BIT17
+#define B_PCH_PCIE_PCIEPMECTL_L1LTRTLV (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4)
+#define N_PCH_PCIE_PCIEPMECTL_L1LTRTLV 4
+#define V_PCH_PCIE_PCIEPMECTL_L1LTRTLV 0x32
+#define B_PCH_PCIE_PCIEPMECTL_L1FSOE BIT0
+
+#define R_PCH_PCIE_PCIEPMECTL2 0x424
+#define B_PCH_PCIE_PCIEPMECTL2_PHYCLPGE BIT11
+#define B_PCH_PCIE_PCIEPMECTL2_FDCPGE BIT8
+#define B_PCH_PCIE_PCIEPMECTL2_DETSCPGE BIT7
+#define B_PCH_PCIE_PCIEPMECTL2_L23RDYSCPGE BIT6
+#define B_PCH_PCIE_PCIEPMECTL2_DISSCPGE BIT5
+#define B_PCH_PCIE_PCIEPMECTL2_L1SCPGE BIT4
+
+#define R_PCH_PCIE_PCE 0x428
+#define B_PCH_PCIE_PCE_HAE BIT5
+#define B_PCH_PCIE_PCE_PMCRE BIT0
+
+#define R_PCH_PCIE_EQCFG1 0x450
+#define S_PCH_PCIE_EQCFG1 4
+#define B_PCH_PCIE_EQCFG1_REC 0xFF000000
+#define N_PCH_PCIE_EQCFG1_REC 24
+#define B_PCH_PCIE_EQCFG1_REIFECE BIT23
+#define N_PCH_PCIE_EQCFG1_LERSMIE 21
+#define B_PCH_PCIE_EQCFG1_LEP23B BIT18
+#define B_PCH_PCIE_EQCFG1_LEP3B BIT17
+#define B_PCH_PCIE_EQCFG1_RTLEPCEB BIT16
+#define B_PCH_PCIE_EQCFG1_RTPCOE BIT15
+#define B_PCH_PCIE_EQCFG1_HPCMQE BIT13
+#define B_PCH_PCIE_EQCFG1_HAED BIT12
+#define B_PCH_PCIE_EQCFG1_EQTS2IRRC BIT7
+#define B_PCH_PCIE_EQCFG1_TUPP BIT1
+
+#define R_PCH_PCIE_RTPCL1 0x454
+#define B_PCH_PCIE_RTPCL1_PCM BIT31
+#define B_PCH_PCIE_RTPCL1_RTPRECL2PL4 0x3F000000
+#define B_PCH_PCIE_RTPCL1_RTPOSTCL1PL3 0xFC0000
+#define B_PCH_PCIE_RTPCL1_RTPRECL1PL2 0x3F000
+#define B_PCH_PCIE_RTPCL1_RTPOSTCL0PL1 0xFC0
+#define B_PCH_PCIE_RTPCL1_RTPRECL0PL0 0x3F
+
+#define R_PCH_PCIE_RTPCL2 0x458
+#define B_PCH_PCIE_RTPCL2_RTPOSTCL3PL 0x3F000
+#define B_PCH_PCIE_RTPCL2_RTPRECL3PL6 0xFC0
+#define B_PCH_PCIE_RTPCL2_RTPOSTCL2PL5 0x3F
+
+#define R_PCH_PCIE_RTPCL3 0x45C
+#define B_PCH_PCIE_RTPCL3_RTPRECL7 0x3F000000
+#define B_PCH_PCIE_RTPCL3_RTPOSTCL6 0xFC0000
+#define B_PCH_PCIE_RTPCL3_RTPRECL6 0x3F000
+#define B_PCH_PCIE_RTPCL3_RTPOSTCL5 0xFC0
+#define B_PCH_PCIE_RTPCL3_RTPRECL5PL10 0x3F
+
+#define R_PCH_PCIE_RTPCL4 0x460
+#define B_PCH_PCIE_RTPCL4_RTPOSTCL9 0x3F000000
+#define B_PCH_PCIE_RTPCL4_RTPRECL9 0xFC0000
+#define B_PCH_PCIE_RTPCL4_RTPOSTCL8 0x3F000
+#define B_PCH_PCIE_RTPCL4_RTPRECL8 0xFC0
+#define B_PCH_PCIE_RTPCL4_RTPOSTCL7 0x3F
+
+#define R_PCH_PCIE_FOMS 0x464
+#define B_PCH_PCIE_FOMS_I (BIT30 | BIT29)
+#define N_PCH_PCIE_FOMS_I 29
+#define B_PCH_PCIE_FOMS_LN 0x1F000000
+#define N_PCH_PCIE_FOMS_LN 24
+#define B_PCH_PCIE_FOMS_FOMSV 0x00FFFFFF
+#define B_PCH_PCIE_FOMS_FOMSV0 0x000000FF
+#define N_PCH_PCIE_FOMS_FOMSV0 0
+#define B_PCH_PCIE_FOMS_FOMSV1 0x0000FF00
+#define N_PCH_PCIE_FOMS_FOMSV1 8
+#define B_PCH_PCIE_FOMS_FOMSV2 0x00FF0000
+#define N_PCH_PCIE_FOMS_FOMSV2 16
+
+#define R_PCH_PCIE_HAEQ 0x468
+#define B_PCH_PCIE_HAEQ_HAPCCPI (BIT31 | BIT30 | BIT29 | BIT28)
+#define N_PCH_PCIE_HAEQ_HAPCCPI 28
+#define B_PCH_PCIE_HAEQ_MACFOMC BIT19
+
+#define R_PCH_PCIE_LTCO1 0x470
+#define B_PCH_PCIE_LTCO1_L1TCOE BIT25
+#define B_PCH_PCIE_LTCO1_L0TCOE BIT24
+#define B_PCH_PCIE_LTCO1_L1TPOSTCO 0xFC0000
+#define N_PCH_PCIE_LTCO1_L1TPOSTCO 18
+#define B_PCH_PCIE_LTCO1_L1TPRECO 0x3F000
+#define N_PCH_PCIE_LTCO1_L1TPRECO 12
+#define B_PCH_PCIE_LTCO1_L0TPOSTCO 0xFC0
+#define N_PCH_PCIE_LTCO1_L0TPOSTCO 6
+#define B_PCH_PCIE_LTCO1_L0TPRECO 0x3F
+#define N_PCH_PCIE_LTCO1_L0TPRECO 0
+
+#define R_PCH_PCIE_LTCO2 0x474
+#define B_PCH_PCIE_LTCO2_L3TCOE BIT25
+#define B_PCH_PCIE_LTCO2_L2TCOE BIT24
+#define B_PCH_PCIE_LTCO2_L3TPOSTCO 0xFC0000
+#define B_PCH_PCIE_LTCO2_L3TPRECO 0x3F000
+#define B_PCH_PCIE_LTCO2_L2TPOSTCO 0xFC0
+#define B_PCH_PCIE_LTCO2_L2TPRECO 0x3F
+
+#define R_PCH_PCIE_G3L0SCTL 0x478
+#define B_PCH_PCIE_G3L0SCTL_G3UCNFTS 0x0000FF00
+#define B_PCH_PCIE_G3L0SCTL_G3CCNFTS 0x000000FF
+
+#define R_PCH_PCIE_EQCFG2 0x47C
+#define B_PCH_PCIE_EQCFG2_NTIC 0xFF000000
+#define B_PCH_PCIE_EQCFG2_EMD BIT23
+#define B_PCH_PCIE_EQCFG2_NTSS (BIT22 | BIT21 | BIT20)
+#define B_PCH_PCIE_EQCFG2_PCET (BIT19 | BIT18 | BIT17 | BIT16)
+#define N_PCH_PCIE_EQCFG2_PCET 16
+#define B_PCH_PCIE_EQCFG2_HAPCSB (BIT15 | BIT14 | BIT13 | BIT12)
+#define N_PCH_PCIE_EQCFG2_HAPCSB 12
+#define B_PCH_PCIE_EQCFG2_NTEME BIT11
+#define B_PCH_PCIE_EQCFG2_MPEME BIT10
+#define B_PCH_PCIE_EQCFG2_REWMETM (BIT9 | BIT8)
+#define B_PCH_PCIE_EQCFG2_REWMET 0xFF
+
+#define R_PCH_PCIE_MM 0x480
+#define B_PCH_PCIE_MM_MSST 0xFFFFFF00
+#define N_PCH_PCIE_MM_MSST 8
+#define B_PCH_PCIE_MM_MSS 0xFF
+
+//
+//PCI Express Extended End Point Capability Registers
+//
+
+#define R_PCH_PCIE_LTRECH_OFFSET 0
+#define R_PCH_PCIE_LTRECH_CID 0x0018
+#define R_PCH_PCIE_LTRECH_MSLR_OFFSET 0x04
+#define R_PCH_PCIE_LTRECH_MNSLR_OFFSET 0x06
+
+//
+// Pcie Uplink ports related registers and defines
+//
+#define PCI_DEVICE_NUMBER_PCH_PCIE_UX16 0
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_UX16 0
+#define PCI_DEVICE_NUMBER_PCH_PCIE_UX8 0
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_UX8 0
+#define V_PCH_LBG_PCIE_DEVICE_ID_UX16 0x37C0 ///< PCI Express Uplink x16 Device ID
+#define V_PCH_LBG_NS_PCIE_DEVICE_ID_UX8 0x37C1 ///< PCI Express Uplink x8 Device ID, LBG-NS
+
+
+
+//
+// PCIE PCRs (PID:SPA SPB SPC SPD SPE)
+//
+#define R_PCH_PCR_SPX_PCD 0 ///< Port configuration and disable
+#define B_PCH_PCR_SPX_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///< Port 1 Function Number
+#define B_PCH_PCR_SPX_PCD_RP1CH BIT3 ///< Port 1 config hide
+#define B_PCH_PCR_SPX_PCD_RP2FN (BIT6 | BIT5 | BIT4) ///< Port 2 Function Number
+#define B_PCH_PCR_SPX_PCD_RP2CH BIT7 ///< Port 2 config hide
+#define B_PCH_PCR_SPX_PCD_RP3FN (BIT10 | BIT9 | BIT8) ///< Port 3 Function Number
+#define B_PCH_PCR_SPX_PCD_RP3CH BIT11 ///< Port 3 config hide
+#define B_PCH_PCR_SPX_PCD_RP4FN (BIT14 | BIT13 | BIT12) ///< Port 4 Function Number
+#define B_PCH_PCR_SPX_PCD_RP4CH BIT15 ///< Port 4 config hide
+#define S_PCH_PCR_SPX_PCD_RP_FIELD 4 ///< 4 bits for each RP FN
+#define B_PCH_PCR_SPX_PCD_P1D BIT16 ///< Port 1 disable
+#define B_PCH_PCR_SPX_PCD_P2D BIT17 ///< Port 2 disable
+#define B_PCH_PCR_SPX_PCD_P3D BIT18 ///< Port 3 disable
+#define B_PCH_PCR_SPX_PCD_P4D BIT19 ///< Port 4 disable
+#define B_PCH_PCR_SPX_PCD_SRL BIT31 ///< Secured Register Lock
+
+#define R_PCH_PCR_SPX_PCIEHBP 0x0004 ///< PCI Express high-speed bypass
+#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPME BIT0 ///< PCIe HBP mode enable
+#define B_PCH_PCR_SPX_PCIEHBP_PCIEGMO (BIT2 | BIT1) ///< PCIe gen mode override
+#define B_PCH_PCR_SPX_PCIEHBP_PCIETIL0O BIT3 ///< PCIe transmitter-in-L0 override
+#define B_PCH_PCR_SPX_PCIEHBP_PCIERIL0O BIT4 ///< PCIe receiver-in-L0 override
+#define B_PCH_PCR_SPX_PCIEHBP_PCIELRO BIT5 ///< PCIe link recovery override
+#define B_PCH_PCR_SPX_PCIEHBP_PCIELDO BIT6 ///< PCIe link down override
+#define B_PCH_PCR_SPX_PCIEHBP_PCIESSM BIT7 ///< PCIe SKP suppression mode
+#define B_PCH_PCR_SPX_PCIEHBP_PCIESST BIT8 ///< PCIe suppress SKP transmission
+#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPPS (BIT13 | BIT12) ///< PCIe HBP port select
+#define B_PCH_PCR_SPX_PCIEHBP_CRCSEL (BIT15 | BIT14) ///< CRC select
+#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPCRC 0xFFFF0000 ///< PCIe HBP CRC
+
+
+//
+// ICC PCR (PID: ICC)
+//
+#define R_PCH_PCR_ICC_TMCSRCCLK 0x1000 ///< Timing Control SRC Clock Register
+#define R_PCH_PCR_ICC_TMCSRCCLK2 0x1004 ///< Timing Control SRC Clock Register 2
+
+
+#define R_PCH_VSPX_ERRCORSTS 0x0110 //< Correctable Error Status Register
+#define B_PCH_VSPX_ERRCORSTS_ANFE BIT13
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPcr.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPcr.h
new file mode 100644
index 0000000000..ad0d54342f
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPcr.h
@@ -0,0 +1,177 @@
+/** @file
+ Register names for PCH private chipset register
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 2013 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_PCR_H_
+#define _PCH_REGS_PCR_H_
+
+///
+/// Definition for PCR base address (defined in PchReservedResources.h)
+///
+//#define PCH_PCR_BASE_ADDRESS 0xFD000000
+//#define PCH_PCR_MMIO_SIZE 0x01000000
+/**
+ Definition for PCR address
+ The PCR address is used to the PCR MMIO programming
+**/
+#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | ((UINT8) (Pid) << 16) | (UINT16) (Offset))
+#define PCH_PCR_ADDRESS_BASE(PcrBaseAddress, Pid, Offset) ((UINTN) (PcrBaseAddress) | ((UINT8) (Pid) << 16) | (UINT16) (Offset))
+
+/**
+ Definition for SBI PID
+ The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well.
+**/
+
+#define PID_BROADCAST1 0xFF
+#define PID_BROADCAST2 0xFE
+//Rsv = 0xFD-0xF0,
+#define PID_DMI 0xEF
+#define PID_ESPISPI 0xEE
+#define PID_ICLK 0xED
+#define PID_MODPHY4 0xEB
+#define PID_MODPHY5 0x10
+#define PID_MODPHY1 0xE9
+#define PID_PMC 0xE8
+//Rsv = 0xE7,
+#define PID_XHCI 0xE6
+#define PID_OTG 0xE5
+#define PID_SPE 0xE4 // Reserved in SKL PCH LP
+#define PID_SPD 0xE3 // Reserved in SKL PCH LP
+#define PID_SPC 0xE2
+#define PID_SPB 0xE1
+#define PID_SPA 0xE0
+#define PID_UPSX8 0x06
+#define PID_UPSX16 0x07
+#define PID_TAP2IOSFSB1 0xDF
+#define PID_TRSB 0xDD
+#define PID_ICC 0xDC
+#define PID_GBE 0xDB
+//Rsv = 0xDA,
+#define PID_SATA 0xD9
+#define PID_SSATA 0x0F
+#define PID_LDO 0x14
+//Rsv = 0xD8,
+#define PID_DSP 0xD7
+//Rsv = 0xD6,
+#define PID_FUSE 0xD5
+#define PID_FSPROX0 0xD4
+#define PID_DRNG 0xD2
+//Rsv = 0xD1,
+#define PID_FIA 0xCF
+#define PID_FIAWM26 0x13
+//Rsv = 0xCE-0xCC,
+#define PID_USB2 0xCA
+//Rsv = 0xC8
+#define PID_LPC 0xC7
+#define PID_SMB 0xC6
+#define PID_P2S 0xC5
+#define PID_ITSS 0xC4
+#define PID_RTC_HOST 0xC3
+//Rsv = 0xC2-0xC1,
+#define PID_PSF5 0x8F
+#define PID_PSF6 0x70
+#define PID_PSF7 0x01
+#define PID_PSF8 0x29
+#define PID_PSF9 0x21
+#define PID_PSF10 0x36
+#define PID_PSF4 0xBD
+#define PID_PSF3 0xBC
+#define PID_PSF2 0xBB
+#define PID_PSF1 0xBA
+#define PID_HOTHARM 0xB9
+#define PID_DCI 0xB8
+#define PID_DFXAGG 0xB7
+#define PID_NPK 0xB6
+//Rsv = 0xB5-0xB1,
+#define PID_MMP0 0xB0
+#define PID_GPIOCOM0 0xAF
+#define PID_GPIOCOM1 0xAE
+#define PID_GPIOCOM2 0xAD
+#define PID_GPIOCOM3 0xAC
+#define PID_GPIOCOM4 0xAB
+#define PID_GPIOCOM5 0x11
+#define PID_MODPHY2 0xA9
+#define PID_MODPHY3 0xA8
+//Rsv = 0xA7-0xA6,
+#define PID_PNCRC 0xA5
+#define PID_PNCRB 0xA4
+#define PID_PNCRA 0xA3
+#define PID_PNCR0 0xA2
+#define PID_CSME15 0x9F // SMS2
+#define PID_CSME14 0x9E // SMS1
+#define PID_CSME13 0x9D // PMT
+#define PID_CSME12 0x9C // PTIO
+#define PID_CSME11 0x9B // PECI
+#define PID_CSME9 0x99 // SMT6
+#define PID_CSME8 0x98 // SMT5
+#define PID_CSME7 0x97 // SMT4
+#define PID_CSME6 0x96 // SMT3
+#define PID_CSME5 0x95 // SMT2
+#define PID_CSME4 0x94 // SMT1 (SMBus Message Transport 1)
+#define PID_CSME3 0x93 // FSC
+#define PID_CSME2 0x92 // USB-R SAI
+#define PID_CSME0 0x90 // CSE
+#define PID_CSME_PSF 0x8F // ME PSF
+//Rsv = 0x88-0x30,
+//#define PID_EVA 0x2F-0x00
+#define PID_CSMERTC 0x8E
+#define PID_IEUART 0x80
+#define PID_IEHOTHAM 0x7F
+#define PID_IEPMT 0x7E
+#define PID_IESSTPECI 0x7D
+#define PID_IEFSC 0x7C
+#define PID_IESMT5 0x7B
+#define PID_IESMT4 0x7A
+#define PID_IESMT3 0x79
+#define PID_IESMT2 0x78
+#define PID_IESMT1 0x77
+#define PID_IESMT0 0x76
+#define PID_IEUSBR 0x74
+#define PID_IEPTIO 0x73
+#define PID_IEIOSFGASKET 0x72
+#define PID_IEPSF 0x70
+#define PID_FPK 0x0A
+#define PID_MP0KR 0x3C
+#define PID_MP1KR 0x3E
+#define PID_RUAUX 0x0B
+#define PID_RUMAIN 0x3B
+#define PID_EC 0x20
+#define PID_CPM2 0x38
+#define PID_CPM1 0x37
+#define PID_CPM0 0x0C
+#define PID_VSPTHERM 0x25
+#define PID_VSPP2SB 0x24
+#define PID_VSPFPK 0x22
+#define PID_VSPCPM2 0x35
+#define PID_VSPCPM1 0x34
+#define PID_VSPCPM0 0x33
+#define PID_MSMROM 0x08
+#define PID_PSTH 0x89
+
+typedef UINT8 PCH_SBI_PID;
+
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPmc.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPmc.h
new file mode 100644
index 0000000000..83a18f92c5
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPmc.h
@@ -0,0 +1,731 @@
+/** @file
+ Register names for PCH PMC device
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_PMC_H_
+#define _PCH_REGS_PMC_H_
+
+//
+//PMC Registers (D31:F2)
+//
+#define PCI_DEVICE_NUMBER_PCH_PMC 31
+#define PCI_FUNCTION_NUMBER_PCH_PMC 2
+
+#define V_PCH_PMC_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_PMC_DEVICE_ID 0x9D21
+//
+// LBG Production (PRQ) PMC Device ID
+//
+#define V_PCH_LBG_PROD_PMC_DEVICE_ID 0xA1A1
+//
+// LBG Super SKU (SSX) PMC Device ID
+//
+#define V_PCH_LBG_PMC_DEVICE_ID 0xA221
+
+#define R_PCH_PMC_BM_CX_CNF 0xA8
+#define V_PCH_LP_PMC_DEVICE_ID 0x9D21
+#define R_PCH_PMC_PM_DATA_BAR 0x10
+#define B_PCH_PMC_PM_DATA_BAR 0xFFFFC000
+#define R_PCH_PMC_ACPI_BASE 0x40
+#define B_PCH_PMC_ACPI_BASE_BAR 0xFFFC
+#define R_PCH_PMC_ACPI_CNT 0x44
+#define B_PCH_PMC_ACPI_CNT_PWRM_EN BIT8 ///< PWRM enable
+#define B_PCH_PMC_ACPI_CNT_ACPI_EN BIT7 ///< ACPI eanble
+#define B_PCH_PMC_ACPI_CNT_SCIS (BIT2 | BIT1 | BIT0) ///< SCI IRQ select
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ9 0
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ10 1
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ11 2
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ20 4
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ21 5
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ22 6
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ23 7
+#define R_PCH_PMC_PWRM_BASE 0x48
+#define B_PCH_PMC_PWRM_BASE_BAR 0xFFFF0000 ///< PWRM must be 64KB alignment to align the source decode.
+#define R_PCH_PMC_GEN_PMCON_A 0xA0
+#define B_PCH_PMC_GEN_PMCON_A_DC_PP_DIS BIT30
+#define B_PCH_PMC_GEN_PMCON_A_DSX_PP_DIS BIT29
+#define B_PCH_PMC_GEN_PMCON_A_AG3_PP_EN BIT28
+#define B_PCH_PMC_GEN_PMCON_A_SX_PP_EN BIT27
+#define B_PCH_PMC_GEN_PMCON_A_DISB BIT23
+#define B_PCH_PMC_GEN_PMCON_A_MEM_SR BIT21
+#define B_PCH_PMC_GEN_PMCON_A_MS4V BIT18
+#define B_PCH_PMC_GEN_PMCON_A_GBL_RST_STS BIT16
+#define B_PCH_PMC_GEN_PMCON_A_ALLOW_PLL_SD_INC0 BIT13
+#define B_PCH_PMC_GEN_PMCON_A_ALLOW_SPXB_CG_INC0 BIT12
+#define B_PCH_PMC_GEN_PMCON_A_BIOS_PCI_EXP_EN BIT10
+#define B_PCH_PMC_GEN_PMCON_A_PWRBTN_LVL BIT9
+#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT7
+#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON BIT6
+#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON BIT5
+#define B_PCH_PMC_GEN_PMCON_A_SMI_LOCK BIT4
+#define B_PCH_PMC_GEN_PMCON_A_ESPI_SMI_LOCK BIT3 ///< ESPI SMI lock
+#define B_PCH_PMC_GEN_PMCON_A_PER_SMI_SEL 0x0003
+#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_64S 0x0000
+#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_32S 0x0001
+#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_16S 0x0002
+#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_8S 0x0003
+#define R_PCH_PMC_GEN_PMCON_B 0xA4
+#define B_PCH_PMC_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18 ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width
+#define B_PCH_PMC_GEN_PMCON_B_ACPI_BASE_LOCK BIT17 ///< Lock ACPI BASE at 0x40, only cleared by reset when set
+#define B_PCH_PMC_GEN_PMCON_B_PM_DATA_BAR_DIS BIT16
+#define B_PCH_PMC_GEN_PMCON_B_PME_B0_S5_DIS BIT15
+#define B_PCH_PMC_GEN_PMCON_B_SUS_PWR_FLR BIT14
+#define B_PCH_PMC_GEN_PMCON_B_WOL_EN_OVRD BIT13
+#define B_PCH_PMC_GEN_PMCON_B_DISABLE_SX_STRETCH BIT12
+#define B_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW 0xC00
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_60US 0x000
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_1MS 0x400
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_50MS 0x800
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_2S 0xC00
+#define B_PCH_PMC_GEN_PMCON_B_HOST_RST_STS BIT9
+#define B_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL 0xC0
+#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_64MS 0xC0
+#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_32MS 0x80
+#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_16MS 0x40
+#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_1_5MS 0x00
+#define B_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW 0x30
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_1S 0x30
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_2S 0x20
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_3S 0x10
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_4S 0x00
+#define B_PCH_PMC_GEN_PMCON_B_SLP_S4_ASE BIT3
+#define B_PCH_PMC_GEN_PMCON_B_RTC_PWR_STS BIT2
+#define B_PCH_PMC_GEN_PMCON_B_PWR_FLR BIT1
+#define B_PCH_PMC_GEN_PMCON_B_AFTERG3_EN BIT0
+#define R_PCH_PMC_BM_CX_CNF 0xA8
+#define B_PCH_PMC_BM_CX_CNF_STORAGE_BREAK_EN BIT31
+#define B_PCH_PMC_BM_CX_CNF_PCIE_BREAK_EN BIT30
+#define B_PCH_PMC_BM_CX_CNF_EHCI_BREAK_EN BIT26
+#define B_PCH_PMC_BM_CX_CNF_AZ_BREAK_EN BIT24
+#define B_PCH_PMC_BM_CX_CNF_DPSN_BREAK_EN BIT19
+#define B_PCH_PMC_BM_CX_CNF_XHCI_BREAK_EN BIT17
+#define B_PCH_PMC_BM_CX_CNF_SATA3_BREAK_EN BIT16
+#define B_PCH_PMC_BM_CX_CNF_SCRATCHPAD BIT15
+#define B_PCH_PMC_BM_CX_CNF_PHOLD_BM_STS_BLOCK BIT14
+#define B_PCH_PMC_BM_CX_CNF_MASK_CF BIT11
+#define B_PCH_PMC_BM_CX_CNF_BM_STS_ZERO_EN BIT10
+#define B_PCH_PMC_BM_CX_CNF_PM_SYNC_MSG_MODE BIT9
+#define R_PCH_PMC_ETR3 0xAC
+#define B_PCH_PMC_ETR3_CF9LOCK BIT31 ///< CF9h Lockdown
+#define B_PCH_PMC_ETR3_USB_CACHE_DIS BIT21
+#define B_PCH_PMC_ETR3_CF9GR BIT20 ///< CF9h Global Reset
+#define B_PCH_PMC_ETR3_SKIP_HOST_RST_HS BIT19
+#define B_PCH_PMC_ETR3_CWORWRE BIT18
+#define R_PCH_PMC_PMC_THROT_1 0xB0
+#define B_PCH_PMC_PMC_PMC_THROT_LOCK BIT15
+#define B_PCH_PMC_PMC_THROT_1_VRALERT_EN BIT0
+#define R_PCH_PMC_MDAP 0xC0
+#define B_PCH_PMC_MDAP_MDAP_POLICY_EN BIT31
+#define B_PCH_PMC_MDAP_PDMA_EN BIT30
+#define B_PCH_PMC_MDAP_AUTO_POLICY_CTL BIT29
+#define V_PCH_PMC_MDAP_MDAP_VALUE 0x1FFFF
+#define R_PCH_PMC_MANID 0xF8
+
+//
+// ACPI and legacy I/O register offsets from ACPIBASE
+//
+#define R_ACPI_IO_PM1_STS 0x00
+#define S_ACPI_IO_PM1_STS 2
+#define B_ACPI_IO_PM1_STS_WAK 0x8000
+#define B_ACPI_IO_PM1_STS_PRBTNOR 0x0800
+#define B_ACPI_IO_PM1_STS_RTC 0x0400
+#define B_ACPI_IO_PM1_STS_PWRBTN 0x0100
+#define B_ACPI_IO_PM1_STS_GBL 0x0020
+#define B_ACPI_IO_PM1_STS_BM 0x0010
+#define B_ACPI_IO_PM1_STS_TMROF 0x0001
+#define N_ACPI_IO_PM1_STS_WAK 15
+#define N_ACPI_IO_PM1_STS_PRBTNOR 11
+#define N_ACPI_IO_PM1_STS_RTC 10
+#define N_ACPI_IO_PM1_STS_PWRBTN 8
+#define N_ACPI_IO_PM1_STS_GBL 5
+#define N_ACPI_IO_PM1_STS_BM 4
+#define N_ACPI_IO_PM1_STS_TMROF 0
+
+#define R_ACPI_IO_PM1_EN 0x02
+#define S_ACPI_IO_PM1_EN 2
+#define B_ACPI_IO_PM1_EN_PCIEXP_WAKE_DIS 0x4000
+#define B_ACPI_IO_PM1_EN_RTC 0x0400
+#define B_ACPI_IO_PM1_EN_PWRBTN 0x0100
+#define B_ACPI_IO_PM1_EN_GBL 0x0020
+#define B_ACPI_IO_PM1_EN_TMROF 0x0001
+#define N_ACPI_IO_PM1_EN_RTC 10
+#define N_ACPI_IO_PM1_EN_PWRBTN 8
+#define N_ACPI_IO_PM1_EN_GBL 5
+#define N_ACPI_IO_PM1_EN_TMROF 0
+
+#define R_ACPI_IO_PM1_CNT 0x04
+#define S_ACPI_IO_PM1_CNT 4
+#define B_ACPI_IO_PM1_CNT_SLP_EN 0x00002000
+#define B_ACPI_IO_PM1_CNT_SLP_TYP 0x00001C00
+#define V_ACPI_IO_PM1_CNT_S0 0x00000000
+#define V_ACPI_IO_PM1_CNT_S1 0x00000400
+#define V_ACPI_IO_PM1_CNT_S3 0x00001400
+#define V_ACPI_IO_PM1_CNT_S4 0x00001800
+#define V_ACPI_IO_PM1_CNT_S5 0x00001C00
+#define B_ACPI_IO_PM1_CNT_GBL_RLS 0x00000004
+#define B_ACPI_IO_PM1_CNT_BM_RLD 0x00000002
+#define B_ACPI_IO_PM1_CNT_SCI_EN 0x00000001
+
+#define R_ACPI_IO_PM1_TMR 0x08
+#define V_ACPI_IO_TMR_FREQUENCY 3579545
+#define B_ACPI_IO_PM1_TMR_VAL 0xFFFFFF
+#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow
+
+#define R_ACPI_IO_SMI_EN 0x30
+#define S_ACPI_IO_SMI_EN 4
+#define B_ACPI_IO_SMI_EN_LEGACY_USB3 BIT31
+#define B_ACPI_IO_SMI_EN_GPIO_UNLOCK_SMI BIT27
+#define B_ACPI_IO_SMI_EN_IE_SMI BIT23
+#define B_ACPI_IO_SMI_EN_INTEL_USB2 BIT18
+#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17
+#define B_ACPI_IO_SMI_EN_PERIODIC BIT14
+#define B_ACPI_IO_SMI_EN_TCO BIT13
+#define B_ACPI_IO_SMI_EN_MCSMI BIT11
+#define B_ACPI_IO_SMI_EN_BIOS_RLS BIT7
+#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6
+#define B_ACPI_IO_SMI_EN_APMC BIT5
+#define B_ACPI_IO_SMI_EN_ON_SLP_EN BIT4
+#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3
+#define B_ACPI_IO_SMI_EN_BIOS BIT2
+#define B_ACPI_IO_SMI_EN_EOS BIT1
+#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0
+#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31
+#define N_ACPI_IO_SMI_EN_ESPI 28
+#define N_ACPI_IO_SMI_EN_GPIO_UNLOCK 27
+#define N_ACPI_IO_SMI_EN_INTEL_USB2 18
+#define N_ACPI_IO_SMI_EN_LEGACY_USB2 17
+#define N_ACPI_IO_SMI_EN_PERIODIC 14
+#define N_ACPI_IO_SMI_EN_TCO 13
+#define N_ACPI_IO_SMI_EN_MCSMI 11
+#define N_ACPI_IO_SMI_EN_BIOS_RLS 7
+#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6
+#define N_ACPI_IO_SMI_EN_APMC 5
+#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4
+#define N_ACPI_IO_SMI_EN_LEGACY_USB 3
+#define N_ACPI_IO_SMI_EN_BIOS 2
+#define N_ACPI_IO_SMI_EN_EOS 1
+#define N_ACPI_IO_SMI_EN_GBL_SMI 0
+
+#define R_ACPI_IO_SMI_STS 0x34
+#define S_ACPI_IO_SMI_STS 4
+#define B_ACPI_IO_SMI_STS_LEGACY_USB3 BIT31
+#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27
+#define B_ACPI_IO_SMI_STS_SPI BIT26
+#define B_ACPI_IO_SMI_STS_IE_SMI BIT23
+#define B_ACPI_IO_SMI_STS_MONITOR BIT21
+#define B_ACPI_IO_SMI_STS_PCI_EXP BIT20
+#define B_ACPI_IO_SMI_STS_PATCH BIT19
+#define B_ACPI_IO_SMI_STS_INTEL_USB2 BIT18
+#define B_ACPI_IO_SMI_STS_LEGACY_USB2 BIT17
+#define B_ACPI_IO_SMI_STS_SMBUS BIT16
+#define B_ACPI_IO_SMI_STS_SERIRQ BIT15
+#define B_ACPI_IO_SMI_STS_PERIODIC BIT14
+#define B_ACPI_IO_SMI_STS_TCO BIT13
+#define B_ACPI_IO_SMI_STS_DEVMON BIT12
+#define B_ACPI_IO_SMI_STS_MCSMI BIT11
+#define B_ACPI_IO_SMI_STS_GPIO_SMI BIT10
+#define B_ACPI_IO_SMI_STS_GPE1 BIT10
+#define B_ACPI_IO_SMI_STS_GPE0 BIT9
+#define B_ACPI_IO_SMI_STS_PM1_STS_REG BIT8
+#define B_ACPI_IO_SMI_STS_SWSMI_TMR BIT6
+#define B_ACPI_IO_SMI_STS_APM BIT5
+#define B_ACPI_IO_SMI_STS_ON_SLP_EN BIT4
+#define B_ACPI_IO_SMI_STS_LEGACY_USB BIT3
+#define B_ACPI_IO_SMI_STS_BIOS BIT2
+#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31
+#define N_ACPI_IO_SMI_STS_ESPI 28
+#define N_ACPI_IO_SMI_STS_GPIO_UNLOCK 27
+#define N_ACPI_IO_SMI_STS_SPI 26
+#define N_ACPI_IO_SMI_STS_MONITOR 21
+#define N_ACPI_IO_SMI_STS_PCI_EXP 20
+#define N_ACPI_IO_SMI_STS_PATCH 19
+#define N_ACPI_IO_SMI_STS_INTEL_USB2 18
+#define N_ACPI_IO_SMI_STS_LEGACY_USB2 17
+#define N_ACPI_IO_SMI_STS_SMBUS 16
+#define N_ACPI_IO_SMI_STS_SERIRQ 15
+#define N_ACPI_IO_SMI_STS_PERIODIC 14
+#define N_ACPI_IO_SMI_STS_TCO 13
+#define N_ACPI_IO_SMI_STS_DEVMON 12
+#define N_ACPI_IO_SMI_STS_MCSMI 11
+#define N_ACPI_IO_SMI_STS_GPIO_SMI 10
+#define N_ACPI_IO_SMI_STS_GPE0 9
+#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8
+#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6
+#define N_ACPI_IO_SMI_STS_APM 5
+#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4
+#define N_ACPI_IO_SMI_STS_LEGACY_USB 3
+#define N_ACPI_IO_SMI_STS_BIOS 2
+
+#define R_ACPI_IO_GPE_CNTL 0x40
+#define B_ACPI_IO_GPE_CNTL_SWGPE_CTRL BIT17
+
+#define R_ACPI_IO_DEVACT_STS 0x44
+#define S_ACPI_IO_DEVACT_STS 2
+#define B_ACPI_IO_DEVACT_STS_MASK 0x13E1
+#define B_ACPI_IO_DEVACT_STS_KBC 0x1000
+#define B_ACPI_IO_DEVACT_STS_PIRQDH 0x0200
+#define B_ACPI_IO_DEVACT_STS_PIRQCG 0x0100
+#define B_ACPI_IO_DEVACT_STS_PIRQBF 0x0080
+#define B_ACPI_IO_DEVACT_STS_PIRQAE 0x0040
+#define B_ACPI_IO_DEVACT_STS_D0_TRP 0x0001
+#define N_ACPI_IO_DEVACT_STS_KBC 12
+#define N_ACPI_IO_DEVACT_STS_PIRQDH 9
+#define N_ACPI_IO_DEVACT_STS_PIRQCG 8
+#define N_ACPI_IO_DEVACT_STS_PIRQBF 7
+#define N_ACPI_IO_DEVACT_STS_PIRQAE 6
+
+#define R_ACPI_IO_PM2_CNT 0x50
+#define B_ACPI_IO_PM2_CNT_ARB_DIS 0x01
+
+#define R_ACPI_IO_OC_WDT_CTL 0x54
+#define B_ACPI_IO_OC_WDT_CTL_RLD BIT31
+#define B_ACPI_IO_OC_WDT_CTL_ICCSURV_STS BIT25
+#define B_ACPI_IO_OC_WDT_CTL_NO_ICCSURV_STS BIT24
+#define B_ACPI_IO_OC_WDT_CTL_FORCE_ALL BIT15
+#define B_ACPI_IO_OC_WDT_CTL_EN BIT14
+#define B_ACPI_IO_OC_WDT_CTL_ICCSURV BIT13
+#define B_ACPI_IO_OC_WDT_CTL_LCK BIT12
+#define B_ACPI_IO_OC_WDT_CTL_TOV_MASK 0x3FF
+#define B_ACPI_IO_OC_WDT_CTL_FAILURE_STS BIT23
+#define B_ACPI_IO_OC_WDT_CTL_UNXP_RESET_STS BIT22
+#define B_ACPI_IO_OC_WDT_CTL_AFTER_POST 0x3F0000
+#define V_ACPI_IO_OC_WDT_CTL_STATUS_FAILURE 1
+#define V_ACPI_IO_OC_WDT_CTL_STATUS_OK 0
+
+#define R_ACPI_IO_GPE0_STS_127_96 0x8C
+#define S_ACPI_IO_GPE0_STS_127_96 4
+#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18
+#define B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS BIT17
+#define B_ACPI_IO_GPE0_STS_127_96_LAN_WAKE BIT16
+#define B_ACPI_IO_GPE0_STS_127_96_GPIO_TIER_2 BIT15
+#define B_ACPI_IO_GPE0_STS_127_96_PME_B0 BIT13
+#define B_ACPI_IO_GPE0_STS_127_96_ME_SCI BIT12
+#define B_ACPI_IO_GPE0_STS_127_96_PME BIT11
+#define B_ACPI_IO_GPE0_STS_127_96_BATLOW BIT10
+#define B_ACPI_IO_GPE0_STS_127_96_PCI_EXP BIT9
+#define B_ACPI_IO_GPE0_STS_127_96_RI BIT8
+#define B_ACPI_IO_GPE0_STS_127_96_SMB_WAK BIT7
+#define B_ACPI_IO_GPE0_STS_127_96_TC0SCI BIT6
+#define B_ACPI_IO_GPE0_STS_127_96_SWGPE BIT2
+#define B_ACPI_IO_GPE0_STS_127_96_HOT_PLUG BIT1
+#define N_ACPI_IO_GPE0_STS_127_96_GPIO_TIER_2 15
+#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13
+#define N_ACPI_IO_GPE0_STS_127_96_PME 11
+#define N_ACPI_IO_GPE0_STS_127_96_BATLOW 10
+#define N_ACPI_IO_GPE0_STS_127_96_PCI_EXP 9
+#define N_ACPI_IO_GPE0_STS_127_96_RI 8
+#define N_ACPI_IO_GPE0_STS_127_96_SMB_WAK 7
+#define N_ACPI_IO_GPE0_STS_127_96_TC0SCI 6
+#define N_ACPI_IO_GPE0_STS_127_96_SWGPE 2
+#define N_ACPI_IO_GPE0_STS_127_96_HOT_PLUG 1
+
+
+#define R_ACPI_IO_GPE0_EN_31_0 0x90
+#define R_ACPI_IO_GPE0_EN_63_31 0x94
+#define R_ACPI_IO_GPE0_EN_94_64 0x98
+#define R_ACPI_IO_GPE0_EN_127_96 0x9C
+#define S_ACPI_IO_GPE0_EN_127_96 4
+#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18
+#define B_ACPI_IO_GPE0_EN_127_96_USB_CON_DSX_EN BIT17
+#define B_ACPI_IO_GPE0_EN_127_96_LAN_WAKE BIT16
+#define B_ACPI_IO_GPE0_EN_127_96_PME_B0 BIT13
+#define B_ACPI_IO_GPE0_EN_127_96_ME_SCI BIT12
+#define B_ACPI_IO_GPE0_EN_127_96_PME BIT11
+#define B_ACPI_IO_GPE0_EN_127_96_BATLOW BIT10
+#define B_ACPI_IO_GPE0_EN_127_96_PCI_EXP BIT9
+#define B_ACPI_IO_GPE0_EN_127_96_RI BIT8
+#define B_ACPI_IO_GPE0_EN_127_96_TC0SCI BIT6
+#define B_ACPI_IO_GPE0_EN_127_96_SWGPE BIT2
+#define B_ACPI_IO_GPE0_EN_127_96_HOT_PLUG BIT1
+#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13
+#define N_ACPI_IO_GPE0_EN_127_96_USB3 12
+#define N_ACPI_IO_GPE0_EN_127_96_PME 11
+#define N_ACPI_IO_GPE0_EN_127_96_BATLOW 10
+#define N_ACPI_IO_GPE0_EN_127_96_PCI_EXP 9
+#define N_ACPI_IO_GPE0_EN_127_96_RI 8
+#define N_ACPI_IO_GPE0_EN_127_96_TC0SCI 6
+#define N_ACPI_IO_GPE0_EN_127_96_SWGPE 2
+#define N_ACPI_IO_GPE0_EN_127_96_HOT_PLUG 1
+
+
+//
+// TCO register I/O map
+//
+#define R_TCO_IO_RLD 0x0
+#define R_TCO_IO_DAT_IN 0x2
+#define R_TCO_IO_DAT_OUT 0x3
+#define R_TCO_IO_TCO1_STS 0x04
+#define S_TCO_IO_TCO1_STS 2
+#define B_TCO_IO_TCO1_STS_DMISERR BIT12
+#define B_TCO_IO_TCO1_STS_DMISMI BIT10
+#define B_TCO_IO_TCO1_STS_DMISCI BIT9
+#define B_TCO_IO_TCO1_STS_BIOSWR BIT8
+#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7
+#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3
+#define B_TCO_IO_TCO1_STS_TCO_INT BIT2
+#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1
+#define B_TCO_IO_TCO1_STS_NMI2SMI BIT0
+#define N_TCO_IO_TCO1_STS_DMISMI 10
+#define N_TCO_IO_TCO1_STS_BIOSWR 8
+#define N_TCO_IO_TCO1_STS_NEWCENTURY 7
+#define N_TCO_IO_TCO1_STS_TIMEOUT 3
+#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1
+#define N_TCO_IO_TCO1_STS_NMI2SMI 0
+
+#define R_TCO_IO_TCO2_STS 0x06
+#define S_TCO_IO_TCO2_STS 2
+#define B_TCO_IO_TCO2_STS_SMLINK_SLV_SMI BIT4
+#define B_TCO_IO_TCO2_STS_BAD_BIOS BIT3
+#define B_TCO_IO_TCO2_STS_BOOT BIT2
+#define B_TCO_IO_TCO2_STS_SECOND_TO BIT1
+#define B_TCO_IO_TCO2_STS_INTRD_DET BIT0
+#define N_TCO_IO_TCO2_STS_INTRD_DET 0
+
+#define R_TCO_IO_TCO1_CNT 0x08
+#define S_TCO_IO_TCO1_CNT 2
+#define B_TCO_IO_TCO1_CNT_LOCK BIT12
+#define B_TCO_IO_TCO1_CNT_TMR_HLT BIT11
+#define B_TCO_IO_TCO1_CNT_NMI2SMI_EN BIT9
+#define B_TCO_IO_TCO1_CNT_NMI_NOW BIT8
+#define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9
+
+#define R_TCO_IO_TCO2_CNT 0x0A
+#define S_TCO_IO_TCO2_CNT 2
+#define B_TCO_IO_TCO2_CNT_OS_POLICY 0x0030
+#define B_TCO_IO_TCO2_CNT_GPI11_ALERT_DISABLE 0x0008
+#define B_TCO_IO_TCO2_CNT_INTRD_SEL 0x0006
+#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2
+
+#define R_TCO_IO_MESSAGE1 0x0C
+#define R_TCO_IO_MESSAGE2 0x0D
+#define R_TCO_IO_TWDS 0x0E ///< TCO_WDSTATUS register.
+#define R_TCO_IO_LE 0x10 ///< LEGACY_ELIM register
+#define B_TCO_IO_LE_IRQ12_CAUSE BIT1
+#define B_TCO_IO_LE_IRQ1_CAUSE BIT0
+#define R_TCO_IO_TMR 0x12
+
+//
+// PWRM Registers
+//
+#define R_PCH_WADT_AC 0x0 ///< Wake Alarm Device Timer: AC
+#define R_PCH_WADT_DC 0x4 ///< Wake Alarm Device Timer: DC
+#define R_PCH_WADT_EXP_AC 0x8 ///< Wake Alarm Device Expired Timer: AC
+#define R_PCH_WADT_EXP_DC 0xC ///< Wake Alarm Device Expired Timer: DC
+#define R_PCH_PWRM_PRSTS 0x10 ///< Power and Reset Status
+#define B_PCH_PWRM_PRSTS_PM_WD_TMR BIT15 ///< Power Management Watchdog Timer
+#define B_PCH_PWRM_PRSTS_VE_WD_TMR_STS BIT7 ///< VE Watchdog Timer Status
+#define B_PCH_PWRM_PRSTS_ME_WD_TMR_STS BIT6 ///< Management Engine Watchdog Timer Status
+#define B_PCH_PWRM_PRSTS_WOL_OVR_WK_STS BIT5
+#define B_PCH_PWRM_PRSTS_FIELD_1 BIT4
+#define B_PCH_PWRM_PRSTS_ME_HOST_PWRDN BIT3
+#define B_PCH_PWRM_PRSTS_ME_HRST_WARM_STS BIT2
+#define B_PCH_PWRM_PRSTS_ME_HRST_COLD_STS BIT1
+#define B_PCH_PWRM_PRSTS_ME_WAKE_STS BIT0
+#define R_PCH_PWRM_14 0x14
+#define R_PCH_PWRM_CFG 0x18 ///< Power Management Configuration
+#define V_PCH_PWRM_CFG_TIMING_T581_10MS (BIT0 | BIT1) ///< Timing t581 - 10ms
+#define B_PCH_PWRM_CFG_ALLOW_24_OSC_SD BIT29 ///< Allow 24MHz Crystal Oscillator Shutdown
+#define B_PCH_PWRM_CFG_ALLOW_USB2_CORE_PG BIT25 ///< Allow USB2 Core Power Gating
+#define B_PCH_PWRM_CFG_RTC_DS_WAKE_DIS BIT21 ///< RTC Wake from Deep S4/S5 Disable
+#define B_PCH_PWRM_CFG_SSMAW_MASK (BIT19 | BIT18) ///< SLP_SUS# Min Assertion Width
+#define V_PCH_PWRM_CFG_SSMAW_4S (BIT19 | BIT18) ///< 4 seconds
+#define V_PCH_PWRM_CFG_SSMAW_1S BIT19 ///< 1 second
+#define V_PCH_PWRM_CFG_SSMAW_0_5S BIT18 ///< 0.5 second (500ms)
+#define V_PCH_PWRM_CFG_SSMAW_0S 0 ///< 0 second
+#define B_PCH_PWRM_CFG_SAMAW_MASK (BIT17 | BIT16) ///< SLP_A# Min Assertion Width
+#define V_PCH_PWRM_CFG_SAMAW_2S (BIT17 | BIT16) ///< 2 seconds
+#define V_PCH_PWRM_CFG_SAMAW_98ms BIT17 ///< 98ms
+#define V_PCH_PWRM_CFG_SAMAW_4S BIT16 ///< 4 seconds
+#define V_PCH_PWRM_CFG_SAMAW_0S 0 ///< 0 second
+#define B_PCH_PWRM_CFG_RPCD_MASK (BIT9 | BIT8) ///< Reset Power Cycle Duration
+#define V_PCH_PWRM_CFG_RPCD_1S (BIT9 | BIT8) ///< 1-2 seconds
+#define V_PCH_PWRM_CFG_RPCD_2S BIT9 ///< 2-3 seconds
+#define V_PCH_PWRM_CFG_RPCD_3S BIT8 ///< 3-4 seconds
+#define V_PCH_PWRM_CFG_RPCD_4S 0 ///< 4-5 seconds (Default)
+#define R_PCH_PWRM_MTPMC 0x20 ///< Message to PMC
+#define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_0_15 0xE ///< Command to override lanes 0-15 power gating
+#define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_16_31 0xF ///< Command to override lanes 16-31 power gating
+#define B_PCH_PWRM_MTPMC_PG_CMD_DATA 0xFFFF0000 ///< Data part of PowerGate Message to PMC
+#define N_PCH_PWRM_MTPMC_PG_CMD_DATA 16
+#define R_PCH_PWRM_PCH_PM_STS 0x1C ///< PCH Power Management Status
+#define B_PCH_PWRM_PCH_PM_STS_ADR_RST_STS BIT16 ///< ADR Reset Status
+#define R_PCH_PWRM_S0_S1_PWRGATE_POL 0x24 ///< S0/S1 Power Gating Policies
+#define R_PCH_PWRM_S3_PWRGATE_POL 0x28 ///< S3 Power Gating Policies
+#define B_PCH_PWRM_S3DC_GATE_SUS BIT1 ///< Deep S3 Enable in DC Mode
+#define B_PCH_PWRM_S3AC_GATE_SUS BIT0 ///< Deep S3 Enable in AC Mode
+#define R_PCH_PWRM_S4_PWRGATE_POL 0x2C ///< Deep S4 Power Policies
+#define B_PCH_PWRM_S4DC_GATE_SUS BIT1 ///< Deep S4 Enable in DC Mode
+#define B_PCH_PWRM_S4AC_GATE_SUS BIT0 ///< Deep S4 Enable in AC Mode
+#define R_PCH_PWRM_S5_PWRGATE_POL 0x30 ///< Deep S5 Power Policies
+#define B_PCH_PWRM_S5DC_GATE_SUS BIT15 ///< Deep S5 Enable in DC Mode
+#define B_PCH_PWRM_S5AC_GATE_SUS BIT14 ///< Deep S5 Enable in AC Mode
+#define R_PCH_PWRM_DSX_CFG 0x34 ///< Deep SX Configuration
+#define B_PCH_PWRM_DSX_CFG_WAKE_PIN_DSX_EN BIT2 ///< WAKE# Pin DeepSx Enable
+#define B_PCH_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS BIT1 ///< AC_PRESENT pin pulldown in DeepSx disable
+#define B_PCH_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 ///< LAN_WAKE Pin DeepSx Enable
+#define R_PCH_PWRM_CFG2 0x3C ///< Power Management Configuration Reg 2
+#define B_PCH_PWRM_CFG2_PBOP (BIT31 | BIT30 | BIT29) ///< Power Button Override Period (PBOP)
+#define N_PCH_PWRM_CFG2_PBOP 29 ///< Power Button Override Period (PBOP)
+#define B_PCH_PWRM_CFG2_PB_DIS BIT28 ///< Power Button Native Mode Disable (PB_DIS)
+#define B_PCH_PWRM_CFG2_DRAM_RESET_CTL BIT26 ///< DRAM RESET# control
+#define R_PCH_PWRM_EN_SN_SLOW_RING 0x48 ///< Enable Snoop Request to SLOW_RING
+#define R_PCH_PWRM_EN_SN_SLOW_RING2 0x4C ///< Enable Snoop Request to SLOW_RING 2nd Reg
+#define R_PCH_PWRM_EN_SN_SA 0x50 ///< Enable Snoop Request to SA
+#define R_PCH_PWRM_EN_SN_SA2 0x54 ///< Enable Snoop Request to SA 2nd Reg
+#define R_PCH_PWRM_EN_SN_SLOW_RING_CF 0x58 ///< Enable Snoop Request to SLOW_RING_CF
+#define R_PCH_PWRM_EN_NS_SA 0x68 ///< Enable Non-Snoop Request to SA
+#define R_PCH_PWRM_EN_CW_SLOW_RING 0x80 ///< Enable Clock Wake to SLOW_RING
+#define R_PCH_PWRM_EN_CW_SLOW_RING2 0x84 ///< Enable Clock Wake to SLOW_RING 2nd Reg
+#define R_PCH_PWRM_EN_CW_SA 0x88 ///< Enable Clock Wake to SA
+#define R_PCH_PWRM_EN_CW_SA2 0x8C ///< Enable Clock Wake to SA 2nd Reg
+#define R_PCH_PWRM_EN_CW_SLOW_RING_CF 0x98 ///< Enable Clock Wake to SLOW_RING_CF
+#define R_PCH_PWRM_EN_PA_SLOW_RING 0xA8 ///< Enable Pegged Active to SLOW_RING
+#define R_PCH_PWRM_EN_PA_SLOW_RING2 0xAC ///< Enable Pegged Active to SLOW_RING 2nd Reg
+#define R_PCH_PWRM_EN_PA_SA 0xB0 ///< Enable Pegged Active to SA
+#define R_PCH_PWRM_EN_PA_SA2 0xB4 ///< Enable Pegged Active to SA 2nd Reg
+#define R_PCH_PWRM_EN_MISC_EVENT 0xC0 ///< Enable Misc PM_SYNC Events
+#define R_PCH_PWRM_PMSYNC_TPR_CONFIG 0xC4
+#define B_PCH_PWRM_PMSYNC_TPR_CONFIG_LOCK BIT31
+#define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_EN BIT26
+#define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE (BIT25 | BIT24)
+#define N_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE 24
+#define V_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE_1 1
+#define R_PCH_PWRM_PMSYNC_MISC_CFG 0xC8
+#define B_PCH_PWRM_PMSYNC_PM_SYNC_LOCK BIT15 ///< PM_SYNC Configuration Lock
+#define B_PCH_PWRM_PMSYNC_GPIO_D_SEL BIT11
+#define B_PCH_PWRM_PMSYNC_GPIO_C_SEL BIT10
+#define B_PCH_PWRM_PMSYNC_GPIO_B_SEL BIT9
+#define B_PCH_PWRM_PMSYNC_GPIO_A_SEL BIT8
+#define R_PCH_PWRM_PMSYNC_TPR_CONFIG2 0xCC
+
+#define R_PCH_PWRM_PM_SYNC_MODE 0xD4
+#define B_PCH_PWRM_PM_SYNC_MODE_GPIO_B BIT13
+#define B_PCH_PWRM_PM_SYNC_MODE_GPIO_C BIT14
+#define PM_SYNC_GPIO_B 0
+#define PM_SYNC_GPIO_C 1
+#define B_PCH_PWRM_PM_SYNC_MODE_32_64_WR BIT29
+#define R_PCH_PWRM_PM_SYNC_MODE_C0 0xF4
+#define R_PCH_PWRM_PM_SYNC_STATE_HYS 0xD0 ///< PM_SYNC State Hysteresis
+#define R_PCH_PWRM_PM_SYNC_MODE 0xD4 ///< PM_SYNC Pin Mode
+#define R_PCH_PWRM_CFG3 0xE0 ///< Power Management Configuration Reg 3
+#define B_PCH_PWRM_CFG3_DSX_WLAN_PP_EN BIT16 ///< Deep-Sx WLAN Phy Power Enable
+#define B_PCH_PWRM_CFG3_HOST_WLAN_PP_EN BIT17 ///< Host Wireless LAN Phy Power Enable
+#define B_PCH_PWRM_CFG3_PWRG_LOCK BIT2 ///< Lock power gating override messages
+#define B_PCH_PWRM_CFG3_GR_PFET_DUR_ON_DEF (BIT25 | BIT24)
+#define N_PCH_PWRM_CFG3_GR_PFET_DUR_ON_DEF 24
+#define V_PCH_PWRM_CFG3_GR_PFET_DUR_ON_DEF_1US 0
+#define V_PCH_PWRM_CFG3_GR_PFET_DUR_ON_DEF_2US 1
+#define V_PCH_PWRM_CFG3_GR_PFET_DUR_ON_DEF_5US 2
+#define V_PCH_PWRM_CFG3_GR_PFET_DUR_ON_DEF_20US 3
+#define R_PCH_PWRM_PM_DOWN_PPB_CFG 0xE4 ///< PM_DOWN PCH_POWER_BUDGET CONFIGURATION
+#define R_PCH_PWRM_CFG4 0xE8 ///< Power Management Configuration Reg 4
+#define B_PCH_PWRM_CFG4_U2_PHY_PG_EN BIT30 ///< USB2 PHY SUS Well Power Gating Enable
+#define B_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR (0x000001FF) ///< CPU I/O VR Ramp Duration, [8:0]
+#define N_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR 0
+#define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_70US 0x007
+#define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_240US 0x018
+#define R_PCH_PWRM_CPU_EPOC 0xEC
+#define R_PCH_PWRM_ADR_EN 0xF0
+#define B_PCH_PWRM_ADR_EN_ADR_FEAT_EN BIT0
+#define B_PCH_PWRM_ADR_EN_CTWDT_ADR_EN BIT9
+#define B_PCH_PWRM_ADR_EN_SYSPWR_ADR_EN BIT12
+#define B_PCH_PWRM_ADR_EN_OCWDT_ADR_EN BIT13
+#define B_PCH_PWRM_ADR_EN_PMC_PARERR_ADR_EN BIT14
+#define B_PCH_PWRM_ADR_EN_HPR_ADR_EN BIT28
+#define B_PCH_PWRM_ADR_EN_ADR_GPIO_SEL_MASK BIT31|BIT30
+#define B_PCH_PWRM_ADR_EN_ADR_GPIO_SEL_GPIO_B BIT30
+#define B_PCH_PWRM_ADR_EN_ADR_GPIO_SEL_GPIO_C BIT31
+#define R_PCH_PWRM_GBL2HOST_EN 0x10C ///< Global to Host Reset Enable
+#define V_PCH_PWRM_GBL2HOST_EN 0x001F2DE4///< Global to Host Reset Enable default value
+#define B_PCH_PWRM_GBL2HOST_EN_G2H_FEAT_EN BIT0 ///< G2H Feature Enable
+#define B_PCH_PWRM_GBL2HOST_EN_LTRESET_G2H_EN BIT1 ///< LT RESET G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_PMCGBL_G2H_EN BIT2 ///< PMC FW-Initiated Global Reset G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_CPUTHRM_G2H_EN BIT3 ///< CPU Thermal Trip G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_PCHTHRM_G2H_EN BIT4 ///< PCH Internal Thermal Trip G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_PBO_G2H_EN BIT5 ///< Power Button Override G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_MEPBO_G2H_EN BIT6 ///< ME-Initiated Power Button Override G2H
+#define B_PCH_PWRM_GBL2HOST_EN_MEWDT_G2H_EN BIT7 ///< ME FW Watchdog Timer G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_MEGBL_G2H_EN BIT8 ///< ME-Initiated Global Reset G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_CTWDT_G2H_EN BIT9 ///< CPU Thermal Watchdog Timer G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_PMCWDT_G2H_EN BIT10 ///< PMC FW Watchdog Timer G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_ME_UERR_G2H_EN BIT11 ///< ME Uncorrectable Error G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_SYSPWR_G2H_EN BIT12 ///< SYS_PWROK Failure G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_OCWDT_G2H_EN BIT13 ///< Over-Clocking WDT G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_PMC_PARERR_G2H_EN BIT14 ///< PMC Parity Error G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_IEPBO_G2H_EN BIT16 ///< IE-Initiated Power Button Override G2H
+#define B_PCH_PWRM_GBL2HOST_EN_IEWDT_G2H_EN BIT17 ///< IE FW Watchdog Timer G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_IEGBL_G2H_EN BIT18 ///< IE-Initiated Global Reset G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_IE_UERR_G2H_EN BIT19 ///< IE Uncorrectable Error G2H Enable
+#define B_PCH_PWRM_GBL2HOST_EN_ACRU_ERR_G2H_EN BIT20 ///< AC RU Error G2H Enable
+#define R_PCH_PWRM_VR_MISC_CTL 0x100
+#define B_PCH_PWRM_VR_MISC_CTL_VIDSOVEN BIT3
+#define R_PCH_PWRM_GPIO_CFG 0x120
+#define B_PCH_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8)
+#define N_PCH_PWRM_GPIO_CFG_GPE0_DW2 8
+#define B_PCH_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 | BIT5 | BIT4)
+#define N_PCH_PWRM_GPIO_CFG_GPE0_DW1 4
+#define B_PCH_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0)
+#define N_PCH_PWRM_GPIO_CFG_GPE0_DW0 0
+#define R_PCH_PWRM_PM_SYNC_MODE_C0 0xF4 ///< PM_SYNC Pin Mode in C0
+#define R_PCH_PWRM_GBLRST_CAUSE0 0x124 //Global reset cause 0
+#define R_PCH_PWRM_GBLRST_CAUSE1 0x128 //Global reset cause 1
+#define R_PCH_PWRM_HPR_CAUSE0 0x12C ///< Host partition reset causes
+#define B_PCH_PWRM_HPR_CAUSE0_GBL_TO_HOST BIT15 ///< Global reset converted to Host reset
+#define R_PCH_PWRM_MODPHY_PM_CFG1 0x200
+#define B_PCH_PWRM_MODPHY_PM_CFG1_MLSXSWPGP 0xFFFF
+#define R_PCH_PWRM_MODPHY_PM_CFG2 0x204 ///< ModPHY Power Management Configuration Reg 2
+#define B_PCH_PWRM_MODPHY_PM_CFG2_MLSPDDGE BIT30 ///< ModPHY Lane SUS Power Domain Dynamic Gating Enable
+#define B_PCH_PWRM_MODPHY_PM_CFG2_EMFC BIT29 ///< Enable ModPHY FET Control
+#define B_PCH_PWRM_MODPHY_PM_CFG2_EFRT (BIT28 | BIT27 | BIT26 | BIT25 | BIT24) ///< External FET Ramp Time
+#define N_PCH_PWRM_MODPHY_PM_CFG2_EFRT 24
+#define V_PCH_PWRM_MODPHY_PM_CFG2_EFRT_200US 0x0A
+#define B_PCH_PWRM_MODPHY_PM_CFG2_ASLOR_UFS BIT16 ///< UFS ModPHY SPD SPD Override
+#define R_PCH_PWRM_MODPHY_PM_CFG3 0x208 ///< ModPHY Power Management Configuration Reg 3
+#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_UFS BIT16 ///< UFS ModPHY SPD RT Request
+#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XDCI BIT15 ///< xDCI ModPHY SPD RT Request
+#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XHCI BIT14 ///< xHCI ModPHY SPD RT Request
+#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_GBE BIT13 ///< GbE ModPHY SPD RT Request
+#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_SATA BIT12 ///< SATA ModPHY SPD RT Request
+#define R_PCH_PWRM_30C 0x30C
+#define R_PCH_PWRM_OBFF_CFG 0x314 ///< OBFF Configuration
+#define R_PCH_PWRM_31C 0x31C
+#define R_PCH_PWRM_CPPM_MISC_CFG 0x320 ///< CPPM Miscellaneous Configuration
+#define R_PCH_PWRM_CPPM_CG_POL1A 0x324 ///< CPPM Clock Gating Policy Reg 1
+#define R_PCH_PWRM_CPPM_CG_POL2A 0x340 ///< CPPM Clock Gating Policy Reg 3
+#define R_PCH_PWRM_34C 0x34C
+#define R_PCH_PWRM_CPPM_CG_POL3A 0x3A8 ///< CPPM Clock Gating Policy Reg 5
+#define B_PCH_PWRM_CPPM_CG_POLXA_CPPM_GX_QUAL BIT30 ///< CPPM Shutdown Qualifier Enable for Clock Source Group X
+#define B_PCH_PWRM_CPPM_CG_POLXA_LTR_GX_THRESH (0x000001FF) ///< LTR Threshold for Clock Source Group X, [8:0]
+#define R_PCH_PWRM_3D0 0x3D0
+#define R_PCH_PWRM_CPPM_MPG_POL1A 0x3E0 ///< CPPM ModPHY Gating Policy Reg 1A
+#define B_PCH_PWRM_CPPM_MPG_POL1A_CPPM_MODPHY_QUAL BIT30 ///< CPPM Shutdown Qualifier Enable for ModPHY
+#define B_PCH_PWRM_CPPM_MPG_POL1A_LT_MODPHY_SEL BIT29 ///< ASLT/PLT Selection for ModPHY
+#define B_PCH_PWRM_CPPM_MPG_POL1A_LTR_MODPHY_THRESH (0x000001FF) ///< LTR Threshold for ModPHY, [8:0]
+#define R_PCH_PWRM_CS_SD_CTL1 0x3E8 ///< Clock Source Shutdown Control Reg 1
+#define B_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG (BIT22 | BIT21 | BIT20) ///< Clock Source 5 Control Configuration
+#define N_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG 20
+#define B_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG (BIT2 | BIT1 | BIT0) ///< Clock Source 1 Control Configuration
+#define N_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG 0
+#define R_PCH_PWRM_CS_SD_CTL2 0x3EC ///< Clock Source Shutdown Control Reg 2
+#define R_PCH_PWRM_HSWPGCR1 0x5D0
+#define B_PCH_PWRM_SW_PG_CTRL_LOCK BIT31
+#define B_PCH_PWRM_DFX_SW_PG_CTRL BIT0
+#define R_PCH_PWRM_600 0x600
+#define R_PCH_PWRM_604 0x604
+#define R_PMC_PWRM_ST_PG_FDIS_PMC_1 0x620 ///< Static PG Related Function Disable Register 1
+#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Static Function Disable Lock (ST_FDIS_LK)
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_CAM_FDIS_PMC BIT6 ///< Camera Function Disable (PMC Version) (CAM_FDIS_PMC)
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_ISH_FDIS_PMC BIT5 ///< SH Function Disable (PMC Version) (ISH_FDIS_PMC)
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_GBE_FDIS_PMC BIT0 ///< GBE Function Disable (PMC Version) (GBE_FDIS_PMC)
+#define R_PCH_PWRM_ST_PG_FDIS_PMC_2 0x624 ///< Static Function Disable Control Register 2
+#define V_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_FDIS_PMC 0x7FF ///< Static Function Disable Control Register 2
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI1_FDIS_PMC BIT10 ///< SerialIo Controller GSPI Device 1 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI0_FDIS_PMC BIT9 ///< SerialIo Controller GSPI Device 0 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART2_FDIS_PMC BIT8 ///< SerialIo Controller UART Device 2 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART1_FDIS_PMC BIT7 ///< SerialIo Controller UART Device 1 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART0_FDIS_PMC BIT6 ///< SerialIo Controller UART Device 0 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C5_FDIS_PMC BIT5 ///< SerialIo Controller I2C Device 5 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C4_FDIS_PMC BIT4 ///< SerialIo Controller I2C Device 4 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C3_FDIS_PMC BIT3 ///< SerialIo Controller I2C Device 3 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C2_FDIS_PMC BIT2 ///< SerialIo Controller I2C Device 2 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C1_FDIS_PMC BIT1 ///< SerialIo Controller I2C Device 1 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C0_FDIS_PMC BIT0 ///< SerialIo Controller I2C Device 0 Function Disable
+#define R_PCH_PWRM_NST_PG_FDIS_1 0x628
+#define B_PCH_PWRM_NST_PG_FDIS_1_SCC_FDIS_PMC BIT25 ///< SCC Function Disable. This is only avaiable in B0 onward.
+#define B_PCH_PWRM_NST_PG_FDIS_1_XDCI_FDIS_PMC BIT24 ///< XDCI Function Disable. This is only avaiable in B0 onward.
+#define B_PCH_PWRM_NST_PG_FDIS_1_ADSP_FDIS_PMC BIT23 ///< ADSP Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_SATA_FDIS_PMC BIT22 ///< SATA Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_sSATA_FDIS_PMC BIT27 ///< sSATA Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C3_FDIS_PMC BIT13 ///< PCIe Controller C Port 3 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C2_FDIS_PMC BIT12 ///< PCIe Controller C Port 2 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C1_FDIS_PMC BIT11 ///< PCIe Controller C Port 1 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C0_FDIS_PMC BIT10 ///< PCIe Controller C Port 0 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B3_FDIS_PMC BIT9 ///< PCIe Controller B Port 3 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B2_FDIS_PMC BIT8 ///< PCIe Controller B Port 2 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B1_FDIS_PMC BIT7 ///< PCIe Controller B Port 1 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B0_FDIS_PMC BIT6 ///< PCIe Controller B Port 0 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A3_FDIS_PMC BIT5 ///< PCIe Controller A Port 3 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A2_FDIS_PMC BIT4 ///< PCIe Controller A Port 2 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A1_FDIS_PMC BIT3 ///< PCIe Controller A Port 1 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A0_FDIS_PMC BIT2 ///< PCIe Controller A Port 0 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_XHCI_FDIS_PMC BIT0 ///< XHCI Function Disable
+#define R_PCH_PWRM_FUSE_DIS_RD_1 0x640 ///< Fuse Disable Read 1 Register
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E3_FUSE_DIS BIT21 ///< PCIe Controller E Port 3 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E2_FUSE_DIS BIT20 ///< PCIe Controller E Port 2 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E1_FUSE_DIS BIT19 ///< PCIe Controller E Port 1 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E0_FUSE_DIS BIT18 ///< PCIe Controller E Port 0 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D3_FUSE_DIS BIT17 ///< PCIe Controller D Port 3 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D2_FUSE_DIS BIT16 ///< PCIe Controller D Port 2 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D1_FUSE_DIS BIT15 ///< PCIe Controller D Port 1 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D0_FUSE_DIS BIT14 ///< PCIe Controller D Port 0 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C3_FUSE_DIS BIT13 ///< PCIe Controller C Port 3 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C2_FUSE_DIS BIT12 ///< PCIe Controller C Port 2 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C1_FUSE_DIS BIT11 ///< PCIe Controller C Port 1 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C0_FUSE_DIS BIT10 ///< PCIe Controller C Port 0 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B3_FUSE_DIS BIT9 ///< PCIe Controller B Port 3 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B2_FUSE_DIS BIT8 ///< PCIe Controller B Port 2 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B1_FUSE_DIS BIT7 ///< PCIe Controller B Port 1 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B0_FUSE_DIS BIT6 ///< PCIe Controller B Port 0 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A3_FUSE_DIS BIT5 ///< PCIe Controller A Port 3 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A2_FUSE_DIS BIT4 ///< PCIe Controller A Port 2 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A1_FUSE_DIS BIT3 ///< PCIe Controller A Port 1 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A0_FUSE_DIS BIT2 ///< PCIe Controller A Port 0 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_XHCI_FUSE_DIS BIT0 ///< XHCI Fuse Disable
+#define R_PCH_PWRM_FUSE_DIS_RD_2 0x644 ///< Fuse Disable Read 2 Register
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SPC_SS_DIS BIT25 ///< SPC Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SPB_SS_DIS BIT24 ///< SPB Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SPA_SS_DIS BIT23 ///< SPA Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_ESPISPI_FUSE_SS_DIS BIT22 ///< ESPISPI Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_PSTH_FUSE_SS_DIS BIT21 ///< PSTH Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_DMI_FUSE_SS_DIS BIT20 ///< DMI Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS BIT19 ///< OTG Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_XHCI_SS_DIS BIT18 ///< XHCI Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_FIA_FUSE_SS_DIS BIT17 ///< FIA Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_DSP_FUSE_SS_DIS BIT16 ///< DSP Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS BIT15 ///< SATA Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_ICC_FUSE_SS_DIS BIT14 ///< ICC Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_LPC_FUSE_SS_DIS BIT13 ///< LPC Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_RTC_FUSE_SS_DIS BIT12 ///< RTC Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_P2S_FUSE_SS_DIS BIT11 ///< P2S Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_TRSB_FUSE_SS_DIS BIT10 ///< TRSB Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SMB_FUSE_SS_DIS BIT9 ///< SMB Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_ITSS_FUSE_SS_DIS BIT8 ///< ITSS Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_TRACEHUB_FUSE_SS_DIS BIT7 ///< TraceHub Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SERIALIO_FUSE_SS_DIS BIT6 ///< SerialIo Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_FLIS_FUSE_SS_DIS BIT5 ///< FLIS Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SCC_FUSE_SS_DIS BIT4 ///< SCC Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_P2D_FUSE_SS_DIS BIT3 ///< P2D Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_CAM_FUSE_SS_DIS BIT2 ///< Camera Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_ISH_FUSE_SS_DIS BIT1 ///< ISH Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 ///< GBE Fuse or Soft Strap Disable
+#define R_PCH_PWRM_FUSE_DIS_RD_3 0x648 ///< Static PG Fuse and Soft Strap Disable Read Register 3
+#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA3_FUSE_SS_DIS BIT3 ///< PNCRA3 Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA2_FUSE_SS_DIS BIT2 ///< PNCRA2 Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA1_FUSE_SS_DIS BIT1 ///< PNCRA1 Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA_FUSE_SS_DIS BIT0 ///< PNCRA Fuse or Soft Strap Disable
+
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPsf.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPsf.h
new file mode 100644
index 0000000000..e824e98913
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPsf.h
@@ -0,0 +1,304 @@
+/** @file
+ Register definition for PSF component
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 2014 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_PSF_H_
+#define _PCH_REGS_PSF_H_
+
+//
+// Private chipset regsiter (Memory space) offset definition
+// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well.
+//
+
+//
+// PSFx segment registers
+//
+#define R_PCH_PCR_PSF_GLOBAL_CONFIG 0x4000 ///< PSF Segment Global Configuration Register
+#define B_PCH_PCR_PSF_GLOBAL_CONFIG_ENTCG BIT4
+#define B_PCH_PCR_PSF_GLOBAL_CONFIG_ENLCG BIT3
+#define R_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0 0x4014 ///< PSF Segment Rootspace Configuration Register
+#define B_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0_ENADDRP2P BIT1
+#define B_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0_VTDEN BIT0
+#define R_PCH_PCR_PSF_PORT_CONFIG_PG0_PORT0 0x4020 ///< PSF Segment Port Configuration Register
+
+#define S_PCH_PSF_DEV_GNTCNT_RELOAD_DGCR 4
+#define S_PCH_PSF_TARGET_GNTCNT_RELOAD 4
+#define B_PCH_PSF_DEV_GNTCNT_RELOAD_DGCR_GNT_CNT_RELOAD 0x1F
+#define B_PCH_PSF_TARGET_GNTCNT_RELOAD_GNT_CNT_RELOAD 0x1F
+
+//
+// PSFx PCRs definitions
+//
+#define R_PCH_PCR_PSFX_T0_SHDW_BAR0 0 ///< PCI BAR0
+#define R_PCH_PCR_PSFX_T0_SHDW_BAR1 0x04 ///< PCI BAR1
+#define R_PCH_PCR_PSFX_T0_SHDW_BAR2 0x08 ///< PCI BAR2
+#define R_PCH_PCR_PSFX_T0_SHDW_BAR3 0x0C ///< PCI BAR3
+#define R_PCH_PCR_PSFX_T0_SHDW_BAR4 0x10 ///< PCI BAR4
+#define R_PCH_PSFX_PCR_T0_SHDW_PCIEN 0x1C ///< PCI configuration space enable bits
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR0DIS BIT16 ///< Disable BAR0
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR1DIS BIT17 ///< Disable BAR1
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR2DIS BIT18 ///< Disable BAR2
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR3DIS BIT19 ///< Disable BAR3
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR4DIS BIT20 ///< Disable BAR4
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR5DIS BIT21 ///< Disable BAR5
+#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS BIT8 ///< Function disable
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_MEMEN BIT1 ///< Memory decoding enable
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_IOEN BIT0 ///< IO decoding enable
+#define R_PCH_PCR_PSFX_T0_SHDW_PMCSR 0x20 ///< PCI power management configuration
+#define B_PCH_PCR_PSFX_T0_SHDW_PMCSR_PWRST (BIT1 | BIT0) ///< Power status
+#define R_PCH_PCR_PSFX_T0_SHDW_CFG_DIS 0x38 ///< PCI configuration disable
+#define B_PCH_PCR_PSFX_T0_SHDW_CFG_DIS_CFGDIS BIT0 ///< config disable
+
+#define R_PCH_PCR_PSFX_T1_SHDW_PCIEN 0x3C ///< PCI configuration space enable bits
+#define B_PCH_PSFX_PCR_T1_SHDW_PCIEN_FUNDIS BIT8 ///< Function disable
+#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_MEMEN BIT1 ///< Memory decoding enable
+#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_IOEN BIT0 ///< IO decoding enable
+
+#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_DEVICE 0x01F0 ///< device number
+#define N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_DEVICE 4
+#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION (BIT3 | BIT2 | BIT1) ///< function number
+#define N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION 1
+
+#define V_PCH_LP_PCR_PSFX_PSF_MC_AGENT_MCAST_TGT_P2SB 0x38A00
+#define V_PCH_H_PCR_PSFX_PSF_MC_AGENT_MCAST_TGT_P2SB 0x38B00
+
+//
+// PSF1 PCRs
+//
+// PSF1 PCH-LP Specific Base Address
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_GBE_REG_BASE 0x0200 ///< D31F6 PSF base address (GBE)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_CAM_REG_BASE 0x0300 ///< D20F3 PSF base address (CAM)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_CSE_WLAN_REG_BASE 0x0500 ///< D22F7 PSF base address (CSME: WLAN)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI3_REG_BASE 0x0700 ///< D22F4 PSF base address (CSME: HECI3)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI2_REG_BASE 0x0800 ///< D22F1 PSF base address (CSME: HECI2)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_CSE_UMA_REG_BASE 0x0900 ///< D18F3 PSF base address (CSME: CSE UMA)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI1_REG_BASE 0x0A00 ///< D22F0 PSF base address (CSME: HECI1)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_KT_REG_BASE 0x0B00 ///< D22F3 PSF base address (CSME: KT)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_IDER_REG_BASE 0x0C00 ///< D22F2 PSF base address (CSME: IDER)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_CLINK_REG_BASE 0x0D00 ///< D18F1 PSF base address (CSME: CLINK)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_PMT_REG_BASE 0x0E00 ///< D18F2 PSF base address (CSME: PMT)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_KVM_REG_BASE 0x0F00 ///< D18F0 PSF base address (CSME: KVM)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_SATA_REG_BASE 0x1000 ///< PCH-LP D23F0 PSF base address (SATA)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2000 ///< PCH-LP D29F3 PSF base address (PCIE PORT 12)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2100 ///< PCH-LP D29F2 PSF base address (PCIE PORT 11)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2200 ///< PCH-LP D29F1 PSF base address (PCIE PORT 10)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2300 ///< PCH-LP D29F0 PSF base address (PCIE PORT 09)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x2400 ///< PCH-LP D28F7 PSF base address (PCIE PORT 08)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x2500 ///< PCH-LP D28F6 PSF base address (PCIE PORT 07)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x2600 ///< PCH-LP D28F5 PSF base address (PCIE PORT 06)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x2700 ///< PCH-LP D28F4 PSF base address (PCIE PORT 05)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x2800 ///< PCH-LP D28F3 PSF base address (PCIE PORT 04)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x2900 ///< PCH-LP D28F2 PSF base address (PCIE PORT 03)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x2A00 ///< PCH-LP D28F1 PSF base address (PCIE PORT 02)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x2B00 ///< PCH-LP D28F0 PSF base address (PCIE PORT 01)
+
+// PSF1 PCH-H Specific Base Address
+#define R_PCH_H_PCR_PSF1_T0_SHDW_CSE_WLAN_REG_BASE 0x0200 ///< D22F7 PSF base address (CSME: WLAN)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI3_REG_BASE 0x0300 ///< SPT-H D22F4 PSF base address (CSME: HECI3)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI2_REG_BASE 0x0400 ///< SPT-H D22F1 PSF base address (CSME: HECI2)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_CSE_UMA_REG_BASE 0x0500 ///< D18F3 PSF base address (CSME: CSE UMA)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI1_REG_BASE 0x0600 ///< SPT-H D22F0 PSF base address (CSME: HECI1)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE 0x0700 ///< SPT-H D22F3 PSF base address (CSME: KT)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE 0x0800 ///< SPT-H D22F2 PSF base address (CSME: IDER)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_PMT_REG_BASE 0x0900 ///< D18F2 PSF base address (CSME: PMT)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_IEPMT_REG_BASE 0x0A00 ///< D16F5 PSF base address (CSME: IEPMT)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_SATA_REG_BASE 0x0B00 ///< D23F0 PSF base address (SATA)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_sSATA_REG_BASE 0x0C00 ///< D17F5 PSF base address (sSATA)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE20_REG_BASE 0x2000 ///< PCH-H D27F3 PSF base address (PCIE PORT 20)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE19_REG_BASE 0x2100 ///< PCH-H D27F2 PSF base address (PCIE PORT 19)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE18_REG_BASE 0x2200 ///< PCH-H D27F1 PSF base address (PCIE PORT 18)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE17_REG_BASE 0x2300 ///< PCH-H D27F0 PSF base address (PCIE PORT 17)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE16_REG_BASE 0x2400 ///< PCH-H D29F7 PSF base address (PCIE PORT 16)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE15_REG_BASE 0x2500 ///< PCH-H D29F6 PSF base address (PCIE PORT 15)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE14_REG_BASE 0x2600 ///< PCH-H D29F5 PSF base address (PCIE PORT 14)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE13_REG_BASE 0x2700 ///< PCH-H D29F4 PSF base address (PCIE PORT 13)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2800 ///< PCH-H D29F3 PSF base address (PCIE PORT 10)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2900 ///< PCH-H D29F2 PSF base address (PCIE PORT 11)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2A00 ///< PCH-H D29F1 PSF base address (PCIE PORT 10)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2B00 ///< PCH-H D29F0 PSF base address (PCIE PORT 09)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x2C00 ///< PCH-H D28F7 PSF base address (PCIE PORT 08)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x2D00 ///< PCH-H D28F6 PSF base address (PCIE PORT 07)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x2E00 ///< PCH-H D28F5 PSF base address (PCIE PORT 06)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x2F00 ///< PCH-H D28F4 PSF base address (PCIE PORT 05)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x3000 ///< PCH-H D28F3 PSF base address (PCIE PORT 04)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x3100 ///< PCH-H D28F2 PSF base address (PCIE PORT 03)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x3200 ///< PCH-H D28F1 PSF base address (PCIE PORT 02)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x3300 ///< PCH-H D28F0 PSF base address (PCIE PORT 01)
+
+// Other PSF1 PCRs definition
+#define R_PCH_H_PCR_PSF1_T0_SHDW_SATA_VS_CAP_VR_RS0_D23_F0_OFFSET16 0x1024
+#define R_PCH_H_PCR_PSF1_T0_SHDW_SATA_MMIOPI_VR_RS0_D23_F0_OFFSET16 0x1030
+#define R_PCH_H_PCR_PSF1_PSF_PORT_CONFIG_PG1_PORT7 0x4040 ///< PSF Port Configuration Register
+#define R_PCH_LP_PCR_PSF1_PSF_PORT_CONFIG_PG1_PORT7 0x403C ///< PSF Port Configuration Register
+#define R_PCH_LP_PCR_PSF1_PSF_MC_CONTROL_MCAST0_EOI 0x4050 ///< Multicast Control Register
+#define R_PCH_LP_PCR_PSF1_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4060 ///< Destination ID
+#define R_PCH_H_PCR_PSF1_PSF_MC_CONTROL_MCAST0_EOI 0x4054 ///< Multicast Control Register
+#define R_PCH_H_PCR_PSF1_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x406C ///< Destination ID
+
+
+//PSF 1 Multicast Message Configuration
+
+#define R_PCH_PCR_PSF1_RC_OWNER_RS0 0x4008 ///< Destination ID
+
+#define B_PCH_PCR_PSF1_TARGET_CHANNELID 0xFF
+#define B_PCH_PCR_PSF1_TARGET_PORTID 0x7F00
+#define N_PCH_PCR_PSF1_TARGET_PORTID 8
+#define B_PCH_PCR_PSF1_TARGET_PORTGROUPID BIT15
+#define N_PCH_PCR_PSF1_TARGET_PORTGROUPID 15
+#define B_PCH_PCR_PSF1_TARGET_PSFID 0xFF0000
+#define N_PCH_PCR_PSF1_TARGET_PSFID 16
+#define B_PCH_PCR_PSF1_TARGET_CHANMAP BIT31
+
+#define V_PCH_PCR_PSF1_RC_OWNER_RS0_CHANNELID 0
+#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PORTID 10
+#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PORTGROUPID_DOWNSTREAM 1
+#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PSFID_PMT 0
+#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PSFID_PSF1 1
+
+#define R_PCH_LP_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1 0x409C ///< Destination ID
+#define R_PCH_H_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1 0x40D0 ///< Destination ID
+#define R_PCH_H_PCR_PSF5_PSF_MC_AGENT_MCAST0_RS0_TGT0_MCTP0 0x404C ///< Destination ID
+#define R_PCH_H_PCR_PSF6_PSF_MC_AGENT_MCAST0_RS0_TGT0_MCTP0 0x4050 ///< Destination ID
+
+#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTGROUPID_UPSTREAM 0
+#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTGROUPID_DOWNSTREAM 1
+#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PSFID_PSF1 1
+
+#define R_PCH_H_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 0x4060 ///< Multicast Control Register
+#define R_PCH_LP_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 0x4058 ///< Multicast Control Register
+#define R_PCH_H_PCR_PSF5_PSF_MC_CONTROL_MCAST0_RS0_MCTP0 0x4040 ///< Multicast Control Register
+#define R_PCH_H_PCR_PSF6_PSF_MC_CONTROL_MCAST0_RS0_MCTP0 0x4044 ///< Multicast Control Register
+
+#define B_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_MULTCEN BIT0
+#define B_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_NUMMC 0xFE
+#define N_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_NUMMC 1
+
+#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_CHANNELID_DMI 0
+#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTID_DMI 0
+
+#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_VR_RS0_D23_F0 0x4240 ///< VR
+#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_PMT_RS0_D18_F2 0x4248 ///< PMT
+#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_PTIO_RS0_D22_F2 0x424C ///< PTIO
+#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_PTIO_RS0_D22_F3 0x4250 ///< PTIO
+#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_CSE_RS0_D22_F0 0x4254 ///< CSE
+#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_CSE_RS0_D18_F3 0x4258 ///< CSE
+#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_CSE_RS0_D22_F1 0x425C ///< CSE
+#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_CSE_RS0_D22_F4 0x4260 ///< CSE
+#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_CSE_RS0_D22_F7 0x4264 ///< CSE
+#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_CSE_RS0_D18_F4 0x4268 ///< CSE
+
+#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_IFR BIT0 ///< IFR
+#define R_PCH_PCR_PSF1_RS_IFR 0x42C0 ///< This register can be used to reset all functions in a particular Root Space simultaneously
+
+//
+// controls the PCI configuration header of a PCI function
+//
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F0 0x4198 ///< SPA
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F1 0x419C ///< SPA
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F2 0x41A0 ///< SPA
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F3 0x41A4 ///< SPA
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F4 0x41A8 ///< SPB
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F5 0x41AC ///< SPB
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F6 0x41B0 ///< SPB
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F7 0x41B4 ///< SPB
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F0 0x41B8 ///< SPC
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F1 0x41BC ///< SPC
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F2 0x41C0 ///< SPC
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F3 0x41C4 ///< SPC
+
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F0 0x426C ///< SPA
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F1 0x4270 ///< SPA
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F2 0x4274 ///< SPA
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F3 0x4278 ///< SPA
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F4 0x427C ///< SPB
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F5 0x4280 ///< SPB
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F6 0x4284 ///< SPB
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F7 0x4288 ///< SPB
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F0 0x428C ///< SPC
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F1 0x4290 ///< SPC
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F2 0x4294 ///< SPC
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F3 0x4298 ///< SPC
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F4 0x429C ///< SPD
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F5 0x42A0 ///< SPD
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F6 0x42A4 ///< SPD
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F7 0x42A8 ///< SPD
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F0 0x42AC ///< SPE
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F1 0x42B0 ///< SPE
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F2 0x42B4 ///< SPE
+#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F3 0x42B8 ///< SPE
+
+//
+// PSF1 grant count registers
+//
+#define R_PCH_LP_PSF1_DEV_GNTCNT_RELOAD_DGCR0 0x41CC
+#define R_PCH_LP_PSF1_TARGET_GNTCNT_RELOAD_PG1_TGT0 0x45D0
+
+#define R_PCH_H_PSF1_DEV_GNTCNT_RELOAD_DGCR0 0x42C0
+#define R_PCH_H_PSF1_TARGET_GNTCNT_RELOAD_PG1_TGT0 0x47AC
+
+//
+// PSF2 PCRs (PID:PSF2)
+//
+#define R_PCH_PCR_PSF2_T0_SHDW_TRH_REG_BASE 0x0100 ///< D20F2 PSF base address (Thermal). // LP&H
+// PSF2 PCH-LP Specific Base Address
+#define R_PCH_LP_PCR_PSF2_T0_SHDW_UFS_REG_BASE 0x0200 ///< D30F7 PSF base address (SCC: UFS)
+#define R_PCH_LP_PCR_PSF2_T0_SHDW_SDCARD_REG_BASE 0x0300 ///< D30F6 PSF base address (SCC: SDCard)
+#define R_PCH_LP_PCR_PSF2_T0_SHDW_SDIO_REG_BASE 0x0400 ///< D30F5 PSF base address (SCC: SDIO)
+#define R_PCH_LP_PCR_PSF2_T0_SHDW_EMMC_REG_BASE 0x0500 ///< D30F4 PSF base address (SCC: eMMC)
+#define R_PCH_LP_PCR_PSF2_T0_SHDW_OTG_REG_BASE 0x0600 ///< D20F1 PSF base address (USB device controller: OTG)
+#define R_PCH_LP_PCR_PSF2_T0_SHDW_XHCI_REG_BASE 0x0700 ///< D20F0 PSF base address (XHCI)
+// PSF2 PCH-H Specific Base Address
+#define R_PCH_H_PCR_PSF2_T0_SHDW_OTG_REG_BASE 0x0200 ///< D20F1 PSF base address (USB device controller: OTG)
+#define R_PCH_H_PCR_PSF2_T0_SHDW_XHCI_REG_BASE 0x0300 ///< D20F0 PSF base address (XHCI)
+
+//
+// PSF3 PCRs (PID:PSF3)
+//
+#define R_PCH_PCR_PSF3_T0_SHDW_HECI3_REG_BASE 0x0100 ///< D16F4 PSF base address (IE: HECI3)
+#define R_PCH_PCR_PSF3_T0_SHDW_HECI2_REG_BASE 0x0200 ///< D16F1 PSF base address (IE: HECI2)
+#define R_PCH_PCR_PSF3_T0_SHDW_HECI1_REG_BASE 0x0400 ///< D16F0 PSF base address (IE: HECI1)
+#define R_PCH_PCR_PSF3_T0_SHDW_KT_REG_BASE 0x0500 ///< D16F3 PSF base address (IE: KT)
+#define R_PCH_PCR_PSF3_T0_SHDW_IDER_REG_BASE 0x0600 ///< D16F2 PSF base address (IE: IDER)
+#define R_PCH_PCR_PSF3_T0_SHDW_P2SB_REG_BASE 0x0700 ///< D31F1 PSF base address (P2SB)
+#define R_PCH_PCR_PSF3_T0_SHDW_TRACE_HUB_ACPI_REG_BASE 0x0800 ///< D20F4 PSF base address (TraceHub ACPI)
+#define R_PCH_PCR_PSF3_T0_SHDW_TRACE_HUB_REG_BASE 0x0900 ///< D31F7 PSF base address (TraceHub PCI)
+#define R_PCH_PCR_PSF3_T0_SHDW_LPC_REG_BASE 0x0A00 ///< D31F0 PSF base address (LPC)
+#define R_PCH_PCR_PSF3_T0_SHDW_SMBUS_REG_BASE 0x0B00 ///< D31F4 PSF base address (SMBUS)
+#define R_PCH_PCR_PSF3_T0_SHDW_PMC_REG_BASE 0x0E00 ///< D31F2 PSF base address (PMC)
+#define R_PCH_PCR_PSF3_T0_SHDW_SPI_SPI_REG_BASE 0x1300 ///< D31F5 PSF base address (SPI SPI)
+#define R_PCH_H_PCR_PSF3_T0_SHDW_GBE_REG_BASE 0x1600 ///< D31F6 PSF base address (GBE)
+#define R_PCH_PCR_PSF3_T0_SHDW_AUD_REG_BASE 0x1800 ///< D31F3 PSF base address (HDA, ADSP)
+#define R_PCH_PCR_PSF3_T0_SHDW_AUD_PCIEN 0x181C ///< D31F3 PCI Configuration space enable bits (HDA, ADSP)
+#define R_PCH_PCR_PSF3_T0_SHDW_MROM1_REG_BASE 0x1A00 ///< D17F1 PSF base address (MROM1)
+#define B_PCH_PCR_PSF3_T0_SHDW_AUD_PCIEN_FUNDIS BIT8 ///< D31F3 Function Disable
+#define R_PCH_PSF3_T0_SHDW_AUD_RS1_D24_F0_BASE 0x1700 ///< RS1D24F0 PSF base address (HDA)
+
+#define R_PCH_PCR_PSF3_T0_AGENT_FUNCTION_CONFIG_GBE_RS0_D31_F6 0x40F8 ///< GBE
+
+#define R_PCH_PCR_PSF3_PSF_MC_CONTROL_MCAST0_EOI 0x4058 ///< Multicast Control Register
+#define R_PCH_PCR_PSF3_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4064 ///< Destination ID
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPsth.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPsth.h
new file mode 100644
index 0000000000..2f30ef3b5d
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPsth.h
@@ -0,0 +1,66 @@
+/** @file
+ Register definition for PSTH component
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 2014 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_PSTH_H_
+#define _PCH_REGS_PSTH_H_
+
+//
+// Private chipset regsiter (Memory space) offset definition
+// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well.
+//
+
+//
+// PSTH and IO Trap PCRs (PID:PSTH)
+//
+#define R_PCH_PCR_PSTH_PSTHCTL 0x1D00 ///< PSTH control register
+#define B_PCH_PCR_PSTH_PSTHIOSFPTCGE BIT2 ///< PSTH IOSF primary trunk clock gating enable
+#define B_PCH_PCR_PSTH_PSTHIOSFSTCGE BIT1 ///< PSTH IOSF sideband trunk clock gating enable
+#define B_PCH_PCR_PSTH_PSTHDCGE BIT0 ///< PSTH dynamic clock gating enable
+#define R_PCH_PCR_PSTH_TRPST 0x1E00 ///< Trap status regsiter
+#define B_PCH_PCR_PSTH_TRPST_CTSS 0x0000000F ///< Cycle Trap SMI# Status mask
+#define R_PCH_PCR_PSTH_TRPC 0x1E10 ///< Trapped cycle
+#define B_PCH_PCR_PSTH_TRPC_RW BIT24 ///< Read/Write#: 1=Read, 0=Write
+#define B_PCH_PCR_PSTH_TRPC_AHBE 0x00000000000F0000 ///< Active high byte enables
+#define B_PCH_PCR_PSTH_TRPC_IOA 0x000000000000FFFC ///< Trap cycle I/O address
+#define R_PCH_PCR_PSTH_TRPD 0x1E18 ///< Trapped write data
+#define B_PCH_PCR_PSTH_TRPD_IOD 0x00000000FFFFFFFF ///< Trap cycle I/O data
+#define R_PCH_PCR_PSTH_TRPREG0 0x1E80 ///< IO Tarp 0 register
+#define R_PCH_PCR_PSTH_TRPREG1 0x1E88 ///< IO Tarp 1 register
+#define R_PCH_PCR_PSTH_TRPREG2 0x1E90 ///< IO Tarp 2 register
+#define R_PCH_PCR_PSTH_TRPREG3 0x1E98 ///< IO Tarp 3 register
+#define B_PCH_PCR_PSTH_TRPREG_RWM BIT17 ///< 49 - 32 for 32 bit access, Read/Write mask
+#define B_PCH_PCR_PSTH_TRPREG_RWIO BIT16 ///< 48 - 32 for 32 bit access, Read/Write#, 1=Read, 0=Write
+#define N_PCH_PCR_PSTH_TRPREG_RWIO 16 ///< 48 - 32 for 32 bit access, 16bit shift for Read/Write field
+#define N_PCH_PCR_PSTH_TRPREG_BEM (36 - 32)
+#define B_PCH_PCR_PSTH_TRPREG_BEM 0x000000F000000000 ///< Byte enable mask
+#define B_PCH_PCR_PSTH_TRPREG_BE 0x0000000F00000000 ///< Byte enable
+#define B_PCH_PCR_PSTH_TRPREG_AM 0x0000000000FC0000 ///< IO Address mask
+#define B_PCH_PCR_PSTH_TRPREG_AD 0x000000000000FFFC ///< IO Address
+#define B_PCH_PCR_PSTH_TRPREG_TSE BIT0 ///< Trap and SMI# Enable
+
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSata.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSata.h
new file mode 100644
index 0000000000..c031c4da76
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSata.h
@@ -0,0 +1,713 @@
+/** @file
+ Register names for PCH SATA controllers
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_SATA_H_
+#define _PCH_REGS_SATA_H_
+
+//
+// SATA Controller Registers (D23:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_SATA 23
+#define PCI_FUNCTION_NUMBER_PCH_SATA 0
+#define V_SATA_CFG_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+
+#define PCH_SATA_FIRST_CONTROLLER 1
+#define PCH_SATA_SECOND_CONTROLLER 2
+
+//
+// SKL PCH-LP SATA Device ID's
+//
+#define V_PCH_LP_SATA_DEVICE_ID_M_AHCI 0x9D03 ///< SATA Controller (AHCI) - Mobile
+#define V_PCH_LP_SATA_DEVICE_ID_M_RAID 0x9D05 ///< SATA Controller (RAID 0/1/5/10) - NOT premium - Mobile
+#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_ALTDIS 0x282A ///< SATA Controller (RAID 0/1/5/10) - NOT premium - Mobile - Alternate ID
+#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_PREM 0x9D07 ///< SATA Controller (RAID 0/1/5/10) - premium - Mobile
+#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_RRT 0x9D0F ///< SATA Controller (RAID 1/RRT Only) - Mobile
+
+//
+// SKL PCH-H SATA Device ID's
+//
+#define V_PCH_H_SATA_DEVICE_ID_D_AHCI 0xA102 ///< SATA Controller (AHCI)
+#define V_PCH_H_SATA_DEVICE_ID_D_AHCI_A0 0xA103 ///< SATA Controller (AHCI) - SPTH A0
+#define V_PCH_H_SATA_DEVICE_ID_D_RAID 0xA105 ///< SATA Controller (RAID 0/1/5/10) - NOT premium
+#define V_PCH_H_SATA_DEVICE_ID_D_RAID_ALTDIS 0x2822 ///< SATA Controller (RAID 0/1/5/10) - premium - Alternate ID
+#define V_PCH_H_SATA_DEVICE_ID_D_RAID_RSTE 0x2826 ///< SATA Controller (RAID 0/1/5/10) - RSTe of Server SKU
+#define V_PCH_H_SATA_DEVICE_ID_D_RAID_PREM 0xA107 ///< SATA Controller (RAID 0/1/5/10) - premium
+#define V_PCH_H_SATA_DEVICE_ID_D_RAID_RRT 0xA10F ///< SATA Controller (RAID 1/RRT Only)
+
+
+//
+// LBG PRODUCTION INCLUDING QUAL SAMPLES SATA Device ID's
+//
+#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_AHCI 0xA182 ///< Server AHCI Mode (Ports 0-5)
+#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID 0xA184 ///< Server RAID 0/1/5/10 - NOT premium
+#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID_PREMIUM 0xA186 ///< Server RAID 0/1/5/10 - premium
+#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID1 0xA18E ///< Server RAID 1/RRT Only
+
+//
+// LBG SSX (Super SKUs and Pre Production) SATA Device ID's
+//
+#define V_PCH_LBG_SATA_DEVICE_ID_D_AHCI 0xA202 ///< Server AHCI Mode (Ports 0-5)
+#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID 0xA204 ///< Server RAID 0/1/5/10 - NOT premium
+#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM 0xA206 ///< Server RAID 0/1/5/10 - premium
+#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID1 0xA20E ///< Server RAID 1/RRT Only
+
+//
+// LBG Alternate RST Device IDs
+//
+#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0 0x2822 ///< Server RAID 0/1/5/10 - premium - Alternate ID for RST
+#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1 0x2826 ///< Server RAID 0/1/5/10 - premium - Alternate ID for RSTe
+
+//
+// SATA Controller common Registers
+//
+#define R_PCH_SATA_PI_REGISTER 0x09
+#define B_PCH_SATA_PI_REGISTER_SNC BIT3
+#define B_PCH_SATA_PI_REGISTER_SNE BIT2
+#define B_PCH_SATA_PI_REGISTER_PNC BIT1
+#define B_PCH_SATA_PI_REGISTER_PNE BIT0
+#define V_PCH_SATA_SUB_CLASS_CODE_AHCI 0x06
+#define V_PCH_SATA_SUB_CLASS_CODE_RAID 0x04
+#define R_PCH_SATA_AHCI_BAR 0x24
+#define B_PCH_SATA_AHCI_BAR_BA 0xFFFFF800
+#define V_PCH_SATA_AHCI_BAR_LENGTH 0x800
+#define N_PCH_SATA_AHCI_BAR_ALIGNMENT 11
+#define V_PCH_SATA_AHCI_BAR_LENGTH_512K 0x80000
+#define N_PCH_SATA_AHCI_BAR_ALIGNMENT_512K 19
+#define B_PCH_SATA_AHCI_BAR_PF BIT3
+#define B_PCH_SATA_AHCI_BAR_TP (BIT2 | BIT1)
+#define B_PCH_SATA_AHCI_BAR_RTE BIT0
+#define R_PCH_SATA_PID 0x70
+#define B_PCH_SATA_PID_NEXT 0xFF00
+#define V_PCH_SATA_PID_NEXT_0 0xB000
+#define V_PCH_SATA_PID_NEXT_1 0xA800
+#define B_PCH_SATA_PID_CID 0x00FF
+#define R_PCH_SATA_PC 0x72
+#define S_PCH_SATA_PC 2
+#define B_PCH_SATA_PC_PME (BIT15 | BIT14 | BIT13 | BIT12 | BIT11)
+#define V_PCH_SATA_PC_PME_0 0x0000
+#define V_PCH_SATA_PC_PME_1 0x4000
+#define B_PCH_SATA_PC_D2_SUP BIT10
+#define B_PCH_SATA_PC_D1_SUP BIT9
+#define B_PCH_SATA_PC_AUX_CUR (BIT8 | BIT7 | BIT6)
+#define B_PCH_SATA_PC_DSI BIT5
+#define B_PCH_SATA_PC_PME_CLK BIT3
+#define B_PCH_SATA_PC_VER (BIT2 | BIT1 | BIT0)
+#define R_PCH_SATA_PMCS 0x74
+#define B_PCH_SATA_PMCS_PMES BIT15
+#define B_PCH_SATA_PMCS_PMEE BIT8
+#define B_PCH_SATA_PMCS_NSFRST BIT3
+#define V_PCH_SATA_PMCS_NSFRST_1 0x01
+#define V_PCH_SATA_PMCS_NSFRST_0 0x00
+#define B_PCH_SATA_PMCS_PS (BIT1 | BIT0)
+#define V_PCH_SATA_PMCS_PS_3 0x03
+#define V_PCH_SATA_PMCS_PS_0 0x00
+#define R_PCH_SATA_MID 0x80
+#define B_PCH_SATA_MID_NEXT 0xFF00
+#define B_PCH_SATA_MID_CID 0x00FF
+#define R_PCH_SATA_MC 0x82
+#define B_PCH_SATA_MC_C64 BIT7
+#define B_PCH_SATA_MC_MME (BIT6 | BIT5 | BIT4)
+#define V_PCH_SATA_MC_MME_4 0x04
+#define V_PCH_SATA_MC_MME_2 0x02
+#define V_PCH_SATA_MC_MME_1 0x01
+#define V_PCH_SATA_MC_MME_0 0x00
+#define B_PCH_SATA_MC_MMC (BIT3 | BIT2 | BIT1)
+#define V_PCH_SATA_MC_MMC_4 0x04
+#define V_PCH_SATA_MC_MMC_0 0x00
+#define B_PCH_SATA_MC_MSIE BIT0
+#define V_PCH_SATA_MC_MSIE_1 0x01
+#define V_PCH_SATA_MC_MSIE_0 0x00
+#define R_PCH_SATA_MA 0x84
+#define B_PCH_SATA_MA 0xFFFFFFFC
+#define R_PCH_SATA_MD 0x88
+#define B_PCH_SATA_MD_MSIMD 0xFFFF
+
+//
+// Sata Register for PCH-LP
+//
+#define R_PCH_LP_SATA_MAP 0x90
+#define B_PCH_LP_SATA_MAP_SPD (BIT10 | BIT9 | BIT8)
+#define N_PCH_LP_SATA_MAP_SPD 8
+#define B_PCH_LP_SATA_MAP_SPD2 BIT10
+#define B_PCH_LP_SATA_MAP_SPD1 BIT9
+#define B_PCH_LP_SATA_MAP_SPD0 BIT8
+#define B_PCH_LP_SATA_MAP_SMS_MASK BIT6
+#define N_PCH_LP_SATA_MAP_SMS_MASK 6
+#define V_PCH_LP_SATA_MAP_SMS_AHCI 0x0
+#define V_PCH_LP_SATA_MAP_SMS_RAID 0x1
+#define R_PCH_LP_SATA_PCS 0x92
+#define B_PCH_LP_SATA_PCS_OOB_RETRY BIT15
+#define B_PCH_LP_SATA_PCS_P2P BIT10
+#define B_PCH_LP_SATA_PCS_P1P BIT9
+#define B_PCH_LP_SATA_PCS_P0P BIT8
+#define B_PCH_LP_SATA_PCS_PXE_MASK (BIT2 | BIT1 | BIT0)
+#define B_PCH_LP_SATA_PCS_P2E BIT2
+#define B_PCH_LP_SATA_PCS_P1E BIT1
+#define B_PCH_LP_SATA_PCS_P0E BIT0
+#define R_PCH_LP_SATA_SCLKGC 0x94
+#define B_PCH_LP_SATA_SCLKGC_PCD (BIT26 | BIT25 | BIT24)
+#define B_PCH_LP_SATA_SCLKGC_PORT2_PCD BIT26
+#define B_PCH_LP_SATA_SCLKGC_PORT1_PCD BIT25
+#define B_PCH_LP_SATA_SCLKGC_PORT0_PCD BIT24
+#define R_PCH_LP_SATA_98 0x98
+
+//
+// Sata Register for PCH-H
+//
+#define R_PCH_H_SATA_MAP 0x90
+#define B_PCH_H_SATA_MAP_SPD 0xFF0000
+#define N_PCH_H_SATA_MAP_SPD 16
+#define B_PCH_H_SATA_MAP_SPD7 BIT23
+#define B_PCH_H_SATA_MAP_SPD6 BIT22
+#define B_PCH_H_SATA_MAP_SPD5 BIT21
+#define B_PCH_H_SATA_MAP_SPD4 BIT20
+#define B_PCH_H_SATA_MAP_SPD3 BIT19
+#define B_PCH_H_SATA_MAP_SPD2 BIT18
+#define B_PCH_H_SATA_MAP_SPD1 BIT17
+#define B_PCH_H_SATA_MAP_SPD0 BIT16
+#define B_PCH_H_SATA_MAP_PCD 0xFF
+#define B_PCH_H_SATA_MAP_PORT7_PCD BIT7
+#define B_PCH_H_SATA_MAP_PORT6_PCD BIT6
+#define B_PCH_H_SATA_MAP_PORT5_PCD BIT5
+#define B_PCH_H_SATA_MAP_PORT4_PCD BIT4
+#define B_PCH_H_SATA_MAP_PORT3_PCD BIT3
+#define B_PCH_H_SATA_MAP_PORT2_PCD BIT2
+#define B_PCH_H_SATA_MAP_PORT1_PCD BIT1
+#define B_PCH_H_SATA_MAP_PORT0_PCD BIT0
+#define R_PCH_H_SATA_PCS 0x94
+#define B_PCH_H_SATA_PCS_P7P BIT23
+#define B_PCH_H_SATA_PCS_P6P BIT22
+#define B_PCH_H_SATA_PCS_P5P BIT21
+#define B_PCH_H_SATA_PCS_P4P BIT20
+#define B_PCH_H_SATA_PCS_P3P BIT19
+#define B_PCH_H_SATA_PCS_P2P BIT18
+#define B_PCH_H_SATA_PCS_P1P BIT17
+#define B_PCH_H_SATA_PCS_P0P BIT16
+#define B_PCH_H_SATA_PCS_PXE_MASK 0xFF
+#define B_PCH_H_SATA_PCS_P7E BIT7
+#define B_PCH_H_SATA_PCS_P6E BIT6
+#define B_PCH_H_SATA_PCS_P5E BIT5
+#define B_PCH_H_SATA_PCS_P4E BIT4
+#define B_PCH_H_SATA_PCS_P3E BIT3
+#define B_PCH_H_SATA_PCS_P2E BIT2
+#define B_PCH_H_SATA_PCS_P1E BIT1
+#define B_PCH_H_SATA_PCS_P0E BIT0
+
+#define R_PCH_SATA_SATAGC 0x9C
+#define B_PCH_H_SATA_SATAGC_SMS_MASK BIT16
+#define N_PCH_H_SATA_SATAGC_SMS_MASK 16
+#define V_PCH_H_SATA_SATAGC_SMS_AHCI 0x0
+#define V_PCH_H_SATA_SATAGC_SMS_RAID 0x1
+#define B_PCH_SATA_SATAGC_AIE BIT7
+#define B_PCH_SATA_SATAGC_AIES BIT6
+#define B_PCH_SATA_SATAGC_MSS (BIT4 | BIT3)
+#define V_PCH_SATA_SATAGC_MSS_8K 0x2
+#define N_PCH_SATA_SATAGC_MSS 3
+#define B_PCH_SATA_SATAGC_ASSEL (BIT2 | BIT1 | BIT0)
+
+#define V_PCH_SATA_SATAGC_ASSEL_2K 0x0
+#define V_PCH_SATA_SATAGC_ASSEL_16K 0x1
+#define V_PCH_SATA_SATAGC_ASSEL_32K 0x2
+#define V_PCH_SATA_SATAGC_ASSEL_64K 0x3
+#define V_PCH_SATA_SATAGC_ASSEL_128K 0x4
+#define V_PCH_SATA_SATAGC_ASSEL_256K 0x5
+#define V_PCH_SATA_SATAGC_ASSEL_512K 0x6
+
+#define R_PCH_SATA_SIRI 0xA0
+#define R_PCH_SATA_STRD 0xA4
+#define R_PCH_SATA_SIR_50 0x50
+#define R_PCH_SATA_SIR_54 0x54
+#define R_PCH_SATA_SIR_58 0x58
+#define R_PCH_SATA_SIR_5C 0x5C
+#define R_PCH_SATA_SIR_60 0x60
+#define R_PCH_SATA_SIR_64 0x64
+#define R_PCH_SATA_SIR_68 0x68
+#define R_PCH_SATA_SIR_6C 0x6C
+#define R_PCH_SATA_SIR_70 0x70
+#define R_PCH_SATA_SIR_80 0x80
+#define R_PCH_SATA_SIR_84 0x84
+#define R_PCH_SATA_SIR_8C 0x8C
+#define R_PCH_SATA_SIR_90 0x90
+#define R_PCH_SATA_SIR_98 0x98
+#define R_PCH_SATA_SIR_9C 0x9C
+#define R_PCH_SATA_SIR_A0 0xA0
+#define R_PCH_SATA_SIR_A4 0xA4
+#define R_PCH_SATA_SIR_A8 0xA8
+#define R_PCH_SATA_SIR_C8 0xC8
+#define R_PCH_SATA_SIR_CC 0xCC
+#define R_PCH_SATA_SIR_D0 0xD0
+#define R_PCH_SATA_SIR_D4 0xD4
+#define B_PCH_SATA_STRD_DTA 0xFFFFFFFF
+#define B_PCH_SATA_SIR_CTM4_ORM BIT6
+#define R_PCH_SATA_CR0 0xA8
+#define B_PCH_SATA_CR0_MAJREV 0x00F00000
+#define B_PCH_SATA_CR0_MINREV 0x000F0000
+#define B_PCH_SATA_CR0_NEXT 0x0000FF00
+#define B_PCH_SATA_CR0_CAP 0x000000FF
+#define R_PCH_SATA_CR1 0xAC
+#define B_PCH_SATA_CR1_BAROFST 0xFFF0
+#define B_PCH_SATA_CR1_BARLOC 0x000F
+#define R_PCH_SATA_FLR_CID 0xB0
+#define B_PCH_SATA_FLR_CID_NEXT 0xFF00
+#define B_PCH_SATA_FLR_CID 0x00FF
+#define V_PCH_SATA_FLR_CID_1 0x0009
+#define V_PCH_SATA_FLR_CID_0 0x0013
+#define R_PCH_SATA_FLR_CLV 0xB2
+#define B_PCH_SATA_FLR_CLV_FLRC_FLRCSSEL_0 BIT9
+#define B_PCH_SATA_FLR_CLV_TXPC_FLRCSSEL_0 BIT8
+#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_0 0x00FF
+#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_1 0x00FF
+#define V_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL 0x0006
+#define R_PCH_SATA_FLRC 0xB4
+#define B_PCH_SATA_FLRC_TXP BIT8
+#define B_PCH_SATA_FLRC_INITFLR BIT0
+#define R_PCH_SATA_SP 0xC0
+#define B_PCH_SATA_SP 0xFFFFFFFF
+#define R_PCH_SATA_MXID 0xD0
+#define N_PCH_SATA_MXID_NEXT 8
+
+#define R_PCH_SATA_BFCS 0xE0
+#define B_PCH_SATA_BFCS_P7BFI BIT17
+#define B_PCH_SATA_BFCS_P6BFI BIT16
+#define B_PCH_SATA_BFCS_P5BFI BIT15
+#define B_PCH_SATA_BFCS_P4BFI BIT14
+#define B_PCH_SATA_BFCS_P3BFI BIT13
+#define B_PCH_SATA_BFCS_P2BFI BIT12
+#define B_PCH_SATA_BFCS_P2BFS BIT11
+#define B_PCH_SATA_BFCS_P2BFF BIT10
+#define B_PCH_SATA_BFCS_P1BFI BIT9
+#define B_PCH_SATA_BFCS_P0BFI BIT8
+#define B_PCH_SATA_BFCS_BIST_FIS_T BIT7
+#define B_PCH_SATA_BFCS_BIST_FIS_A BIT6
+#define B_PCH_SATA_BFCS_BIST_FIS_S BIT5
+#define B_PCH_SATA_BFCS_BIST_FIS_L BIT4
+#define B_PCH_SATA_BFCS_BIST_FIS_F BIT3
+#define B_PCH_SATA_BFCS_BIST_FIS_P BIT2
+#define R_PCH_SATA_BFTD1 0xE4
+#define B_PCH_SATA_BFTD1 0xFFFFFFFF
+#define R_PCH_SATA_BFTD2 0xE8
+#define B_PCH_SATA_BFTD2 0xFFFFFFFF
+
+#define R_PCH_SATA_VS_CAP 0xA4
+#define B_PCH_SATA_VS_CAP_NRMBE BIT0 ///< NVM Remap Memory BAR Enable
+#define B_PCH_SATA_VS_CAP_MSL 0x1FFE ///< Memory Space Limit
+#define N_PCH_SATA_VS_CAP_MSL 1
+#define V_PCH_SATA_VS_CAP_MSL 0x1EF ///< Memory Space Limit Field Value
+#define B_PCH_SATA_VS_CAP_NRMO 0xFFF0000 ///< NVM Remapped Memory Offset
+#define N_PCH_SATA_VS_CAP_NRMO 16
+#define V_PCH_SATA_VS_CAP_NRMO 0x10 ///< NVM Remapped Memory Offset Field Value
+
+//
+// RST PCIe Storage Remapping Registers
+//
+#define R_PCH_RST_PCIE_STORAGE_RCR 0x800 ///< Remap Capability Register
+#define B_PCH_RST_PCIE_STORAGE_RCR_NRS (BIT2|BIT1|BIT0) ///< Number of Remapping Supported
+#define B_PCH_RST_PCIE_STORAGE_RCR_NRS_CR1 BIT0 ///< Number of Remapping Supported (RST PCIe Storage Cycle Router #1)
+#define R_PCH_RST_PCIE_STORAGE_AMXC 0x808 ///< AHCI MSI-X Configuration
+#define B_PCH_RST_PCIE_STORAGE_AMXC_AMXV 0x7FF ///< AHCI MSI-X Vector
+#define R_PCH_RST_PCIE_STORAGE_SPR 0x80C ///< Scratch Pad Register
+#define R_PCH_RST_PCIE_STORAGE_CR1_DCC 0x880 ///< CR#1 Device Class Code
+#define N_PCH_RST_PCIE_STORAGE_CR1_DCC_SCC 8
+#define N_PCH_RST_PCIE_STORAGE_CR1_DCC_BCC 16
+#define B_PCH_RST_PCIE_STORAGE_CR1_DCC_DT BIT31 ///< Device Type
+#define R_PCH_RST_PCIE_STORAGE_CR1_DMBL 0x884 ///< CR#1 Device Memory BAR Length
+#define R_PCH_RST_PCIE_STORAGE_CR1_DMXC 0x888 ///< CR#1 Device MSI-X Configuration
+#define N_PCH_RST_PCIE_STORAGE_CR1_DMXC_MXEV 16
+#define V_PCH_RST_PCIE_STORAGE_REMAP_CONFIG_CR 0x80 ///< Remapped Configuration for RST PCIe Storage Cycle Router #n
+#define V_PCH_RST_PCIE_STORAGE_REMAP_RP_OFFSET 0x100 ///< Remapped Root Port Offset Value
+#define R_PCH_RST_PCIE_STORAGE_GCR 0x300 ///< General Configuration Register
+#define R_PCH_RST_PCIE_STORAGE_CCFG 0x1D0 ///< Port Configuration Register
+#define B_PCH_RST_PCIE_STORAGE_GCR_CRE BIT0 ///< RST PCIe Storage Cycle Router Enable
+#define B_PCH_RST_PCIE_STORAGE_GCR_PLS 0x1FFFFE ///< PCIe Lane Selected Field
+#define B_PCH_RST_PCIE_STORAGE_GCR_PNCAIDL BIT29 ///< Configuration Access Index/Data Lockdown
+#define B_PCH_RST_PCIE_STORAGE_GCR_RCL BIT30 ///< Remapping Configuration Lockdown
+#define B_PCH_RST_PCIE_STORAGE_GCR_CREL BIT31 ///< RST PCIe Storage Cycle Router Enable Lockdown
+#define R_PCH_RST_PCIE_STORAGE_GSR 0x304 ///< General Status Register
+#define B_PCH_RST_PCIE_STORAGE_GSR_PLRC 0x1FFFFE ///< PCIe Lane Remap Capable Field
+#define B_PCH_RST_PCIE_STORAGE_GSR_PCCS BIT30 ///< Port Configuration Check Status
+#define B_PCH_RST_PCIE_STORAGE_GSR_PCCD BIT31 ///< Port Configuration Check Disable
+#define R_PCH_RST_PCIE_STORAGE_CAIR 0x308 ///< Configuration Access Index Register
+#define R_PCH_RST_PCIE_STORAGE_CADR 0x30C ///< Configuration Access Data Register
+#define R_PCH_RST_PCIE_STORAGE_MBRC 0x310 ///< Memory BAR Remap Configuration
+#define B_PCH_RST_PCIE_STORAGE_MBRC_TMB (BIT19|BIT18|BIT17|BIT16) ///< Memory BAR Remap Configuration Target Memory BAR
+#define N_PCH_RST_PCIE_STORAGE_MBRC_TMB 16
+#define V_PCH_RST_PCIE_STORAGE_MBRC_TMB_BAR0 0x4 ///< Memory BAR Remap Configuration Target Memory BAR - BAR0
+#define V_PCH_RST_PCIE_STORAGE_MBRC_TMB_BAR5 0x9 ///< Memory BAR Remap Configuration Target Memory BAR - BAR5
+#define B_PCH_RST_PCIE_STORAGE_MBRC_TT BIT20 ///< Remap Configuration Target Type
+#define B_PCH_RST_PCIE_STORAGE_MBRC_RE BIT31 ///< Remap Configuration Remap Enable
+#define R_PCH_RST_PCIE_STORAGE_IOBRSC 0x320 ///< I/O BAR Remap Source Configuration
+#define B_PCH_RST_PCIE_STORAGE_IOBRSC_RE BIT31 ///< I/O BAR Remap Source Configuration Remap Enable
+#define R_PCH_RST_PCIE_STORAGE_AIDPCRC 0x338 ///< AHCI Index/Data Pair Capability Remap Configuration
+#define B_PCH_RST_PCIE_STORAGE_AIDPCRC_TCSO 0xFF0000 ///< AHCI Index/Data Pair Capability Remap Configuration Target Capability Structure OffsBet
+#define N_PCH_RST_PCIE_STORAGE_AIDPCRC_TCSO 16
+#define B_PCH_RST_PCIE_STORAGE_AIDPCRC_RE BIT31 ///< AHCI Index/Data Pair Capability Remap Configuration Remap Enable
+#define R_PCH_RST_PCIE_STORAGE_MXCRC 0x33C ///< MSI-X Capability Remap Configuration
+#define B_PCH_RST_PCIE_STORAGE_MXCRCC_TCSO 0xFF0000 ///< MSI-X Capability Remap Configuration Target Capability Structure Offset
+#define N_PCH_RST_PCIE_STORAGE_MXCRCC_TCSO 16
+#define B_PCH_RST_PCIE_STORAGE_MXCRC_RE BIT31 ///< MSI-X Capability Remap Configuration Remap Enable
+#define R_PCH_RST_PCIE_STORAGE_MXTRC 0x340 ///< MSI-X Table Remap Configuration
+#define B_PCH_RST_PCIE_STORAGE_MXTRC_TBIR 0x07 ///< MSI-X Table Remap Configuration Table BIR
+#define B_PCH_RST_PCIE_STORAGE_MXTRC_TO 0xFFFFFFF8 ///< MSI-X Table Remap Configuration Table Offset
+#define R_PCH_RST_PCIE_STORAGE_MXTBAR 0x344 ///< MSI-X Table Base Address Register
+#define B_PCH_RST_PCIE_STORAGE_MXTBAR_TBAV BIT0 ///< MSI-X Table Base Address Register Table Base Address Valid
+#define R_PCH_RST_PCIE_STORAGE_MXPRC 0x348 ///< MSI-X PBA Remap Configuration
+#define B_PCH_RST_PCIE_STORAGE_MXPRC_TBIR 0x07 ///< MSI-X PBA Remap Configuration Table BIR
+#define B_PCH_RST_PCIE_STORAGE_MXPRC_TO 0xFFFFFFF8 ///< MSI-X PBA Remap Configuration Table Offset
+#define R_PCH_RST_PCIE_STORAGE_MXPBAR 0x34C ///< MSI-X PBA Base Address Register
+#define B_PCH_RST_PCIE_STORAGE_MXPBAR_TBAV BIT0 ///< MSI-X PBA Base Address Register Table Base Address Valid
+#define R_PCH_RST_PCIE_STORAGE_NRDF 0x350 ///< NVM Remapping Device:Function
+#define R_PCH_RST_PCIE_STORAGE_EGCR 0x354 ///< Extended General Configuration Register
+#define B_PCH_RST_PCIE_STORAGE_EGCR_CRDCGE BIT16 ///< RST PCIe Storage Cycle Router Dynamic Clock Gating Enable
+#define B_PCH_RST_PCIE_STORAGE_EGCR_CRTCGE BIT17 ///< RST PCIe Storage Cycle Router Trunk Clock Gating Enable
+#define B_PCH_RST_PCIE_STORAGE_EGCR_ICAS BIT19 ///< IOSF CLKREQ Assertion Select
+#define B_PCH_RST_PCIE_STORAGE_EGCR_TSCAS BIT20 ///< To SATA CLKREQ Assertion Select
+#define R_PCH_RST_PCIE_STORAGE_SAPI 0x358 ///< Shadowed AHCI Ports Implemented
+#define R_PCH_RST_PCIE_STORAGE_CRGC 0xFC0 ///< RST PCIe Storage Cycle Router Global Control
+#define B_PCH_RST_PCIE_STORAGE_CRGC_CRAS (BIT1|BIT0) ///< RST PCIe Storage Cycle Router Global Control Cycle Router Accessibility Select
+
+//
+// AHCI BAR Area related Registers
+//
+#define R_PCH_SATA_AHCI_CAP 0x0
+#define B_PCH_SATA_AHCI_CAP_S64A BIT31
+#define B_PCH_SATA_AHCI_CAP_SCQA BIT30
+#define B_PCH_SATA_AHCI_CAP_SSNTF BIT29
+#define B_PCH_SATA_AHCI_CAP_SIS BIT28 ///< Supports Interlock Switch
+#define B_PCH_SATA_AHCI_CAP_SSS BIT27 ///< Supports Stagger Spin-up
+#define B_PCH_SATA_AHCI_CAP_SALP BIT26
+#define B_PCH_SATA_AHCI_CAP_SAL BIT25
+#define B_PCH_SATA_AHCI_CAP_SCLO BIT24 ///< Supports Command List Override
+#define B_PCH_SATA_AHCI_CAP_ISS_MASK (BIT23 | BIT22 | BIT21 | BIT20)
+#define N_PCH_SATA_AHCI_CAP_ISS 20 ///< Interface Speed Support
+#define V_PCH_SATA_AHCI_CAP_ISS_1_5_G 0x01
+#define V_PCH_SATA_AHCI_CAP_ISS_3_0_G 0x02
+#define V_PCH_SATA_AHCI_CAP_ISS_6_0_G 0x03
+#define B_PCH_SATA_AHCI_CAP_SNZO BIT19
+#define B_PCH_SATA_AHCI_CAP_SAM BIT18
+#define B_PCH_SATA_AHCI_CAP_PMS BIT17 ///< Supports Port Multiplier
+#define B_PCH_SATA_AHCI_CAP_PMD BIT15 ///< PIO Multiple DRQ Block
+#define B_PCH_SATA_AHCI_CAP_SSC BIT14
+#define B_PCH_SATA_AHCI_CAP_PSC BIT13
+#define B_PCH_SATA_AHCI_CAP_NCS 0x1F00
+#define B_PCH_SATA_AHCI_CAP_CCCS BIT7
+#define B_PCH_SATA_AHCI_CAP_EMS BIT6
+#define B_PCH_SATA_AHCI_CAP_SXS BIT5 ///< External SATA is supported
+#define B_PCH_SATA_AHCI_CAP_NPS 0x001F
+
+#define R_PCH_SATA_AHCI_GHC 0x04
+#define B_PCH_SATA_AHCI_GHC_AE BIT31
+#define B_PCH_SATA_AHCI_GHC_MRSM BIT2
+#define B_PCH_SATA_AHCI_GHC_IE BIT1
+#define B_PCH_SATA_AHCI_GHC_HR BIT0
+
+#define R_PCH_SATA_AHCI_IS 0x08
+#define B_PCH_SATA_AHCI_IS_PORT7 BIT7
+#define B_PCH_SATA_AHCI_IS_PORT6 BIT6
+#define B_PCH_SATA_AHCI_IS_PORT5 BIT5
+#define B_PCH_SATA_AHCI_IS_PORT4 BIT4
+#define B_PCH_SATA_AHCI_IS_PORT3 BIT3
+#define B_PCH_SATA_AHCI_IS_PORT2 BIT2
+#define B_PCH_SATA_AHCI_IS_PORT1 BIT1
+#define B_PCH_SATA_AHCI_IS_PORT0 BIT0
+#define R_SATA_MEM_AHCI_PI 0x0C
+#define B_PCH_H_SATA_PORT_MASK 0xFF
+#define B_PCH_LP_SATA_PORT_MASK 0x03
+#define B_PCH_SATA_PORT7_IMPLEMENTED BIT7
+#define B_PCH_SATA_PORT6_IMPLEMENTED BIT6
+#define B_PCH_SATA_PORT5_IMPLEMENTED BIT5
+#define B_PCH_SATA_PORT4_IMPLEMENTED BIT4
+#define B_PCH_SATA_PORT3_IMPLEMENTED BIT3
+#define B_PCH_SATA_PORT2_IMPLEMENTED BIT2
+#define B_PCH_SATA_PORT1_IMPLEMENTED BIT1
+#define B_PCH_SATA_PORT0_IMPLEMENTED BIT0
+#define R_PCH_SATA_AHCI_VS 0x10
+#define B_PCH_SATA_AHCI_VS_MJR 0xFFFF0000
+#define B_PCH_SATA_AHCI_VS_MNR 0x0000FFFF
+#define R_PCH_SATA_AHCI_EM_LOC 0x1C
+#define B_PCH_SATA_AHCI_EM_LOC_OFST 0xFFFF0000
+#define B_PCH_SATA_AHCI_EM_LOC_SZ 0x0000FFFF
+#define R_PCH_SATA_AHCI_EM_CTRL 0x20
+#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_ALHD BIT26
+#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_XMT BIT25
+#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_SMB BIT24
+#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SGPIO BIT19
+#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SES2 BIT18
+#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SAFTE BIT17
+#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_LED BIT16
+#define B_PCH_SATA_AHCI_EM_CTRL_RST BIT9
+#define B_PCH_SATA_AHCI_EM_CTRL_CTL_TM BIT8
+#define B_PCH_SATA_AHCI_EM_CTRL_STS_MR BIT0
+#define R_PCH_SATA_AHCI_CAP2 0x24
+#define B_PCH_SATA_AHCI_CAP2_DESO BIT5
+#define B_PCH_SATA_AHCI_CAP2_SADM BIT4
+#define B_PCH_SATA_AHCI_CAP2_SDS BIT3
+#define B_PCH_SATA_AHCI_CAP2_APST BIT2 ///< Automatic Partial to Slumber Transitions
+#define R_PCH_SATA_AHCI_VSP 0xA0
+#define B_PCH_SATA_AHCI_VSP_SLPD BIT0
+#define R_PCH_SATA_AHCI_RSTF 0xC8 ///< RST Feature Capabilities
+#define B_PCH_SATA_AHCI_RSTF_OUD (BIT11 | BIT10)
+#define N_PCH_SATA_AHCI_RSTF_OUD 10
+#define B_PCH_SATA_AHCI_RSTF_SEREQ BIT9
+#define B_PCH_SATA_AHCI_RSTF_IROES BIT8
+#define B_PCH_SATA_AHCI_RSTF_LEDL BIT7
+#define B_PCH_SATA_AHCI_RSTF_HDDLK BIT6
+#define B_PCH_SATA_AHCI_RSTF_IRSTOROM BIT5
+#define B_PCH_SATA_AHCI_RSTF_RSTE BIT4
+#define B_PCH_SATA_AHCI_RSTF_R5E BIT3
+#define B_PCH_SATA_AHCI_RSTF_R10E BIT2
+#define B_PCH_SATA_AHCI_RSTF_R1E BIT1
+#define B_PCH_SATA_AHCI_RSTF_R0E BIT0
+#define B_PCH_SATA_AHCI_RSTF_LOWBYTES 0x1FF
+#define R_PCH_SATA_AHCI_P0CLB 0x100
+#define R_PCH_SATA_AHCI_P1CLB 0x180
+#define R_PCH_SATA_AHCI_P2CLB 0x200
+#define R_PCH_SATA_AHCI_P3CLB 0x280
+#define R_PCH_SATA_AHCI_P4CLB 0x300
+#define R_PCH_SATA_AHCI_P5CLB 0x380
+#define R_PCH_SATA_AHCI_P6CLB 0x400
+#define R_PCH_SATA_AHCI_P7CLB 0x480
+#define B_PCH_SATA_AHCI_PXCLB 0xFFFFFC00
+#define R_PCH_SATA_AHCI_P0CLBU 0x104
+#define R_PCH_SATA_AHCI_P1CLBU 0x184
+#define R_PCH_SATA_AHCI_P2CLBU 0x204
+#define R_PCH_SATA_AHCI_P3CLBU 0x284
+#define R_PCH_SATA_AHCI_P4CLBU 0x304
+#define R_PCH_SATA_AHCI_P5CLBU 0x384
+#define R_PCH_SATA_AHCI_P6CLBU 0x404
+#define R_PCH_SATA_AHCI_P7CLBU 0x484
+#define B_PCH_SATA_AHCI_PXCLBU 0xFFFFFFFF
+#define R_PCH_SATA_AHCI_P0FB 0x108
+#define R_PCH_SATA_AHCI_P1FB 0x188
+#define R_PCH_SATA_AHCI_P2FB 0x208
+#define R_PCH_SATA_AHCI_P3FB 0x288
+#define R_PCH_SATA_AHCI_P4FB 0x308
+#define R_PCH_SATA_AHCI_P5FB 0x388
+#define R_PCH_SATA_AHCI_P6FB 0x408
+#define R_PCH_SATA_AHCI_P7FB 0x488
+#define B_PCH_SATA_AHCI_PXFB 0xFFFFFF00
+#define R_PCH_SATA_AHCI_P0FBU 0x10C
+#define R_PCH_SATA_AHCI_P1FBU 0x18C
+#define R_PCH_SATA_AHCI_P2FBU 0x20C
+#define R_PCH_SATA_AHCI_P3FBU 0x28C
+#define R_PCH_SATA_AHCI_P4FBU 0x30C
+#define R_PCH_SATA_AHCI_P5FBU 0x38C
+#define R_PCH_SATA_AHCI_P6FBU 0x40C
+#define R_PCH_SATA_AHCI_P7FBU 0x48C
+#define B_PCH_SATA_AHCI_PXFBU 0xFFFFFFFF
+#define R_PCH_SATA_AHCI_P0IS 0x110
+#define R_PCH_SATA_AHCI_P1IS 0x190
+#define R_PCH_SATA_AHCI_P2IS 0x210
+#define R_PCH_SATA_AHCI_P3IS 0x290
+#define R_PCH_SATA_AHCI_P4IS 0x310
+#define R_PCH_SATA_AHCI_P5IS 0x390
+#define R_PCH_SATA_AHCI_P6IS 0x410
+#define R_PCH_SATA_AHCI_P7IS 0x490
+#define B_PCH_SATA_AHCI_PXIS_CPDS BIT31
+#define B_PCH_SATA_AHCI_PXIS_TFES BIT30
+#define B_PCH_SATA_AHCI_PXIS_HBFS BIT29
+#define B_PCH_SATA_AHCI_PXIS_HBDS BIT28
+#define B_PCH_SATA_AHCI_PXIS_IFS BIT27
+#define B_PCH_SATA_AHCI_PXIS_INFS BIT26
+#define B_PCH_SATA_AHCI_PXIS_OFS BIT24
+#define B_PCH_SATA_AHCI_PXIS_IPMS BIT23
+#define B_PCH_SATA_AHCI_PXIS_PRCS BIT22
+#define B_PCH_SATA_AHCI_PXIS_DIS BIT7
+#define B_PCH_SATA_AHCI_PXIS_PCS BIT6
+#define B_PCH_SATA_AHCI_PXIS_DPS BIT5
+#define B_PCH_SATA_AHCI_PXIS_UFS BIT4
+#define B_PCH_SATA_AHCI_PXIS_SDBS BIT3
+#define B_PCH_SATA_AHCI_PXIS_DSS BIT2
+#define B_PCH_SATA_AHCI_PXIS_PSS BIT1
+#define B_PCH_SATA_AHCI_PXIS_DHRS BIT0
+#define R_PCH_SATA_AHCI_P0IE 0x114
+#define R_PCH_SATA_AHCI_P1IE 0x194
+#define R_PCH_SATA_AHCI_P2IE 0x214
+#define R_PCH_SATA_AHCI_P3IE 0x294
+#define R_PCH_SATA_AHCI_P4IE 0x314
+#define R_PCH_SATA_AHCI_P5IE 0x394
+#define R_PCH_SATA_AHCI_P6IE 0x414
+#define R_PCH_SATA_AHCI_P7IE 0x494
+#define B_PCH_SATA_AHCI_PXIE_CPDE BIT31
+#define B_PCH_SATA_AHCI_PXIE_TFEE BIT30
+#define B_PCH_SATA_AHCI_PXIE_HBFE BIT29
+#define B_PCH_SATA_AHCI_PXIE_HBDE BIT28
+#define B_PCH_SATA_AHCI_PXIE_IFE BIT27
+#define B_PCH_SATA_AHCI_PXIE_INFE BIT26
+#define B_PCH_SATA_AHCI_PXIE_OFE BIT24
+#define B_PCH_SATA_AHCI_PXIE_IPME BIT23
+#define B_PCH_SATA_AHCI_PXIE_PRCE BIT22
+#define B_PCH_SATA_AHCI_PXIE_DIE BIT7
+#define B_PCH_SATA_AHCI_PXIE_PCE BIT6
+#define B_PCH_SATA_AHCI_PXIE_DPE BIT5
+#define B_PCH_SATA_AHCI_PXIE_UFIE BIT4
+#define B_PCH_SATA_AHCI_PXIE_SDBE BIT3
+#define B_PCH_SATA_AHCI_PXIE_DSE BIT2
+#define B_PCH_SATA_AHCI_PXIE_PSE BIT1
+#define B_PCH_SATA_AHCI_PXIE_DHRE BIT0
+#define R_PCH_SATA_AHCI_P0CMD 0x118
+#define R_PCH_SATA_AHCI_P1CMD 0x198
+#define R_PCH_SATA_AHCI_P2CMD 0x218
+#define R_PCH_SATA_AHCI_P3CMD 0x298
+#define R_PCH_SATA_AHCI_P4CMD 0x318
+#define R_PCH_SATA_AHCI_P5CMD 0x398
+#define R_PCH_SATA_AHCI_P6CMD 0x418
+#define R_PCH_SATA_AHCI_P7CMD 0x498
+#define B_PCH_SATA_AHCI_PxCMD_ICC (BIT31 | BIT30 | BIT29 | BIT28)
+#define B_PCH_SATA_AHCI_PxCMD_MASK (BIT27 | BIT26 | BIT22 | BIT21 | BIT19 | BIT18)
+#define B_PCH_SATA_AHCI_PxCMD_ASP BIT27
+#define B_PCH_SATA_AHCI_PxCMD_ALPE BIT26
+#define B_PCH_SATA_AHCI_PxCMD_DLAE BIT25
+#define B_PCH_SATA_AHCI_PxCMD_ATAPI BIT24
+#define B_PCH_SATA_AHCI_PxCMD_APSTE BIT23
+#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1
+#define R_PCH_SATA_AHCI_P0DEVSLP 0x144
+#define R_PCH_SATA_AHCI_P1DEVSLP 0x1C4
+#define R_PCH_SATA_AHCI_P2DEVSLP 0x244
+#define R_PCH_SATA_AHCI_P3DEVSLP 0x2C4
+#define R_PCH_SATA_AHCI_P4DEVSLP 0x344
+#define R_PCH_SATA_AHCI_P5DEVSLP 0x3C4
+#define R_PCH_SATA_AHCI_P6DEVSLP 0x444
+#define R_PCH_SATA_AHCI_P7DEVSLP 0x4C4
+#define B_PCH_SATA_AHCI_PxDEVSLP_DSP BIT1
+#define B_PCH_SATA_AHCI_PxDEVSLP_ADSE BIT0
+#define B_PCH_SATA_AHCI_PxDEVSLP_DITO_MASK 0x01FF8000
+#define V_PCH_SATA_AHCI_PxDEVSLP_DITO_625 0x01388000
+#define B_PCH_SATA_AHCI_PxDEVSLP_DM_MASK 0x1E000000
+#define V_PCH_SATA_AHCI_PxDEVSLP_DM_16 0x1E000000
+#define B_PCH_SATA_AHCI_PxCMD_ESP BIT21 ///< Used with an external SATA device
+#define B_PCH_SATA_AHCI_PxCMD_MPSP BIT19 ///< Mechanical Switch Attached to Port
+#define B_PCH_SATA_AHCI_PxCMD_HPCP BIT18 ///< Hotplug capable
+#define B_PCH_SATA_AHCI_PxCMD_CR BIT15
+#define B_SATA_MEM_AHCI_PxCMD_FR BIT14
+#define B_PCH_SATA_AHCI_PxCMD_ISS BIT13
+#define B_PCH_SATA_AHCI_PxCMD_CCS 0x00001F00
+#define B_SATA_MEM_AHCI_PxCMD_FRE BIT4
+#define B_PCH_SATA_AHCI_PxCMD_CLO BIT3
+#define B_PCH_SATA_AHCI_PxCMD_POD BIT2
+#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1
+#define B_PCH_SATA_AHCI_PxCMD_ST BIT0
+#define R_PCH_SATA_AHCI_P0TFD 0x120
+#define R_PCH_SATA_AHCI_P1TFD 0x1A0
+#define R_PCH_SATA_AHCI_P2TFD 0x220
+#define R_PCH_SATA_AHCI_P3TFD 0x2A0
+#define R_PCH_SATA_AHCI_P4TFD 0x320
+#define R_PCH_SATA_AHCI_P5TFD 0x3A0
+#define R_PCH_SATA_AHCI_P6TFD 0x420
+#define B_PCH_SATA_AHCI_PXTFD_ERR 0x0000FF00
+#define B_PCH_SATA_AHCI_PXTFD_STS 0x000000FF
+#define R_PCH_SATA_AHCI_P0SIG 0x124
+#define R_PCH_SATA_AHCI_P1SIG 0x1A4
+#define R_PCH_SATA_AHCI_P2SIG 0x224
+#define R_PCH_SATA_AHCI_P3SIG 0x2A4
+#define R_PCH_SATA_AHCI_P4SIG 0x324
+#define R_PCH_SATA_AHCI_P5SIG 0x3A4
+#define R_PCH_SATA_AHCI_P6SIG 0x424
+#define B_PCH_SATA_AHCI_PXSIG_LBA_HR 0xFF000000
+#define B_PCH_SATA_AHCI_PXSIG_LBA_MR 0x00FF0000
+#define B_PCH_SATA_AHCI_PXSIG_LBA_LR 0x0000FF00
+#define B_PCH_SATA_AHCI_PXSIG_SCR 0x000000FF
+#define R_PCH_SATA_AHCI_P0SSTS 0x128
+#define R_PCH_SATA_AHCI_P1SSTS 0x1A8
+#define R_PCH_SATA_AHCI_P2SSTS 0x228
+#define R_PCH_SATA_AHCI_P3SSTS 0x2A8
+#define R_PCH_SATA_AHCI_P4SSTS 0x328
+#define R_PCH_SATA_AHCI_P5SSTS 0x3A8
+#define R_PCH_SATA_AHCI_P6SSTS 0x428
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_0 0x00000000
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_1 0x00000100
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_2 0x00000200
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_6 0x00000600
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_0 0x00000000
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_1 0x00000010
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_2 0x00000020
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_3 0x00000030
+#define B_PCH_SATA_AHCI_PXSSTS_DET_0 0x00000000
+#define B_PCH_SATA_AHCI_PXSSTS_DET_1 0x00000001
+#define B_PCH_SATA_AHCI_PXSSTS_DET_3 0x00000003
+#define B_PCH_SATA_AHCI_PXSSTS_DET_4 0x00000004
+#define R_PCH_SATA_AHCI_P0SCTL 0x12C
+#define R_PCH_SATA_AHCI_P1SCTL 0x1AC
+#define R_PCH_SATA_AHCI_P2SCTL 0x22C
+#define R_PCH_SATA_AHCI_P3SCTL 0x2AC
+#define R_PCH_SATA_AHCI_P4SCTL 0x32C
+#define R_PCH_SATA_AHCI_P5SCTL 0x3AC
+#define R_PCH_SATA_AHCI_P6SCTL 0x42C
+#define B_PCH_SATA_AHCI_PXSCTL_IPM 0x00000F00
+#define V_PCH_SATA_AHCI_PXSCTL_IPM_0 0x00000000
+#define V_PCH_SATA_AHCI_PXSCTL_IPM_1 0x00000100
+#define V_PCH_SATA_AHCI_PXSCTL_IPM_2 0x00000200
+#define V_PCH_SATA_AHCI_PXSCTL_IPM_3 0x00000300
+#define B_PCH_SATA_AHCI_PXSCTL_SPD 0x000000F0
+#define V_PCH_SATA_AHCI_PXSCTL_SPD_0 0x00000000
+#define V_PCH_SATA_AHCI_PXSCTL_SPD_1 0x00000010
+#define V_PCH_SATA_AHCI_PXSCTL_SPD_2 0x00000020
+#define V_PCH_SATA_AHCI_PXSCTL_SPD_3 0x00000030
+#define B_PCH_SATA_AHCI_PXSCTL_DET 0x0000000F
+#define V_PCH_SATA_AHCI_PXSCTL_DET_0 0x00000000
+#define V_PCH_SATA_AHCI_PXSCTL_DET_1 0x00000001
+#define V_PCH_SATA_AHCI_PXSCTL_DET_4 0x00000004
+#define R_PCH_SATA_AHCI_P0SERR 0x130
+#define R_PCH_SATA_AHCI_P1SERR 0x1B0
+#define R_PCH_SATA_AHCI_P2SERR 0x230
+#define R_PCH_SATA_AHCI_P3SERR 0x2B0
+#define R_PCH_SATA_AHCI_P4SERR 0x330
+#define R_PCH_SATA_AHCI_P5SERR 0x3B0
+#define R_PCH_SATA_AHCI_P6SERR 0x430
+#define B_PCH_SATA_AHCI_PXSERR_EXCHG BIT26
+#define B_PCH_SATA_AHCI_PXSERR_UN_FIS_TYPE BIT25
+#define B_PCH_SATA_AHCI_PXSERR_TRSTE_24 BIT24
+#define B_PCH_SATA_AHCI_PXSERR_TRSTE_23 BIT23
+#define B_PCH_SATA_AHCI_PXSERR_HANDSHAKE BIT22
+#define B_PCH_SATA_AHCI_PXSERR_CRC_ERROR BIT21
+#define B_PCH_SATA_AHCI_PXSERR_10B8B_DECERR BIT19
+#define B_PCH_SATA_AHCI_PXSERR_COMM_WAKE BIT18
+#define B_PCH_SATA_AHCI_PXSERR_PHY_ERROR BIT17
+#define B_PCH_SATA_AHCI_PXSERR_PHY_RDY_CHG BIT16
+#define B_PCH_SATA_AHCI_PXSERR_INTRNAL_ERR BIT11
+#define B_PCH_SATA_AHCI_PXSERR_PROTOCOL_ERR BIT10
+#define B_PCH_SATA_AHCI_PXSERR_PCDIE BIT9
+#define B_PCH_SATA_AHCI_PXSERR_TDIE BIT8
+#define B_PCH_SATA_AHCI_PXSERR_RCE BIT1
+#define B_PCH_SATA_AHCI_PXSERR_RDIE BIT0
+#define R_PCH_SATA_AHCI_P0SACT 0x134
+#define R_PCH_SATA_AHCI_P1SACT 0x1B4
+#define R_PCH_SATA_AHCI_P2SACT 0x234
+#define R_PCH_SATA_AHCI_P3SACT 0x2B4
+#define R_PCH_SATA_AHCI_P4SACT 0x334
+#define R_PCH_SATA_AHCI_P5SACT 0x3B4
+#define R_PCH_SATA_AHCI_P6SACT 0x434
+#define B_PCH_SATA_AHCI_PXSACT_DS 0xFFFFFFFF
+#define R_PCH_SATA_AHCI_P0CI 0x138
+#define R_PCH_SATA_AHCI_P1CI 0x1B8
+#define R_PCH_SATA_AHCI_P2CI 0x238
+#define R_PCH_SATA_AHCI_P3CI 0x2B8
+#define R_PCH_SATA_AHCI_P4CI 0x338
+#define R_PCH_SATA_AHCI_P5CI 0x3B8
+#define R_PCH_SATA_AHCI_P6CI 0x438
+#define B_PCH_SATA_AHCI_PXCI 0xFFFFFFFF
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSmbus.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSmbus.h
new file mode 100644
index 0000000000..80d116493a
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSmbus.h
@@ -0,0 +1,157 @@
+/** @file
+ Register names for PCH Smbus Device.
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_SMBUS_H_
+#define _PCH_REGS_SMBUS_H_
+
+//
+// SMBus Controller Registers (D31:F4)
+//
+#define PCI_DEVICE_NUMBER_PCH_SMBUS 31
+#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4
+#define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_SMBUS_DEVICE_ID 0xA123
+//
+// LBG Production SMBus Controller Device ID
+//
+#define V_PCH_LBG_PROD_SMBUS_DEVICE_ID 0xA1A3
+//
+// LBG SSX (Super SKU) SMBus Controller Device ID
+//
+#define V_PCH_LBG_SMBUS_DEVICE_ID 0xA223
+#define V_PCH_LP_SMBUS_DEVICE_ID 0x9D23
+#define R_PCH_SMBUS_BASE 0x20
+#define V_PCH_SMBUS_BASE_SIZE (1 << 5)
+#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0
+#define R_PCH_SMBUS_HOSTC 0x40
+#define B_PCH_SMBUS_HOSTC_SPDWD BIT4
+#define B_PCH_SMBUS_HOSTC_SSRESET BIT3
+#define B_PCH_SMBUS_HOSTC_I2C_EN BIT2
+#define B_PCH_SMBUS_HOSTC_SMI_EN BIT1
+#define B_PCH_SMBUS_HOSTC_HST_EN BIT0
+#define R_PCH_SMBUS_TCOBASE 0x50
+#define B_PCH_SMBUS_TCOBASE_BAR 0x0000FFE0
+#define R_PCH_SMBUS_TCOCTL 0x54
+#define B_PCH_SMBUS_TCOCTL_TCO_BASE_EN BIT8
+#define B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK BIT0
+#define R_PCH_SMBUS_64 0x64
+#define R_PCH_SMBUS_80 0x80
+
+//
+// SMBus I/O Registers
+//
+#define R_PCH_SMBUS_HSTS 0x00 ///< Host Status Register R/W
+#define B_PCH_SMBUS_HBSY 0x01
+#define B_PCH_SMBUS_INTR 0x02
+#define B_PCH_SMBUS_DERR 0x04
+#define B_PCH_SMBUS_BERR 0x08
+#define B_PCH_SMBUS_FAIL 0x10
+#define B_PCH_SMBUS_SMBALERT_STS 0x20
+#define B_PCH_SMBUS_IUS 0x40
+#define B_PCH_SMBUS_BYTE_DONE_STS 0x80
+#define B_PCH_SMBUS_ERROR (B_PCH_SMBUS_DERR | B_PCH_SMBUS_BERR | B_PCH_SMBUS_FAIL)
+#define B_PCH_SMBUS_HSTS_ALL 0xFF
+#define R_PCH_SMBUS_HCTL 0x02 ///< Host Control Register R/W
+#define B_PCH_SMBUS_INTREN 0x01
+#define B_PCH_SMBUS_KILL 0x02
+#define B_PCH_SMBUS_SMB_CMD 0x1C
+#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00
+#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04
+#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08
+#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C
+#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10
+#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14
+#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18
+#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C
+#define B_PCH_SMBUS_LAST_BYTE 0x20
+#define B_PCH_SMBUS_START 0x40
+#define B_PCH_SMBUS_PEC_EN 0x80
+#define R_PCH_SMBUS_HCMD 0x03 ///< Host Command Register R/W
+#define R_PCH_SMBUS_TSA 0x04 ///< Transmit Slave Address Register R/W
+#define B_PCH_SMBUS_RW_SEL 0x01
+#define B_PCH_SMBUS_READ 0x01 // RW
+#define B_PCH_SMBUS_WRITE 0x00 // RW
+#define B_PCH_SMBUS_ADDRESS 0xFE
+#define R_PCH_SMBUS_HD0 0x05 ///< Data 0 Register R/W
+#define R_PCH_SMBUS_HD1 0x06 ///< Data 1 Register R/W
+#define R_PCH_SMBUS_HBD 0x07 ///< Host Block Data Register R/W
+#define R_PCH_SMBUS_PEC 0x08 ///< Packet Error Check Data Register R/W
+#define R_PCH_SMBUS_RSA 0x09 ///< Receive Slave Address Register R/W
+#define B_PCH_SMBUS_SLAVE_ADDR 0x7F
+#define R_PCH_SMBUS_SD 0x0A ///< Receive Slave Data Register R/W
+#define R_PCH_SMBUS_AUXS 0x0C ///< Auxiliary Status Register R/WC
+#define B_PCH_SMBUS_CRCE 0x01
+#define B_PCH_SMBUS_STCO 0x02 ///< SMBus TCO Mode
+#define R_PCH_SMBUS_AUXC 0x0D ///< Auxiliary Control Register R/W
+#define B_PCH_SMBUS_AAC 0x01
+#define B_PCH_SMBUS_E32B 0x02
+#define R_PCH_SMBUS_SMLC 0x0E ///< SMLINK Pin Control Register R/W
+#define B_PCH_SMBUS_SMLINK0_CUR_STS 0x01
+#define B_PCH_SMBUS_SMLINK1_CUR_STS 0x02
+#define B_PCH_SMBUS_SMLINK_CLK_CTL 0x04
+#define R_PCH_SMBUS_SMBC 0x0F ///< SMBus Pin Control Register R/W
+#define B_PCH_SMBUS_SMBCLK_CUR_STS 0x01
+#define B_PCH_SMBUS_SMBDATA_CUR_STS 0x02
+#define B_PCH_SMBUS_SMBCLK_CTL 0x04
+#define R_PCH_SMBUS_SSTS 0x10 ///< Slave Status Register R/WC
+#define B_PCH_SMBUS_HOST_NOTIFY_STS 0x01
+#define R_PCH_SMBUS_SCMD 0x11 ///< Slave Command Register R/W
+#define B_PCH_SMBUS_HOST_NOTIFY_INTREN 0x01
+#define B_PCH_SMBUS_HOST_NOTIFY_WKEN 0x02
+#define B_PCH_SMBUS_SMBALERT_DIS 0x04
+#define R_PCH_SMBUS_NDA 0x14 ///< Notify Device Address Register RO
+#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE
+#define R_PCH_SMBUS_NDLB 0x16 ///< Notify Data Low Byte Register RO
+#define R_PCH_SMBUS_NDHB 0x17 ///< Notify Data High Byte Register RO
+
+//
+// SMBus Private Config Registers
+// (PID:SMB)
+//
+#define R_PCH_PCR_SMBUS_TCOCFG 0x00 ///< TCO Configuration register
+#define B_PCH_PCR_SMBUS_TCOCFG_IE BIT7 ///< TCO IRQ Enable
+#define B_PCH_PCR_SMBUS_TCOCFG_IS (BIT2 | BIT1 | BIT0) ///< TCO IRQ Select
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_9 0x00
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_10 0x01
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_11 0x02
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_20 0x04 ///< only if APIC enabled
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_21 0x05 ///< only if APIC enabled
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_22 0x06 ///< only if APIC enabled
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_23 0x07 ///< only if APIC enabled
+#define R_PCH_PCR_SMBUS_SMBTM 0x04 ///< SMBus Test Mode
+#define B_PCH_PCR_SMBUS_SMBTM_SMBCT BIT1 ///< SMBus Counter
+#define B_PCH_PCR_SMBUS_SMBTM_SMBDG BIT0 ///< SMBus Deglitch
+#define R_PCH_PCR_SMBUS_SCTM 0x08 ///< Short Counter Test Mode
+#define B_PCH_PCR_SMBUS_SCTM_SSU BIT31 ///< Simulation Speed-Up
+#define R_PCH_PCR_SMBUS_GC 0x0C ///< General Control
+#define B_PCH_PCR_SMBUS_GC_FD BIT0 ///< Function Disable
+#define B_PCH_PCR_SMBUS_GC_NR BIT1 ///< No Reboot
+#define B_PCH_PCR_SMBUS_GC_SMBSCGE BIT2 ///< SMB Static Clock Gating Enable
+#define R_PCH_PCR_SMBUS_PCE 0x10 ///< Power Control Enable
+#define B_PCH_PCR_SMBUS_PCE_HAE BIT5 ///< Hardware Autonomous Enable
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSpi.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSpi.h
new file mode 100644
index 0000000000..cbd3dad872
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSpi.h
@@ -0,0 +1,354 @@
+/** @file
+ Register names for PCH SPI device.
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_SPI_H_
+#define _PCH_REGS_SPI_H_
+
+//
+// SPI Registers (D31:F5)
+//
+
+#define PCI_DEVICE_NUMBER_PCH_SPI 31
+#define PCI_FUNCTION_NUMBER_PCH_SPI 5
+#define V_PCH_SPI_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_SPI_DEVICE_ID 0xA124
+//
+// LBG PRODUCTION SPI Device ID
+//
+#define V_PCH_LBG_PROD_SPI_DEVICE_ID 0xA1A4
+//
+// LBG SSX (Super SKU) SPI Device ID
+//
+#define V_PCH_LBG_SPI_DEVICE_ID 0xA224
+#define V_PCH_LP_SPI_DEVICE_ID 0x9D24
+#define R_SPI_CFG_BAR0 0x10
+#define B_SPI_CFG_BAR0_MASK 0x0FFF
+
+#define R_SPI_CFG_BDE 0xD8
+#define B_SPI_CFG_BDE_F8 0x8000
+#define B_SPI_CFG_BDE_F0 0x4000
+#define B_SPI_CFG_BDE_E8 0x2000
+#define B_SPI_CFG_BDE_E0 0x1000
+#define B_SPI_CFG_BDE_D8 0x0800
+#define B_SPI_CFG_BDE_D0 0x0400
+#define B_SPI_CFG_BDE_C8 0x0200
+#define B_SPI_CFG_BDE_C0 0x0100
+#define B_SPI_CFG_BDE_LEG_F 0x0080
+#define B_SPI_CFG_BDE_LEG_E 0x0040
+#define B_SPI_CFG_BDE_70 0x0008
+#define B_SPI_CFG_BDE_60 0x0004
+#define B_SPI_CFG_BDE_50 0x0002
+#define B_SPI_CFG_BDE_40 0x0001
+
+#define R_SPI_CFG_BC 0xDC
+#define S_SPI_CFG_BC 4
+#define N_SPI_CFG_BC_ASE_BWP 11
+#define B_SPI_CFG_BC_ASE_BWP BIT11
+#define N_SPI_CFG_BC_ASYNC_SS 10
+#define B_SPI_CFG_BC_ASYNC_SS BIT10
+#define B_SPI_CFG_BC_OSFH BIT9 ///< OS Function Hide
+#define N_SPI_CFG_BC_SYNC_SS 8
+#define B_SPI_CFG_BC_SYNC_SS BIT8
+#define B_SPI_CFG_BC_BILD BIT7
+#define B_SPI_CFG_BC_BBS BIT6 ///< Boot BIOS strap
+#define N_SPI_CFG_BC_BBS 6
+#define V_SPI_CFG_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI
+#define V_SPI_CFG_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC
+#define B_SPI_CFG_BC_EISS BIT5 ///< Enable InSMM.STS
+#define B_SPI_CFG_BC_TSS BIT4
+#define B_SPI_CFG_BC_SRC (BIT3 | BIT2)
+#define N_SPI_CFG_BC_SRC 2
+#define V_SPI_CFG_BC_SRC_PREF_EN_CACHE_EN 0x02 ///< Prefetching and Caching enabled
+#define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefetching and no caching
+#define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_EN 0x00 ///< No prefetching, but caching enabled
+#define B_SPI_CFG_BC_LE BIT1 ///< Lock Enable
+#define N_SPI_CFG_BC_BLE 1
+#define B_SPI_CFG_BC_WPD BIT0 ///< Write Protect Disable
+
+//
+// BIOS Flash Program Registers (based on SPI_BAR0)
+//
+#define R_SPI_MEM_BFPR 0x00 ///< BIOS Flash Primary Region Register(32bits), which is RO and contains the same value from FREG1
+#define B_SPI_MEM_BFPR_PRL 0x7FFF0000 ///< BIOS Flash Primary Region Limit mask
+#define N_SPI_MEM_BFPR_PRL 16 ///< BIOS Flash Primary Region Limit bit position
+#define B_SPI_MEM_BFPR_PRB 0x00007FFF ///< BIOS Flash Primary Region Base mask
+#define N_SPI_MEM_BFPR_PRB 0 ///< BIOS Flash Primary Region Base bit position
+#define B_PCH_SPI_BFPR_SBRS BIT31 ///< BIOS Flash Primary Region Shadowed BIOS Region Select
+#define R_SPI_MEM_HSFSC 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits)
+#define B_SPI_MEM_HSFSC_FSMIE BIT31 ///< Flash SPI SMI# Enable
+#define B_SPI_MEM_HSFSC_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
+#define N_SPI_MEM_HSFSC_FDBC 24
+#define B_SPI_MEM_HSFSC_CYCLE_MASK 0x001E0000 ///< Flash Cycle.
+#define N_SPI_MEM_HSFSC_CYCLE 17
+#define V_SPI_MEM_HSFSC_CYCLE_READ 0 ///< Flash Cycle Read
+#define V_SPI_MEM_HSFSC_CYCLE_WRITE 2 ///< Flash Cycle Write
+#define V_SPI_MEM_HSFSC_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase
+#define V_SPI_MEM_HSFSC_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase
+#define V_SPI_MEM_HSFSC_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP
+#define V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID
+#define V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status
+#define V_SPI_MEM_HSFSC_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status
+#define B_SPI_MEM_HSFSC_CYCLE_FGO BIT16 ///< Flash Cycle Go.
+#define B_SPI_MEM_HSFSC_FLOCKDN BIT15 ///< Flash Configuration Lock-Down
+#define B_SPI_MEM_HSFSC_FDV BIT14 ///< Flash Descriptor Valid, once valid software can use hareware sequencing regs
+#define B_SPI_MEM_HSFSC_FDOPSS BIT13 ///< Flash Descriptor Override Pin-Strap Status
+#define B_SPI_MEM_HSFSC_PRR34_LOCKDN BIT12 ///< PRR3 PRR4 Lock-Down
+#define B_SPI_MEM_HSFSC_WRSDIS BIT11 ///< Flash Write Status Register Disable
+#define B_SPI_MEM_HSFSC_SAF_CE BIT8 ///< SAF ctype error
+#define B_SPI_MEM_HSFSC_SAF_MODE_ACTIVE BIT7 ///< Indicates flash is attached either directly to the PCH via the SPI bus or EC/BMC
+#define B_SPI_MEM_HSFSC_SAF_LE BIT6 ///< SAF link error
+#define B_SPI_MEM_HSFSC_SCIP BIT5 ///< SPI cycle in progress
+#define B_SPI_MEM_HSFSC_SAF_DLE BIT4 ///< SAF Data length error
+#define B_SPI_MEM_HSFSC_SAF_ERROR BIT3 ///< SAF Error
+#define B_SPI_MEM_HSFSC_AEL BIT2 ///< Access Error Log
+#define B_SPI_MEM_HSFSC_FCERR BIT1 ///< Flash Cycle Error
+#define B_SPI_MEM_HSFSC_FDONE BIT0 ///< Flash Cycle Done
+#define R_SPI_MEM_FADDR 0x08 ///< SPI Flash Address
+#define B_SPI_MEM_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit)
+#define R_SPI_MEM_DLOCK 0x0C ///< Discrete Lock Bits
+#define B_SPI_MEM_DLOCK_PR0LOCKDN BIT8 ///< PR0LOCKDN
+#define R_SPI_MEM_FDATA00 0x10 ///< SPI Data 00 (32 bits)
+#define R_SPI_MEM_FDATA01 0x14 ///< SPI Data 01
+#define R_SPI_MEM_FDATA02 0x18 ///< SPI Data 02
+#define R_SPI_MEM_FDATA03 0x1C ///< SPI Data 03
+#define R_SPI_MEM_FDATA04 0x20 ///< SPI Data 04
+#define R_SPI_MEM_FDATA05 0x24 ///< SPI Data 05
+#define R_SPI_MEM_FDATA06 0x28 ///< SPI Data 06
+#define R_SPI_MEM_FDATA07 0x2C ///< SPI Data 07
+#define R_SPI_MEM_FDATA08 0x30 ///< SPI Data 08
+#define R_SPI_MEM_FDATA09 0x34 ///< SPI Data 09
+#define R_SPI_MEM_FDATA10 0x38 ///< SPI Data 10
+#define R_SPI_MEM_FDATA11 0x3C ///< SPI Data 11
+#define R_SPI_MEM_FDATA12 0x40 ///< SPI Data 12
+#define R_SPI_MEM_FDATA13 0x44 ///< SPI Data 13
+#define R_SPI_MEM_FDATA14 0x48 ///< SPI Data 14
+#define R_SPI_MEM_FDATA15 0x4C ///< SPI Data 15
+#define R_SPI_MEM_FRAP 0x50 ///< Flash Region Access Permisions Register
+#define B_SPI_MEM_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
+#define N_SPI_MEM_FRAP_BRWA 8 ///< BIOS Region Write Access bit position
+#define B_SPI_MEM_FRAP_BRRA_MASK 0x000000FF ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
+#define B_SPI_MEM_FRAP_BMRAG_MASK 0x00FF0000 ///< BIOS Master Read Access Grant
+#define B_SPI_MEM_FRAP_BMWAG_MASK 0xFF000000 ///< BIOS Master Write Access Grant
+#define R_PCH_SPI_BM_RAP 0x118 ///< SPI Flash BIOS Master Read Access Permissions
+#define R_PCH_SPI_BM_WAP 0x11C ///< SPI Flash BIOS Master Write Access Permissions
+#define B_PCH_SPI_BM_AP_REG15 BIT15 ///< Region read or write access for Region15
+#define B_PCH_SPI_BM_AP_PLATFORM BIT4 ///< Region read or write access for Region4 PlatformData
+#define B_PCH_SPI_BM_AP_GBE BIT3 ///< Region read or write access for Region3 GbE
+#define B_PCH_SPI_BM_AP_ME BIT2 ///< Region read or write access for Region2 ME
+#define B_PCH_SPI_BM_AP_BIOS BIT1 ///< Region read or write access for Region1 BIOS
+#define B_PCH_SPI_BM_AP_FLASHD BIT0 ///< Region read or write access for Region0 Flash Descriptor
+#define R_SPI_MEM_FREG0_FLASHD 0x54 ///< Flash Region 0(Flash Descriptor)(32bits)
+#define B_SPI_MEM_FREG0_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_MEM_FREG0_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_MEM_FREG0_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_MEM_FREG0_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
+#define B_SPI_MEM_FREG1_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_MEM_FREG1_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_MEM_FREG1_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_MEM_FREG1_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
+#define B_SPI_MEM_FREG2_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_MEM_FREG2_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_MEM_FREG2_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_MEM_FREG2_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
+#define B_SPI_MEM_FREG3_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_MEM_FREG3_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_MEM_FREG3_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_MEM_FREG3_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
+#define R_SPI_MEM_FREG1_BIOS 0x58 ///< Flash Region 1(BIOS)(32bits)
+#define R_SPI_MEM_FREG2_ME 0x5C ///< Flash Region 2(ME)(32bits)
+#define R_SPI_MEM_FREG3_GBE 0x60 ///< Flash Region 3(GbE)(32bits)
+#define R_SPI_MEM_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4(Platform Data)(32bits)
+#define B_SPI_MEM_FREG4_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_MEM_FREG4_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_MEM_FREG4_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_MEM_FREG4_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
+#define R_SPI_MEM_FREG5_DER 0x68 ///< Flash Region 5(Device Expansion Region)(32bits)
+#define R_SPI_MEM_FREG6_SECONDARY_BIOS 0x6C ///< Flash Region 6(Secondary BIOS)(32bits)
+#define R_PCH_SPI_FREG7_UCODE_PATCH 0x70 ///< Flash Region 7(uCode Patch)(32bits)
+#define R_PCH_SPI_FREG12 0xE0 ///< Flash Region 12(32bits)
+#define R_PCH_SPI_FREG15 0xEC ///< Flash Region 15 (32bits)
+#define B_SPI_MEM_FREG15_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_MEM_FREG15_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_MEM_FREG15_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_MEM_FREG15_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
+#define S_SPI_MEM_FREGX 4 ///< Size of Flash Region register
+#define B_SPI_MEM_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh
+#define N_SPI_MEM_FREGX_LIMIT 16 ///< Region limit bit position
+#define N_SPI_MEM_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position
+#define B_SPI_MEM_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12]
+#define N_SPI_MEM_FREGX_BASE 0 ///< Region base bit position
+#define N_SPI_MEM_FREGX_BASE_REPR 12 ///< Region base bit represents position
+#define R_SPI_MEM_PR0 0x84 ///< Protected Region 0 Register
+#define R_SPI_MEM_PR1 0x88 ///< Protected Region 1 Register
+#define R_SPI_MEM_PR2 0x8C ///< Protected Region 2 Register
+#define R_SPI_MEM_PR3 0x90 ///< Protected Region 3 Register
+#define R_SPI_MEM_PR4 0x94 ///< Protected Region 4 Register
+#define S_SPI_MEM_PRX 4 ///< Protected Region X Register size
+#define B_SPI_MEM_PRX_WPE BIT31 ///< Write Protection Enable
+#define B_SPI_MEM_PRX_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask, [30:16] here represents upper limit of address [26:12]
+#define N_SPI_MEM_PRX_PRL 16 ///< Protected Range Limit bit position
+#define B_SPI_MEM_PRX_RPE BIT15 ///< Read Protection Enable
+#define B_SPI_MEM_PRX_PRB_MASK 0x00007FFF ///< Protected Range Base Mask, [14:0] here represents base limit of address [26:12]
+#define N_SPI_MEM_PRX_PRB 0 ///< Protected Range Base bit position
+#define R_SPI_MEM_SFRAP 0xB0 ///< Secondary Flash Regions Access Permisions Register
+#define R_SPI_MEM_FDOC 0xB4 ///< Flash Descriptor Observability Control Register(32 bits)
+#define B_SPI_MEM_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descritor Section Select
+#define V_SPI_MEM_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map
+#define V_SPI_MEM_FDOC_FDSS_COMP 0x1000 ///< Component
+#define V_SPI_MEM_FDOC_FDSS_REGN 0x2000 ///< Region
+#define V_SPI_MEM_FDOC_FDSS_MSTR 0x3000 ///< Master
+#define V_SPI_MEM_FDOC_FDSS_PCHS 0x4000 ///< PCH soft straps
+#define V_SPI_MEM_FDOC_FDSS_SFDP 0x5000 ///< SFDP Parameter Table
+#define B_SPI_MEM_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index
+#define R_SPI_MEM_FDOD 0xB8 ///< Flash Descriptor Observability Data Register(32 bits)
+#define R_SPI_MEM_SFDP0_VSCC0 0xC4 ///< Vendor Specific Component Capabilities Register(32 bits)
+#define B_SPI_MEM_SFDPX_VSCCX_CPPTV BIT31 ///< Component Property Parameter Table Valid
+#define B_SPI_MEM_SFDP0_VSCC0_VCL BIT30 ///< Vendor Component Lock
+#define B_SPI_MEM_SFDPX_VSCCX_EO_64K BIT29 ///< 64k Erase valid (EO_64k_valid)
+#define B_SPI_MEM_SFDPX_VSCCX_EO_4K BIT28 ///< 4k Erase valid (EO_4k_valid)
+#define B_SPI_MEM_SFDPX_VSCCX_RPMC BIT27 ///< RPMC Supported
+#define B_SPI_MEM_SFDPX_VSCCX_DPD BIT26 ///< Deep Powerdown Supported
+#define B_SPI_MEM_SFDPX_VSCCX_SUSRES BIT25 ///< Suspend/Resume Supported
+#define B_SPI_MEM_SFDPX_VSCCX_SOFTRES BIT24 ///< Soft Reset Supported
+#define B_SPI_MEM_SFDPX_VSCCX_64k_EO_MASK 0x00FF0000 ///< 64k Erase Opcode (EO_64k)
+#define B_SPI_MEM_SFDPX_VSCCX_4k_EO_MASK 0x0000FF00 ///< 4k Erase Opcode (EO_4k)
+#define B_SPI_MEM_SFDPX_VSCCX_QER (BIT7 | BIT6 | BIT5) ///< Quad Enable Requirements
+#define B_SPI_MEM_SFDPX_VSCCX_WEWS BIT4 ///< Write Enable on Write Status
+#define B_SPI_MEM_SFDPX_VSCCX_WSR BIT3 ///< Write Status Required
+#define B_SPI_MEM_SFDPX_VSCCX_WG_64B BIT2 ///< Write Granularity, 0: 1 Byte; 1: 64 Bytes
+#define R_SPI_MEM_SFDP1_VSCC1 0xC8 ///< Vendor Specific Component Capabilities Register(32 bits)
+#define R_SPI_MEM_PINTX 0xCC ///< Parameter Table Index
+#define N_SPI_MEM_PINTX_SPT 14
+#define V_SPI_MEM_PINTX_SPT_CPT0 0x0 ///< Component 0 Property Parameter Table
+#define V_SPI_MEM_PINTX_SPT_CPT1 0x1 ///< Component 1 Property Parameter Table
+#define N_SPI_MEM_PINTX_HORD 12
+#define V_SPI_MEM_PINTX_HORD_SFDP 0x0 ///< SFDP Header
+#define V_SPI_MEM_PINTX_HORD_PT 0x1 ///< Parameter Table Header
+#define V_SPI_MEM_PINTX_HORD_DATA 0x2 ///< Data
+#define R_SPI_MEM_PTDATA 0xD0 ///< Parameter Table Data
+#define R_SPI_MEM_SBRS 0xD4 ///< SPI Bus Requester Status
+#define R_PCH_SPI_SSML 0xF0 ///< Set Strap Msg Lock
+#define B_PCH_SPI_SSML_SSL BIT0 ///< Set_Strap Lock
+#define R_PCH_SPI_SSMC 0xF4 ///< Set Strap Msg Control
+#define B_PCH_SPI_SSMC_SSMS BIT0 ///< Set_Strap Mux Select
+#define R_PCH_SPI_SSMD 0xF8 ///< Set Strap Msg Data
+//
+// @todo Follow up with EDS owner if it should be 3FFF or FFFF.
+//
+#define B_SPI_MEM_SRD_SSD 0x0000FFFF ///< Set_Strap Data
+//
+// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
+//
+#define R_SPI_FLASH_FDBAR_FLVALSIG 0x00 ///< Flash Valid Signature
+#define V_SPI_FLASH_FDBAR_FLVALSIG 0x0FF0A55A
+#define R_SPI_FLASH_FDBAR_FLASH_MAP0 0x04
+#define B_SPI_FLASH_FDBAR_FCBA 0x000000FF ///< Flash Component Base Address
+#define B_SPI_FLASH_FDBAR_NC 0x00000300 ///< Number Of Components
+#define N_SPI_FLASH_FDBAR_NC 8 ///< Number Of Components
+#define V_SPI_FLASH_FDBAR_NC_1 0x00000000
+#define V_SPI_FLASH_FDBAR_NC_2 0x00000100
+#define B_SPI_FLASH_FDBAR_FRBA 0x00FF0000 ///< Flash Region Base Address
+#define B_SPI_FLASH_FDBAR_NR 0x07000000 ///< Number Of Regions
+#define R_SPI_FLASH_FDBAR_FLASH_MAP1 0x08
+#define B_SPI_FLASH_FDBAR_FMBA 0x000000FF ///< Flash Master Base Address
+#define B_SPI_FLASH_FDBAR_NM 0x00000700 ///< Number Of Masters
+#define B_SPI_FLASH_FDBAR_FPSBA 0x00FF0000 ///< PCH Strap Base Address, [23:16] represents [11:4]
+#define N_SPI_FLASH_FDBAR_FPSBA 16 ///< PCH Strap base Address bit position
+#define N_SPI_FLASH_FDBAR_FPSBA_REPR 4 ///< PCH Strap base Address bit represents position
+#define B_SPI_FLASH_FDBAR_PCHSL 0xFF000000 ///< PCH Strap Length, [31:24] represents number of Dwords
+#define R_SPI_MEM_FDBAR_FLASH_MAP1_RW 0x18 ///< For Use With FlashRead() and FlashWrite()
+#define N_SPI_FLASH_FDBAR_PCHSL 24 ///< PCH Strap Length bit position
+#define R_SPI_FLASH_FDBAR_FLASH_MAP2 0x0C
+#define B_SPI_FLASH_FDBAR_FCPUSBA 0x000000FF ///< CPU Strap Base Address, [7:0] represents [11:4]
+#define N_SPI_FLASH_FDBAR_FCPUSBA 0 ///< CPU Strap Base Address bit position
+#define N_SPI_FLASH_FDBAR_FCPUSBA_REPR 4 ///< CPU Strap Base Address bit represents position
+#define B_SPI_FLASH_FDBAR_CPUSL 0x0000FF00 ///< CPU Strap Length, [15:8] represents number of Dwords
+#define N_SPI_FLASH_FDBAR_CPUSL 8 ///< CPU Strap Length bit position
+//
+// Flash Component Base Address (FCBA) from Flash Region 0
+//
+#define R_SPI_FLASH_FCBA_FLCOMP 0x00 ///< Flash Components Register
+#define B_SPI_FLASH_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27) ///< Read ID and Read Status Clock Frequency
+#define B_SPI_FLASH_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24) ///< Write and Erase Clock Frequency
+#define B_SPI_FLASH_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21) ///< Fast Read Clock Frequency
+#define B_SPI_FLASH_FLCOMP_FR_SUP BIT20 ///< Fast Read Support.
+#define B_SPI_FLASH_FLCOMP_RC_FREQ (BIT19 | BIT18 | BIT17) ///< Read Clock Frequency.
+#define V_SPI_FLASH_FLCOMP_FREQ_48MHZ 0x02
+#define V_SPI_FLASH_FLCOMP_FREQ_30MHZ 0x04
+#define V_SPI_FLASH_FLCOMP_FREQ_17MHZ 0x06
+#define B_SPI_FLASH_FLCOMP_COMP1_MASK 0xF0 ///< Flash Component 1 Size MASK
+#define N_SPI_FLASH_FLCOMP_COMP1 4 ///< Flash Component 1 Size bit position
+#define B_SPI_FLASH_FLCOMP_COMP0_MASK 0x0F ///< Flash Component 0 Size MASK
+#define V_SPI_FLASH_FLCOMP_COMP_512KB 0x80000
+//
+// Descriptor Upper Map Section from Flash Region 0
+//
+#define R_SPI_FLASH_UMAP1 0xEFC ///< Flash Upper Map 1
+#define B_SPI_FLASH_UMAP1_VTBA 0x000000FF ///< VSCC Table Base Address
+#define B_SPI_FLASH_UMAP1_VTL 0x0000FF00 ///< VSCC Table Length
+
+#define R_SPI_MEM_VTBA_JID0 0x00 ///< JEDEC-ID 0 Register
+#define S_SPI_MEM_VTBA_JID0 0x04
+#define B_SPI_MEM_VTBA_JID0_VID 0x000000FF
+#define B_SPI_MEM_VTBA_JID0_DID0 0x0000FF00
+#define B_SPI_MEM_VTBA_JID0_DID1 0x00FF0000
+#define N_SPI_MEM_VTBA_JID0_DID0 0x08
+#define N_SPI_MEM_VTBA_JID0_DID1 0x10
+#define R_SPI_MEM_VTBA_VSCC0 0x04
+#define S_SPI_MEM_VTBA_VSCC0 0x04
+
+#define R_PCH_PCR_SPI_CONF_VALUE 0xC00C
+#define B_ESPI_ENABLE_STRAP BIT0
+
+//
+// SPI Private Configuration Space Registers
+//
+#define R_SPI_PCR_CLK_CTL 0xC004
+#define R_SPI_PCR_PWR_CTL 0xC008
+
+//
+// MMP0
+//
+#define R_SPI_MEM_STRP_MMP0 0xC4 ///< MMP0 Soft strap offset
+#define B_SPI_MEM_STRP_MMP0 0x10 ///< MMP0 Soft strap bit
+
+
+#define R_SPI_MEM_STRP_SFDP 0xF0 ///< PCH Soft Strap SFDP
+#define B_SPI_MEM_STRP_SFDP_QIORE BIT3 ///< Quad IO Read Enable
+#define B_SPI_MEM_STRP_SFDP_QORE BIT2 ///< Quad Output Read Enable
+#define B_SPI_MEM_STRP_SFDP_DIORE BIT1 ///< Dual IO Read Enable
+#define B_SPI_MEM_STRP_SFDP_DORE BIT0 ///< Dual Output Read Enable
+
+//
+// Descriptor Record 0
+//
+#define R_SPI_MEM_STRP_DSCR_0 0x00 ///< PCH Soft Strap 0
+#define B_SPI_MEM_STRP_DSCR_0_PTT_SUPP BIT22 ///< PTT Supported
+
+#define R_PCH_SPI_SS119_PMC 0x1DC ///< PCH soft strap 119 - PMC
+#define B_PCH_SPI_SS119_PMC_GBE_DIS BIT14 ///< PCH soft strap 119 - GbE Disable
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsThermal.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsThermal.h
new file mode 100644
index 0000000000..97faa15255
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsThermal.h
@@ -0,0 +1,113 @@
+/** @file
+ Register names for PCH Thermal Device
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_THERMAL_H_
+#define _PCH_REGS_THERMAL_H_
+
+//
+// Thermal Device Registers (D20:2)
+//
+#define PCI_DEVICE_NUMBER_PCH_THERMAL 20
+#define PCI_FUNCTION_NUMBER_PCH_THERMAL 2
+#define V_PCH_THERMAL_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_THERMAL_DEVICE_ID 0x8C24
+
+//
+// LBG Production Thermal Device Device ID
+//
+#define V_PCH_LBG_PROD_THERMAL_DEVICE_ID 0xA1B1
+//
+// LBG SSX (Super SKU) Thermal Device Device ID
+//
+#define V_PCH_LBG_THERMAL_DEVICE_ID 0xA231
+
+#define V_PCH_LP_THERMAL_DEVICE_ID 0x9C24
+#define R_PCH_THERMAL_TBAR 0x10
+#define V_PCH_THERMAL_TBAR_SIZE (4 * 1024)
+#define N_PCH_THREMAL_TBAR_ALIGNMENT 12
+#define B_PCH_THERMAL_TBAR_MASK 0xFFFFF000
+#define R_PCH_THERMAL_TBARH 0x14
+#define R_PCH_THERMAL_TBARB 0x40
+#define V_PCH_THERMAL_TBARB_SIZE (4 * 1024)
+#define N_PCH_THREMAL_TBARB_ALIGNMENT 12
+#define B_PCH_THERMAL_SPTYPEN BIT0
+#define R_PCH_THERMAL_TBARBH 0x44
+#define B_PCH_THERMAL_TBARB_MASK 0xFFFFF000
+
+//
+// Thermal TBAR MMIO registers
+//
+#define R_PCH_TBAR_TSC 0x04
+#define B_PCH_TBAR_TSC_PLD BIT7
+#define B_PCH_TBAR_TSC_CPDE BIT0
+#define R_PCH_TBAR_TSS 0x06
+#define R_PCH_TBAR_TSEL 0x08
+#define B_PCH_TBAR_TSEL_PLD BIT7
+#define B_PCH_TBAR_TSEL_ETS BIT0
+#define R_PCH_TBAR_TSREL 0x0A
+#define R_PCH_TBAR_TSMIC 0x0C
+#define B_PCH_TBAR_TSMIC_PLD BIT7
+#define B_PCH_TBAR_TSMIC_SMIE BIT0
+#define R_PCH_TBAR_CTT 0x10
+#define R_PCH_TBAR_TAHV 0x14
+#define R_PCH_TBAR_TALV 0x18
+#define R_PCH_TBAR_TSPM 0x1C
+#define B_PCH_TBAR_TSPM_LTT (BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
+#define V_PCH_TBAR_TSPM_LTT 0x0C8
+#define B_PCH_TBAR_TSPM_MAXTSST (BIT11 | BIT10 | BIT9)
+#define V_PCH_TBAR_TSPM_MAXTSST (0x4 << 9)
+#define B_PCH_TBAR_TSPM_MINTSST BIT12
+#define B_PCH_TBAR_TSPM_DTSSIC0 BIT13
+#define B_PCH_TBAR_TSPM_DTSSS0EN BIT14
+#define B_PCH_TBAR_TSPM_TSPMLOCK BIT15
+#define R_PCH_TBAR_TL 0x40
+#define B_PCH_TBAR_TL_LOCK BIT31
+#define B_PCH_TBAR_TL_TTEN BIT29
+#define R_PCH_TBAR_TL2 0x50
+#define R_PCH_TBAR_TL2_LOCK BIT15
+#define R_PCH_TBAR_TL2_PMCTEN BIT14
+#define R_PCH_TBAR_PHL 0x60
+#define B_PCH_TBAR_PHLE BIT15
+#define R_PCH_TBAR_PHLC 0x62
+#define B_PCH_TBAR_PHLC_LOCK BIT0
+#define R_PCH_TBAR_TAS 0x80
+#define R_PCH_TBAR_TSPIEN 0x82
+#define R_PCH_TBAR_TSGPEN 0x84
+#define B_PCH_TBAR_TL2_PMCTEN BIT14
+#define R_PCH_TBAR_A4 0xA4
+#define R_PCH_TBAR_C0 0xC0
+#define R_PCH_TBAR_C4 0xC4
+#define R_PCH_TBAR_C8 0xC8
+#define R_PCH_TBAR_CC 0xCC
+#define R_PCH_TBAR_D0 0xD0
+#define R_PCH_TBAR_E0 0xE0
+#define R_PCH_TBAR_E4 0xE4
+#define R_PCH_TBAR_E8 0xE8
+#define R_PCH_TBAR_TCFD 0xF0 ///< Thermal controller function disable
+#define B_PCH_TBAR_TCFD_TCD BIT0 ///< Thermal controller disable
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsTraceHub.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsTraceHub.h
new file mode 100644
index 0000000000..87d0f2cb34
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsTraceHub.h
@@ -0,0 +1,147 @@
+/** @file
+ Register names for PCH TraceHub device
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 2013 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_TRACE_HUB_H_
+#define _PCH_REGS_TRACE_HUB_H_
+
+//
+// TraceHub Registers (D31:F7)
+//
+#define PCI_DEVICE_NUMBER_PCH_TRACE_HUB 31
+#define PCI_FUNCTION_NUMBER_PCH_TRACE_HUB 7
+
+#define V_PCH_TRACE_HUB_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_TRACE_HUB_DEVICE_ID 0x0963
+
+//
+// LBG Production (PRQ) TraceHub Device ID
+//
+#define V_PCH_LBG_PROD_TRACE_HUB_DEVICE_ID 0xA1A6
+//
+// LBG SuperSKU (SSX) TraceHub Device ID
+//
+#define V_PCH_LBG_TRACE_HUB_DEVICE_ID 0xA226
+
+#define R_TRACE_HUB_CFG_CSR_MTB_LBAR 0x10
+#define B_TRACE_HUB_CFG_CSR_MTB_RBAL 0xFFF00000
+#define R_TRACE_HUB_CFG_CSR_MTB_UBAR 0x14
+#define B_PCH_TRACE_HUB_CSR_MTB_RBAU 0xFFFFFFFF
+#define R_PCH_TRACE_HUB_SW_LBAR 0x18
+#define B_PCH_TRACE_HUB_SW_RBAL 0xFFE00000
+#define R_PCH_TRACE_HUB_SW_UBAR 0x1C
+#define B_PCH_TRACE_HUB_SW_RBAU 0xFFFFFFFF
+#define R_PCH_TRACE_HUB_RTIT_LBAR 0x20
+#define B_PCH_TRACE_HUB_RTIT_RBAL 0xFFFFFF00
+#define R_PCH_TRACE_HUB_RTIT_UBAR 0x24
+#define B_PCH_TRACE_HUB_RTIT_RBAU 0xFFFFFFFF
+#define R_PCH_TRACE_HUB_MSICID 0x40
+#define R_PCH_TRACE_HUB_MSINCP 0x41
+#define R_PCH_TRACE_HUB_MSIMC 0x42
+#define R_PCH_TRACE_HUB_MSILMA 0x44
+#define R_PCH_TRACE_HUB_MSIUMA 0x48
+#define R_PCH_TRACE_HUB_MSIMD 0x4C
+#define R_PCH_TRACE_HUB_FW_LBAR 0x70
+#define B_PCH_TRACE_HUB_FW_RBAL 0xFFFC0000
+#define R_PCH_TRACE_HUB_FW_UBAR 0x74
+#define B_PCH_TRACE_HUB_FW_RBAU 0xFFFFFFFF
+#define R_PCH_TRACE_HUB_DSC 0x80
+#define B_PCH_TRACE_HUB_BYP BIT0 //< TraceHub Bypass
+#define R_PCH_TRACE_HUB_DSS 0x81
+#define R_PCH_TRACE_HUB_ISTOT 0x84
+#define R_PCH_TRACE_HUB_ICTOT 0x88
+#define R_PCH_TRACE_HUB_IPAD 0x8C
+#define R_PCH_TRACE_HUB_DSD 0x90
+
+//
+// Offsets from CSR_MTB_BAR
+//
+#define R_PCH_TRACE_HUB_MTB_GTHOPT0 0x00
+#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P0FLUSH BIT7
+#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P1FLUSH BIT15
+#define V_PCH_TRACE_HUB_MTB_SWDEST_PTI 0x0A
+#define V_PCH_TRACE_HUB_MTB_SWDEST_MEMEXI 0x08
+#define V_PCH_TRACE_HUB_MTB_SWDEST_DISABLE 0x00
+#define R_PCH_TRACE_HUB_MTB_SWDEST_1 0x0C
+#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_1 0x0000000F
+#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_2 0x000000F0
+#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_3 0x00000F00
+#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_1 0x0000F000
+#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_2 0x000F0000
+#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_3 0x00F00000
+#define B_PCH_TRACE_HUB_MTB_SWDEST_AUDIO 0x0F000000
+#define B_PCH_TRACE_HUB_MTB_SWDEST_PMC 0xF0000000
+#define R_PCH_TRACE_HUB_MTB_SWDEST_2 0x10
+#define B_PCH_TRACE_HUB_MTB_SWDEST_FTH 0x0000000F
+#define R_PCH_TRACE_HUB_MTB_SWDEST_3 0x14
+#define B_PCH_TRACE_HUB_MTB_SWDEST_MAESTRO 0x00000F00
+#define B_PCH_TRACE_HUB_MTB_SWDEST_SKYCAM 0x0F000000
+#define B_PCH_TRACE_HUB_MTB_SWDEST_AET 0xF0000000
+#define R_PCH_TRACE_HUB_MTB_SWDEST_4 0x18
+#define R_PCH_TRACE_HUB_MTB_MSC0CTL 0xA0100
+#define R_PCH_TRACE_HUB_MTB_MSC1CTL 0xA0200
+#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DCI 0x2
+#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DEBUG 0x3
+#define B_PCH_TRACE_HUB_MTB_MSCNLEN (BIT10 | BIT9 | BIT8)
+#define B_PCH_TRACE_HUB_MTB_MSCNMODE (BIT5 | BIT4)
+#define N_PCH_TRACE_HUB_MTB_MSCNMODE 0x4
+#define B_PCH_TRACE_HUB_MTB_MSCN_RD_HDR_OVRD BIT2
+#define B_PCH_TRACE_HUB_MTB_WRAPENN BIT1
+#define B_PCH_TRACE_HUB_MTB_MSCNEN BIT0
+#define R_PCH_TRACE_HUB_MTB_GTHSTAT 0xD4
+#define R_PCH_TRACE_HUB_MTB_SCR2 0xD8
+#define B_PCH_TRACE_HUB_MTB_SCR2_FCD BIT0
+#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF2 BIT2
+#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF3 BIT3
+#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF4 BIT4
+#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF5 BIT5
+#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF6 BIT6
+#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF7 BIT7
+#define R_PCH_TRACE_HUB_MTB_MSC0BAR 0xA0108
+#define R_PCH_TRACE_HUB_MTB_MSC0SIZE 0xA010C
+#define R_PCH_TRACE_HUB_MTB_MSC1BAR 0xA0208
+#define R_PCH_TRACE_HUB_MTB_MSC1SIZE 0xA020C
+#define R_PCH_TRACE_HUB_MTB_STREAMCFG1 0xA1000
+#define B_PCH_TRACE_HUB_MTB_STREAMCFG1_ENABLE BIT28
+#define R_PCH_TRACE_HUB_MTB_PTI_CTL 0x1C00
+#define B_PCH_TRACE_HUB_MTB_PTIMODESEL 0xF0
+#define B_PCH_TRACE_HUB_MTB_PTICLKDIV (BIT17 | BIT16)
+#define B_PCH_TRACE_HUB_MTB_PATGENMOD (BIT22 | BIT21 | BIT20)
+#define B_PCH_TRACE_HUB_MTB_PTI_EN BIT0
+#define R_PCH_TRACE_HUB_MTB_SCR 0xC8
+#define R_PCH_TRACE_HUB_MTB_GTH_FREQ 0xCC
+#define V_PCH_TRACE_HUB_MTB_SCR 0x00130000
+#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD0 0xE0
+#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD1 0xE4
+#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD10 0xE40
+#define R_PCH_TRACE_HUB_MTB_CTPGCS 0x1C14
+#define B_PCH_TRACE_HUB_MTB_CTPEN BIT0
+#define V_PCH_TRACE_HUB_MTB_CHLCNT 0x80
+#define V_PCH_TRACE_HUB_MTB_STHMSTR 0x20
+#define R_PCH_TRACE_HUB_CSR_MTB_TSUCTRL 0x2000
+#define B_PCH_TRACE_HUB_CSR_MTB_TSUCTRL_CTCRESYNC BIT0
+
+#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsUsb.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsUsb.h
new file mode 100644
index 0000000000..6ae9ec1640
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsUsb.h
@@ -0,0 +1,529 @@
+/** @file
+ Register names for PCH USB devices
+ Conventions:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, PCH registers are denoted by "_PCH_" in register names
+ Registers / bits that are different between PCH generations are denoted by
+ _PCH_[generation_name]_" in register/bit names.
+ Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
+ Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
+ e.g., "_PCH_H_", "_PCH_LP_"
+ Registers / bits names without _H_ or _LP_ apply for both H and LP.
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a PCH generation will be just named
+ as "_PCH_" without [generation_name] inserted.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_USB_H_
+#define _PCH_REGS_USB_H_
+
+//
+// USB3 (XHCI) related definitions
+//
+#define PCI_BUS_NUMBER_PCH_XHCI 0
+#define PCI_DEVICE_NUMBER_PCH_XHCI 20
+#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
+
+//
+// XHCI PCI Config Space registers
+//
+#define V_PCH_USB_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_USB_DEVICE_ID_XHCI_1 0x8C31 ///< SKL PCH H XHCI#1
+//
+// LBG Production (PRQ) XHCI Controller Device ID
+//
+#define V_PCH_LBG_PROD_USB_DEVICE_ID_XHCI_1 0xA1AF ///< LBG Production DID XHCI#1
+//
+// LBG Super SKU (SSX) XHCI Controller Device ID
+//
+#define V_PCH_LBG_USB_DEVICE_ID_XHCI_1 0xA22F ///< LBG Super SKU DID XHCI#1
+#define V_PCH_LP_USB_DEVICE_ID_XHCI_1 0x9C31 ///< SKL PCH LP XHCI#1
+
+#define B_PCH_XHCI_CMD_PER BIT6 // PCI_COMMAND_OFFSET, Parity Error Response
+#define B_PCH_XHCI_CMD_SERR BIT8 // PCI_COMMAND_OFFSET, SERR# Enable
+
+#define R_XHCI_CFG_BAR0 0x10
+#define V_PCH_XHCI_MEM_LENGTH 0x10000
+#define N_PCH_XHCI_MEM_ALIGN 16
+#define B_PCH_XHCI_MEM_ALIGN_MASK 0xFFFF
+
+#define R_PCH_XHCI_XHCC1 0x40
+#define B_PCH_XHCI_XHCC1_ACCTRL BIT31
+#define B_PCH_XHCI_XHCC1_RMTASERR BIT24
+#define B_PCH_XHCI_XHCC1_URD BIT23
+#define B_PCH_XHCI_XHCC1_URRE BIT22
+#define B_PCH_XHCI_XHCC1_IIL1E (BIT21 | BIT20 | BIT19)
+#define V_PCH_XHCI_XHCC1_IIL1E_DIS 0
+#define V_PCH_XHCI_XHCC1_IIL1E_32 (BIT19)
+#define V_PCH_XHCI_XHCC1_IIL1E_64 (BIT20)
+#define V_PCH_XHCI_XHCC1_IIL1E_128 (BIT20 | BIT19)
+#define V_PCH_XHCI_XHCC1_IIL1E_256 (BIT21)
+#define V_PCH_XHCI_XHCC1_IIL1E_512 (BIT21 | BIT19)
+#define V_PCH_XHCI_XHCC1_IIL1E_1024 (BIT21 | BIT20)
+#define V_PCH_XHCI_XHCC1_IIL1E_131072 (BIT21 | BIT20 | BIT19)
+#define B_PCH_XHCI_XHCC1_XHCIL1E BIT18
+#define B_PCH_XHCI_XHCC1_D3IL1E BIT17
+#define B_PCH_XHCI_XHCC1_UNPPA (BIT16 | BIT15 | BIT14 | BIT13 | BIT12)
+#define B_PCH_XHCI_XHCC1_SWAXHCI BIT11
+#define B_PCH_XHCI_XHCC1_L23HRAWC (BIT10 | BIT9 | BIT8)
+#define B_PCH_XHCI_XHCC1_UTAGCP (BIT7 | BIT6)
+#define B_PCH_XHCI_XHCC1_UDAGCNP (BIT5 | BIT4)
+#define B_PCH_XHCI_XHCC1_UDAGCCP (BIT3 | BIT2)
+#define B_PCH_XHCI_XHCC1_UDAGC (BIT1 | BIT0)
+
+#define R_PCH_XHCI_XHCC2 0x44
+#define B_PCH_XHCI_XHCC2_OCCFDONE BIT31
+#define B_PCH_XHCI_XHCC2_XHCUPRDROE BIT21
+#define B_PCH_XHCI_XHCC2_IOSFSRAD BIT10
+#define B_PCH_XHCI_XHCC2_SWACXIHB (BIT9 | BIT8)
+#define B_PCH_XHCI_XHCC2_SWADMIL1IHB (BIT7 | BIT6)
+#define B_PCH_XHCI_XHCC2_L1FP2CGWC (BIT5 | BIT4 | BIT3)
+#define B_PCH_XHCI_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0)
+
+#define R_PCH_XHCI_XHCLKGTEN 0x50
+#define B_PCH_XHCI_XHCLKGTEN_SRAMPGTEN BIT27
+#define N_PCH_XHCI_XHCLKGTEN_HSTCGE 20
+#define V_PCH_XHCI_XHCLKGTEN_HSTCGE 0xC
+#define N_PCH_XHCI_XHCLKGTEN_SSTCGE 16
+#define V_PCH_XHCI_XHCLKGTEN_SSTCGE 0xE
+#define N_PCH_XHCI_XHCLKGTEN_HSPLLSU 8
+#define V_PCH_XHCI_XHCLKGTEN_HSPLLSU 0x2
+#define N_PCH_XHCI_XHCLKGTEN_SSPLLSUE 5
+#define V_PCH_XHCI_XHCLKGTEN_SSPLLSUE 0x2
+#define B_PCH_XHCI_XHCLKGTEN_SSLSE BIT26
+#define B_PCH_XHCI_XHCLKGTEN_USB2PLLSE BIT25
+#define B_PCH_XHCI_XHCLKGTEN_IOSFSTCGE BIT24
+#define B_PCH_XHCI_XHCLKGTEN_HSTCGE (BIT23 | BIT22 | BIT21 | BIT20)
+#define B_PCH_XHCI_XHCLKGTEN_SSTCGE (BIT19 | BIT18 | BIT17 | BIT16)
+#define B_PCH_XHCI_XHCLKGTEN_XHCIGEU3S BIT15
+#define B_PCH_XHCI_XHCLKGTEN_XHCFTCLKSE BIT14
+#define B_PCH_XHCI_XHCLKGTEN_XHCBBTCGIPISO BIT13
+#define B_PCH_XHCI_XHCLKGTEN_XHCHSTCGU2NRWE BIT12
+#define B_PCH_XHCI_XHCLKGTEN_XHCUSB2PLLSDLE (BIT11 | BIT10)
+#define B_PCH_XHCI_XHCLKGTEN_HSPLLSUE (BIT9 | BIT8)
+#define B_PCH_XHCI_XHCLKGTEN_SSPLLSUE (BIT7 | BIT6 | BIT5)
+#define B_PCH_XHCI_XHCLKGTEN_XHCBLCGE BIT4
+#define B_PCH_XHCI_XHCLKGTEN_HSLTCGE BIT3
+#define B_PCH_XHCI_XHCLKGTEN_SSLTCGE BIT2
+#define B_PCH_XHCI_XHCLKGTEN_IOSFBTCGE BIT1
+#define B_PCH_XHCI_XHCLKGTEN_IOSFGBLCGE BIT0
+
+#define R_PCH_XHCI_USB_RELNUM 0x60
+#define B_PCH_XHCI_USB_RELNUM 0xFF
+#define R_PCH_XHCI_FL_ADJ 0x61
+#define B_PCH_XHCI_FL_ADJ 0x3F
+#define R_PCH_XHCI_PWR_CAPID 0x70
+#define B_PCH_XHCI_PWR_CAPID 0xFF
+#define R_PCH_XHCI_NXT_PTR1 0x71
+#define B_PCH_XHCI_NXT_PTR1 0xFF
+#define R_PCH_XHCI_PWR_CAP 0x72
+#define B_PCH_XHCI_PWR_CAP_PME_SUP 0xF800
+#define B_PCH_XHCI_PWR_CAP_D2_SUP BIT10
+#define B_PCH_XHCI_PWR_CAP_D1_SUP BIT9
+#define B_PCH_XHCI_PWR_CAP_AUX_CUR (BIT8 | BIT7 | BIT6)
+#define B_PCH_XHCI_PWR_CAP_DSI BIT5
+#define B_PCH_XHCI_PWR_CAP_PME_CLK BIT3
+#define B_PCH_XHCI_PWR_CAP_VER (BIT2 | BIT1 | BIT0)
+#define R_PCH_XHCI_PWR_CNTL_STS 0x74
+#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15
+#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13)
+#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9)
+#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8
+#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)
+#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)
+#define R_PCH_XHCI_MSI_MCTL 0x82
+#define R_PCH_XHCI_U2OCM 0xB0
+#define R_PCH_XHCI_U3OCM 0xD0
+#define V_PCH_XHCI_NUMBER_OF_OC_PINS 8
+
+#define R_PCH_XHCI_FUS 0xE0
+#define B_PCH_XHCI_FUS_USBR (BIT5)
+#define V_PCH_XHCI_FUS_USBR_EN 0
+#define V_PCH_XHCI_FUS_USBR_DIS (BIT5)
+
+#define R_PCH_XHCI_FC 0xFC
+
+#define B_PCH_XHCI_FUS_SSPRTCNT (BIT4 | BIT3)
+#define V_PCH_XHCI_FUS_SSPRTCNT_00B 0
+#define V_PCH_XHCI_FUS_SSPRTCNT_01B (BIT3)
+#define V_PCH_XHCI_FUS_SSPRTCNT_10B (BIT4)
+#define V_PCH_XHCI_FUS_SSPRTCNT_11B (BIT4 | BIT3)
+
+#define B_PCH_XHCI_FUS_HSPRTCNT (BIT2 | BIT1)
+#define V_PCH_XHCI_FUS_HSPRTCNT_00B 0
+#define V_PCH_XHCI_FUS_HSPRTCNT_01B (BIT1)
+#define V_PCH_XHCI_FUS_HSPRTCNT_10B (BIT2)
+#define V_PCH_XHCI_FUS_HSPRTCNT_11B (BIT2 | BIT1)
+
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_CNT 6
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_CNT 4
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_CNT 2
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_CNT 0
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_MASK 0x3F
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_MASK 0x0F
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_MASK 0x03
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_MASK 0x00
+
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_CNT 14
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_CNT 12
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_CNT 10
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_CNT 8
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_MASK 0x3FFF
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_MASK 0x3F3F
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_MASK 0x03FF
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_MASK 0x00FF
+
+#define V_PCH_LP_XHCI_FIXED_SSPRTCNT 4
+#define V_PCH_LP_XHCI_FIXED_SSPRTCNT_MASK 0x0F
+
+#define V_PCH_LP_XHCI_FIXED_HSPRTCNT 8
+#define V_PCH_LP_XHCI_FIXED_HSPRTCNT_MASK 0x00FF
+
+//
+// xHCI MMIO registers
+//
+
+//
+// 0x00 - 0x1F - Capability Registers
+//
+#define R_PCH_XHCI_CAPLENGTH 0x00
+#define R_PCH_XHCI_HCIVERSION 0x02
+#define R_PCH_XHCI_HCSPARAMS1 0x04
+#define R_PCH_XHCI_HCSPARAMS2 0x08
+#define R_PCH_XHCI_HCSPARAMS3 0x0C
+#define B_PCH_XHCI_HCSPARAMS3_U2DEL 0xFFFF0000
+#define B_PCH_XHCI_HCSPARAMS3_U1DEL 0x0000FFFF
+#define R_PCH_XHCI_HCCPARAMS 0x10
+#define B_PCH_XHCI_HCCPARAMS_LHRC BIT5
+#define B_PCH_XHCI_HCCPARAMS_MAXPSASIZE 0xF000
+#define R_PCH_XHCI_DBOFF 0x14
+#define R_PCH_XHCI_RTSOFF 0x18
+
+//
+// 0x80 - 0xBF - Operational Registers
+//
+#define R_PCH_XHCI_USBCMD 0x80
+#define B_PCH_XHCI_USBCMD_RS BIT0 ///< Run/Stop
+#define B_PCH_XHCI_USBCMD_RST BIT1 ///< HCRST
+#define B_PCH_XHCI_USBCMD_HSEE BIT3 //Host System Error Enable
+#define R_PCH_XHCI_USBSTS 0x84
+#define B_PCH_XHCI_USBSTS_HCH BIT0
+#define B_PCH_XHCI_USBSTS_CNR BIT11
+
+//
+// 0x480 - 0x5CF - Port Status and Control Registers
+//
+#define R_PCH_LP_XHCI_PORTSC01USB2 0x480
+#define R_PCH_LP_XHCI_PORTSC02USB2 0x490
+#define R_PCH_LP_XHCI_PORTSC03USB2 0x4A0
+#define R_PCH_LP_XHCI_PORTSC04USB2 0x4B0
+#define R_PCH_LP_XHCI_PORTSC05USB2 0x4C0
+#define R_PCH_LP_XHCI_PORTSC06USB2 0x4D0
+#define R_PCH_LP_XHCI_PORTSC07USB2 0x4E0
+#define R_PCH_LP_XHCI_PORTSC08USB2 0x4F0
+#define R_PCH_LP_XHCI_PORTSC09USB2 0x500
+#define R_PCH_LP_XHCI_PORTSC10USB2 0x510
+
+#define R_PCH_LP_XHCI_PORTSC13USBR 0x520
+#define R_PCH_LP_XHCI_PORTSC14USBR 0x530
+
+#define R_PCH_LP_XHCI_PORTSC01USB3 0x540
+#define R_PCH_LP_XHCI_PORTSC02USB3 0x550
+#define R_PCH_LP_XHCI_PORTSC03USB3 0x560
+#define R_PCH_LP_XHCI_PORTSC04USB3 0x570
+#define R_PCH_LP_XHCI_PORTSC05USB3 0x580
+#define R_PCH_LP_XHCI_PORTSC06USB3 0x590
+
+//
+// 0x480 - 0x5CF - Port Status and Control Registers
+//
+#define R_PCH_H_XHCI_PORTSC01USB2 0x480
+#define R_PCH_H_XHCI_PORTSC02USB2 0x490
+#define R_PCH_H_XHCI_PORTSC03USB2 0x4A0
+#define R_PCH_H_XHCI_PORTSC04USB2 0x4B0
+#define R_PCH_H_XHCI_PORTSC05USB2 0x4C0
+#define R_PCH_H_XHCI_PORTSC06USB2 0x4D0
+#define R_PCH_H_XHCI_PORTSC07USB2 0x4E0
+#define R_PCH_H_XHCI_PORTSC08USB2 0x4F0
+#define R_PCH_H_XHCI_PORTSC09USB2 0x500
+#define R_PCH_H_XHCI_PORTSC10USB2 0x510
+#define R_PCH_H_XHCI_PORTSC11USB2 0x520
+#define R_PCH_H_XHCI_PORTSC12USB2 0x530
+#define R_PCH_H_XHCI_PORTSC13USB2 0x540
+#define R_PCH_H_XHCI_PORTSC14USB2 0x550
+
+#define R_PCH_H_XHCI_PORTSC15USBR 0x560
+#define R_PCH_H_XHCI_PORTSC16USBR 0x570
+
+#define R_PCH_H_XHCI_PORTSC01USB3 0x580
+#define R_PCH_H_XHCI_PORTSC02USB3 0x590
+#define R_PCH_H_XHCI_PORTSC03USB3 0x5A0
+#define R_PCH_H_XHCI_PORTSC04USB3 0x5B0
+#define R_PCH_H_XHCI_PORTSC05USB3 0x5C0
+#define R_PCH_H_XHCI_PORTSC06USB3 0x5D0
+#define R_PCH_H_XHCI_PORTSC07USB3 0x5E0
+#define R_PCH_H_XHCI_PORTSC08USB3 0x5F0
+#define R_PCH_H_XHCI_PORTSC09USB3 0x600
+#define R_PCH_H_XHCI_PORTSC10USB3 0x610
+
+#define B_PCH_XHCI_PORTSCXUSB2_WPR BIT31 ///< Warm Port Reset
+#define B_PCH_XHCI_PORTSCXUSB2_WDE BIT26 ///< Wake on Disconnect Enable
+#define B_PCH_XHCI_PORTSCXUSB2_WCE BIT25 ///< Wake on Connect Enable
+#define B_PCH_XHCI_PORTSCXUSB2_CEC BIT23 ///< Port Config Error Change
+#define B_PCH_XHCI_PORTSCXUSB2_PLC BIT22 ///< Port Link State Change
+#define B_PCH_XHCI_PORTSCXUSB2_PRC BIT21 ///< Port Reset Change
+#define B_PCH_XHCI_PORTSCXUSB2_OCC BIT20 ///< Over-current Change
+#define B_PCH_XHCI_PORTSCXUSB2_WRC BIT19 ///< Warm Port Reset Change
+#define B_PCH_XHCI_PORTSCXUSB2_PEC BIT18 ///< Port Enabled Disabled Change
+#define B_PCH_XHCI_PORTSCXUSB2_CSC BIT17 ///< Connect Status Change
+#define B_PCH_XHCI_PORTSCXUSB2_LWS BIT16 ///< Port Link State Write Strobe
+#define B_PCH_XHCI_USB2_U3_EXIT (BIT5 | BIT6 | BIT7 | BIT8)
+#define B_PCH_XHCI_USB2_U0_MASK (BIT5 | BIT6 | BIT7 | BIT8)
+#define B_PCH_XHCI_PORTSCXUSB2_PP BIT9
+#define B_PCH_XHCI_PORTSCXUSB2_PLS (BIT5 | BIT6 | BIT7 | BIT8) ///< Port Link State
+#define B_PCH_XHCI_PORTSCXUSB2_PR BIT4 ///< Port Reset
+#define B_PCH_XHCI_PORTSCXUSB2_PED BIT1 ///< Port Enable/Disabled
+#define B_PCH_XHCI_PORTSCXUSB2_CCS BIT0 ///< Current Connect Status
+#define B_PCH_XHCI_PORT_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB2_CEC | B_PCH_XHCI_PORTSCXUSB2_PLC | B_PCH_XHCI_PORTSCXUSB2_PRC | B_PCH_XHCI_PORTSCXUSB2_OCC | B_PCH_XHCI_PORTSCXUSB2_WRC | B_PCH_XHCI_PORTSCXUSB2_PEC | B_PCH_XHCI_PORTSCXUSB2_CSC | B_PCH_XHCI_PORTSCXUSB2_PED)
+#define B_PCH_XHCI_PORTPMSCXUSB2_PTC (BIT28 | BIT29 | BIT30 | BIT31) ///< Port Test Control
+
+#define B_PCH_XHCI_PORTSCXUSB3_WPR BIT31 ///< Warm Port Reset
+#define B_PCH_XHCI_PORTSCXUSB3_WDE BIT26 ///< Wake on Disconnect Enable
+#define B_PCH_XHCI_PORTSCXUSB3_WCE BIT25 ///< Wake on Connect Enable
+#define B_PCH_XHCI_PORTSCXUSB3_CEC BIT23 ///< Port Config Error Change
+#define B_PCH_XHCI_PORTSCXUSB3_PLC BIT22 ///< Port Link State Change
+#define B_PCH_XHCI_PORTSCXUSB3_PRC BIT21 ///< Port Reset Change
+#define B_PCH_XHCI_PORTSCXUSB3_OCC BIT20 ///< Over-current Change
+#define B_PCH_XHCI_PORTSCXUSB3_WRC BIT19 ///< Warm Port Reset Change
+#define B_PCH_XHCI_PORTSCXUSB3_PEC BIT18 ///< Port Enabled Disabled Change
+#define B_PCH_XHCI_PORTSCXUSB3_CSC BIT17 ///< Connect Status Change
+#define B_PCH_XHCI_PORTSCXUSB3_PP BIT9 ///< Port Power
+#define B_PCH_XHCI_PORTSCXUSB3_PLS (BIT8 | BIT7 | BIT6 | BIT5) ///< Port Link State
+#define V_PCH_XHCI_PORTSCXUSB3_PLS_POLLING 0x000000E0 ///< Link is in the Polling State
+#define V_PCH_XHCI_PORTSCXUSB3_PLS_RXDETECT 0x000000A0 ///< Link is in the RxDetect State
+#define B_PCH_XHCI_PORTSCXUSB3_PR BIT4 ///< Port Reset
+#define B_PCH_XHCI_PORTSCXUSB3_PED BIT1 ///< Port Enable/Disabled
+#define B_PCH_XHCI_PORTSCXUSB3_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB3_CEC | B_PCH_XHCI_PORTSCXUSB3_PLC | B_PCH_XHCI_PORTSCXUSB3_PRC | B_PCH_XHCI_PORTSCXUSB3_OCC | B_PCH_XHCI_PORTSCXUSB3_WRC | B_PCH_XHCI_PORTSCXUSB3_PEC | B_PCH_XHCI_PORTSCXUSB3_CSC | B_PCH_XHCI_PORTSCXUSB3_PED)
+//
+// 0x2000 - 0x21FF - Runtime Registers
+// 0x3000 - 0x307F - Doorbell Registers
+//
+
+
+#define R_PCH_XHCI_PCE 0xA2
+#define R_PCH_XHCI_HSCFG2 0xA4
+#define R_PCH_XHCI_SSCFG1 0xA8
+#define R_PCH_XHCI_HSCFG1 0xAC
+
+#define R_PCH_XHCI_XECP_SUPP_USB2_2 0x8008
+#define R_PCH_XHCI_XECP_SUPP_USB3_2 0x8028
+#define R_PCH_XHCI_HOST_CTRL_TRM_REG 0x8090
+#define R_PCH_XHCI_HOST_CTRL_SCH_REG 0x8094
+#define R_PCH_XHCI_HOST_CTRL_IDMA_REG 0x809C
+#define R_PCH_XHCI_PMCTRL 0x80A4
+#define R_PCH_XHCI_PGCBCTRL 0x80A8 ///< PGCB Control
+#define R_PCH_XHCI_HOST_CTRL_MISC_REG 0x80B0 ///< Host Controller Misc Reg
+#define R_PCH_XHCI_HOST_CTRL_MISC_REG_2 0x80B4 ///< Host Controller Misc Reg 2
+#define R_PCH_XHCI_SSPE 0x80B8 ///< Super Speed Port Enables
+#define B_PCH_XHCI_LP_SSPE_MASK 0x3F ///< LP: Mask for 6 USB3 ports
+#define B_PCH_XHCI_H_SSPE_MASK 0x3FF ///< H: Mask for 10 USB3 ports
+#define R_PCH_XHCI_DUAL_ROLE_CFG0 0x80D8
+#define R_PCH_XHCI_DUAL_ROLE_CFG1 0x80DC
+#define R_PCH_XHCI_AUX_CTRL_REG1 0x80E0
+#define R_PCH_XHCI_HOST_CTRL_PORT_LINK_REG 0x80EC ///< SuperSpeed Port Link Control
+#define R_PCH_XHCI_XECP_CMDM_CTRL_REG1 0x818C ///< Command Manager Control 1
+#define R_PCH_XHCI_XECP_CMDM_CTRL_REG2 0x8190 ///< Command Manager Control 2
+#define R_PCH_XHCI_XECP_CMDM_CTRL_REG3 0x8194 ///< Command Manager Control 3
+#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW1 0x80F0 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
+#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW2 0x80F4 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
+#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW3 0x80F8 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
+#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW4 0x80FC ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
+#define R_PCH_XHCI_HOST_CTRL_TRM_REG2 0x8110 ///< HOST_CTRL_TRM_REG2 - Host Controller Transfer Manager Control 2
+#define R_PCH_XHCI_HOST_CTRL_BW_MAX_REG_DW1 0x8128 ///< HOST_CTRL_BW_MAX_REG - MAX BW Control Reg 4
+#define R_PCH_XHCI_HOST_CTRL_BW_MAX_REG_DW2 0x812C ///< HOST_CTRL_BW_MAX_REG - MAX BW Control Reg 4
+#define R_PCH_XHCI_AUX_CTRL_REG2 0x8154 ///< AUX_CTRL_REG2 - Aux PM Control Register 2
+#define R_PCH_XHCI_AUXCLKCTL 0x816C ///< xHCI Aux Clock Control Register
+#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG0 0x8140 ///< HOST_IF_PWR_CTRL_REG0 - Power Scheduler Control 0
+#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG1 0x8144 ///< HOST_IF_PWR_CTRL_REG1 - Power Scheduler Control 1
+#define R_PCH_XHCI_XHCLTVCTL2 0x8174 ///< xHC Latency Tolerance Parameters - LTV Control
+#define R_PCH_XHCI_LTVHIT 0x817C ///< xHC Latency Tolerance Parameters - High Idle Time Control
+#define R_PCH_XHCI_LTVMIT 0x8180 ///< xHC Latency Tolerance Parameters - Medium Idle Time Control
+#define R_PCH_XHCI_LTVLIT 0x8184 ///< xHC Latency Tolerance Parameters - Low Idle Time Control
+#define R_PCH_XHCI_USB2PHYPM 0x8164 ///< USB2 PHY Power Management Control
+#define R_PCH_XHCI_PDDIS 0x8198 ///< xHC Pulldown Disable Control
+#define R_PCH_XHCI_THROTT 0x819C ///< XHCI Throttle Control
+#define R_PCH_XHCI_LFPSPM 0x81A0 ///< LFPS PM Control
+#define R_PCH_XHCI_THROTT2 0x81B4 ///< XHCI Throttle
+#define R_PCH_XHCI_LFPSONCOUNT 0x81B8 ///< LFPS On Count
+#define R_PCH_XHCI_D0I2CTRL 0x81BC ///< D0I2 Control Register
+#define R_PCH_XHCI_USB2PMCTRL 0x81C4 ///< USB2 Power Management Control
+
+//
+// SKL PCH LP FUSE
+//
+#define R_PCH_XHCI_LP_FUSE1 0x8410
+#define B_PCH_XHCI_LP_FUS_HSPRTCNT (BIT1)
+#define B_PCH_XHCI_LP_FUS_USBR (BIT5)
+#define R_PCH_XHCI_STRAP2 0x8420 ///< USB3 Mode Strap
+#define R_PCH_XHCI_USBLEGCTLSTS 0x8470 ///< USB Legacy Support Control Status
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIBAR BIT31 ///< SMI on BAR Status
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCIC BIT30 ///< SMI on PCI Command Status
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSC BIT29 ///< SMI on OS Ownership Change Status
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIBARE BIT15 ///< SMI on BAR Enable
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCICE BIT14 ///< SMI on PCI Command Enable
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSOE BIT13 ///< SMI on OS Ownership Enable
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIHSEE BIT4 ///< SMI on Host System Error Enable
+#define B_PCH_XHCI_USBLEGCTLSTS_USBSMIE BIT0 ///< USB SMI Enable
+
+//
+// Extended Capability Registers
+//
+#define R_PCH_XHCI_USB2PDO 0x84F8
+#define B_PCH_XHCI_LP_USB2PDO_MASK 0x3FF ///< LP: Mask for 10 USB2 ports
+#define B_PCH_XHCI_H_USB2PDO_MASK 0x7FFF ///< H: Mask for 14 USB2 ports
+#define B_PCH_XHCI_USB2PDO_DIS_PORT0 BIT0
+
+#define R_PCH_XHCI_USB3PDO 0x84FC
+#define B_PCH_XHCI_LP_USB3PDO_MASK 0x3F ///< LP: Mask for 6 USB3 ports
+#define B_PCH_XHCI_H_USB3PDO_MASK 0x3FF ///< H: Mask for 10 USB3 ports
+#define B_PCH_XHCI_USB3PDO_DIS_PORT0 BIT0
+
+//
+// Debug Capability Descriptor Parameters
+//
+#define R_PCH_XHCI_DBC_DBCCTL 0x8760 ///< DBCCTL - DbC Control
+
+//
+// xDCI (OTG) USB Device Controller
+//
+#define PCI_DEVICE_NUMBER_PCH_XDCI 20
+#define PCI_FUNCTION_NUMBER_PCH_XDCI 1
+
+#define V_PCH_XDCI_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_XDCI_DEVICE_ID 0x9D30
+
+//
+// LBG Pruduction (PRQ) xDCI (OTG) USB Device Controller Device ID
+//
+#define V_PCH_LBG_PROD_XDCI_DEVICE_ID 0xA1B0
+//
+// LBG SuperSKU (SSX) xDCI (OTG) USB Device Controller Device ID
+//
+#define V_PCH_LBG_XDCI_DEVICE_ID 0xA230
+
+//
+// xDCI (OTG) PCI Config Space Registers
+//
+#define R_PCH_XDCI_MEM_BASE 0x10
+#define V_PCH_XDCI_MEM_LENGTH 0x200000
+#define R_PCH_XDCI_PMCSR 0x84 ///< Power Management Control and Status Register
+#define R_PCH_XDCI_GENERAL_PURPOSER_REG1 0xA0 ///< General Purpose PCI RW Register1
+#define R_PCH_XDCI_CPGE 0xA2 ///< Chassis Power Gate Enable
+#define R_PCH_XDCI_GENERAL_PURPOSER_REG4 0xAC ///< General Purpose PCI RW Register4
+#define R_PCH_OTG_GENERAL_INPUT_REG 0xC0 ///< General Input Register
+
+//
+// xDCI (OTG) MMIO registers
+//
+#define R_PCH_XDCI_GCTL 0xC110 ///< Xdci Global Ctrl
+#define B_PCH_XDCI_GCTL_GHIBEREN BIT1 ///< Hibernation enable
+#define R_PCH_XDCI_GUSB2PHYCFG 0xC200 ///< Global USB2 PHY Configuration Register
+#define B_PCH_XDCI_GUSB2PHYCFG_SUSPHY BIT6 ///< Suspend USB2.0 HS/FS/LS PHY
+#define R_PCH_XDCI_GUSB3PIPECTL0 0xC2C0 ///< Global USB3 PIPE Control Register 0
+#define B_PCH_XDCI_GUSB3PIPECTL0_UX_IN_PX BIT27 ///< Ux Exit in Px
+#define R_PCH_XDCI_APBFC_U3PMU_CFG2 0x10F810
+#define R_PCH_XDCI_APBFC_U3PMU_CFG4 0x10F818
+
+//
+// xDCI (OTG) Private Configuration Registers
+// (PID:OTG)
+//
+#define R_PCH_PCR_OTG_IOSF_A2 0xA2
+#define R_PCH_PCR_OTG_IOSF_PMCTL 0x1D0
+#define R_PCH_PCR_OTG_PCICFGCTRL1 0x200
+#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 0x0FF00000
+#define N_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 20
+#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 0x000FF000
+#define N_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 12
+#define B_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 0x00000F00
+#define N_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 8
+#define B_PCH_PCR_OTG_PCICFGCTRL_BAR1_DIS 0x00000080
+#define B_PCH_PCR_OTG_PCICFGCTRL_PME_SUP 0x0000007C
+#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_INT_EN 0x00000002
+#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_CFG_DIS 0x00000001
+
+//
+// USB2 Private Configuration Registers
+// USB2 HIP design featured
+// (PID:USB2)
+//
+#define R_PCH_PCR_USB2_GLOBAL_PORT 0x4001 ///< USB2 GLOBAL PORT
+#define R_PCH_PCR_USB2_400C 0x400C
+#define R_PCH_PCR_USB2_PP_LANE_BASE_ADDR 0x4000 ///< PP LANE base address
+#define V_PCH_PCR_USB2_PER_PORT 0x00 ///< USB2 PER PORT Addr[7:2] = 0x00
+#define V_PCH_PCR_USB2_UTMI_MISC_PER_PORT 0x08 ///< UTMI MISC REG PER PORT Addr[7:2] = 0x08
+#define V_PCH_PCR_USB2_PER_PORT_2 0x26 ///< USB2 PER PORT 2 Addr[7:2] = 0x26
+#define R_PCH_PCR_USB2_402A 0x402A
+#define R_PCH_PCR_USB2_GLB_ADP_VBUS_REG 0x402B ///< GLB ADP VBUS REG
+#define R_PCH_PCR_USB2_GLOBAL_PORT_2 0x402C ///< USB2 GLOBAL PORT 2
+#define R_PCH_PCR_USB2_PLLDIVRATIOS_0 0x7000
+#define R_PCH_PCR_USB2_SFRCONFIG_0 0x702C
+#define R_PCH_PCR_USB2_CONFIG_0 0x7008
+#define R_PCH_PCR_USB2_CONFIG_3 0x7014
+#define R_PCH_PCR_USB2_DFT_1 0x7024
+#define R_PCH_PCR_USB2_7034 0x7034
+#define R_PCH_PCR_USB2_7038 0x7038
+#define R_PCH_PCR_USB2_703C 0x703C
+#define R_PCH_PCR_USB2_7040 0x7040
+#define R_PCH_PCR_USB2_7044 0x7044
+#define R_PCH_PCR_USB2_7048 0x7048
+#define R_PCH_PCR_USB2_704C 0x704C
+#define R_PCH_PCR_USB2_CFG_COMPBG 0x7F04 ///< USB2 COMPBG
+
+//
+// xHCI SSIC registers
+//
+#define R_PCH_XHCI_SSIC_GLOBAL_CONF_CTRL 0x8804 ///< SSIC Global Configuration Control
+#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_1 0x8808 ///< SSIC Configuration Register 1 Port 1
+#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_1 0x880C ///< SSIC Configuration Register 2 Port 1
+#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_1 0x8810 ///< SSIC Configuration Register 3 Port 1
+#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_2 0x8838 ///< SSIC Configuration Register 1 Port 2
+#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_2 0x883C ///< SSIC Configuration Register 2 Port 2
+#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_2 0x8840 ///< SSIC Configuration Register 3 Port 2
+#define B_PCH_XHCI_SSIC_CONF_REG2_PORT_UNUSED BIT31
+#define B_PCH_XHCI_SSIC_CONF_REG2_PROG_DONE BIT30
+
+#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_1 0x8900 ///< Profile Attributes: Port 1 ... N
+#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_1 0x8904 ///< SSIC Port N Register Access Control: Port 1
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_0C 0x890C
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_10 0x8910
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_14 0x8914
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_18 0x8918
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_1C 0x891C
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_20 0x8920
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_24 0x8924
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_28 0x8928
+
+#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_2 0x8A10 ///< Profile Attributes: Port 2 ... N
+#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_2 0x8A14 ///< SSIC Port N Register Access Control: Port 2
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_0C 0x8A1C
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_10 0x8A20
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_14 0x8A24
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_18 0x8A28
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_1C 0x8A2C
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_20 0x8A30
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_24 0x8A34
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_28 0x8A38
+
+#endif
--
2.27.0.windows.1
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