[edk2-devel] [edk2-platforms] [PATCH V1 02/18] PurleyRefreshSiliconPkg/Pch: Add Register Header Files
Nate DeSimone
nathaniel.l.desimone at intel.com
Tue May 11 09:48:10 UTC 2021
Cc: Chasel Chiu <chasel.chiu at intel.com>
Cc: Mike Kinney <michael.d.kinney at intel.com>
Cc: Isaac Oram <isaac.w.oram at intel.com>
Cc: Mohamed Abbas <mohamed.abbas at intel.com>
Cc: Michael Kubacki <michael.kubacki at microsoft.com>
Cc: Zachary Bobroff <zacharyb at ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad at ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
---
.../Pch/Include/Register/PchRegsDci.h | 24 +
.../Pch/Include/Register/PchRegsDmi.h | 188 ++++++
.../Pch/Include/Register/PchRegsEva.h | 110 +++
.../Pch/Include/Register/PchRegsFia.h | 81 +++
.../Pch/Include/Register/PchRegsGpio.h | 511 ++++++++++++++
.../Pch/Include/Register/PchRegsHda.h | 226 +++++++
.../Pch/Include/Register/PchRegsHsio.h | 171 +++++
.../Pch/Include/Register/PchRegsIsh.h | 51 ++
.../Pch/Include/Register/PchRegsItss.h | 68 ++
.../Pch/Include/Register/PchRegsLan.h | 135 ++++
.../Pch/Include/Register/PchRegsLpc.h | 430 ++++++++++++
.../Pch/Include/Register/PchRegsP2sb.h | 100 +++
.../Pch/Include/Register/PchRegsPcie.h | 513 ++++++++++++++
.../Pch/Include/Register/PchRegsPcr.h | 64 ++
.../Pch/Include/Register/PchRegsPmc.h | 627 +++++++++++++++++
.../Pch/Include/Register/PchRegsPsf.h | 210 ++++++
.../Pch/Include/Register/PchRegsPsth.h | 46 ++
.../Pch/Include/Register/PchRegsSata.h | 634 ++++++++++++++++++
.../Pch/Include/Register/PchRegsScs.h | 152 +++++
.../Pch/Include/Register/PchRegsSerialIo.h | 282 ++++++++
.../Pch/Include/Register/PchRegsSmbus.h | 134 ++++
.../Pch/Include/Register/PchRegsSpi.h | 291 ++++++++
.../Pch/Include/Register/PchRegsThermal.h | 93 +++
.../Pch/Include/Register/PchRegsTraceHub.h | 125 ++++
.../Pch/Include/Register/PchRegsUsb.h | 463 +++++++++++++
25 files changed, 5729 insertions(+)
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsDci.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsDmi.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsEva.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsFia.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsGpio.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsHda.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsHsio.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsIsh.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsItss.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsLan.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsLpc.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsP2sb.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPcie.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPcr.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPmc.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPsf.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPsth.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSata.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsScs.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSmbus.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSpi.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsThermal.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsTraceHub.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsUsb.h
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsDci.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsDci.h
new file mode 100644
index 0000000000..93d54793f3
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsDci.h
@@ -0,0 +1,24 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_DCI_H_
+#define _PCH_REGS_DCI_H_
+
+//
+// DCI PCR Registers
+//
+#define R_PCH_PCR_DCI_ECTRL 0x04 ///< DCI Control Register
+#define B_PCH_PCR_DCI_ECTRL_HDCILOCK BIT0 ///< Host DCI lock
+#define B_PCH_PCR_DCI_ECTRL_HDCIEN BIT4 ///< Host DCI enable
+#define R_PCH_PCR_DCI_ECKPWRCTL 0x08 ///< DCI Power Control
+#define R_PCH_PCR_DCI_PCE 0x30 ///< DCI Power Control Enable Register
+#define B_PCH_PCR_DCI_PCE_HAE BIT5 ///< Hardware Autonomous Enable
+#define B_PCH_PCR_DCI_PCE_D3HE BIT2 ///< D3-Hot Enable
+#define B_PCH_PCR_DCI_PCE_I3E BIT1 ///< I3 Enable
+#define B_PCH_PCR_DCI_PCE_PMCRE BIT0 ///< PMC Request Enable
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsDmi.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsDmi.h
new file mode 100644
index 0000000000..098cac742a
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsDmi.h
@@ -0,0 +1,188 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_DMI_H_
+#define _PCH_REGS_DMI_H_
+
+//
+// DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// VC Configuration (Common)
+//
+#define R_PCH_PCR_DMI_V0CTL 0x2014 ///< Virtual channel 0 resource control
+#define B_PCH_PCR_DMI_V0CTL_EN BIT31
+#define B_PCH_PCR_DMI_V0CTL_ID (7 << 24) ///< Bit[26:24]
+#define N_PCH_PCR_DMI_V0CTL_ID 24
+#define V_PCH_PCR_DMI_V0CTL_ETVM_MASK 0xFC00
+#define V_PCH_PCR_DMI_V0CTL_TVM_MASK 0x7E
+#define R_PCH_PCR_DMI_V0STS 0x201A ///< Virtual channel 0 status
+#define B_PCH_PCR_DMI_V0STS_NP BIT1
+#define R_PCH_PCR_DMI_V1CTL 0x2020 ///< Virtual channel 1 resource control
+#define B_PCH_PCR_DMI_V1CTL_EN BIT31
+#define B_PCH_PCR_DMI_V1CTL_ID (0x0F << 24) ///< Bit[27:24]
+#define N_PCH_PCR_DMI_V1CTL_ID 24
+#define V_PCH_PCR_DMI_V1CTL_ETVM_MASK 0xFC00
+#define V_PCH_PCR_DMI_V1CTL_TVM_MASK 0xFE
+#define R_PCH_PCR_DMI_V1STS 0x2026 ///< Virtual channel 1 status
+#define B_PCH_PCR_DMI_V1STS_NP BIT1
+#define R_PCH_PCR_DMI_VMCTL 0x2040 ///< ME Virtual Channel (VCm) resource control
+#define R_PCH_PCR_DMI_VMSTS 0x2046 ///< ME Virtual Channel Resource Status
+#define R_PCH_PCR_DMI_UEM 0x2088 ///< Uncorrectable Error Mask
+#define R_PCH_PCR_DMI_REC 0x20AC ///< Root Error Command
+
+//
+// Internal Link Configuration (DMI Only)
+//
+#define R_PCH_PCR_DMI_LCAP 0x21A4 ///< Link Capabilities
+#define B_PCH_PCR_DMI_LCAP_EL1 (BIT17 | BIT16 | BIT15)
+#define B_PCH_PCR_DMI_LCAP_EL0 (BIT14 | BIT13 | BIT12)
+#define B_PCH_PCR_DMI_LCAP_APMS (BIT11 | BIT10) ///< L0 is supported on DMI
+#define B_PCH_PCR_DMI_LCAP_MLW 0x000003F0
+#define B_PCH_PCR_DMI_LCAP_MLS 0x0000000F
+#define R_PCH_PCR_DMI_LCTL 0x21A8 ///< Link Control
+#define B_PCH_PCR_DMI_LCTL_ES BIT7
+#define B_PCH_PCR_DMI_LCTL_ASPM (BIT1 | BIT0) ///< Link ASPM
+#define R_PCH_PCR_DMI_LSTS 0x21AA ///< Link Status
+#define R_PCH_PCR_DMI_LCTL2 0x21B0 ///< Link Control 2
+#define R_PCH_PCR_DMI_LSTS2 0x21B2 ///< Link Status 2
+#define R_PCH_PCR_DMI_L01EC 0x21BC ///< Lane 0 and Lane 1 Equalization Control
+#define R_PCH_PCR_DMI_L23EC 0x21C0 ///< Lane 2 and Lane 3 Equalization Control
+#define B_PCH_PCR_DMI_UPL13RPH 0x0F000000 ///< Upstream Port Lane 1/3 Transmitter Preset Hint mask
+#define N_PCH_PCR_DMI_UPL13RPH 24 ///< Upstream Port Lane 1/3 Transmitter Preset Hint value offset
+#define B_PCH_PCR_DMI_UPL02RPH 0x000000F0 ///< Upstream Port Lane 0/2 Transmitter Preset Hint mask
+#define N_PCH_PCR_DMI_UPL02RPH 8 ///< Upstream Port Lane 0/2 Transmitter Preset Hint value offset
+#define V_PCH_PCR_DMI_UPL0RPH 7 ///< Upstream Port Lane 0 Transmitter Preset Hint value
+#define V_PCH_PCR_DMI_UPL1RPH 7 ///< Upstream Port Lane 1 Transmitter Preset Hint value
+#define V_PCH_PCR_DMI_UPL2RPH 7 ///< Upstream Port Lane 2 Transmitter Preset Hint value
+#define V_PCH_PCR_DMI_UPL3RPH 7 ///< Upstream Port Lane 3 Transmitter Preset Hint value
+
+
+//
+// North Port Error Injection Configuration (DMI Only)
+//
+#define R_PCH_PCR_DMI_DMIEN 0x2230 ///< DMI Error Injection Enable
+
+//
+// DMI Control
+//
+#define R_PCH_PCR_DMI_DMIC 0x2234 ///< DMI Control
+#define B_PCH_PCR_DMI_DMIC_SRL BIT31 ///< Secured register lock
+#define B_PCH_PCR_DMI_DMIC_ORCE (BIT25 | BIT24) ///< Offset Re-Calibration Enable
+#define N_PCH_PCR_DMI_DMIC_ORCE 24
+#define V_PCH_PCR_DMI_DMIC_ORCE_EN_GEN2_GEN3 1 ///< Enable offset re-calibration for Gen 2 and Gen 3 data rate only.
+#define B_PCH_PCR_DMI_DMIC_DMICGEN (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) ///< DMI Clock Gate Enable
+#define R_PCH_PCR_DMI_DMIHWAWC 0x2238 ///< DMI HW Autonomus Width Control
+#define R_PCH_PCR_DMI_IOSFSBCS 0x223E ///< IOSF Sideband Control and Status
+#define B_PCH_PCR_DMI_IOSFSBCS_DMICGEN (BIT6 | BIT5 | BIT3 | BIT2) ///< DMI Clock Gate Enable
+
+#define R_PCH_PCR_DMI_2300 0x2300
+#define R_PCH_PCR_DMI_2304 0x2304
+#define R_PCH_PCR_DMI_2310 0x2310
+#define R_PCH_PCR_DMI_2314 0x2314
+#define R_PCH_PCR_DMI_2320 0x2320
+#define R_PCH_PCR_DMI_2324 0x2324
+#define R_PCH_PCR_DMI_232C 0x232C
+#define R_PCH_PCR_DMI_2334 0x2334
+#define R_PCH_PCR_DMI_2338 0x2338
+#define R_PCH_PCR_DMI_2340 0x2340
+#define R_PCH_PCR_DMI_2344 0x2344
+#define R_PCH_PCR_DMI_2348 0x2348
+#define R_PCH_PCR_DMI_234C 0x234C
+
+//
+// Port Configuration Extension(DMI Only)
+//
+#define R_PCH_PCR_DMI_EQCFG1 0x2450
+#define B_PCH_PCR_DMI_EQCFG1_RTLEPCEB BIT16
+#define R_PCH_PCR_DMI_LTCO1 0x2470 ///< Local Transmitter Coefficient Override 1
+#define R_PCH_PCR_DMI_LTCO2 0x2474 ///< Local Transmitter Coefficient Override 2
+#define B_PCH_PCR_DMI_L13TCOE BIT25 ///< Lane 1/3 Transmitter Coefficient Override Enable
+#define B_PCH_PCR_DMI_L02TCOE BIT24 ///< Lane 0/2 Transmitter Coefficient Override Enable
+#define B_PCH_PCR_DMI_L13TPOSTCO 0x00fc0000 ///< Lane 1/3 Transmitter Post-Cursor Coefficient Override mask
+#define N_PCH_PCR_DMI_L13TPOSTCO 18 ///< Lane 1/3 Transmitter Post-Cursor Coefficient Override value offset
+#define B_PCH_PCR_DMI_L13TPRECO 0x0003f000 ///< Lane 1/3 Transmitter Pre-Cursor Coefficient Override mask
+#define N_PCH_PCR_DMI_L13TPRECO 12 ///< Lane 1/3 Transmitter Pre-Cursor Coefficient Override value offset
+#define B_PCH_PCR_DMI_L02TPOSTCO 0x00000fc0 ///< Lane 0/2 Transmitter Post-Cursor Coefficient Override mask
+#define N_PCH_PCR_DMI_L02TPOSTCO 6 ///< Lane 0/2 Transmitter Post-Cursor Coefficient Override value offset
+#define B_PCH_PCR_DMI_L02TPRECO 0x0000003f ///< Lane 0/2 Transmitter Pre-Cursor Coefficient Override mask
+#define N_PCH_PCR_DMI_L02TPRECO 0 ///< Lane 0/2 Transmitter Pre-Cursor Coefficient Override value offset
+#define R_PCH_PCR_DMI_G3L0SCTL 0x2478 ///< GEN3 L0s Control
+
+//
+// OP-DMI Specific Registers (OP-DMI Only)
+//
+#define R_PCH_PCR_OPDMI_LCTL 0x2600 ///< Link Control
+#define R_PCH_PCR_OPDMI_STC 0x260C ///< Sideband Timing Control
+#define R_PCH_PCR_OPDMI_LPMC 0x2614 ///< Link Power Management Control
+#define R_PCH_PCR_OPDMI_LCFG 0x2618 ///< Link Configuration
+
+//
+// DMI Source Decode PCRs (Common)
+//
+#define R_PCH_PCR_DMI_PCIEPAR1E 0x2700 ///< PCIE Port IOxAPIC Range 1 Enable
+#define R_PCH_PCR_DMI_PCIEPAR2E 0x2704 ///< PCIE Port IOxAPIC Range 2 Enable
+#define R_PCH_PCR_DMI_PCIEPAR3E 0x2708 ///< PCIE Port IOxAPIC Range 3 Enable
+#define R_PCH_PCR_DMI_PCIEPAR4E 0x270C ///< PCIE Port IOxAPIC Range 4 Enable
+#define R_PCH_PCR_DMI_PCIEPAR1DID 0x2710 ///< PCIE Port IOxAPIC Range 1 Destination ID
+#define R_PCH_PCR_DMI_PCIEPAR2DID 0x2714 ///< PCIE Port IOxAPIC Range 2 Destination ID
+#define R_PCH_PCR_DMI_PCIEPAR3DID 0x2718 ///< PCIE Port IOxAPIC Range 3 Destination ID
+#define R_PCH_PCR_DMI_PCIEPAR4DID 0x271C ///< PCIE Port IOxAPIC Range 4 Destination ID
+#define R_PCH_PCR_DMI_P2SBIOR 0x2720 ///< P2SB IO Range
+#define R_PCH_PCR_DMI_TTTBARB 0x2724 ///< Thermal Throttling BIOS Assigned Thermal Base Address
+#define R_PCH_PCR_DMI_TTTBARBH 0x2728 ///< Thermal Throttling BIOS Assigned Thermal Base High Address
+#define R_PCH_PCR_DMI_LPCLGIR1 0x2730 ///< LPC Generic I/O Range 1
+#define R_PCH_PCR_DMI_LPCLGIR2 0x2734 ///< LPC Generic I/O Range 2
+#define R_PCH_PCR_DMI_LPCLGIR3 0x2738 ///< LPC Generic I/O Range 3
+#define R_PCH_PCR_DMI_LPCLGIR4 0x273C ///< LPC Generic I/O Range 4
+#define R_PCH_PCR_DMI_LPCGMR 0x2740 ///< LPC Generic Memory Range
+#define R_PCH_PCR_DMI_LPCBDE 0x2744 ///< LPC BIOS Decode Enable
+#define R_PCH_PCR_DMI_UCPR 0x2748 ///< uCode Patch Region
+#define B_PCH_PCR_DMI_UCPR_UPRE BIT0 ///< uCode Patch Region Enable
+#define R_PCH_PCR_DMI_GCS 0x274C ///< Generic Control and Status
+#define B_PCH_PCR_DMI_RPRDID 0xFFFF0000 ///< RPR Destination ID
+#define B_PCH_PCR_DMI_BBS BIT10 ///< Boot BIOS Strap
+#define B_PCH_PCR_DMI_RPR BIT11 ///< Reserved Page Route
+#define B_PCH_PCR_DMI_BILD BIT0 ///< BIOS Interface Lock-Down
+#define R_PCH_PCR_DMI_IOT1 0x2750 ///< I/O Trap Register 1
+#define R_PCH_PCR_DMI_IOT2 0x2758 ///< I/O Trap Register 2
+#define R_PCH_PCR_DMI_IOT3 0x2760 ///< I/O Trap Register 3
+#define R_PCH_PCR_DMI_IOT4 0x2768 ///< I/O Trap Register 4
+#define R_PCH_PCR_DMI_LPCIOD 0x2770 ///< LPC I/O Decode Ranges
+#define R_PCH_PCR_DMI_LPCIOE 0x2774 ///< LPC I/O Enables
+#define R_PCH_PCR_DMI_TCOBASE 0x2778 ///< TCO Base Address
+#define B_PCH_PCR_DMI_TCOBASE_TCOBA 0xFFE0 ///< TCO Base Address Mask
+#define R_PCH_PCR_DMI_GPMR1 0x277C ///< General Purpose Memory Range 1
+#define R_PCH_PCR_DMI_GPMR1DID 0x2780 ///< General Purpose Memory Range 1 Destination ID
+#define R_PCH_PCR_DMI_GPMR2 0x2784 ///< General Purpose Memory Range 2
+#define R_PCH_PCR_DMI_GPMR2DID 0x2788 ///< General Purpose Memory Range 2 Destination ID
+#define R_PCH_PCR_DMI_GPMR3 0x278C ///< General Purpose Memory Range 3
+#define R_PCH_PCR_DMI_GPMR3DID 0x2790 ///< General Purpose Memory Range 3 Destination ID
+#define R_PCH_PCR_DMI_GPIOR1 0x2794 ///< General Purpose I/O Range 1
+#define R_PCH_PCR_DMI_GPIOR1DID 0x2798 ///< General Purpose I/O Range 1 Destination ID
+#define R_PCH_PCR_DMI_GPIOR2 0x279C ///< General Purpose I/O Range 2
+#define R_PCH_PCR_DMI_GPIOR2DID 0x27A0 ///< General Purpose I/O Range 2 Destination ID
+#define R_PCH_PCR_DMI_GPIOR3 0x27A4 ///< General Purpose I/O Range 3
+#define R_PCH_PCR_DMI_GPIOR3DID 0x27A8 ///< General Purpose I/O Range 3 Destination ID
+#define R_PCH_PCR_DMI_PMBASEA 0x27AC ///< PM Base Address
+#define R_PCH_PCR_DMI_PMBASEC 0x27B0 ///< PM Base Control
+#define R_PCH_PCR_DMI_ACPIBA 0x27B4 ///< ACPI Base Address
+#define R_PCH_PCR_DMI_ACPIBDID 0x27B8 ///< ACPI Base Destination ID
+
+
+//
+// Opi PHY registers
+//
+#define R_PCH_PCR_OPIPHY_0110 0x0110
+#define R_PCH_PCR_OPIPHY_0118 0x0118
+#define R_PCH_PCR_OPIPHY_011C 0x011C
+#define R_PCH_PCR_OPIPHY_0354 0x0354
+#define R_PCH_PCR_OPIPHY_B104 0xB104
+#define R_PCH_PCR_OPIPHY_B10C 0xB10C
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsEva.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsEva.h
new file mode 100644
index 0000000000..b429afa1e3
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsEva.h
@@ -0,0 +1,110 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_EVA_H_
+#define _PCH_REGS_EVA_H_
+
+#define PCI_DEVICE_NUMBER_EVA 17
+#define PCI_FUNCTION_NUMBER_EVA_MROM0 0
+#define PCI_FUNCTION_NUMBER_EVA_MROM1 1
+#define PCI_FUNCTION_NUMBER_EVA_SSATA 5
+
+///
+/// Lewisburg SKUs
+///
+#define LBG_SKU_G 1
+#define LBG_SKU_X 2
+#define LBG_SKU_A 3
+
+#define PCI_DEVICE_NUMBER_PCH_SSATA 17
+#define PCI_FUNCTION_NUMBER_PCH_SSATA 5
+
+#define PCH_SSATA_MAX_CONTROLLERS 1
+#define PCH_SSATA_MAX_PORTS 6 // But only 4 ports are enable, BIOS needs to disable Port 4 and 5
+
+#define R_PCH_LBG_SSATA_DEVICE_ID 0x02
+
+///
+/// LBG Production sSATA Controller DID definition
+///
+#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_AHCI 0xA1D2 // LBG Production Server Secondary AHCI Mode (Ports 0-4)
+#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID 0xA1D4 // LBG Production Server RAID 0/1/5/10 - NOT premium
+#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID_PREMIUM 0xA1D6 // LBG Production Server RAID 0/1/5/10 - premium
+#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID1 0xA1DE // LBG Production Server RAID 1/RRT
+
+///
+/// LBG Production (PRQ) MSUint SMBUS DID definition
+///
+#define V_PCH_LBG_PROD_MROM_DEVICE_ID_0 0xA1F0 // LBG MS Unit MROM 0 PRQ DID
+#define V_PCH_LBG_PROD_MROM_DEVICE_ID_1 0xA1F1 // LBG MS Unit MROM 1 PRQ DID
+
+
+///
+/// LBG SSX (Super SKUs and Pre Production) sSATA Controller DID definition
+///
+#define V_PCH_LBG_SSATA_DEVICE_ID_D_AHCI 0xA252 // LBG SSX Server Secondary AHCI Mode (Ports 0-4)
+#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID 0xA254 // LBG SSX Server RAID 0/1/5/10 - NOT premium
+#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM 0xA256 // LBG SSX Server RAID 0/1/5/10 - premium
+#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID1 0xA25E // LBG SSX Server RAID 1/RRT
+
+#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0 0x2823 // Server RAID 0/1/5/10 - premium - Alternate ID for RST
+#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1 0x2827 // Server RAID 0/1/5/10 - premium - Alternate ID for RSTe
+
+///
+/// LBG Super SKU (SSX) MSUint DID definition
+///
+#define V_PCH_LBG_MROM_DEVICE_ID_0 0xA270 // LBG NS MS Unit MROM 0 Super SKU DID
+#define V_PCH_LBG_MROM_DEVICE_ID_1 0xA271 // LBG NS MS Unit MROM 1 Super SKU DID
+
+#define R_PCH_LBG_MROM_DEVCLKGCTL 0xE4
+
+#define R_PCH_LBG_MROM_PLKCTL 0xE8
+
+#define ADR_TMR_HELD_OFF_SETUP_OPTION 2
+#define R_PCH_LBG_MROM_ADRTIMERCTRL 0x180
+#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_MASK (BIT27|BIT26|BIT25|BIT24)
+#define N_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT 24
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_1 0x0
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_8 0x1
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_24 0x2
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_40 0x3
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_56 0x4
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_64 0x5
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_72 0x6
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_80 0x7
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_88 0x8
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_96 0x9
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_MAX (V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_96)
+#define ADR_MULT_SETUP_DEFAULT_POR 99
+#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_DBG_DIS BIT28
+#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_DIS BIT29
+#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_MASK (BIT30|BIT31)
+#define N_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR 30
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_25US 0x0
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_50US 0x1
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_100US 0x2
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_0US 0x3
+#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_MAX (V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_0US)
+#define ADR_TMR_SETUP_DEFAULT_POR 4
+
+///
+/// MS Unit Hide Control Register
+///
+#define PCH_LBG_MSUINT_FUNCS 3
+#define R_PCH_LBG_MSUINT_MSDEVFUNCHIDE 0xD4
+#define B_PCH_LBG_MSUINT_MSDEVFUNCHIDE_RSVD (BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|\
+ BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|\
+ BIT16|BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|\
+ BIT9|BIT8|BIT7|BIT6|BIT4|BIT3|BIT2)
+
+#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_SSATA (BIT5)
+
+#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_MROM1 BIT1
+#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_MROM0 BIT0
+#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_REGLOCK BIT31
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsFia.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsFia.h
new file mode 100644
index 0000000000..985e1e2a1d
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsFia.h
@@ -0,0 +1,81 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_FIA_H_
+#define _PCH_REGS_FIA_H_
+
+
+//
+// Private chipset regsiter (Memory space) offset definition
+// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well.
+//
+
+//
+// PID:FIA
+//
+#define PCH_MAX_FIA_DRCRM 3
+#define R_PCH_PCR_FIA_CC 0
+#define B_PCH_PCR_FIA_CC_SRL BIT31
+#define B_PCH_PCR_FIA_CC_PTOCGE BIT17
+#define B_PCH_PCR_FIA_CC_OSCDCGE BIT16
+#define B_PCH_PCR_FIA_CC_SCPTCGE BIT15
+
+#define R_PCH_PCR_FIA_PLLCTL 0x20
+#define R_PCH_PCR_FIA_DRCRM1 0x100
+#define R_PCH_PCR_FIA_DRCRM2 0x104
+#define R_PCH_PCR_FIA_DRCRM3 0x108
+#define S_PCH_PCR_FIA_DRCRM 4
+#define R_PCH_PCR_FIA_STRPFUSECFG1_REG_BASE 0x200
+#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIE_PEN BIT31
+#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL (BIT30 | BIT29 | BIT28)
+#define N_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL 28
+#define R_PCH_PCR_FIA_PCIESATA_FUSECFG_REG_BASE 0x204
+#define R_PCH_PCR_FIA_PCIESATA_STRPCFG_REG_BASE 0x208
+#define R_PCH_PCR_FIA_PCIEUSB3_STRPFUSECFG_REG_BASE 0x20C
+#define R_PCH_PCR_FIA_EXP_FUSECFG_REG_BASE 0x210
+#define R_PCH_PCR_FIA_USB3SSIC_STRPFUSECFG_REG_BASE 0x214
+#define R_PCH_PCR_FIA_CSI3_STRPFUSECFG_REG_BASE 0x218
+#define R_PCH_PCR_FIA_USB3SATA_STRPFUSECFG_REG_BASE 0x21C
+#define R_PCH_PCR_FIA_UFS_STRPFUSECFG_REG_BASE 0x220
+#define R_PCH_PCR_FIA_LOS1_REG_BASE 0x250
+#define R_PCH_PCR_FIA_LOS2_REG_BASE 0x254
+#define R_PCH_PCR_FIA_LOS3_REG_BASE 0x258
+#define R_PCH_PCR_FIA_LOS4_REG_BASE 0x25C
+#define V_PCH_PCR_FIA_LANE_OWN_PCIEDMI 0x0
+#define V_PCH_PCR_FIA_LANE_OWN_USB3 0x1
+#define V_PCH_PCR_FIA_LANE_OWN_SATA 0x2
+#define V_PCH_PCR_FIA_LANE_OWN_GBE 0x3
+#define V_PCH_PCR_FIA_LANE_OWN_SSIC 0x5
+
+#define B_PCH_PCR_FIA_L0O (BIT3 | BIT2 | BIT1 | BIT0)
+#define B_PCH_PCR_FIA_L1O (BIT7 | BIT6 | BIT5 | BIT4)
+#define B_PCH_PCR_FIA_L2O (BIT11 | BIT10 | BIT9 | BIT8)
+#define B_PCH_PCR_FIA_L3O (BIT15 | BIT14 | BIT13 | BIT12)
+#define B_PCH_PCR_FIA_L4O (BIT19 | BIT18 | BIT17 | BIT16)
+#define B_PCH_PCR_FIA_L5O (BIT23 | BIT22 | BIT21 | BIT20)
+#define B_PCH_PCR_FIA_L6O (BIT27 | BIT26 | BIT25 | BIT24)
+#define B_PCH_PCR_FIA_L7O (BIT31 | BIT30 | BIT29 | BIT28)
+#define B_PCH_PCR_FIA_L8O (BIT3 | BIT2 | BIT1 | BIT0)
+#define B_PCH_PCR_FIA_L9O (BIT7 | BIT6 | BIT5 | BIT4)
+#define B_PCH_PCR_FIA_L10O (BIT11 | BIT10 | BIT9 | BIT8)
+#define B_PCH_PCR_FIA_L11O (BIT15 | BIT14 | BIT13 | BIT12)
+#define B_PCH_PCR_FIA_L12O (BIT19 | BIT18 | BIT17 | BIT16)
+#define B_PCH_PCR_FIA_L13O (BIT23 | BIT22 | BIT21 | BIT20)
+#define B_PCH_PCR_FIA_L14O (BIT27 | BIT26 | BIT25 | BIT24)
+#define B_PCH_PCR_FIA_L15O (BIT31 | BIT30 | BIT29 | BIT28)
+#define B_PCH_PCR_FIA_L16O (BIT3 | BIT2 | BIT1 | BIT0)
+#define B_PCH_PCR_FIA_L17O (BIT7 | BIT6 | BIT5 | BIT4)
+#define B_PCH_PCR_FIA_L18O (BIT11 | BIT10 | BIT9 | BIT8)
+#define B_PCH_PCR_FIA_L19O (BIT15 | BIT14 | BIT13 | BIT12)
+#define B_PCH_PCR_FIA_L20O (BIT19 | BIT18 | BIT17 | BIT16)
+#define B_PCH_PCR_FIA_L21O (BIT23 | BIT22 | BIT21 | BIT20)
+#define B_PCH_PCR_FIA_L22O (BIT27 | BIT26 | BIT25 | BIT24)
+#define B_PCH_PCR_FIA_L23O (BIT31 | BIT30 | BIT29 | BIT28)
+#define B_PCH_PCR_FIA_L24O (BIT3 | BIT2 | BIT1 | BIT0)
+#define B_PCH_PCR_FIA_L25O (BIT7 | BIT6 | BIT5 | BIT4)
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsGpio.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsGpio.h
new file mode 100644
index 0000000000..3e5afb182c
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsGpio.h
@@ -0,0 +1,511 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_GPIO_H_
+#define _PCH_REGS_GPIO_H_
+
+#define V_PCH_GPIO_GPP_A_PAD_MAX 24
+#define V_PCH_GPIO_GPP_B_PAD_MAX 24
+#define V_PCH_GPIO_GPP_C_PAD_MAX 24
+#define V_PCH_GPIO_GPP_D_PAD_MAX 24
+#define V_PCH_LP_GPIO_GPP_E_PAD_MAX 24
+#define V_PCH_H_GPIO_GPP_E_PAD_MAX 13
+#define V_PCH_GPIO_GPP_F_PAD_MAX 24
+#define V_PCH_LP_GPIO_GPP_G_PAD_MAX 8
+#define V_PCH_H_GPIO_GPP_G_PAD_MAX 24
+#define V_PCH_H_GPIO_GPP_H_PAD_MAX 24
+#define V_PCH_H_GPIO_GPP_J_PAD_MAX 24
+#define V_PCH_H_GPIO_GPP_K_PAD_MAX 11
+#define V_PCH_H_GPIO_GPP_L_PAD_MAX 20
+#define V_PCH_H_GPIO_GPP_I_PAD_MAX 11
+
+#define V_PCH_GPIO_GPD_PAD_MAX 12
+
+#define V_PCH_GPIO_GROUP_MAX 13
+#define V_PCH_H_GPIO_GROUP_MAX V_PCH_GPIO_GROUP_MAX
+#define V_PCH_LP_GPIO_GROUP_MAX 8
+#define V_PCH_GPIO_NUM_SUPPORTED_GPIS 261
+#define S_PCH_GPIO_GP_SMI_EN 4
+#define S_PCH_GPIO_GP_SMI_STS 4
+
+///
+/// Groups mapped to 2-tier General Purpose Event will all be under
+/// one master GPE_111 (0x6F)
+///
+#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F
+
+
+//
+// GPIO Common Private Configuration Registers
+//
+#define R_PCH_PCR_GPIO_REV_ID 0x00
+#define R_PCH_PCR_GPIO_CAP_LIST 0x04
+#define R_PCH_PCR_GPIO_FAMBAR 0x08
+#define R_PCH_PCR_GPIO_PADBAR 0x0C
+#define B_PCH_PCR_GPIO_PADBAR 0x0000FFFF
+#define R_PCH_PCR_GPIO_MISCCFG 0x10
+#define B_PCH_PCR_GPIO_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16)
+#define N_PCH_PCR_GPIO_MISCCFG_GPE0_DW2 16
+#define B_PCH_PCR_GPIO_MISCCFG_GPE0_DW1 (BIT15 | BIT14 | BIT13 | BIT12)
+#define N_PCH_PCR_GPIO_MISCCFG_GPE0_DW1 12
+#define B_PCH_PCR_GPIO_MISCCFG_GPE0_DW0 (BIT11 | BIT10 | BIT9 | BIT8)
+#define N_PCH_PCR_GPIO_MISCCFG_GPE0_DW0 8
+#define B_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE BIT3
+#define N_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE 3
+#define B_PCH_PCR_GPIO_MISCCFG_GPDPCGEN BIT1
+#define B_PCH_PCR_GPIO_MISCCFG_GPDLCGEN BIT0
+// SKL PCH-H:
+#define R_PCH_H_PCR_GPIO_MISCSECCFG 0x14
+
+//
+// GPIO Community 0 Private Configuration Registers
+//
+// SKL PCH-LP
+#define R_PCH_LP_PCR_GPIO_GPP_A_PAD_OWN 0x20
+#define R_PCH_LP_PCR_GPIO_GPP_B_PAD_OWN 0x30
+#define R_PCH_LP_PCR_GPIO_GPP_A_GPI_VWM_EN 0x80
+#define R_PCH_LP_PCR_GPIO_GPP_B_GPI_VWM_EN 0x84
+#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCK 0xA0
+#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCKTX 0xA4
+#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCK 0xA8
+#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCKTX 0xAC
+// SKX Server PCH
+#define R_PCH_H_PCR_GPIO_GPP_A_PAD_OWN 0x20
+#define R_PCH_H_PCR_GPIO_GPP_B_PAD_OWN 0x2C
+#define R_PCH_H_PCR_GPIO_GPP_F_PAD_OWN 0x38
+#define R_PCH_H_PCR_GPIO_GPP_A_GPI_VWM_EN 0x50
+#define R_PCH_H_PCR_GPIO_GPP_B_GPI_VWM_EN 0x54
+#define R_PCH_H_PCR_GPIO_GPP_F_GPI_VWM_EN 0x58
+#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCK 0x60
+#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCKTX 0x64
+#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCK 0x68
+#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCKTX 0x6C
+#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCK 0x70
+#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCKTX 0x74
+#define R_PCH_H_PCR_GPIO_GPP_F_HOSTSW_OWN 0x88
+#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IS 0x0108
+#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IE 0x0118
+#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0128
+#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0138
+#define R_PCH_H_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x580
+
+// Common
+#define R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN 0x80
+#define R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN 0x84
+#define R_PCH_PCR_GPIO_GPP_A_GPI_IS 0x0100
+#define R_PCH_PCR_GPIO_GPP_B_GPI_IS 0x0104
+#define R_PCH_PCR_GPIO_GPP_A_GPI_IE 0x0110
+#define R_PCH_PCR_GPIO_GPP_B_GPI_IE 0x0114
+#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS 0x0120
+#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS 0x0124
+#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_EN 0x0130
+#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_EN 0x0134
+#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0144
+#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x0154
+#define R_PCH_PCR_GPIO_GPP_B_NMI_STS 0x0164
+#define R_PCH_PCR_GPIO_GPP_B_NMI_EN 0x0174
+#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400
+#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0
+
+//
+// GPIO Community 1 Private Configuration Registers
+//
+//SKL PCH-LP:
+#define R_PCH_LP_PCR_GPIO_GPP_C_PAD_OWN 0x20
+#define R_PCH_LP_PCR_GPIO_GPP_D_PAD_OWN 0x30
+#define R_PCH_LP_PCR_GPIO_GPP_E_PAD_OWN 0x40
+#define R_PCH_LP_PCR_GPIO_GPP_C_GPI_VWM_EN 0x80
+#define R_PCH_LP_PCR_GPIO_GPP_D_GPI_VWM_EN 0x84
+#define R_PCH_LP_PCR_GPIO_GPP_E_GPI_VWM_EN 0x88
+#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCK 0xA0
+#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCKTX 0xA4
+#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCK 0xA8
+#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCKTX 0xAC
+#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCK 0xB0
+#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCKTX 0xB4
+//SKL PCH-H:
+#define R_PCH_H_PCR_GPIO_GPP_C_PAD_OWN 0x20
+#define R_PCH_H_PCR_GPIO_GPP_D_PAD_OWN 0x2C
+#define R_PCH_H_PCR_GPIO_GPP_E_PAD_OWN 0x38
+// Server SKX PCH
+#define R_PCH_H_PCR_GPIO_GPP_C_GPI_VWM_EN 0x50
+#define R_PCH_H_PCR_GPIO_GPP_D_GPI_VWM_EN 0x54
+#define R_PCH_H_PCR_GPIO_GPP_E_GPI_VWM_EN 0x58
+#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCK 0x60
+#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCKTX 0x64
+#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCK 0x68
+#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCKTX 0x6C
+#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCK 0x70
+#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCKTX 0x74
+// Common
+#define R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN 0x80
+#define R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN 0x84
+#define R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN 0x88
+#define R_PCH_PCR_GPIO_GPP_C_GPI_IS 0x0100
+#define R_PCH_PCR_GPIO_GPP_D_GPI_IS 0x0104
+#define R_PCH_PCR_GPIO_GPP_E_GPI_IS 0x0108
+#define R_PCH_PCR_GPIO_GPP_C_GPI_IE 0x0110
+#define R_PCH_PCR_GPIO_GPP_D_GPI_IE 0x0114
+#define R_PCH_PCR_GPIO_GPP_E_GPI_IE 0x0114
+#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS 0x0120
+#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS 0x0124
+#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS 0x0128
+#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_EN 0x0130
+#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_EN 0x0134
+#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_EN 0x0138
+#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0140
+#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0144
+#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0148
+#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x0150
+#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x0154
+#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x0158
+#define R_PCH_PCR_GPIO_GPP_C_NMI_STS 0x0160
+#define R_PCH_PCR_GPIO_GPP_D_NMI_STS 0x0164
+#define R_PCH_PCR_GPIO_GPP_E_NMI_STS 0x0168
+#define R_PCH_PCR_GPIO_GPP_C_NMI_EN 0x0170
+#define R_PCH_PCR_GPIO_GPP_D_NMI_EN 0x0174
+#define R_PCH_PCR_GPIO_GPP_E_NMI_EN 0x0178
+
+
+// Common:
+#define R_PCH_PCR_GPIO_CAP_LIST_1_PWM 0x0200
+#define R_PCH_PCR_GPIO_PWMC 0x0204
+#define R_PCH_PCR_GPIO_CAP_LIST_2_SER_BLINK 0x0208
+#define R_PCH_PCR_GPIO_GP_SER_BLINK 0x020C
+#define B_PCH_PCR_GPIO_GP_SER_BLINK 0x1F
+#define R_PCH_PCR_GPIO_GP_SER_CMDSTS 0x0210
+#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_DLS (BIT23 | BIT22)
+#define N_PCH_PCR_GPIO_GP_SER_CMDSTS_DLS 22
+#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_DRS 0x003F0000
+#define N_PCH_PCR_GPIO_GP_SER_CMDSTS_DRS 16
+#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_BUSY BIT8
+#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_GO BIT0
+#define R_PCH_PCR_GPIO_GP_SER_DATA 0x0210
+// Common:
+#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400
+#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0
+#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580
+
+//
+// GPIO Community 2 Private Configuration Registers
+//
+// SKL PCH-LP
+#define R_PCH_LP_PCR_GPIO_GPD_PAD_OWN 0x20
+#define R_PCH_LP_PCR_GPIO_GPD_GPI_VWM_EN 0x80
+#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCK 0xA0
+#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCKTX 0xA4
+// SKX Server PCH
+#define R_PCH_H_PCR_GPIO_GPD_PAD_OWN 0x20
+#define R_PCH_H_PCR_GPIO_GPD_GPI_VWM_EN 0x50
+#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCK 0x60
+#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCKTX 0x64
+// Common
+#define R_PCH_PCR_GPIO_GPD_HOSTSW_OWN 0x80
+#define R_PCH_PCR_GPIO_GPD_GPI_IS 0x0100
+#define R_PCH_PCR_GPIO_GPD_GPI_IE 0x0110
+#define R_PCH_PCR_GPIO_GPD_GPI_GPE_STS 0x0120
+#define R_PCH_PCR_GPIO_GPD_GPI_GPE_EN 0x0130
+#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400
+
+//
+// GPIO Community 3 Private Configuration Registers
+//
+// SKL PCH-LP:
+#define R_PCH_LP_PCR_GPIO_GPP_F_PAD_OWN 0x20
+#define R_PCH_LP_PCR_GPIO_GPP_G_PAD_OWN 0x30
+#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_VWM_EN 0x80
+#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_VWM_EN 0x84
+#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCK 0xA0
+#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCKTX 0xA4
+#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCK 0xA8
+#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCKTX 0xAC
+#define R_PCH_LP_PCR_GPIO_GPP_F_HOSTSW_OWN 0xD0
+#define R_PCH_LP_PCR_GPIO_GPP_G_HOSTSW_OWN 0xD4
+#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IS 0x0100
+#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IS 0x0104
+#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IE 0x0120
+#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IE 0x0124
+#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0140
+#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0144
+#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0160
+#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0164
+#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400
+#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0
+
+// SKX Server PCH
+#define R_PCH_H_PCR_GPIO_GPP_I_PAD_OWN 0x20
+#define R_PCH_H_PCR_GPIO_GPP_I_GPI_VWM_EN 0x50
+#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCK 0x60
+#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCKTX 0x64
+#define R_PCH_H_PCR_GPIO_GPP_I_HOSTSW_OWN 0x80
+#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IS 0x0100
+#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IE 0x0110
+#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_STS 0x0120
+#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_EN 0x0130
+#define R_PCH_H_PCR_GPIO_GPP_I_SMI_STS 0x0140
+#define R_PCH_H_PCR_GPIO_GPP_I_SMI_EN 0x0150
+#define R_PCH_H_PCR_GPIO_GPP_I_NMI_STS 0x0160
+#define R_PCH_H_PCR_GPIO_GPP_I_NMI_EN 0x0170
+#define R_PCH_H_PCR_GPIO_GPP_I_PADCFG_OFFSET 0x400
+
+//
+// GPIO Community 4 Private Configuration Registers
+//
+
+// SKX Server PCH
+#define R_PCH_H_PCR_GPIO_GPP_J_PAD_OWN 0x20
+#define R_PCH_H_PCR_GPIO_GPP_K_PAD_OWN 0x2C
+#define R_PCH_H_PCR_GPIO_GPP_J_GPI_VWM_EN 0x50
+#define R_PCH_H_PCR_GPIO_GPP_K_GPI_VWM_EN 0x54
+#define R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCK 0x60
+#define R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCKTX 0x64
+#define R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCK 0x68
+#define R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCKTX 0x6C
+#define R_PCH_H_PCR_GPIO_GPP_J_HOSTSW_OWN 0x80
+#define R_PCH_H_PCR_GPIO_GPP_K_HOSTSW_OWN 0x84
+#define R_PCH_H_PCR_GPIO_GPP_J_GPI_IS 0x0100
+#define R_PCH_H_PCR_GPIO_GPP_K_GPI_IS 0x0104
+#define R_PCH_H_PCR_GPIO_GPP_J_GPI_IE 0x0110
+#define R_PCH_H_PCR_GPIO_GPP_K_GPI_IE 0x0114
+#define R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_STS 0x0120
+#define R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_STS 0x0124
+#define R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_EN 0x0130
+#define R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_EN 0x0134
+#define R_PCH_H_PCR_GPIO_GPP_J_PADCFG_OFFSET 0x400
+#define R_PCH_H_PCR_GPIO_GPP_K_PADCFG_OFFSET 0x4C0
+
+//
+// GPIO Community 5 Private Configuration Registers
+//
+
+// SKX Server PCH
+#define R_PCH_H_PCR_GPIO_GPP_G_PAD_OWN 0x20
+#define R_PCH_H_PCR_GPIO_GPP_H_PAD_OWN 0x2C
+#define R_PCH_H_PCR_GPIO_GPP_L_PAD_OWN 0x38
+#define R_PCH_H_PCR_GPIO_GPP_G_GPI_VWM_EN 0x50
+#define R_PCH_H_PCR_GPIO_GPP_H_GPI_VWM_EN 0x54
+#define R_PCH_H_PCR_GPIO_GPP_L_GPI_VWM_EN 0x58
+#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCK 0x60
+#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCKTX 0x64
+#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCK 0x68
+#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCKTX 0x6C
+#define R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCK 0x70
+#define R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCKTX 0x74
+#define R_PCH_H_PCR_GPIO_GPP_G_HOSTSW_OWN 0x80
+#define R_PCH_H_PCR_GPIO_GPP_H_HOSTSW_OWN 0x84
+#define R_PCH_H_PCR_GPIO_GPP_L_HOSTSW_OWN 0x88
+#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IS 0x0100
+#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IS 0x0104
+#define R_PCH_H_PCR_GPIO_GPP_L_GPI_IS 0x0108
+#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IE 0x0110
+#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IE 0x0114
+#define R_PCH_H_PCR_GPIO_GPP_L_GPI_IE 0x0118
+#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0120
+#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_STS 0x0124
+#define R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_STS 0x0128
+#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0130
+#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_EN 0x0134
+#define R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_EN 0x0138
+#define R_PCH_H_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x400
+#define R_PCH_H_PCR_GPIO_GPP_H_PADCFG_OFFSET 0x4C0
+#define R_PCH_H_PCR_GPIO_GPP_L_PADCFG_OFFSET 0x580
+
+
+
+
+//
+// Define Pad Number
+//
+#define V_GPIO_PAD0 0
+#define V_GPIO_PAD1 1
+#define V_GPIO_PAD2 2
+#define V_GPIO_PAD3 3
+#define V_GPIO_PAD4 4
+#define V_GPIO_PAD5 5
+#define V_GPIO_PAD6 6
+#define V_GPIO_PAD7 7
+#define V_GPIO_PAD8 8
+#define V_GPIO_PAD9 9
+#define V_GPIO_PAD10 10
+#define V_GPIO_PAD11 11
+#define V_GPIO_PAD12 12
+#define V_GPIO_PAD13 13
+#define V_GPIO_PAD14 14
+#define V_GPIO_PAD15 15
+#define V_GPIO_PAD16 16
+#define V_GPIO_PAD17 17
+#define V_GPIO_PAD18 18
+#define V_GPIO_PAD19 19
+#define V_GPIO_PAD20 20
+#define V_GPIO_PAD21 21
+#define V_GPIO_PAD22 22
+#define V_GPIO_PAD23 23
+
+//
+// Host Software Pad Ownership modes
+//
+#define V_PCH_PCR_GPIO_HOSTSW_OWN_ACPI 0x00
+#define V_PCH_PCR_GPIO_HOSTSW_OWN_GPIO 0x01
+
+//
+// Pad Ownership modes
+//
+#define V_PCH_PCR_GPIO_PAD_OWN_HOST 0x00
+#define V_PCH_PCR_GPIO_PAD_OWN_CSME 0x01
+#define V_PCH_PCR_GPIO_PAD_OWN_ISH 0x02
+
+//
+// Pad Configuration Register DW0
+//
+
+//Pad Reset Config
+#define B_PCH_GPIO_RST_CONF (BIT31 | BIT30)
+#define N_PCH_GPIO_RST_CONF 30
+#define V_PCH_GPIO_RST_CONF_POW_GOOD 0x00
+#define V_PCH_GPIO_RST_CONF_DEEP_RST 0x01
+#define V_PCH_GPIO_RST_CONF_GPIO_RST 0x02
+#define V_PCH_GPIO_RST_CONF_RESUME_RST 0x03 // Only for GPD Group
+
+//RX Pad State Select
+#define B_PCH_GPIO_RX_PAD_STATE BIT29
+#define N_PCH_GPIO_RX_PAD_STATE 29
+#define V_PCH_GPIO_RX_PAD_STATE_RAW 0x00
+#define V_PCH_GPIO_RX_PAD_STATE_INT 0x01
+
+//RX Raw Overrride to 1
+#define B_PCH_GPIO_RX_RAW1 BIT28
+#define N_PCH_GPIO_RX_RAW1 28
+#define V_PCH_GPIO_RX_RAW1_DIS 0x00
+#define V_PCH_GPIO_RX_RAW1_EN 0x01
+
+//RX Level/Edge Configuration
+#define B_PCH_GPIO_RX_LVL_EDG (BIT26 | BIT25)
+#define N_PCH_GPIO_RX_LVL_EDG 25
+#define V_PCH_GPIO_RX_LVL_EDG_LVL 0x00
+#define V_PCH_GPIO_RX_LVL_EDG_EDG 0x01
+#define V_PCH_GPIO_RX_LVL_EDG_0 0x02
+#define V_PCH_GPIO_RX_LVL_EDG_RIS_FAL 0x03
+
+//RX Invert
+#define B_PCH_GPIO_RXINV BIT23
+#define N_PCH_GPIO_RXINV 23
+#define V_PCH_GPIO_RXINV_NO 0x00
+#define V_PCH_GPIO_RXINV_YES 0x01
+
+//GPIO Input Route IOxAPIC
+#define B_PCH_GPIO_RX_APIC_ROUTE BIT20
+#define N_PCH_GPIO_RX_APIC_ROUTE 20
+#define V_PCH_GPIO_RX_APIC_ROUTE_DIS 0x00
+#define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01
+
+//GPIO Input Route SCI
+#define B_PCH_GPIO_RX_SCI_ROUTE BIT19
+#define N_PCH_GPIO_RX_SCI_ROUTE 19
+#define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00
+#define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01
+
+//GPIO Input Route SMI
+#define B_PCH_GPIO_RX_SMI_ROUTE BIT18
+#define N_PCH_GPIO_RX_SMI_ROUTE 18
+#define V_PCH_GPIO_RX_SMI_ROUTE_DIS 0x00
+#define V_PCH_GPIO_RX_SMI_ROUTE_EN 0x01
+
+//GPIO Input Route NMI
+#define B_PCH_GPIO_RX_NMI_ROUTE BIT17
+#define N_PCH_GPIO_RX_NMI_ROUTE 17
+#define V_PCH_GPIO_RX_NMI_ROUTE_DIS 0x00
+#define V_PCH_GPIO_RX_NMI_ROUTE_EN 0x01
+
+//GPIO Pad Mode
+#define B_PCH_GPIO_PAD_MODE (BIT12 | BIT11 | BIT10)
+#define N_PCH_GPIO_PAD_MODE 10
+#define V_PCH_GPIO_PAD_MODE_GPIO 0
+#define V_PCH_GPIO_PAD_MODE_NAT_1 1
+#define V_PCH_GPIO_PAD_MODE_NAT_2 2
+#define V_PCH_GPIO_PAD_MODE_NAT_3 3
+#define V_PCH_GPIO_PAD_MODE_NAT_4 4 // SPT-H only
+
+//GPIO RX Disable
+#define B_PCH_GPIO_RXDIS BIT9
+#define N_PCH_GPIO_RXDIS 9
+#define V_PCH_GPIO_RXDIS_EN 0x00
+#define V_PCH_GPIO_RXDIS_DIS 0x01
+
+//GPIO TX Disable
+#define B_PCH_GPIO_TXDIS BIT8
+#define N_PCH_GPIO_TXDIS 8
+#define V_PCH_GPIO_TXDIS_EN 0x00
+#define V_PCH_GPIO_TXDIS_DIS 0x01
+
+//GPIO RX State
+#define B_PCH_GPIO_RX_STATE BIT1
+#define N_PCH_GPIO_RX_STATE 1
+#define V_PCH_GPIO_RX_STATE_LOW 0x00
+#define V_PCH_GPIO_RX_STATE_HIGH 0x01
+
+//GPIO TX State
+#define B_PCH_GPIO_TX_STATE BIT0
+#define N_PCH_GPIO_TX_STATE 0
+#define V_PCH_GPIO_TX_STATE_LOW 0x00
+#define V_PCH_GPIO_TX_STATE_HIGH 0x01
+
+//
+// Pad Configuration Register DW1
+//
+
+//Padtol
+#define B_PCH_GPIO_PADTOL BIT25
+#define N_PCH_GPIO_PADTOL 25
+#define V_PCH_GPIO_PADTOL_NONE 0x00
+#define V_PCH_GPIO_PADTOL_CLEAR 0x00
+#define V_PCH_GPIO_PADTOL_SET 0x01
+
+//Termination
+#define B_PCH_GPIO_TERM (BIT13 | BIT12 | BIT11 | BIT10)
+#define N_PCH_GPIO_TERM 10
+#define V_PCH_GPIO_TERM_WPD_NONE 0x00
+#define V_PCH_GPIO_TERM_WPD_5K 0x02
+#define V_PCH_GPIO_TERM_WPD_20K 0x04
+#define V_PCH_GPIO_TERM_WPU_NONE 0x08
+#define V_PCH_GPIO_TERM_WPU_1K 0x09
+#define V_PCH_GPIO_TERM_WPU_2K 0x0B
+#define V_PCH_GPIO_TERM_WPU_5K 0x0A
+#define V_PCH_GPIO_TERM_WPU_20K 0x0C
+#define V_PCH_GPIO_TERM_WPU_1K_2K 0x0D
+#define V_PCH_GPIO_TERM_NATIVE 0x0F
+
+//Interrupt number
+#define B_PCH_GPIO_INTSEL 0x7F
+#define N_PCH_GPIO_INTSEL 0
+
+//
+// Ownership
+//
+#define V_PCH_GPIO_OWN_GPIO 0x01
+#define V_PCH_GPIO_OWN_ACPI 0x00
+
+//
+// GPE
+//
+#define V_PCH_GPIO_GPE_EN 0x01
+#define V_PCH_GPIO_GPE_DIS 0x00
+//
+// SMI
+//
+#define V_PCH_GPIO_SMI_EN 0x01
+#define V_PCH_GPIO_SMI_DIS 0x00
+//
+// NMI
+//
+#define V_PCH_GPIO_NMI_EN 0x01
+#define V_PCH_GPIO_NMI_DIS 0x00
+//
+// Reserved: RSVD1
+//
+#define V_PCH_GPIO_RSVD1 0x00
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsHda.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsHda.h
new file mode 100644
index 0000000000..a6049cb5aa
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsHda.h
@@ -0,0 +1,226 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_HDA_H_
+#define _PCH_REGS_HDA_H_
+
+//
+// HD-A Controller Registers (D31:F3)
+//
+// PCI Configuration Space Registers
+//
+#define PCI_DEVICE_NUMBER_PCH_HDA 31
+#define PCI_FUNCTION_NUMBER_PCH_HDA 3
+
+#define V_PCH_HDA_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_LP_HDA_DEVICE_ID_0 0x9D70
+#define V_PCH_LP_HDA_DEVICE_ID_1 0x9D71
+#define V_PCH_LP_HDA_DEVICE_ID_2 0x9D72
+#define V_PCH_LP_HDA_DEVICE_ID_3 0x9D73
+#define V_PCH_LP_HDA_DEVICE_ID_4 0x9D74
+#define V_PCH_LP_HDA_DEVICE_ID_5 0x9D75
+#define V_PCH_LP_HDA_DEVICE_ID_6 0x9D76
+#define V_PCH_LP_HDA_DEVICE_ID_7 0x9D77
+#define V_PCH_H_HDA_DEVICE_ID_0 0xA170
+#define V_PCH_H_HDA_DEVICE_ID_1 0xA171
+#define V_PCH_H_HDA_DEVICE_ID_2 0xA172
+#define V_PCH_H_HDA_DEVICE_ID_3 0xA173
+#define V_PCH_H_HDA_DEVICE_ID_4 0xA174
+#define V_PCH_H_HDA_DEVICE_ID_5 0xA175
+#define V_PCH_H_HDA_DEVICE_ID_6 0xA176
+#define V_PCH_H_HDA_DEVICE_ID_7 0xA177
+//
+// LBG SSX (Super SKU) DIDs
+//
+#define V_PCH_LBG_HDA_DEVICE_ID_0 0xA270
+#define V_PCH_LBG_HDA_DEVICE_ID_1 0xA271
+#define V_PCH_LBG_HDA_DEVICE_ID_2 0xA272
+#define V_PCH_LBG_HDA_DEVICE_ID_3 0xA273
+#define V_PCH_LBG_HDA_DEVICE_ID_4 0xA274
+#define V_PCH_LBG_HDA_DEVICE_ID_5 0xA275
+#define V_PCH_LBG_HDA_DEVICE_ID_6 0xA276
+#define V_PCH_LBG_HDA_DEVICE_ID_7 0xA277
+//
+// LBG PRODUCTION (PRQ) DIDs
+//
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_0 0xA1F0
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_1 0xA1F1
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_2 0xA1F2
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_3 0xA1F3
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_4 0xA1F4
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_5 0xA1F5
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_6 0xA1F6
+#define V_PCH_LBG_PROD_HDA_DEVICE_ID_7 0xA1F7
+
+
+#define R_PCH_HDA_PI 0x09
+#define V_PCH_HDA_PI_ADSP_UAA 0x80
+#define R_PCH_HDA_SCC 0x0A
+#define V_PCH_HDA_SCC_ADSP 0x01
+#define R_PCH_HDA_HDALBA 0x10
+#define B_PCH_HDA_HDALBA_LBA 0xFFFFC000
+#define V_PCH_HDA_HDBAR_SIZE (1 << 14)
+#define R_PCH_HDA_HDAUBA 0x14
+#define B_PCH_HDA_HDAUBA_UBA 0xFFFFFFFF
+#define R_PCH_HDA_CGCTL 0x48
+#define B_PCH_HDA_CGCTL_MEMDCGE BIT0
+#define B_PCH_HDA_CGCTL_HDALDCGE BIT3
+#define B_PCH_HDA_CGCTL_MISCBDCGE BIT6
+#define B_PCH_HDA_CGCTL_ODMABDCGE BIT4
+#define B_PCH_HDA_CGCTL_IDMABDCGE BIT5
+#define B_PCH_HDA_CGCTL_IOSFBDCGE BIT7
+#define B_PCH_HDA_CGCTL_IOSFSDCGE BIT8
+#define B_PCH_HDA_CGCTL_APTCGE BIT16
+#define B_PCH_HDA_CGCTL_XOTCGE BIT17
+#define B_PCH_HDA_CGCTL_SROTCGE BIT18
+#define B_PCH_HDA_CGCTL_IOSFBTCGE BIT19
+#define B_PCH_HDA_CGCTL_IOSFSTCGE BIT20
+#define B_PCH_HDA_CGCTL_FROTCGE BIT21
+#define B_PCH_HDA_CGCTL_APLLSE BIT31
+#define R_PCH_HDA_CGCTL 0x48
+#define B_PCH_HDA_CGCTL_MISCBDCGE BIT6
+#define R_PCH_HDA_PC 0x52
+#define V_PCH_HDA_PC_PMES 0x18
+#define N_PCH_HDA_PC_PMES 11
+#define R_PCH_HDA_PCS 0x54
+#define B_PCH_HDA_PCS_PMES BIT15
+#define B_PCH_HDA_PCS_PMEE BIT8
+#define B_PCH_HDA_PCS_PS (BIT1 | BIT0)
+#define R_PCH_HDA_MMC 0x62
+#define B_PCH_HDA_MMC_ME BIT0
+#define R_PCH_HDA_DEVC 0x78
+#define B_PCH_HDA_DEVC_NSNPEN BIT11
+#define R_PCH_HDA_SEM1 0xC0
+#define B_PCH_HDA_SEM1_LFLCS BIT24
+#define B_PCH_HDA_SEM1_BLKC3DIS BIT17
+#define B_PCH_HDA_SEM1_TMODE BIT12
+#define B_PCH_HDA_SEM1_FIFORDYSEL (BIT10 | BIT9)
+#define R_PCH_HDA_SEM2 0xC4
+#define B_PCH_HDA_SEM2_BSMT (BIT27 | BIT26)
+#define V_PCH_HDA_SEM2_BSMT 0x1
+#define N_PCH_HDA_SEM2_BSMT 26
+#define B_PCH_HDA_SEM2_VC0PSNR BIT24
+#define R_PCH_HDA_SEM3L 0xC8
+#define B_PCH_HDA_SEM3L_ISL1EXT2 (BIT21 | BIT20)
+#define V_PCH_HDA_SEM3L_ISL1EXT2 0x2
+#define N_PCH_HDA_SEM3L_ISL1EXT2 20
+#define R_PCH_HDA_SEM4L 0xD0
+#define B_PCH_HDA_SEM4L_OSL1EXT2 (BIT21 | BIT20)
+#define V_PCH_HDA_SEM4L_OSL1EXT2 0x3
+#define N_PCH_HDA_SEM4L_OSL1EXT2 20
+
+//
+// Memory Space Registers
+//
+//
+// Resides in 'HD Audio Global Registers' (0000h)
+//
+#define R_PCH_HDABA_GCAP 0x00
+#define R_PCH_HDABA_GCTL 0x08
+#define B_PCH_HDABA_GCTL_CRST BIT0
+
+#define R_PCH_HDABA_OUTPAY 0x04
+#define R_PCH_HDABA_INPAY 0x06
+#define V_PCH_HDABA_INPAY_DEFAULT 0x1C
+
+#define R_PCH_HDABA_WAKEEN 0x0C
+#define B_PCH_HDABA_WAKEEN_SDI_3 BIT3
+#define B_PCH_HDABA_WAKEEN_SDI_2 BIT2
+#define B_PCH_HDABA_WAKEEN_SDI_1 BIT1
+#define B_PCH_HDABA_WAKEEN_SDI_0 BIT0
+
+#define R_PCH_HDABA_WAKESTS 0x0E
+#define B_PCH_HDABA_WAKESTS_SDIN3 BIT3
+#define B_PCH_HDABA_WAKESTS_SDIN2 BIT2
+#define B_PCH_HDABA_WAKESTS_SDIN1 BIT1
+#define B_PCH_HDABA_WAKESTS_SDIN0 BIT0
+
+//
+// Resides in 'HD Audio Controller Registers' (0030h)
+//
+#define R_PCH_HDABA_IC 0x60
+#define R_PCH_HDABA_IR 0x64
+#define R_PCH_HDABA_ICS 0x68
+#define B_PCH_HDABA_ICS_IRV BIT1
+#define B_PCH_HDABA_ICS_ICB BIT0
+
+//
+// Resides in 'HD Audio Processing Pipe Capability Structure' (0800h)
+//
+#define R_PCH_HDABA_PPC 0x0800 // Processing Pipe Capability Structure (Memory Space, offset 0800h)
+#define R_PCH_HDABA_PPCTL (R_PCH_HDABA_PPC + 0x04)
+#define B_PCH_HDABA_PPCTL_GPROCEN BIT30
+
+//
+// Resides in 'HD Audio Multiple Links Capability Structure' (0C00h)
+//
+#define V_PCH_HDA_HDALINK_INDEX 0
+#define V_PCH_HDA_IDISPLINK_INDEX 1
+
+#define R_PCH_HDABA_MLC 0x0C00 // Multiple Links Capability Structure (Memory Space, offset 0C00h)
+#define R_PCH_HDABA_LCTLX(x) (R_PCH_HDABA_MLC + (0x40 + (0x40 * (x)) + 0x04)) // x - Link index: 0 - HDA Link, 1 - iDisp Link
+#define B_PCH_HDABA_LCTLX_CPA BIT23
+#define B_PCH_HDABA_LCTLX_SPA BIT16
+#define N_PCH_HDABA_LCTLX_SCF 0
+#define V_PCH_HDABA_LCTLX_SCF_6MHZ 0x0
+#define V_PCH_HDABA_LCTLX_SCF_12MHZ 0x1
+#define V_PCH_HDABA_LCTLX_SCF_24MHZ 0x2
+#define V_PCH_HDABA_LCTLX_SCF_48MHZ 0x3
+#define V_PCH_HDABA_LCTLX_SCF_96MHZ 0x4
+
+//
+// Resides in 'HD Audio Vendor Specific Registers' (1000h)
+//
+#define R_PCH_HDABA_LTRC 0x1048
+#define V_PCH_HDABA_LTRC_GB 0x29
+#define N_PCH_HDABA_LTRC_GB 0
+#define R_PCH_HDABA_PCE 0x104B
+#define B_PCH_HDABA_PCE_D3HE BIT2
+
+//
+// Private Configuration Space Registers
+//
+//
+// Resides in IOSF & Fabric Configuration Registers (000h)
+//
+#define R_PCH_PCR_HDA_TTCCFG 0xE4
+#define B_PCH_PCR_HDA_TTCCFG_HCDT BIT1
+
+//
+// Resides in PCI & Codec Configuration Registers (500h)
+//
+#define R_PCH_PCR_HDA_PCICDCCFG 0x500 // PCI & Codec Configuration Registers (PCR, offset 500h)
+#define B_PCH_PCR_HDA_PCICDCCFG_ACPIIN 0x0000FF00
+#define N_PCH_PCR_HDA_PCICDCCFG_ACPIIN 8
+#define R_PCH_PCR_HDA_FNCFG (R_PCH_PCR_HDA_PCICDCCFG + 0x30)
+#define B_PCH_PCR_HDA_FNCFG_PGD BIT5
+#define B_PCH_PCR_HDA_FNCFG_BCLD BIT4
+#define B_PCH_PCR_HDA_FNCFG_CGD BIT3
+#define B_PCH_PCR_HDA_FNCFG_ADSPD BIT2
+#define B_PCH_PCR_HDA_FNCFG_HDASD BIT0
+#define R_PCH_PCR_HDA_CDCCFG (R_PCH_PCR_HDA_PCICDCCFG + 0x34)
+#define B_PCH_PCR_HDA_CDCCFG_DIS_SDIN2 BIT2
+
+//
+// Resides in Power Management & EBB Configuration Registers (600h)
+//
+#define R_PCH_PCR_HDA_PWRMANCFG 0x600 // Power Management & EBB Configuration Registers (PCR, offset 600h)
+#define R_PCH_PCR_HDA_APLLP0 (R_PCH_PCR_HDA_PWRMANCFG + 0x10)
+#define V_PCH_PCR_HDA_APLLP0 0xFC1E0000
+#define R_PCH_PCR_HDA_APLLP1 (R_PCH_PCR_HDA_PWRMANCFG + 0x14)
+#define V_PCH_PCR_HDA_APLLP1 0x00003F00
+#define R_PCH_PCR_HDA_APLLP2 (R_PCH_PCR_HDA_PWRMANCFG + 0x18)
+#define V_PCH_PCR_HDA_APLLP2 0x0000011D
+#define R_PCH_PCR_HDA_IOBCTL (R_PCH_PCR_HDA_PWRMANCFG + 0x1C)
+#define B_PCH_PCR_HDA_IOBCTL_OSEL (BIT9 | BIT8)
+#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK 0
+#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK_I2S 1
+#define V_PCH_PCR_HDA_IOBCTL_OSEL_I2S 3
+#define N_PCH_PCR_HDA_IOBCTL_OSEL 8
+#define B_PCH_PCR_HDA_IOBCTL_VSEL BIT1
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsHsio.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsHsio.h
new file mode 100644
index 0000000000..8eb62a64a1
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsHsio.h
@@ -0,0 +1,171 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_HSIO_H_
+#define _PCH_REGS_HSIO_H_
+
+#define B_PCH_HSIO_ACCESS_TYPE (BIT15 | BIT14)
+#define N_PCH_HSIO_ACCESS_TYPE 14
+#define V_PCH_HSIO_ACCESS_TYPE_BDCAST (BIT15 | BIT14)
+#define V_PCH_HSIO_ACCESS_TYPE_MULCAST BIT15
+#define B_PCH_HSIO_LANE_GROUP_NO (BIT13 | BIT12 | BIT11 | BIT10 | BIT9)
+#define B_PCH_HSIO_FUNCTION_NO (BIT8 | BIT7)
+#define N_PCH_HSIO_FUNCTION_NO 7
+#define B_PCH_HSIO_REG_OFFSET (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
+
+#define V_PCH_HSIO_ACCESS_TYPE_BCAST 0x03
+#define V_PCH_HSIO_ACCESS_TYPE_MCAST 0x02
+#define V_PCH_HSIO_ACCESS_TYPE_UCAST 0x00
+
+#define V_PCH_HSIO_LANE_GROUP_NO_CMN_LANE 0x00
+
+#define V_PCH_HSIO_FUNCTION_NO_PCS 0x00
+#define V_PCH_HSIO_FUNCTION_NO_TX 0x01
+#define V_PCH_HSIO_FUNCTION_NO_RX 0x02
+
+#define V_PCH_HSIO_FUNCTION_NO_CMNDIG 0x00
+#define V_PCH_HSIO_FUNCTION_NO_CMNANA 0x01
+#define V_PCH_HSIO_FUNCTION_NO_PLL 0x02
+
+#define R_PCH_HSIO_PCS_DWORD4 0x10
+
+#define R_PCH_HSIO_PCS_DWORD8 0x20
+#define B_PCH_HSIO_PCS_DWORD8_CRI_RXEB_PTR_INIT_4_0 0x1F000000
+#define B_PCH_HSIO_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 0x001F0000
+#define N_PCH_HSIO_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 16
+#define B_PCH_HSIO_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 0x00001F00
+#define N_PCH_HSIO_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 8
+
+#define R_PCH_HSIO_PCS_DWORD9 0x24
+#define B_PCH_HSIO_PCS_DWORD9_REG_ENABLE_PWR_GATING BIT29
+
+#define R_PCH_HSIO_RX_DWORD8 0x120
+#define B_PCH_HSIO_RX_DWORD8_ICFGDFETAP3_EN BIT10
+
+#define R_PCH_HSIO_RX_DWORD9 0x124
+#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP4_OVERRIDE_EN BIT24
+#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP3_OVERRIDE_EN BIT26
+#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP2_OVERRIDE_EN BIT28
+#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP1_OVERRIDE_EN BIT30
+
+#define R_PCH_HSIO_RX_DWORD12 0x130
+#define B_PCH_HSIO_RX_DWORD12_O_CFGEWMARGINSEL BIT14
+
+#define R_PCH_HSIO_RX_DWORD20 0x150
+#define B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24)
+#define N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 24
+
+#define R_PCH_HSIO_RX_DWORD21 0x154
+#define B_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
+#define N_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 8
+#define B_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
+#define N_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 0
+
+#define R_PCH_HSIO_RX_DWORD23 0x15C
+#define B_PCH_HSIO_RX_DWORD23_ICFGVGABLWTAP_OVERRIDE_EN BIT2
+#define B_PCH_HSIO_RX_DWORD23_CFGVGATAP_ADAPT_OVERRIDE_EN BIT4
+
+#define R_PCH_HSIO_RX_DWORD25 0x164
+#define B_PCH_HSIO_RX_DWORD25_RX_TAP_CFG_CTRL BIT3
+#define B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 0x1F0000
+#define N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 16
+
+#define R_PCH_HSIO_RX_DWORD26 0x168
+#define B_PCH_HSIO_RX_DWORD26_SATA_EQ_DIS BIT16
+
+#define R_PCH_HSIO_RX_DWORD34 0x188
+#define B_PCH_HSIO_RX_DWORD34_MM_PH_OFC_SCALE_2_0 (BIT14 | BIT13 | BIT12)
+#define N_PCH_HSIO_RX_DWORD34_MM_PH_OFC_SCALE_2_0 12
+
+#define R_PCH_HSIO_RX_DWORD44 0x1B0
+#define B_PCH_HSIO_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 0xFF0000
+#define N_PCH_HSIO_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 16
+
+#define R_PCH_HSIO_RX_DWORD56 0x1E0
+#define B_PCH_HSIO_RX_DWORD56_ICFGPIDACCFGVALID BIT16
+
+#define R_PCH_HSIO_RX_DWORD57 0x1E4
+#define B_PCH_HSIO_RX_DWORD57_JIM_COURSE BIT30
+#define B_PCH_HSIO_RX_DWORD57_JIM_ENABLE BIT29
+#define B_PCH_HSIO_RX_DWORD57_JIMMODE BIT28
+#define B_PCH_HSIO_RX_DWORD57_JIMNUMCYCLES_3_0 0x0F000000
+#define N_PCH_HSIO_RX_DWORD57_JIMNUMCYCLES_3_0 24
+#define B_PCH_HSIO_RX_DWORD57_ICFGMARGINEN BIT0
+
+#define R_PCH_HSIO_RX_DWORD59 0x1EC
+#define R_PCH_HSIO_RX_DWORD60 0x1F0
+
+#define R_PCH_HSIO_TX_DWORD5 0x94
+#define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
+#define N_PCH_HSIO_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 16
+#define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
+#define N_PCH_HSIO_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 8
+
+#define R_PCH_HSIO_TX_DWORD6 0x98
+#define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
+#define N_PCH_HSIO_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 16
+#define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
+#define N_PCH_HSIO_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 8
+#define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN1DEEMPH6P0_5_0 (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
+
+#define R_PCH_HSIO_TX_DWORD8 0xA0
+#define B_PCH_HSIO_TX_DWORD8_ORATE10MARGIN_5_0 (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24)
+#define N_PCH_HSIO_TX_DWORD8_ORATE10MARGIN_5_0 24
+#define B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
+#define N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0 16
+#define B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
+#define N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0 8
+
+#define R_PCH_HSIO_TX_DWORD19 0xCC
+
+#define R_PCH_LP_HSIO_LANE10_PCS_DWORD8 0x020
+#define R_PCH_LP_HSIO_LANE11_PCS_DWORD8 0x220
+#define R_PCH_LP_HSIO_LANE14_PCS_DWORD8 0x820
+#define R_PCH_LP_HSIO_LANE15_PCS_DWORD8 0xA20
+#define R_PCH_H_HSIO_LANE18_PCS_DWORD8 0x820
+#define R_PCH_H_HSIO_LANE19_PCS_DWORD8 0xA20
+#define R_PCH_H_HSIO_LANE22_PCS_DWORD8 0x020
+#define R_PCH_H_HSIO_LANE23_PCS_DWORD8 0x220
+#define R_PCH_H_HSIO_LANE24_PCS_DWORD8 0x420
+#define R_PCH_H_HSIO_LANE25_PCS_DWORD8 0x620
+#define R_PCH_H_HSIO_LANE26_PCS_DWORD8 0x820
+#define R_PCH_H_HSIO_LANE27_PCS_DWORD8 0xA20
+#define R_PCH_H_HSIO_LANE28_PCS_DWORD8 0xC20
+#define R_PCH_H_HSIO_LANE29_PCS_DWORD8 0xE20
+
+#define R_PCH_HSIO_CLANE0_CMN_ANA_DWORD2 0x8088
+#define B_PCH_HSIO_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_PLLEN_H_OVRDEN BIT5
+#define B_PCH_HSIO_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_FULLCALRESET_L_OVERDEN BIT3
+
+#define R_PCH_HSIO_PLL_SSC_DWORD2 0x8108
+#define B_PCH_HSIO_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
+#define N_PCH_HSIO_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 16
+#define B_PCH_HSIO_PLL_SSC_DWORD2_SSCSEN BIT10
+#define N_PCH_HSIO_PLL_SSC_DWORD2_SSCSEN 10
+
+#define R_PCH_HSIO_PLL_SSC_DWORD3 0x810C
+#define B_PCH_HSIO_PLL_SSC_DWORD3_SSC_PROPAGATE BIT0
+
+#define R_PCH_PCR_MODPHY0_COM0_CMN_DIG_DWORD12 0x8030
+#define B_PCH_PCR_MODPHY0_COM0_CMN_DIG_DWORD12_O_CFG_PWR_GATING_CTRL BIT0
+
+//
+// xHCI SSIC Private Configuration Register, but with opcode 4/5 for read/write access
+//
+#define R_PCH_PCR_MMP0_LANE_0_OFFSET 0x0
+#define R_PCH_PCR_MMP0_LANE_1_OFFSET 0x2000
+#define R_PCH_PCR_MMP0_IMPREG21 0x1050
+#define R_PCH_PCR_MMP0_IMPREG22 0x1054
+#define R_PCH_PCR_MMP0_IMPREG23 0x1058
+#define R_PCH_PCR_MMP0_IMPREG24 0x105C
+#define R_PCH_PCR_MMP0_IMPREG25 0x1060
+#define R_PCH_PCR_MMP0_CMNREG4 0xF00C
+#define R_PCH_PCR_MMP0_CMNREG15 0xF038
+#define R_PCH_PCR_MMP0_CMNREG16 0xF03C
+
+#endif //_PCH_REGS_HSIO_H_
+
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsIsh.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsIsh.h
new file mode 100644
index 0000000000..2f519c539f
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsIsh.h
@@ -0,0 +1,51 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_ISH_H_
+#define _PCH_REGS_ISH_H_
+
+//
+// ISH Controller Registers (D19:F0)
+//
+// PCI Configuration Space Registers
+#define PCI_DEVICE_NUMBER_PCH_ISH 19
+#define PCI_FUNCTION_NUMBER_PCH_ISH 0
+#define V_PCH_ISH_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_ISH_DEVICE_ID 0xA135
+#define V_PCH_LP_ISH_DEVICE_ID 0x9D35
+
+#define R_PCH_ISH_BAR0_LOW 0x10
+#define R_PCH_ISH_BAR0_HIGH 0x14
+#define V_PCH_ISH_BAR0_SIZE 0x100000
+#define N_PCH_ISH_BAR0_ALIGNMENT 20
+#define R_PCH_ISH_BAR1_LOW 0x18
+#define R_PCH_ISH_BAR1_HIGH 0x1C
+#define V_PCH_ISH_BAR1_SIZE 0x1000
+#define N_PCH_ISH_BAR1_ALIGNMENT 12
+
+//
+// ISH Private Configuration Space Registers (IOSF2OCP)
+// (PID:ISH)
+//
+#define R_PCH_PCR_ISH_PMCTL 0x1D0 ///< Power Management
+#define R_PCH_PCR_ISH_PCICFGCTRL 0x200 ///< PCI Configuration Control
+#define B_PCH_PCR_ISH_PCICFGCTR_PCI_IRQ 0x0FF00000 ///< PCI IRQ number
+#define N_PCH_PCR_ISH_PCICFGCTR_PCI_IRQ 20
+#define B_PCH_PCR_ISH_PCICFGCTR_ACPI_IRQ 0x000FF000 ///< ACPI IRQ number
+#define N_PCH_PCR_ISH_PCICFGCTR_ACPI_IRQ 12
+#define B_PCH_PCR_ISH_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | BIT8) ///< Interrupt Pin
+#define N_PCH_PCR_ISH_PCICFGCTR_IPIN1 8
+#define B_PCH_PCR_ISH_PCICFGCTRL_BAR1DIS BIT7 ///< BAR1 Disable
+
+//
+// Number of pins used by ISH controllers
+//
+#define PCH_ISH_PINS_PER_I2C_CONTROLLER 2
+#define PCH_ISH_PINS_PER_UART_CONTROLLER 4
+#define PCH_ISH_PINS_PER_SPI_CONTROLLER 4
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsItss.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsItss.h
new file mode 100644
index 0000000000..762fbe3b8e
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsItss.h
@@ -0,0 +1,68 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_ITSS_H_
+#define _PCH_REGS_ITSS_H_
+
+//
+// ITSS PCRs (PID:ITSS)
+//
+#define R_PCH_PCR_ITSS_PIRQA_ROUT 0x3100 ///< PIRQA Routing Control register
+#define R_PCH_PCR_ITSS_PIRQB_ROUT 0x3101 ///< PIRQB Routing Control register
+#define R_PCH_PCR_ITSS_PIRQC_ROUT 0x3102 ///< PIRQC Routing Control register
+#define R_PCH_PCR_ITSS_PIRQD_ROUT 0x3103 ///< PIRQD Routing Control register
+#define R_PCH_PCR_ITSS_PIRQE_ROUT 0x3104 ///< PIRQE Routing Control register
+#define R_PCH_PCR_ITSS_PIRQF_ROUT 0x3105 ///< PIRQF Routing Control register
+#define R_PCH_PCR_ITSS_PIRQG_ROUT 0x3106 ///< PIRQG Routing Control register
+#define R_PCH_PCR_ITSS_PIRQH_ROUT 0x3107 ///< PIRQH Routing Control register
+#define B_PCH_PCR_ITSS_PIRQX_ROUT_REN 0x80 ///< Interrupt Routing Enable
+#define B_PCH_PCR_ITSS_PIRQX_ROUT_IR 0x0F ///< IRQ Routng
+#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_3 0x03 ///< Route PIRQx to IRQ3
+#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_4 0x04 ///< Route PIRQx to IRQ4
+#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_5 0x05 ///< Route PIRQx to IRQ5
+#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_6 0x06 ///< Route PIRQx to IRQ6
+#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_7 0x07 ///< Route PIRQx to IRQ7
+#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_9 0x09 ///< Route PIRQx to IRQ9
+#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_10 0x0A ///< Route PIRQx to IRQ10
+#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_11 0x0B ///< Route PIRQx to IRQ11
+#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_12 0x0C ///< Route PIRQx to IRQ12
+#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_14 0x0E ///< Route PIRQx to IRQ14
+#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_15 0x0F ///< Route PIRQx to IRQ15
+
+#define R_PCH_PCR_ITSS_PIR0 0x3140 ///< PCI Interrupt Route 0
+#define R_PCH_PCR_ITSS_PIR1 0x3142 ///< PCI Interrupt Route 1
+#define R_PCH_PCR_ITSS_PIR2 0x3144 ///< PCI Interrupt Route 2
+#define R_PCH_PCR_ITSS_PIR3 0x3146 ///< PCI Interrupt Route 3
+#define R_PCH_PCR_ITSS_PIR4 0x3148 ///< PCI Interrupt Route 4
+#define R_PCH_PCR_ITSS_PIR5 0x314A ///< PCI Interrupt Route 5
+#define R_PCH_PCR_ITSS_PIR6 0x314C ///< PCI Interrupt Route 6
+#define R_PCH_PCR_ITSS_PIR7 0x314E ///< PCI Interrupt Route 7
+#define R_PCH_PCR_ITSS_PIR8 0x3150 ///< PCI Interrupt Route 8
+#define R_PCH_PCR_ITSS_PIR9 0x3152 ///< PCI Interrupt Route 9
+#define R_PCH_PCR_ITSS_PIR10 0x3154 ///< PCI Interrupt Route 10
+#define R_PCH_PCR_ITSS_PIR11 0x3156 ///< PCI Interrupt Route 11
+#define R_PCH_PCR_ITSS_PIR12 0x3158 ///< PCI Interrupt Route 12
+
+#define R_PCH_PCR_ITSS_GIC 0x31FC ///< General Interrupt Control
+#define B_PCH_PCR_ITSS_GIC_MAX_IRQ_24 BIT9 ///< Max IRQ entry size, 1 = 24 entry size, 0 = 120 entry size
+#define B_PCH_PCR_ITSS_GIC_AME BIT17 ///< Alternate Access Mode Enable
+#define B_PCH_PCR_ITSS_GIC_SPS BIT16 ///< Shutdown Policy Select
+#define R_PCH_PCR_ITSS_IPC0 0x3200 ///< Interrupt Polarity Control 0
+#define R_PCH_PCR_ITSS_IPC1 0x3204 ///< Interrupt Polarity Control 1
+#define R_PCH_PCR_ITSS_IPC2 0x3208 ///< Interrupt Polarity Control 2
+#define R_PCH_PCR_ITSS_IPC3 0x320C ///< Interrupt Polarity Control 3
+#define R_PCH_PCR_ITSS_ITSSPRC 0x3300 ///< ITSS Power Reduction Control
+#define B_PCH_PCR_ITSS_ITSSPRC_PGCBDCGE BIT4 ///< PGCB Dynamic Clock Gating Enable
+#define B_PCH_PCR_ITSS_ITSSPRC_HPETDCGE BIT3 ///< HPET Dynamic Clock Gating Enable
+#define B_PCH_PCR_ITSS_ITSSPRC_8254CGE BIT2 ///< 8254 Static Clock Gating Enable
+#define B_PCH_PCR_ITSS_ITSSPRC_IOSFICGE BIT1 ///< IOSF-Sideband Interface Clock Gating Enable
+#define B_PCH_PCR_ITSS_ITSSPRC_ITSSCGE BIT0 ///< ITSS Clock Gate Enable
+
+#define R_PCH_PCR_ITSS_MMC 0x3334 ///< Master Message Control
+#define B_PCH_PCR_ITSS_MMC_MSTRMSG_EN BIT0 ///< Master Message Enable
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsLan.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsLan.h
new file mode 100644
index 0000000000..473216f61f
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsLan.h
@@ -0,0 +1,135 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_LAN_H_
+#define _PCH_REGS_LAN_H_
+
+//
+// Gigabit LAN Controller configuration registers (D31:F6)
+//
+#define PCI_DEVICE_NUMBER_PCH_LAN 31
+#define PCI_FUNCTION_NUMBER_PCH_LAN 6
+
+#define V_PCH_LAN_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_LAN_DEVICE_ID 0x156F
+
+//
+// LBG Production Gigabit LAN Controller Device ID
+//
+#define V_PCH_LBG_PROD_LAN_DEVICE_ID 0xA1A5
+//
+// LBG SSX (Super SKU) Gigabit LAN Controller Device ID
+//
+#define V_PCH_LBG_LAN_DEVICE_ID 0xA225
+
+#define V_PCH_LP_LAN_DEVICE_ID 0x156F
+#define R_PCH_LAN_MBARA 0x10
+#define B_PCH_LAN_MBARA_BA 0xFFFE0000
+#define N_PCH_LAN_MBARA_ALIGN 17
+#define R_PCH_LAN_LTR_CAP 0xA8
+#define R_PCH_LAN_CLIST1 0xC8
+#define B_PCH_LAN_CLIST1_NEXT 0xFF00
+#define B_PCH_LAN_CLIST1_CID 0x00FF
+#define R_PCH_LAN_PMC 0xCA
+#define B_PCH_LAN_PMC_PMES 0xF800
+#define B_PCH_LAN_PMC_D2S BIT10
+#define B_PCH_LAN_PMC_D1S BIT9
+#define B_PCH_LAN_PMC_AC (BIT8 | BIT7 | BIT6)
+#define B_PCH_LAN_PMC_DSI BIT5
+#define B_PCH_LAN_PMC_PMEC BIT3
+#define B_PCH_LAN_PMC_VS (BIT2 | BIT1 | BIT0)
+#define R_PCH_LAN_PMCS 0xCC
+#define B_PCH_LAN_PMCS_PMES BIT15
+#define B_PCH_LAN_PMCS_DSC (BIT14 | BIT13)
+#define B_PCH_LAN_PMCS_DSL 0x1E00
+#define V_PCH_LAN_PMCS_DSL0 0x0000
+#define V_PCH_LAN_PMCS_DSL3 0x0600
+#define V_PCH_LAN_PMCS_DSL4 0x0800
+#define V_PCH_LAN_PMCS_DSL7 0x0E00
+#define V_PCH_LAN_PMCS_DSL8 0x1000
+#define B_PCH_LAN_PMCS_PMEE BIT8
+#define B_PCH_LAN_PMCS_PS (BIT1 | BIT0)
+#define V_PCH_LAN_PMCS_PS0 0x00
+#define V_PCH_LAN_PMCS_PS3 0x03
+#define R_PCH_LAN_DR 0xCF
+#define B_PCH_LAN_DR 0xFF
+#define R_PCH_LAN_CLIST2 0xD0
+#define B_PCH_LAN_CLIST2_NEXT 0xFF00
+#define B_PCH_LAN_CLIST2_CID 0x00FF
+#define R_PCH_LAN_MCTL 0xD2
+#define B_PCH_LAN_MCTL_CID BIT7
+#define B_PCH_LAN_MCTL_MME (BIT6 | BIT5 | BIT4)
+#define B_PCH_LAN_MCTL_MMC (BIT3 | BIT2 | BIT1)
+#define B_PCH_LAN_MCTL_MSIE BIT0
+#define R_PCH_LAN_MADDL 0xD4
+#define B_PCH_LAN_MADDL 0xFFFFFFFF
+#define R_PCH_LAN_MADDH 0xD8
+#define B_PCH_LAN_MADDH 0xFFFFFFFF
+#define R_PCH_LAN_MDAT 0xDC
+#define B_PCH_LAN_MDAT 0xFFFFFFFF
+#define R_PCH_LAN_FLRCAP 0xE0
+#define B_PCH_LAN_FLRCAP_NEXT 0xFF00
+#define B_PCH_LAN_FLRCAP_CID 0x00FF
+#define V_PCH_LAN_FLRCAP_CID_SSEL0 0x13
+#define V_PCH_LAN_FLRCAP_CID_SSEL1 0x09
+#define R_PCH_LAN_FLRCLV 0xE2
+#define B_PCH_LAN_FLRCLV_FLRC_SSEL0 BIT9
+#define B_PCH_LAN_FLRCLV_TXP_SSEL0 BIT8
+#define B_PCH_LAN_FLRCLV_VSCID_SSEL1 0xF000
+#define B_PCH_LAN_FLRCLV_CAPVER_SSEL1 0x0F00
+#define B_PCH_LAN_FLRCLV_CAPLNG 0x00FF
+#define R_PCH_LAN_DEVCTRL 0xE4
+#define B_PCH_LAN_DEVCTRL BIT0
+#define R_PCH_LAN_CPCE 0x80
+#define B_PCH_LAN_CPCE_HAE BIT5
+#define B_PCH_LAN_CPCE_SE BIT3
+#define B_PCH_LAN_CPCE_D3HE BIT2
+#define B_PCH_LAN_CPCE_I3E BIT1
+#define B_PCH_LAN_CPCE_PCMCRE BIT0
+#define R_PCH_LAN_CD0I3 0x84
+#define B_PCH_LAN_CD0I3_RR BIT3
+#define B_PCH_LAN_CD0I3_D0I3 BIT2
+#define R_PCH_LAN_CLCTL 0x94
+#define R_PCH_LAN_LANDISCTRL 0xA0
+#define B_PCH_LAN_LANDISCTRL_DISABLE BIT0
+#define R_PCH_LAN_LOCKLANDIS 0xA4
+#define B_PCH_LAN_LOCKLANDIS_LOCK BIT0
+//
+// Gigabit LAN Capabilities and Status Registers (Memory space)
+//
+#define R_PCH_LAN_CSR_CTRL 0
+#define B_PCH_LAN_CSR_CTRL_MEHE BIT19
+#define R_PCH_LAN_CSR_STRAP 0x000C
+#define B_PCH_LAN_CSR_STRAP_NVM_VALID BIT11
+#define R_PCH_LAN_CSR_FEXTNVM6 0x0010
+#define R_PCH_LAN_CSR_CTRL_EXT 0x0018
+#define B_PCH_LAN_CSR_CTRL_EXT_FORCE_SMB BIT11
+#define R_PCH_LAN_CSR_MDIC 0x0020
+#define B_PCH_LAN_CSR_MDIC_RB BIT28
+#define B_PCH_LAN_CSR_MDIC_DATA 0xFFFF
+#define R_PCH_LAN_CSR_FEXT 0x002C
+#define B_PCH_LAN_CSR_FEXT_WOL BIT30
+#define B_PCH_LAN_CSR_FEXT_WOL_VALID BIT31
+#define R_PCH_LAN_CSR_EXTCNF_CTRL 0x0F00
+#define B_PCH_LAN_CSR_EXTCNF_CTRL_SWFLAG BIT5
+#define B_PCH_LAN_CSR_EXTCNF_K1OFF_EN BIT8
+#define R_PCH_LAN_CSR_PHY_CTRL 0x0F10
+#define B_PCH_LAN_CSR_PHY_CTRL_GGD BIT6
+#define B_PCH_LAN_CSR_PHY_CTRL_GBEDIS BIT3
+#define B_PCH_LAN_CSR_PHY_CTRL_LPLUND BIT2
+#define B_PCH_LAN_CSR_PHY_CTRL_LPLUD BIT1
+#define R_PCH_LAN_CSR_F18 0x0F18
+#define B_PCH_LAN_CSR_F18_K1OFF_EN BIT31
+#define R_PCH_LAN_CSR_PBECCSTS 0x100C
+#define B_PCH_LAN_CSR_PBECCSTS_ECC_EN BIT16
+#define R_PCH_LAN_CSR_RAL 0x5400
+#define R_PCH_LAN_CSR_RAH 0x5404
+#define B_PCH_LAN_CSR_RAH_RAH 0x0000FFFF
+#define R_PCH_LAN_CSR_WUC 0x5800
+#define B_PCH_LAN_CSR_WUC_APME BIT0
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsLpc.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsLpc.h
new file mode 100644
index 0000000000..27fb432fbf
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsLpc.h
@@ -0,0 +1,430 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_LPC_H_
+#define _PCH_REGS_LPC_H_
+
+#include <PchLimits.h>
+//
+// PCI to LPC Bridge Registers (D31:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_LPC 31
+#define PCI_FUNCTION_NUMBER_PCH_LPC 0
+
+typedef enum {
+ PchHA0 = 0x00,
+ PchHB0 = 0x01,
+ PchHC0,
+ PchHD0,
+ PchHD1,
+#ifdef SIMICS_FLAG
+ PchLpA0 = 0x20,
+#endif
+ PchLpB0 = 0x23,
+ PchLpB1,
+ PchLpC0,
+ PchLpC1,
+ LbgA0 = LBG_A0,
+ LbgB0,
+ LbgB1,
+ LbgB2,
+ LbgS0,
+ LbgS1,
+#ifdef SKXD_EN
+ LbgB1_D,
+#endif // SKXD_EN
+ PchSteppingMax
+} PCH_STEPPING;
+
+#define PCH_H_MIN_SUPPORTED_STEPPING PchHA0
+#define PCH_LP_MIN_SUPPORTED_STEPPING PchLpB0
+
+#define PCH_LBG_MIN_SUPPORTED_STEPPING LbgA0
+#define V_PCH_LPC_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+
+//
+//
+// SKL PCH Server/WS LPC Device IDs
+//
+#define V_PCH_H_LPC_DEVICE_ID_SVR_0 0xA149 ///< Server SKU Intel C236 Chipset
+#define V_PCH_H_LPC_DEVICE_ID_SVR_1 0xA14A ///< Server SKU Intel C232 Chipset
+#define V_PCH_H_LPC_DEVICE_ID_SVR_2 0xA150 ///< Server SKU Intel CM236 Chipset
+#define V_PCH_H_LPC_DEVICE_ID_A14B 0xA14B ///< Super SKU Unlocked
+
+//
+// SKL PCH-H Desktop LPC Device IDs
+//
+#define V_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU 0xA141 ///< PCH H Desktop Super SKU unlocked
+#define V_PCH_H_LPC_DEVICE_ID_DT_0 0xA142 ///< PCH H Desktop Super SKU locked
+#define V_PCH_H_LPC_DEVICE_ID_DT_1 0xA143 ///< PCH H Desktop H110
+#define V_PCH_H_LPC_DEVICE_ID_DT_2 0xA144 ///< PCH H Desktop H170
+#define V_PCH_H_LPC_DEVICE_ID_DT_3 0xA145 ///< PCH H Desktop Z170
+#define V_PCH_H_LPC_DEVICE_ID_DT_4 0xA146 ///< PCH H Desktop Q170
+#define V_PCH_H_LPC_DEVICE_ID_DT_5 0xA147 ///< PCH H Desktop Q150
+#define V_PCH_H_LPC_DEVICE_ID_DT_6 0xA148 ///< PCH H Desktop B150
+#define V_PCH_H_LPC_DEVICE_ID_UNFUSE 0xA140 ///< PCH-H Unfuse
+//
+// PCH-H Mobile LPC Device IDs
+//
+#define V_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU 0xA141 ///< PCH H Mobile Super SKU unlocked
+#define V_PCH_H_LPC_DEVICE_ID_MB_0 0xA14D ///< PCH H Mobile QM170
+#define V_PCH_H_LPC_DEVICE_ID_MB_1 0xA14E ///< PCH H Mobile HM170
+#define V_PCH_H_LPC_DEVICE_ID_MB_2 0xA14F ///< PCH H Mobile QMS170 (SFF)
+//
+// PCH-LP LPC Device IDs
+//
+#define V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU 0x9D41 ///< PCH LP Mobile Super SKU unlocked
+#define V_PCH_LP_LPC_DEVICE_ID_MB_0 0x9D42 ///< PCH LP Mobile Super SKU locked
+#define V_PCH_LP_LPC_DEVICE_ID_MB_1 0x9D43 ///< PCH LP Mobile (U) Base SKU
+#define V_PCH_LP_LPC_DEVICE_ID_MB_2 0x9D46 ///< PCH LP Mobile (Y) Premium SKU
+#define V_PCH_LP_LPC_DEVICE_ID_MB_3 0x9D48 ///< PCH LP Mobile (U) Premium SKU
+#define V_PCH_LP_LPC_DEVICE_ID_UNFUSE 0x9D40 ///< PCH LP Unfuse
+
+//
+// Lewisburg Production LPC Device ID's
+//
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_0 0xA1C0 ///< LBG PRQ Unfused LBG 0 SKU
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_1G 0xA1C1 ///< LBG PRQ Fused LBG 1G
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_2 0xA1C2 ///< LBG PRQ Fused LBG 2
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_4 0xA1C3 ///< LBG PRQ Fused LBG 4
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_E 0xA1C4 ///< LBG PRQ Fused LBG E
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_M 0xA1C5 ///< LBG PRQ Fused LBG M
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_T 0xA1C6 ///< LBG PRQ Fused LBG T (both uplinks SKU - NS)
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_LP 0xA1C7 ///< LBG PRQ Fused LBG LP
+
+#define V_PCH_LBG_PROD_LPC_DEVICE_ID_RESERVED_MAX 0xA1CF ///< 0xA1C8-0xA1CF reserved for future QS/PRQ SKUs
+
+//
+// Lewisburg SSX (Super SKUs and pre production) LPC Device ID's
+//
+#define V_PCH_LBG_LPC_DEVICE_ID_UNFUSED 0xA240 ///< LBG SSX Unfused SKU
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_0 0xA241 ///< LBG SSX Super SKU 0
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_4_SD 0xA242 ///< LBG SSX Super SKU 4/SD
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_T80_NS 0xA243 ///< LBG SSX Super SKU T80/NS
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_1G 0xA244 ///< LBG SSX Super SKU 1G
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_T 0xA245 ///< LBG Super SKU - T
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_L 0xA246 ///< LBG Super SKU - L
+#ifdef SKXD_EN
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_D1 0xA247 ///< LBG Super SKU - D co.fb.sh.1
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_D2 0xA248 ///< LBG Super SKU - D st.gp.sh.2
+#define V_PCH_LBG_LPC_DEVICE_ID_SS_D3 0xA249 ///< LBG Super SKU - D ne.gp.sh.1
+#endif // SKXD_EN
+
+#define V_PCH_LBG_LPC_DEVICE_ID_RESERVED_SS_MAX 0xA24F ///< 0xA247-0xA24F Super SKU reserved
+
+
+#define V_PCH_LBG_LPC_RID_0 0x00 ///< A0 stepping
+#define V_PCH_LBG_LPC_RID_1 0x01 ///< A1 stepping
+#define V_PCH_LBG_LPC_RID_2 0x02 ///< B0 stepping
+#define V_PCH_LBG_LPC_RID_3 0x03 ///< B1 stepping
+#define V_PCH_LBG_LPC_RID_4 0x04 ///< B2 stepping
+#define V_PCH_LBG_LPC_RID_8 0x08 ///< S0 stepping
+#define V_PCH_LBG_LPC_RID_9 0x09 ///< S1 stepping
+
+#define V_PCH_LPC_RID_0 0x00
+#define V_PCH_LPC_RID_1 0x01
+#define V_PCH_LPC_RID_9 0x09
+#define V_PCH_LPC_RID_10 0x10
+#define V_PCH_LPC_RID_11 0x11
+#define V_PCH_LPC_RID_20 0x20
+#define V_PCH_LPC_RID_21 0x21
+#define V_PCH_LPC_RID_30 0x30
+#define V_PCH_LPC_RID_31 0x31
+#define R_PCH_LPC_SERIRQ_CNT 0x64
+#define B_PCH_LPC_SERIRQ_CNT_SIRQEN 0x80
+#define B_PCH_LPC_SERIRQ_CNT_SIRQMD 0x40
+#define B_PCH_LPC_SERIRQ_CNT_SIRQSZ 0x3C
+#define N_PCH_LPC_SERIRQ_CNT_SIRQSZ 2
+#define B_PCH_LPC_SERIRQ_CNT_SFPW 0x03
+#define N_PCH_LPC_SERIRQ_CNT_SFPW 0
+#define V_PCH_LPC_SERIRQ_CNT_SFPW_4CLK 0x00
+#define V_PCH_LPC_SERIRQ_CNT_SFPW_6CLK 0x01
+#define V_PCH_LPC_SERIRQ_CNT_SFPW_8CLK 0x02
+#define R_PCH_LPC_IOD 0x80
+#define B_PCH_LPC_IOD_FDD 0x1000
+#define N_PCH_LPC_IOD_FDD 12
+#define V_PCH_LPC_IOD_FDD_3F0 0
+#define V_PCH_LPC_IOD_FDD_370 1
+#define B_PCH_LPC_IOD_LPT 0x0300
+#define N_PCH_LPC_IOD_LPT 8
+#define V_PCH_LPC_IOD_LPT_378 0
+#define V_PCH_LPC_IOD_LPT_278 1
+#define V_PCH_LPC_IOD_LPT_3BC 2
+#define B_PCH_LPC_IOD_COMB 0x0070
+#define N_PCH_LPC_IOD_COMB 4
+#define V_PCH_LPC_IOD_COMB_3F8 0
+#define V_PCH_LPC_IOD_COMB_2F8 1
+#define V_PCH_LPC_IOD_COMB_220 2
+#define V_PCH_LPC_IOD_COMB_228 3
+#define V_PCH_LPC_IOD_COMB_238 4
+#define V_PCH_LPC_IOD_COMB_2E8 5
+#define V_PCH_LPC_IOD_COMB_338 6
+#define V_PCH_LPC_IOD_COMB_3E8 7
+#define B_PCH_LPC_IOD_COMA 0x0007
+#define N_PCH_LPC_IOD_COMA 0
+#define V_PCH_LPC_IOD_COMA_3F8 0
+#define V_PCH_LPC_IOD_COMA_2F8 1
+#define V_PCH_LPC_IOD_COMA_220 2
+#define V_PCH_LPC_IOD_COMA_228 3
+#define V_PCH_LPC_IOD_COMA_238 4
+#define V_PCH_LPC_IOD_COMA_2E8 5
+#define V_PCH_LPC_IOD_COMA_338 6
+#define V_PCH_LPC_IOD_COMA_3E8 7
+#define R_PCH_LPC_IOE 0x82
+#define B_PCH_LPC_IOE_ME2 BIT13 ///< Microcontroller Enable #2, Enables decoding of I/O locations 4Eh and 4Fh to LPC
+#define B_PCH_LPC_IOE_SE BIT12 ///< Super I/O Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC.
+#define B_PCH_LPC_IOE_ME1 BIT11 ///< Microcontroller Enable #1, Enables decoding of I/O locations 62h and 66h to LPC.
+#define B_PCH_LPC_IOE_KE BIT10 ///< Keyboard Enable, Enables decoding of the keyboard I/O locations 60h and 64h to LPC.
+#define B_PCH_LPC_IOE_HGE BIT9 ///< High Gameport Enable, Enables decoding of the I/O locations 208h to 20Fh to LPC.
+#define B_PCH_LPC_IOE_LGE BIT8 ///< Low Gameport Enable, Enables decoding of the I/O locations 200h to 207h to LPC.
+#define B_PCH_LPC_IOE_FDE BIT3 ///< Floppy Drive Enable, Enables decoding of the FDD range to LPC. Range is selected by LIOD.FDE
+#define B_PCH_LPC_IOE_PPE BIT2 ///< Parallel Port Enable, Enables decoding of the LPT range to LPC. Range is selected by LIOD.LPT.
+#define B_PCH_LPC_IOE_CBE BIT1 ///< Com Port B Enable, Enables decoding of the COMB range to LPC. Range is selected LIOD.CB.
+#define B_PCH_LPC_IOE_CAE BIT0 ///< Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA.
+#define R_PCH_LPC_GEN1_DEC 0x84
+#define R_PCH_LPC_GEN2_DEC 0x88
+#define R_PCH_LPC_GEN3_DEC 0x8C
+#define R_PCH_LPC_GEN4_DEC 0x90
+#define B_PCH_LPC_GENX_DEC_IODRA 0x00FC0000
+#define B_PCH_LPC_GENX_DEC_IOBAR 0x0000FFFC
+#define B_PCH_LPC_GENX_DEC_EN 0x00000001
+#define R_PCH_LPC_ULKMC 0x94
+#define B_PCH_LPC_ULKMC_SMIBYENDPS BIT15
+#define B_PCH_LPC_ULKMC_TRAPBY64W BIT11
+#define B_PCH_LPC_ULKMC_TRAPBY64R BIT10
+#define B_PCH_LPC_ULKMC_TRAPBY60W BIT9
+#define B_PCH_LPC_ULKMC_TRAPBY60R BIT8
+#define B_PCH_LPC_ULKMC_SMIATENDPS BIT7
+#define B_PCH_LPC_ULKMC_PSTATE BIT6
+#define B_PCH_LPC_ULKMC_A20PASSEN BIT5
+#define B_PCH_LPC_ULKMC_USBSMIEN BIT4
+#define B_PCH_LPC_ULKMC_64WEN BIT3
+#define B_PCH_LPC_ULKMC_64REN BIT2
+#define B_PCH_LPC_ULKMC_60WEN BIT1
+#define B_PCH_LPC_ULKMC_60REN BIT0
+#define R_PCH_LPC_LGMR 0x98
+#define B_PCH_LPC_LGMR_MA 0xFFFF0000
+#define B_PCH_LPC_LGMR_LMRD_EN BIT0
+#define LPC_ESPI_FIRST_SLAVE 0
+#define ESPI_SECONDARY_SLAVE 1
+
+#define R_PCH_LPC_FWH_BIOS_SEL 0xD0
+#define B_PCH_LPC_FWH_BIOS_SEL_F8 0xF0000000
+#define B_PCH_LPC_FWH_BIOS_SEL_F0 0x0F000000
+#define B_PCH_LPC_FWH_BIOS_SEL_E8 0x00F00000
+#define B_PCH_LPC_FWH_BIOS_SEL_E0 0x000F0000
+#define B_PCH_LPC_FWH_BIOS_SEL_D8 0x0000F000
+#define B_PCH_LPC_FWH_BIOS_SEL_D0 0x00000F00
+#define B_PCH_LPC_FWH_BIOS_SEL_C8 0x000000F0
+#define B_PCH_LPC_FWH_BIOS_SEL_C0 0x0000000F
+#define R_PCH_LPC_FWH_BIOS_SEL2 0xD4
+#define B_PCH_LPC_FWH_BIOS_SEL2_70 0xF000
+#define B_PCH_LPC_FWH_BIOS_SEL2_60 0x0F00
+#define B_PCH_LPC_FWH_BIOS_SEL2_50 0x00F0
+#define B_PCH_LPC_FWH_BIOS_SEL2_40 0x000F
+#define R_PCH_LPC_BDE 0xD8 ///< BIOS decode enable
+#define B_PCH_LPC_BDE_F8 0x8000
+#define B_PCH_LPC_BDE_F0 0x4000
+#define B_PCH_LPC_BDE_E8 0x2000
+#define B_PCH_LPC_BDE_E0 0x1000
+#define B_PCH_LPC_BDE_D8 0x0800
+#define B_PCH_LPC_BDE_D0 0x0400
+#define B_PCH_LPC_BDE_C8 0x0200
+#define B_PCH_LPC_BDE_C0 0x0100
+#define B_PCH_LPC_BDE_LEG_F 0x0080
+#define B_PCH_LPC_BDE_LEG_E 0x0040
+#define B_PCH_LPC_BDE_70 0x0008
+#define B_PCH_LPC_BDE_60 0x0004
+#define B_PCH_LPC_BDE_50 0x0002
+#define B_PCH_LPC_BDE_40 0x0001
+#define R_PCH_LPC_PCC 0xE0
+#define B_PCH_LPC_PCC_CLKRUN_EN 0x0001
+#define B_PCH_LPC_FVEC0_USB_PORT_CAP 0x00000C00
+#define V_PCH_LPC_FVEC0_USB_14_PORT 0x00000000
+#define V_PCH_LPC_FVEC0_USB_12_PORT 0x00000400
+#define V_PCH_LPC_FVEC0_USB_10_PORT 0x00000800
+#define B_PCH_LPC_FVEC0_SATA_RAID_CAP 0x00000080
+#define B_PCH_LPC_FVEC0_SATA_PORT23_CAP 0x00000040
+#define B_PCH_LPC_FVEC0_SATA_PORT1_6GB_CAP 0x00000008
+#define B_PCH_LPC_FVEC0_SATA_PORT0_6GB_CAP 0x00000004
+#define B_PCH_LPC_FVEC0_PCI_CAP 0x00000002
+#define R_PCH_LPC_FVEC1 0x01
+#define B_PCH_LPC_FVEC1_USB_R_CAP 0x00400000
+#define R_PCH_LPC_FVEC2 0x02
+#define V_PCH_LPC_FVEC2_PCIE_PORT78_CAP 0x00200000
+#define V_PCH_LPC_FVEC2_PCH_IG_SUPPORT_CAP 0x00020000 ///< PCH Integrated Graphics Support Capability
+#define R_PCH_LPC_FVEC3 0x03
+#define B_PCH_LPC_FVEC3_DCMI_CAP 0x00002000 ///< Data Center Manageability Interface (DCMI) Capability
+#define B_PCH_LPC_FVEC3_NM_CAP 0x00001000 ///< Node Manager Capability
+
+#define R_PCH_LPC_MDAP 0xC0
+#define B_PCH_LPC_MDAP_POLICY_EN BIT31
+#define B_PCH_LPC_MDAP_PDMA_EN BIT30
+#define B_PCH_LPC_MDAP_VALUE 0x0001FFFF
+
+//
+// APM Registers
+//
+#define R_PCH_APM_CNT 0xB2
+#define R_PCH_APM_STS 0xB3
+
+#define R_PCH_LPC_BC 0xDC ///< Bios Control
+#define S_PCH_LPC_BC 1
+#define B_PCH_LPC_BC_BILD BIT7 ///< BIOS Interface Lock-Down
+#define B_PCH_LPC_BC_BBS BIT6 ///< Boot BIOS strap
+#define N_PCH_LPC_BC_BBS 6
+#define V_PCH_LPC_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI
+#define V_PCH_LPC_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC
+#define B_PCH_LPC_BC_EISS BIT5 ///< Enable InSMM.STS
+#define B_PCH_LPC_BC_TS BIT4 ///< Top Swap
+#define B_PCH_LPC_BC_LE BIT1 ///< Lock Enable
+#define N_PCH_LPC_BC_LE 1
+#define B_PCH_LPC_BC_WPD BIT0 ///< Write Protect Disable
+
+#define R_PCH_ESPI_PCBC 0xDC ///< Peripheral Channel BIOS Control
+#define S_PCH_ESPI_PCBC 4 ///< Peripheral Channel BIOS Control register size
+#define B_PCH_ESPI_PCBC_BWRE BIT11 ///< BIOS Write Report Enable
+#define N_PCH_ESPI_PCBC_BWRE 11 ///< BIOS Write Report Enable bit position
+#define B_PCH_ESPI_PCBC_BWRS BIT10 ///< BIOS Write Report Status
+#define N_PCH_ESPI_PCBC_BWRS 10 ///< BIOS Write Report Status bit position
+#define B_PCH_ESPI_PCBC_BWPDS BIT8 ///< BIOS Write Protect Disable Status
+#define N_PCH_ESPI_PCBC_BWPDS 8 ///< BIOS Write Protect Disable Status bit position
+#define B_PCH_ESPI_PCBC_ESPI_EN BIT2 ///< eSPI Enable Pin Strap
+#define B_PCH_ESPI_PCBC_LE BIT1 ///< Lock Enable
+
+//
+// Processor interface registers
+//
+#define R_PCH_NMI_SC 0x61
+#define B_PCH_NMI_SC_SERR_NMI_STS BIT7
+#define B_PCH_NMI_SC_IOCHK_NMI_STS BIT6
+#define B_PCH_NMI_SC_TMR2_OUT_STS BIT5
+#define B_PCH_NMI_SC_REF_TOGGLE BIT4
+#define B_PCH_NMI_SC_IOCHK_NMI_EN BIT3
+#define B_PCH_NMI_SC_PCI_SERR_EN BIT2
+#define B_PCH_NMI_SC_SPKR_DAT_EN BIT1
+#define B_PCH_NMI_SC_TIM_CNT2_EN BIT0
+#define R_PCH_NMI_EN 0x70
+#define B_PCH_NMI_EN_NMI_EN BIT7
+
+//
+// PCH I/O Port Defines
+//
+#define R_PCH_IOPORT_PCI_INDEX 0xCF8
+#define R_PCH_IOPORT_PCI_DATA 0xCFC
+#define PCI_CF8_ADDR(Bus, Dev, Func, Off) \
+ (((Off) & 0xFF) | (((Func) & 0x07) << 8) | (((Dev) & 0x1F) << 11) | (((Bus) & 0xFF) << 16) | (1 << 31))
+
+#define PCH_LPC_CF8_ADDR(Offset) PCI_CF8_ADDR(DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, Offset)
+//
+// Reset Generator I/O Port
+//
+#define R_PCH_RST_CNT 0xCF9
+#define B_PCH_RST_CNT_FULL_RST BIT3
+#define B_PCH_RST_CNT_RST_CPU BIT2
+#define B_PCH_RST_CNT_SYS_RST BIT1
+#define V_PCH_RST_CNT_FULLRESET 0x0E
+#define V_PCH_RST_CNT_HARDRESET 0x06
+#define V_PCH_RST_CNT_SOFTRESET 0x04
+#define V_PCH_RST_CNT_HARDSTARTSTATE 0x02
+#define V_PCH_RST_CNT_SOFTSTARTSTATE 0x00
+
+//
+// RTC register
+//
+#define R_PCH_RTC_INDEX 0x70
+#define R_PCH_RTC_TARGET 0x71
+#define R_PCH_RTC_EXT_INDEX 0x72
+#define R_PCH_RTC_EXT_TARGET 0x73
+#define R_PCH_RTC_INDEX_ALT 0x74
+#define R_PCH_RTC_TARGET_ALT 0x75
+#define R_PCH_RTC_EXT_INDEX_ALT 0x76
+#define R_PCH_RTC_EXT_TARGET_ALT 0x77
+#define R_PCH_RTC_REGA 0x0A
+#define B_PCH_RTC_REGA_UIP 0x80
+#define R_PCH_RTC_REGB 0x0B
+#define B_PCH_RTC_REGB_SET 0x80
+#define B_PCH_RTC_REGB_PIE 0x40
+#define B_PCH_RTC_REGB_AIE 0x20
+#define B_PCH_RTC_REGB_UIE 0x10
+#define B_PCH_RTC_REGB_DM 0x04
+#define B_PCH_RTC_REGB_HOURFORM 0x02
+#define R_PCH_RTC_REGC 0x0C
+#define R_PCH_RTC_REGD 0x0D
+
+//
+// Private Configuration Register
+// RTC PCRs (PID:RTC)
+//
+#define R_PCH_PCR_RTC_CONF 0x3400 ///< RTC Configuration register
+#define S_PCH_PCR_RTC_CONF 4
+#define B_PCH_PCR_RTC_CONF_UCMOS_LOCK BIT4
+#define B_PCH_PCR_RTC_CONF_LCMOS_LOCK BIT3
+#define B_PCH_PCR_RTC_CONF_RESERVED BIT31
+#define B_PCH_PCR_RTC_CONF_UCMOS_EN BIT2 ///< Upper CMOS bank enable
+#define R_PCH_PCR_RTC_BUC 0x3414 ///< Backed Up Control
+#define B_PCH_PCR_RTC_BUC_TS BIT0 ///< Top Swap
+#define R_PCH_PCR_RTC_RTCDCG 0x3418 ///< RTC Dynamic Clock Gating Control
+#define R_PCH_PCR_RTC_RTCDCG_RTCPCICLKDCGEN BIT1 ///< ipciclk_clk (24 MHz) Dynamic Clock Gate Enable
+#define R_PCH_PCR_RTC_RTCDCG_RTCROSIDEDCGEN BIT0 ///< rosc_side_clk (120 MHz) Dynamic Clock Gate Enable
+#define R_PCH_PCR_RTC_3F00 0x3F00
+#define R_PCH_PCR_RTC_UIPSMI 0x3F04 ///< RTC Update In Progress SMI Control
+
+//
+// LPC PCR Registers
+//
+#define R_PCH_PCR_LPC_HVMTCTL 0x3410
+#define R_PCH_PCR_LPC_GCFD 0x3418
+#define R_PCH_PCR_LPC_PCT 0x3420
+#define R_PCH_PCR_LPC_SCT 0x3424
+#define R_PCH_PCR_LPC_LPCCT 0x3428
+#define R_PCH_PCR_LPC_ULTOR 0x3500
+
+//
+// eSPI PCR Registers
+//
+#define R_PCH_PCR_ESPI_SLV_CFG_REG_CTL 0x4000 ///< Slave Configuration Register and Link Control
+#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRE BIT31 ///< Slave Configuration Register Access Enable
+#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28) ///< Slave Configuration Register Access Status
+#define N_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRS 28 ///< Slave Configuration Register Access Status bit position
+#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SBLCL BIT27 ///< IOSF-SB eSPI Link Configuration Lock
+#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRS_NOERR 7 ///< No errors (transaction completed successfully)
+#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) ///< Slave ID
+#define N_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SID 19 ///< Slave ID bit position
+#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) ///< Slave Configuration Register Access Type
+#define N_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT 16 ///< Slave Configuration Register Access Type bit position
+#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_RD 0 ///< Slave Configuration register read from address SCRA[11:0]
+#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_WR 1 ///< Slave Configuration register write to address SCRA[11:0]
+#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_STS 2 ///< Slave Status register read
+#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_RS 3 ///< In-Band reset
+#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRA 0x00000FFF ///< Slave Configuration Register Address
+#define R_PCH_PCR_ESPI_SLV_CFG_REG_DATA 0x4004 ///< Slave Configuration Register Data
+
+#define R_PCH_PCR_ESPI_PCERR_SLV0 0x4020 ///< Peripheral Channel Error for Slave 0
+#define R_PCH_PCR_ESPI_PCERR_SLV1 0x4024 ///< Peripheral Channel Error for Slave 1
+#define R_PCH_PCR_ESPI_VWERR_SLV0 0x4030 ///< Virtual Wire Channel Error for Slave 0
+#define R_PCH_PCR_ESPI_VWERR_SLV1 0x4034 ///< Virtual Wire Channel Error for Slave 1
+#define R_PCH_PCR_ESPI_FCERR_SLV0 0x4040 ///< Flash Access Channel Error for Slave 0
+#define B_PCH_PCR_ESPI_XERR_XNFEE (BIT14 | BIT13) ///< Non-Fatal Error Reporting Enable bits
+#define N_PCH_PCR_ESPI_XERR_XNFEE 13 ///< Non-Fatal Error Reporting Enable bit position
+#define V_PCH_PCR_ESPI_XERR_XNFEE_SMI 3 ///< Enable Non-Fatal Error Reporting as SMI
+#define B_PCH_PCR_ESPI_XERR_XNFES BIT12 ///< Fatal Error Status
+#define B_PCH_PCR_ESPI_XERR_XFEE (BIT6 | BIT5) ///< Fatal Error Reporting Enable bits
+#define N_PCH_PCR_ESPI_XERR_XFEE 5 ///< Fatal Error Reporting Enable bit position
+#define V_PCH_PCR_ESPI_XERR_XFEE_SMI 3 ///< Enable Fatal Error Reporting as SMI
+#define B_PCH_PCR_ESPI_XERR_XFES BIT4 ///< Fatal Error Status
+#define B_PCH_PCR_ESPI_PCERR_SLV0_PCURD BIT24 ///< Peripheral Channel Unsupported Request Detected
+#define R_PCH_PCR_ESPI_LNKERR_SLV0 0x4050 ///< Link Error for Slave 0
+#define S_PCH_PCR_ESPI_LNKERR_SLV0 4 ///< Link Error for Slave 0 register size
+#define B_PCH_PCR_ESPI_LNKERR_SLV0_SLCRR BIT31 ///< eSPI Link and Slave Channel Recovery Required
+#define B_PCH_PCR_ESPI_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fatal Error Type 1 Reporting Enable
+#define N_PCH_PCR_ESPI_LNKERR_SLV0_LFET1E 21 ///< Fatal Error Type 1 Reporting Enable bit position
+#define V_PCH_PCR_ESPI_LNKERR_SLV0_LFET1E_SMI 3 ///< Enable Fatal Error Type 1 Reporting as SMI
+#define B_PCH_PCR_ESPI_LNKERR_SLV0_LFET1S BIT20 ///< Link Fatal Error Type 1 Status
+
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsP2sb.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsP2sb.h
new file mode 100644
index 0000000000..3a3f8d5967
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsP2sb.h
@@ -0,0 +1,100 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_P2SB_H_
+#define _PCH_REGS_P2SB_H_
+
+//
+// PCI to P2SB Bridge Registers (D31:F1)
+//
+#define PCI_DEVICE_NUMBER_PCH_P2SB 31
+#define PCI_FUNCTION_NUMBER_PCH_P2SB 1
+
+#define V_PCH_P2SB_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define R_PCH_P2SB_SBREG_BAR 0x10
+#define B_PCH_P2SB_SBREG_RBA 0xFF000000
+#define R_PCH_P2SB_SBREG_BARH 0x14
+#define B_PCH_P2SB_SBREG_RBAH 0xFFFFFFFF
+#define R_PCH_P2SB_VBDF 0x50
+#define B_PCH_P2SB_VBDF_BUF 0xFF00
+#define B_PCH_P2SB_VBDF_DEV 0x00F8
+#define B_PCH_P2SB_VBDF_FUNC 0x0007
+#define R_PCH_P2SB_ESMBDF 0x52
+#define B_PCH_P2SB_ESMBDF_BUF 0xFF00
+#define B_PCH_P2SB_ESMBDF_DEV 0x00F8
+#define B_PCH_P2SB_ESMBDF_FUNC 0x0007
+#define R_PCH_P2SB_RCFG 0x54
+#define B_PCH_P2SB_RCFG_RPRID 0x0000FF00
+#define B_PCH_P2SB_RCFG_RSE BIT0
+#define R_PCH_P2SB_HPTC 0x60
+#define B_PCH_P2SB_HPTC_AE BIT7
+#define B_PCH_P2SB_HPTC_AS 0x0003
+#define N_PCH_HPET_ADDR_ASEL 12
+#define V_PCH_HPET_BASE0 0xFED00000
+#define V_PCH_HPET_BASE1 0xFED01000
+#define V_PCH_HPET_BASE2 0xFED02000
+#define V_PCH_HPET_BASE3 0xFED03000
+#define R_PCH_P2SB_IOAC 0x64
+#define B_PCH_P2SB_IOAC_AE BIT8
+#define B_PCH_P2SB_IOAC_ASEL 0x00FF
+#define N_PCH_IO_APIC_ASEL 12
+#define R_PCH_IO_APIC_INDEX 0xFEC00000
+#define R_PCH_IO_APIC_DATA 0xFEC00010
+#define R_PCH_IO_APIC_EOI 0xFEC00040
+#define R_PCH_P2SB_IBDF 0x6C
+#define B_PCH_P2SB_IBDF_BUF 0xFF00
+#define B_PCH_P2SB_IBDF_DEV 0x00F8
+#define B_PCH_P2SB_IBDF_FUNC 0x0007
+#define R_PCH_P2SB_HBDF 0x70
+#define B_PCH_P2SB_HBDF_BUF 0xFF00
+#define B_PCH_P2SB_HBDF_DEV 0x00F8
+#define B_PCH_P2SB_HBDF_FUNC 0x0007
+#define R_PCH_P2SB_80 0x80
+#define R_PCH_P2SB_84 0x84
+#define R_PCH_P2SB_88 0x88
+#define R_PCH_P2SB_8C 0x8C
+#define R_PCH_P2SB_90 0x90
+#define R_PCH_P2SB_94 0x94
+#define R_PCH_P2SB_98 0x98
+#define R_PCH_P2SB_9C 0x9C
+#define R_PCH_P2SB_DISPBDF 0xA0
+#define B_PCH_P2SB_DISPBDF_DTBLK 0x00070000
+#define B_PCH_P2SB_DISPBDF_BUF 0x0000FF00
+#define B_PCH_P2SB_DISPBDF_DEV 0x000000F8
+#define B_PCH_P2SB_DISPBDF_FUNC 0x00000007
+#define R_PCH_P2SB_ICCOS 0xA4
+#define B_PCH_P2SB_ICCOS_MODBASE 0xFF00
+#define B_PCH_P2SB_ICCOS_BUFBASE 0x00FF
+
+//
+// Definition for SBI
+//
+#define R_PCH_P2SB_SBIADDR 0xD0
+#define B_PCH_P2SB_SBIADDR_DESTID 0xFF000000
+#define B_PCH_P2SB_SBIADDR_RS 0x000F0000
+#define B_PCH_P2SB_SBIADDR_OFFSET 0x0000FFFF
+#define R_PCH_P2SB_SBIDATA 0xD4
+#define B_PCH_P2SB_SBIDATA_DATA 0xFFFFFFFF
+#define R_PCH_P2SB_SBISTAT 0xD8
+#define B_PCH_P2SB_SBISTAT_OPCODE 0xFF00
+#define B_PCH_P2SB_SBISTAT_POSTED BIT7
+#define B_PCH_P2SB_SBISTAT_RESPONSE 0x0006
+#define N_PCH_P2SB_SBISTAT_RESPONSE 1
+#define B_PCH_P2SB_SBISTAT_INITRDY BIT0
+#define R_PCH_P2SB_SBIRID 0xDA
+#define B_PCH_P2SB_SBIRID_FBE 0xF000
+#define B_PCH_P2SB_SBIRID_BAR 0x0700
+#define B_PCH_P2SB_SBIRID_FID 0x00FF
+#define R_PCH_P2SB_SBIEXTADDR 0xDC
+#define B_PCH_P2SB_SBIEXTADDR_ADDR 0xFFFFFFFF
+
+//
+// Others
+//
+#define R_PCH_P2SB_E0 0xE0
+#define R_PCH_P2SB_F4 0xF4
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPcie.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPcie.h
new file mode 100644
index 0000000000..e31d699b4d
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPcie.h
@@ -0,0 +1,513 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_PCIE_H_
+#define _PCH_REGS_PCIE_H_
+
+//
+// PCH PCI Express Root Ports (D28:F0~7 & D29:F0~3)
+//
+#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5 4
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6 5
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7 6
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8 7
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9 0
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10 1
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11 2
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12 3
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13 4
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14 5
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15 6
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16 7
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17 0
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18 1
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19 2
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20 3
+
+#define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+
+#define V_PCH_H_PCIE_DEVICE_ID_PORT1 0xA110 ///< PCI Express Root Port #1, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT2 0xA111 ///< PCI Express Root Port #2, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT3 0xA112 ///< PCI Express Root Port #3, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT4 0xA113 ///< PCI Express Root Port #4, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT5 0xA114 ///< PCI Express Root Port #5, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT6 0xA115 ///< PCI Express Root Port #6, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT7 0xA116 ///< PCI Express Root Port #7, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT8 0xA117 ///< PCI Express Root Port #8, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT9 0xA118 ///< PCI Express Root Port #9, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT10 0xA119 ///< PCI Express Root Port #10, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT11 0xA11A ///< PCI Express Root Port #11, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT12 0xA11B ///< PCI Express Root Port #12, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT13 0xA11C ///< PCI Express Root Port #13, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT14 0xA11D ///< PCI Express Root Port #14, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT15 0xA11E ///< PCI Express Root Port #15, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT16 0xA11F ///< PCI Express Root Port #16, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT17 0xA167 ///< PCI Express Root Port #17, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT18 0xA168 ///< PCI Express Root Port #18, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT19 0xA169 ///< PCI Express Root Port #19, SKL PCH H
+#define V_PCH_H_PCIE_DEVICE_ID_PORT20 0xA16A ///< PCI Express Root Port #20, SKL PCH H
+
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT1 0x9D10 ///< PCI Express Root Port #1, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT2 0x9D11 ///< PCI Express Root Port #2, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT3 0x9D12 ///< PCI Express Root Port #3, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT4 0x9D13 ///< PCI Express Root Port #4, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT5 0x9D14 ///< PCI Express Root Port #5, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT6 0x9D15 ///< PCI Express Root Port #6, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT7 0x9D16 ///< PCI Express Root Port #7, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT8 0x9D17 ///< PCI Express Root Port #8, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT9 0x9D18 ///< PCI Express Root Port #9, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT10 0x9D19 ///< PCI Express Root Port #10, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT11 0x9D1A ///< PCI Express Root Port #11, SKL PCH LP PCIe Device ID
+#define V_PCH_LP_PCIE_DEVICE_ID_PORT12 0x9D1B ///< PCI Express Root Port #12, SKL PCH LP PCIe Device ID
+
+//
+// LBG Production (PRQ) PCI Express Root Ports Device ID's
+//
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT1 0xA190 ///< PCI Express Root Port #1, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT2 0xA191 ///< PCI Express Root Port #2, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT3 0xA192 ///< PCI Express Root Port #3, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT4 0xA193 ///< PCI Express Root Port #4, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT5 0xA194 ///< PCI Express Root Port #5, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT6 0xA195 ///< PCI Express Root Port #6, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT7 0xA196 ///< PCI Express Root Port #7, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT8 0xA197 ///< PCI Express Root Port #8, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT9 0xA198 ///< PCI Express Root Port #9, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT10 0xA199 ///< PCI Express Root Port #10, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT11 0xA19A ///< PCI Express Root Port #11, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT12 0xA19B ///< PCI Express Root Port #12, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT13 0xA19C ///< PCI Express Root Port #13, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT14 0xA19D ///< PCI Express Root Port #14, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT15 0xA19E ///< PCI Express Root Port #15, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT16 0xA19F ///< PCI Express Root Port #16, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT17 0xA1E7 ///< PCI Express Root Port #17, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT18 0xA1E8 ///< PCI Express Root Port #18, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT19 0xA1E9 ///< PCI Express Root Port #19, LBG PRQ
+#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT20 0xA1EA ///< PCI Express Root Port #20, LBG PRQ
+//
+// LBG Super SKU (SSX) PCI Express Root Ports Device ID's
+//
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT1 0xA210 ///< PCI Express Root Port #1, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT2 0xA211 ///< PCI Express Root Port #2, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT3 0xA212 ///< PCI Express Root Port #3, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT4 0xA213 ///< PCI Express Root Port #4, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT5 0xA214 ///< PCI Express Root Port #5, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT6 0xA215 ///< PCI Express Root Port #6, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT7 0xA216 ///< PCI Express Root Port #7, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT8 0xA217 ///< PCI Express Root Port #8, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT9 0xA218 ///< PCI Express Root Port #9, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT10 0xA219 ///< PCI Express Root Port #10, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT11 0xA21A ///< PCI Express Root Port #11, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT12 0xA21B ///< PCI Express Root Port #12, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT13 0xA21C ///< PCI Express Root Port #13, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT14 0xA21D ///< PCI Express Root Port #14, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT15 0xA21E ///< PCI Express Root Port #15, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT16 0xA21F ///< PCI Express Root Port #16, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT17 0xA267 ///< PCI Express Root Port #17, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT18 0xA268 ///< PCI Express Root Port #18, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT19 0xA269 ///< PCI Express Root Port #19, LBG SSKU
+#define V_PCH_LBG_PCIE_DEVICE_ID_PORT20 0xA26A ///< PCI Express Root Port #20, LBG SSKU
+
+#define R_PCH_PCIE_CLIST 0x40
+#define R_PCH_PCIE_XCAP (R_PCH_PCIE_CLIST + R_PCIE_XCAP_OFFSET)
+#define R_PCH_PCIE_DCAP (R_PCH_PCIE_CLIST + R_PCIE_DCAP_OFFSET)
+#define R_PCH_PCIE_DCTL (R_PCH_PCIE_CLIST + R_PCIE_DCTL_OFFSET)
+#define R_PCH_PCIE_DSTS (R_PCH_PCIE_CLIST + R_PCIE_DSTS_OFFSET)
+#define R_PCH_PCIE_LCAP (R_PCH_PCIE_CLIST + R_PCIE_LCAP_OFFSET)
+#define B_PCH_PCIE_LCAP_PN 0xFF000000
+#define N_PCH_PCIE_LCAP_PN 24
+#define R_PCH_PCIE_LCTL (R_PCH_PCIE_CLIST + R_PCIE_LCTL_OFFSET)
+#define R_PCH_PCIE_LSTS (R_PCH_PCIE_CLIST + R_PCIE_LSTS_OFFSET)
+#define R_PCH_PCIE_SLCAP (R_PCH_PCIE_CLIST + R_PCIE_SLCAP_OFFSET)
+#define R_PCH_PCIE_SLCTL (R_PCH_PCIE_CLIST + R_PCIE_SLCTL_OFFSET)
+#define R_PCH_PCIE_SLSTS (R_PCH_PCIE_CLIST + R_PCIE_SLSTS_OFFSET)
+#define R_PCH_PCIE_RCTL (R_PCH_PCIE_CLIST + R_PCIE_RCTL_OFFSET)
+#define R_PCH_PCIE_RSTS (R_PCH_PCIE_CLIST + R_PCIE_RSTS_OFFSET)
+#define R_PCH_PCIE_DCAP2 (R_PCH_PCIE_CLIST + R_PCIE_DCAP2_OFFSET)
+#define R_PCH_PCIE_DCTL2 (R_PCH_PCIE_CLIST + R_PCIE_DCTL2_OFFSET)
+#define R_PCH_PCIE_LCTL2 (R_PCH_PCIE_CLIST + R_PCIE_LCTL2_OFFSET)
+#define R_PCH_PCIE_LSTS2 (R_PCH_PCIE_CLIST + R_PCIE_LSTS2_OFFSET)
+
+
+#define R_PCH_PCIE_MID 0x80
+#define S_PCH_PCIE_MID 2
+#define R_PCH_PCIE_MC 0x82
+#define S_PCH_PCIE_MC 2
+#define R_PCH_PCIE_MA 0x84
+#define S_PCH_PCIE_MA 4
+#define R_PCH_PCIE_MD 0x88
+#define S_PCH_PCIE_MD 2
+
+#define R_PCH_PCIE_SVCAP 0x90
+#define S_PCH_PCIE_SVCAP 2
+#define R_PCH_PCIE_SVID 0x94
+#define S_PCH_PCIE_SVID 4
+
+#define R_PCH_PCIE_PMCAP 0xA0
+#define R_PCH_PCIE_PMCS (R_PCH_PCIE_PMCAP + R_PCIE_PMCS_OFFST)
+#define R_PCH_PCIE_MPC2 0xD4
+#define S_PCH_PCIE_MPC2 4
+#define B_PCH_PCIE_MPC2_PTNFAE BIT12
+#define B_PCH_PCIE_MPC2_LSTP BIT6
+#define B_PCH_PCIE_MPC2_IEIME BIT5
+#define B_PCH_PCIE_MPC2_ASPMCOEN BIT4
+#define B_PCH_PCIE_MPC2_ASPMCO (BIT3 | BIT2)
+#define V_PCH_PCIE_MPC2_ASPMCO_DISABLED 0
+#define V_PCH_PCIE_MPC2_ASPMCO_L0S (1 << 2)
+#define V_PCH_PCIE_MPC2_ASPMCO_L1 (2 << 2)
+#define V_PCH_PCIE_MPC2_ASPMCO_L0S_L1 (3 << 2)
+#define B_PCH_PCIE_MPC2_EOIFD BIT1
+
+#define R_PCH_PCIE_MPC 0xD8
+#define S_PCH_PCIE_MPC 4
+#define B_PCH_PCIE_MPC_PMCE BIT31
+#define B_PCH_PCIE_MPC_HPCE BIT30
+#define B_PCH_PCIE_MPC_MMBNCE BIT27
+#define B_PCH_PCIE_MPC_P8XDE BIT26
+#define B_PCH_PCIE_MPC_IRRCE BIT25
+#define B_PCH_PCIE_MPC_SRL BIT23
+#define B_PCH_PCIE_MPC_UCEL (BIT20 | BIT19 | BIT18)
+#define N_PCH_PCIE_MPC_UCEL 18
+#define B_PCH_PCIE_MPC_CCEL (BIT17 | BIT16 | BIT15)
+#define N_PCH_PCIE_MPC_CCEL 15
+#define B_PCH_PCIE_MPC_PCIESD (BIT14 | BIT13)
+#define N_PCH_PCIE_MPC_PCIESD 13
+#define V_PCH_PCIE_MPC_PCIESD_GEN1 1
+#define V_PCH_PCIE_MPC_PCIESD_GEN2 2
+#define B_PCH_PCIE_MPC_MCTPSE BIT3
+#define B_PCH_PCIE_MPC_HPME BIT1
+#define N_PCH_PCIE_MPC_HPME 1
+#define B_PCH_PCIE_MPC_PMME BIT0
+
+#define R_PCH_PCIE_SMSCS 0xDC
+#define S_PCH_PCIE_SMSCS 4
+#define N_PCH_PCIE_SMSCS_LERSMIS 5
+#define N_PCH_PCIE_SMSCS_HPLAS 4
+#define N_PCH_PCIE_SMSCS_HPPDM 1
+
+#define R_PCH_PCIE_RPDCGEN 0xE1
+#define S_PCH_PCIE_RPDCGEN 1
+#define B_PCH_PCIE_RPDCGEN_RPSCGEN BIT7
+#define B_PCH_PCIE_RPDCGEN_PTOCGE BIT6
+#define B_PCH_PCIE_RPDCGEN_LCLKREQEN BIT5
+#define B_PCH_PCIE_RPDCGEN_BBCLKREQEN BIT4
+#define B_PCH_PCIE_RPDCGEN_SRDBCGEN BIT2
+#define B_PCH_PCIE_RPDCGEN_RPDLCGEN BIT1
+#define B_PCH_PCIE_RPDCGEN_RPDBCGEN BIT0
+
+
+#define R_PCH_PCIE_PWRCTL 0xE8
+#define B_PCH_PCIE_PWRCTL_LTSSMRTC BIT20
+#define B_PCH_PCIE_PWRCTL_WPDMPGEP BIT17
+#define B_PCH_PCIE_PWRCTL_DBUPI BIT15
+#define B_PCH_PCIE_PWRCTL_TXSWING BIT13
+#define B_PCH_PCIE_PWRCTL_RPL1SQPOL BIT1
+#define B_PCH_PCIE_PWRCTL_RPDTSQPOL BIT0
+
+#define R_PCH_PCIE_DC 0xEC
+#define B_PCH_PCIE_DC_PCIBEM BIT2
+
+#define R_PCH_PCIE_PHYCTL2 0xF5
+#define B_PCH_PCIE_PHYCTL2_TDFT (BIT7 | BIT6)
+#define B_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4)
+#define N_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT 4
+#define B_PCH_PCIE_PHYCTL2_PXPG3PLLOFFEN BIT1
+#define B_PCH_PCIE_PHYCTL2_PXPG2PLLOFFEN BIT0
+
+#define R_PCH_PCIE_IOSFSBCS 0xF7
+#define B_PCH_PCIE_IOSFSBCS_SCPTCGE BIT6
+#define B_PCH_PCIE_IOSFSBCS_SIID (BIT3 | BIT2)
+
+#define R_PCH_PCIE_STRPFUSECFG 0xFC
+#define B_PCH_PCIE_STRPFUSECFG_PXIP (BIT27 | BIT26 | BIT25 | BIT24)
+#define N_PCH_PCIE_STRPFUSECFG_PXIP 24
+#define B_PCH_PCIE_STRPFUSECFG_RPC (BIT15 | BIT14)
+#define V_PCH_PCIE_STRPFUSECFG_RPC_1_1_1_1 0
+#define V_PCH_PCIE_STRPFUSECFG_RPC_2_1_1 1
+#define V_PCH_PCIE_STRPFUSECFG_RPC_2_2 2
+#define V_PCH_PCIE_STRPFUSECFG_RPC_4 3
+#define N_PCH_PCIE_STRPFUSECFG_RPC 14
+#define B_PCH_PCIE_STRPFUSECFG_MODPHYIOPMDIS BIT9
+#define B_PCH_PCIE_STRPFUSECFG_PLLSHTDWNDIS BIT8
+#define B_PCH_PCIE_STRPFUSECFG_STPGATEDIS BIT7
+#define B_PCH_PCIE_STRPFUSECFG_ASPMDIS BIT6
+#define B_PCH_PCIE_STRPFUSECFG_LDCGDIS BIT5
+#define B_PCH_PCIE_STRPFUSECFG_LTCGDIS BIT4
+#define B_PCH_PCIE_STRPFUSECFG_CDCGDIS BIT3
+#define B_PCH_PCIE_STRPFUSECFG_DESKTOPMOB BIT2
+
+//
+//PCI Express Extended Capability Registers
+//
+
+#define R_PCH_PCIE_EXCAP_OFFSET 0x100
+
+#define R_PCH_PCIE_EX_AECH 0x100 ///< Advanced Error Reporting Capability Header
+#define V_PCH_PCIE_EX_AEC_CV 0x1
+#define R_PCH_PCIE_EX_UEM (R_PCH_PCIE_EX_AECH + R_PCIE_EX_UEM_OFFSET)
+
+#define R_PCH_PCIE_EX_CES 0x110 ///< Correctable Error Status
+#define B_PCH_PCIE_EX_CES_BD BIT7 ///< Bad DLLP Status
+#define B_PCH_PCIE_EX_CES_BT BIT6 ///< Bad TLP Status
+#define B_PCH_PCIE_EX_CES_RE BIT0 ///< Receiver Error Status
+
+
+//CES.RE, CES.BT, CES.BD
+
+#define R_PCH_PCIE_EX_ACSECH 0x140 ///< ACS Extended Capability Header
+#define V_PCH_PCIE_EX_ACS_CV 0x1
+#define R_PCH_PCIE_EX_ACSCAPR (R_PCH_PCIE_EX_ACSECH + R_PCIE_EX_ACSCAPR_OFFSET)
+
+#define R_PCH_PCIE_EX_L1SECH 0x200 ///< L1 Sub-States Extended Capability Header
+#define V_PCH_PCIE_EX_L1S_CV 0x1
+#define R_PCH_PCIE_EX_L1SCAP (R_PCH_PCIE_EX_L1SECH + R_PCIE_EX_L1SCAP_OFFSET)
+#define R_PCH_PCIE_EX_L1SCTL1 (R_PCH_PCIE_EX_L1SECH + R_PCIE_EX_L1SCTL1_OFFSET)
+#define R_PCH_PCIE_EX_L1SCTL2 (R_PCH_PCIE_EX_L1SECH + R_PCIE_EX_L1SCTL2_OFFSET)
+
+#define R_PCH_PCIE_EX_SPEECH 0x220 ///< Secondary PCI Express Extended Capability Header
+#define V_PCH_PCIE_EX_SPEECH_CV 0x1
+
+#define R_PCH_PCIE_EX_LCTL3 (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_LCTL3_OFFSET)
+#define R_PCH_PCIE_EX_LES (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_LES_OFFSET)
+#define R_PCH_PCIE_EX_LECTL (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L01EC_OFFSET)
+#define B_PCH_PCIE_EX_LECTL_UPTPH (BIT14 | BIT13 | BIT12)
+#define N_PCH_PCIE_EX_LECTL_UPTPH 12
+#define B_PCH_PCIE_EX_LECTL_UPTP 0x0F00
+#define N_PCH_PCIE_EX_LECTL_UPTP 8
+#define B_PCH_PCIE_EX_LECTL_DPTPH (BIT6 | BIT5 | BIT4)
+#define N_PCH_PCIE_EX_LECTL_DPTPH 4
+#define B_PCH_PCIE_EX_LECTL_DPTP 0x000F
+#define N_PCH_PCIE_EX_LECTL_DPTP 0
+
+#define R_PCH_PCIE_EX_L01EC (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L01EC_OFFSET)
+#define R_PCH_PCIE_EX_L23EC (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L23EC_OFFSET)
+
+#define R_PCH_PCIE_PCIERTP1 0x300
+#define R_PCH_PCIE_PCIERTP2 0x304
+#define R_PCH_PCIE_PCIENFTS 0x314
+#define R_PCH_PCIE_PCIEL0SC 0x318
+
+#define R_PCH_PCIE_PCIECFG2 0x320
+#define B_PCH_PCIE_PCIECFG2_LBWSSTE BIT30
+#define B_PCH_PCIE_PCIECFG2_RLLG3R BIT27
+#define B_PCH_PCIE_PCIECFG2_CROAOV BIT24
+#define B_PCH_PCIE_PCIECFG2_CROAOE BIT23
+#define B_PCH_PCIE_PCIECFG2_CRSREN BIT22
+#define B_PCH_PCIE_PCIECFG2_PMET (BIT21 | BIT20)
+#define V_PCH_PCIE_PCIECFG2_PMET 1
+#define N_PCH_PCIE_PCIECFG2_PMET 20
+
+#define R_PCH_PCIE_PCIEDBG 0x324
+#define B_PCH_PCIE_PCIEDBG_USSP (BIT27 | BIT26)
+#define B_PCH_PCIE_PCIEDBG_LGCLKSQEXITDBTIMERS (BIT25 | BIT24)
+#define B_PCH_PCIE_PCIEDBG_CTONFAE BIT14
+#define B_PCH_PCIE_PCIEDBG_SQOL0 BIT7
+#define B_PCH_PCIE_PCIEDBG_SPCE BIT5
+#define B_PCH_PCIE_PCIEDBG_LR BIT4
+
+#define R_PCH_PCIE_PCIESTS1 0x328
+#define B_PCH_PCIE_PCIESTS1_LTSMSTATE 0xFF000000
+#define N_PCH_PCIE_PCIESTS1_LTSMSTATE 24
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDY 0x01
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDYECINP1CG 0x0E
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_L0 0x33
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DISWAIT 0x5E
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DISWAITPG 0x60
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_RECOVERYSPEEDREADY 0x6C
+#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_RECOVERYLNK2DETECT 0x6F
+
+
+#define B_PCH_PCIE_PCIESTS1_LNKSTAT (BIT22 | BIT21 | BIT20 | BIT19)
+#define N_PCH_PCIE_PCIESTS1_LNKSTAT 19
+#define V_PCH_PCIE_PCIESTS1_LNKSTAT_L0 0x7
+
+#define R_PCH_PCIE_PCIESTS2 0x32C
+#define B_PCH_PCIE_PCIESTS2_P4PNCCWSSCMES BIT31
+#define B_PCH_PCIE_PCIESTS2_P3PNCCWSSCMES BIT30
+#define B_PCH_PCIE_PCIESTS2_P2PNCCWSSCMES BIT29
+#define B_PCH_PCIE_PCIESTS2_P1PNCCWSSCMES BIT28
+#define B_PCH_PCIE_PCIESTS2_CLRE 0x0000F000
+#define N_PCH_PCIE_PCIESTS2_CLRE 12
+
+#define R_PCH_PCIE_PCIEALC 0x338
+#define B_PCH_PCIE_PCIEALC_ITLRCLD BIT29
+#define B_PCH_PCIE_PCIEALC_ILLRCLD BIT28
+#define B_PCH_PCIE_PCIEALC_BLKDQDA BIT26
+#define R_PCH_PCIE_PHYCTL4 0x408
+#define B_PCH_PCIE_PHYCTL4_SQDIS BIT27
+
+#define R_PCH_PCIE_PCIEPMECTL2 0x424
+#define B_PCH_PCIE_PCIEPMECTL2_PHYCLPGE BIT11
+#define B_PCH_PCIE_PCIEPMECTL2_FDCPGE BIT8
+#define B_PCH_PCIE_PCIEPMECTL2_DETSCPGE BIT7
+#define B_PCH_PCIE_PCIEPMECTL2_L23RDYSCPGE BIT6
+#define B_PCH_PCIE_PCIEPMECTL2_DISSCPGE BIT5
+#define B_PCH_PCIE_PCIEPMECTL2_L1SCPGE BIT4
+
+#define R_PCH_PCIE_PCE 0x428
+#define B_PCH_PCIE_PCE_HAE BIT5
+#define B_PCH_PCIE_PCE_PMCRE BIT0
+
+#define R_PCH_PCIE_EQCFG1 0x450
+#define S_PCH_PCIE_EQCFG1 4
+#define B_PCH_PCIE_EQCFG1_REC 0xFF000000
+#define N_PCH_PCIE_EQCFG1_REC 24
+#define B_PCH_PCIE_EQCFG1_REIFECE BIT23
+#define N_PCH_PCIE_EQCFG1_LERSMIE 21
+#define B_PCH_PCIE_EQCFG1_LEP23B BIT18
+#define B_PCH_PCIE_EQCFG1_LEP3B BIT17
+#define B_PCH_PCIE_EQCFG1_RTLEPCEB BIT16
+#define B_PCH_PCIE_EQCFG1_RTPCOE BIT15
+#define B_PCH_PCIE_EQCFG1_HPCMQE BIT13
+#define B_PCH_PCIE_EQCFG1_HAED BIT12
+#define B_PCH_PCIE_EQCFG1_EQTS2IRRC BIT7
+#define B_PCH_PCIE_EQCFG1_TUPP BIT1
+
+#define R_PCH_PCIE_RTPCL1 0x454
+#define B_PCH_PCIE_RTPCL1_PCM BIT31
+#define B_PCH_PCIE_RTPCL1_RTPRECL2PL4 0x3F000000
+#define B_PCH_PCIE_RTPCL1_RTPOSTCL1PL3 0xFC0000
+#define B_PCH_PCIE_RTPCL1_RTPRECL1PL2 0x3F000
+#define B_PCH_PCIE_RTPCL1_RTPOSTCL0PL1 0xFC0
+#define B_PCH_PCIE_RTPCL1_RTPRECL0PL0 0x3F
+
+#define R_PCH_PCIE_RTPCL2 0x458
+#define B_PCH_PCIE_RTPCL2_RTPOSTCL3PL 0x3F000
+#define B_PCH_PCIE_RTPCL2_RTPRECL3PL6 0xFC0
+#define B_PCH_PCIE_RTPCL2_RTPOSTCL2PL5 0x3F
+
+#define R_PCH_PCIE_RTPCL3 0x45C
+#define B_PCH_PCIE_RTPCL3_RTPRECL7 0x3F000000
+#define B_PCH_PCIE_RTPCL3_RTPOSTCL6 0xFC0000
+#define B_PCH_PCIE_RTPCL3_RTPRECL6 0x3F000
+#define B_PCH_PCIE_RTPCL3_RTPOSTCL5 0xFC0
+#define B_PCH_PCIE_RTPCL3_RTPRECL5PL10 0x3F
+
+#define R_PCH_PCIE_RTPCL4 0x460
+#define B_PCH_PCIE_RTPCL4_RTPOSTCL9 0x3F000000
+#define B_PCH_PCIE_RTPCL4_RTPRECL9 0xFC0000
+#define B_PCH_PCIE_RTPCL4_RTPOSTCL8 0x3F000
+#define B_PCH_PCIE_RTPCL4_RTPRECL8 0xFC0
+#define B_PCH_PCIE_RTPCL4_RTPOSTCL7 0x3F
+
+#define R_PCH_PCIE_FOMS 0x464
+#define B_PCH_PCIE_FOMS_I (BIT30 | BIT29)
+#define N_PCH_PCIE_FOMS_I 29
+#define B_PCH_PCIE_FOMS_LN 0x1F000000
+#define N_PCH_PCIE_FOMS_LN 24
+#define B_PCH_PCIE_FOMS_FOMSV 0x00FFFFFF
+#define B_PCH_PCIE_FOMS_FOMSV0 0x000000FF
+#define N_PCH_PCIE_FOMS_FOMSV0 0
+#define B_PCH_PCIE_FOMS_FOMSV1 0x0000FF00
+#define N_PCH_PCIE_FOMS_FOMSV1 8
+#define B_PCH_PCIE_FOMS_FOMSV2 0x00FF0000
+#define N_PCH_PCIE_FOMS_FOMSV2 16
+
+#define R_PCH_PCIE_HAEQ 0x468
+#define B_PCH_PCIE_HAEQ_HAPCCPI (BIT31 | BIT30 | BIT29 | BIT28)
+#define N_PCH_PCIE_HAEQ_HAPCCPI 28
+#define B_PCH_PCIE_HAEQ_MACFOMC BIT19
+
+#define R_PCH_PCIE_LTCO1 0x470
+#define B_PCH_PCIE_LTCO1_L1TCOE BIT25
+#define B_PCH_PCIE_LTCO1_L0TCOE BIT24
+#define B_PCH_PCIE_LTCO1_L1TPOSTCO 0xFC0000
+#define N_PCH_PCIE_LTCO1_L1TPOSTCO 18
+#define B_PCH_PCIE_LTCO1_L1TPRECO 0x3F000
+#define N_PCH_PCIE_LTCO1_L1TPRECO 12
+#define B_PCH_PCIE_LTCO1_L0TPOSTCO 0xFC0
+#define N_PCH_PCIE_LTCO1_L0TPOSTCO 6
+#define B_PCH_PCIE_LTCO1_L0TPRECO 0x3F
+#define N_PCH_PCIE_LTCO1_L0TPRECO 0
+
+#define R_PCH_PCIE_LTCO2 0x474
+#define B_PCH_PCIE_LTCO2_L3TCOE BIT25
+#define B_PCH_PCIE_LTCO2_L2TCOE BIT24
+#define B_PCH_PCIE_LTCO2_L3TPOSTCO 0xFC0000
+#define B_PCH_PCIE_LTCO2_L3TPRECO 0x3F000
+#define B_PCH_PCIE_LTCO2_L2TPOSTCO 0xFC0
+#define B_PCH_PCIE_LTCO2_L2TPRECO 0x3F
+
+#define R_PCH_PCIE_G3L0SCTL 0x478
+#define B_PCH_PCIE_G3L0SCTL_G3UCNFTS 0x0000FF00
+#define B_PCH_PCIE_G3L0SCTL_G3CCNFTS 0x000000FF
+
+#define R_PCH_PCIE_EQCFG2 0x47C
+#define B_PCH_PCIE_EQCFG2_NTIC 0xFF000000
+#define B_PCH_PCIE_EQCFG2_EMD BIT23
+#define B_PCH_PCIE_EQCFG2_NTSS (BIT22 | BIT21 | BIT20)
+#define B_PCH_PCIE_EQCFG2_PCET (BIT19 | BIT18 | BIT17 | BIT16)
+#define N_PCH_PCIE_EQCFG2_PCET 16
+#define B_PCH_PCIE_EQCFG2_HAPCSB (BIT15 | BIT14 | BIT13 | BIT12)
+#define N_PCH_PCIE_EQCFG2_HAPCSB 12
+#define B_PCH_PCIE_EQCFG2_NTEME BIT11
+#define B_PCH_PCIE_EQCFG2_MPEME BIT10
+#define B_PCH_PCIE_EQCFG2_REWMETM (BIT9 | BIT8)
+#define B_PCH_PCIE_EQCFG2_REWMET 0xFF
+
+#define R_PCH_PCIE_MM 0x480
+#define B_PCH_PCIE_MM_MSST 0xFFFFFF00
+#define N_PCH_PCIE_MM_MSST 8
+#define B_PCH_PCIE_MM_MSS 0xFF
+
+//
+//PCI Express Extended End Point Capability Registers
+//
+
+#define R_PCH_PCIE_LTRECH_OFFSET 0
+#define R_PCH_PCIE_LTRECH_CID 0x0018
+#define R_PCH_PCIE_LTRECH_MSLR_OFFSET 0x04
+#define R_PCH_PCIE_LTRECH_MNSLR_OFFSET 0x06
+
+
+//
+// PCIE PCRs (PID:SPA SPB SPC SPD SPE)
+//
+#define R_PCH_PCR_SPX_PCD 0 ///< Port configuration and disable
+#define B_PCH_PCR_SPX_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///< Port 1 Function Number
+#define B_PCH_PCR_SPX_PCD_RP1CH BIT3 ///< Port 1 config hide
+#define B_PCH_PCR_SPX_PCD_RP2FN (BIT6 | BIT5 | BIT4) ///< Port 2 Function Number
+#define B_PCH_PCR_SPX_PCD_RP2CH BIT7 ///< Port 2 config hide
+#define B_PCH_PCR_SPX_PCD_RP3FN (BIT10 | BIT9 | BIT8) ///< Port 3 Function Number
+#define B_PCH_PCR_SPX_PCD_RP3CH BIT11 ///< Port 3 config hide
+#define B_PCH_PCR_SPX_PCD_RP4FN (BIT14 | BIT13 | BIT12) ///< Port 4 Function Number
+#define B_PCH_PCR_SPX_PCD_RP4CH BIT15 ///< Port 4 config hide
+#define S_PCH_PCR_SPX_PCD_RP_FIELD 4 ///< 4 bits for each RP FN
+#define B_PCH_PCR_SPX_PCD_P1D BIT16 ///< Port 1 disable
+#define B_PCH_PCR_SPX_PCD_P2D BIT17 ///< Port 2 disable
+#define B_PCH_PCR_SPX_PCD_P3D BIT18 ///< Port 3 disable
+#define B_PCH_PCR_SPX_PCD_P4D BIT19 ///< Port 4 disable
+#define B_PCH_PCR_SPX_PCD_SRL BIT31 ///< Secured Register Lock
+
+#define R_PCH_PCR_SPX_PCIEHBP 0x0004 ///< PCI Express high-speed bypass
+#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPME BIT0 ///< PCIe HBP mode enable
+#define B_PCH_PCR_SPX_PCIEHBP_PCIEGMO (BIT2 | BIT1) ///< PCIe gen mode override
+#define B_PCH_PCR_SPX_PCIEHBP_PCIETIL0O BIT3 ///< PCIe transmitter-in-L0 override
+#define B_PCH_PCR_SPX_PCIEHBP_PCIERIL0O BIT4 ///< PCIe receiver-in-L0 override
+#define B_PCH_PCR_SPX_PCIEHBP_PCIELRO BIT5 ///< PCIe link recovery override
+#define B_PCH_PCR_SPX_PCIEHBP_PCIELDO BIT6 ///< PCIe link down override
+#define B_PCH_PCR_SPX_PCIEHBP_PCIESSM BIT7 ///< PCIe SKP suppression mode
+#define B_PCH_PCR_SPX_PCIEHBP_PCIESST BIT8 ///< PCIe suppress SKP transmission
+#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPPS (BIT13 | BIT12) ///< PCIe HBP port select
+#define B_PCH_PCR_SPX_PCIEHBP_CRCSEL (BIT15 | BIT14) ///< CRC select
+#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPCRC 0xFFFF0000 ///< PCIe HBP CRC
+
+
+//
+// ICC PCR (PID: ICC)
+//
+#define R_PCH_PCR_ICC_TMCSRCCLK 0x1000 ///< Timing Control SRC Clock Register
+#define R_PCH_PCR_ICC_TMCSRCCLK2 0x1004 ///< Timing Control SRC Clock Register 2
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPcr.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPcr.h
new file mode 100644
index 0000000000..eea1b11ca8
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPcr.h
@@ -0,0 +1,64 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_PCR_H_
+#define _PCH_REGS_PCR_H_
+
+///
+/// Definition for PCR base address (defined in PchReservedResources.h)
+///
+//#define PCH_PCR_BASE_ADDRESS 0xFD000000
+//#define PCH_PCR_MMIO_SIZE 0x01000000
+/**
+ Definition for PCR address
+ The PCR address is used to the PCR MMIO programming
+**/
+#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | ((UINT8)(Pid) << 16) | (UINT16)(Offset))
+
+/**
+ Definition for SBI PID
+ The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well.
+**/
+typedef enum {
+ PID_DMI = 0xEF,
+ PID_ESPISPI = 0xEE,
+ PID_MODPHY1 = 0xE9,
+ PID_OTG = 0xE5,
+ PID_SPE = 0xE4, // Reserved in SKL PCH LP
+ PID_SPD = 0xE3, // Reserved in SKL PCH LP
+ PID_SPC = 0xE2,
+ PID_SPB = 0xE1,
+ PID_SPA = 0xE0,
+ PID_ICC = 0xDC,
+ PID_DSP = 0xD7,
+ PID_FIA = 0xCF,
+ PID_FIAWM26 = 0x13,
+ PID_USB2 = 0xCA,
+ PID_LPC = 0xC7,
+ PID_SMB = 0xC6,
+ PID_ITSS = 0xC4,
+ PID_RTC = 0xC3,
+ PID_PSF4 = 0xBD,
+ PID_PSF3 = 0xBC,
+ PID_PSF2 = 0xBB,
+ PID_PSF1 = 0xBA,
+ PID_DCI = 0xB8,
+ PID_MMP0 = 0xB0,
+ PID_GPIOCOM0 = 0xAF,
+ PID_GPIOCOM1 = 0xAE,
+ PID_GPIOCOM2 = 0xAD,
+ PID_GPIOCOM3 = 0xAC,
+ PID_GPIOCOM4 = 0xAB,
+ PID_GPIOCOM5 = 0x11,
+ PID_MODPHY2 = 0xA9,
+ PID_MODPHY3 = 0xA8,
+ PID_CSME0 = 0x90, // CSE
+ PID_CSME_PSF = 0x8F, // ME PSF
+ PID_PSTH = 0x89
+} PCH_SBI_PID;
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPmc.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPmc.h
new file mode 100644
index 0000000000..e1d780be14
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPmc.h
@@ -0,0 +1,627 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_PMC_H_
+#define _PCH_REGS_PMC_H_
+
+//
+//PMC Registers (D31:F2)
+//
+#define PCI_DEVICE_NUMBER_PCH_PMC 31
+#define PCI_FUNCTION_NUMBER_PCH_PMC 2
+
+#define V_PCH_PMC_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_PMC_DEVICE_ID 0x9D21
+//
+// LBG Production (PRQ) PMC Device ID
+//
+#define V_PCH_LBG_PROD_PMC_DEVICE_ID 0xA1A1
+//
+// LBG Super SKU (SSX) PMC Device ID
+//
+#define V_PCH_LBG_PMC_DEVICE_ID 0xA221
+
+#define V_PCH_LP_PMC_DEVICE_ID 0x9D21
+#define R_PCH_PMC_PM_DATA_BAR 0x10
+#define B_PCH_PMC_PM_DATA_BAR 0xFFFFC000
+#define R_PCH_PMC_ACPI_BASE 0x40
+#define B_PCH_PMC_ACPI_BASE_BAR 0xFFFC
+#define R_PCH_PMC_ACPI_CNT 0x44
+#define B_PCH_PMC_ACPI_CNT_PWRM_EN BIT8 ///< PWRM enable
+#define B_PCH_PMC_ACPI_CNT_ACPI_EN BIT7 ///< ACPI eanble
+#define B_PCH_PMC_ACPI_CNT_SCIS (BIT2 | BIT1 | BIT0) ///< SCI IRQ select
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ9 0
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ10 1
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ11 2
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ20 4
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ21 5
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ22 6
+#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ23 7
+#define R_PCH_PMC_PWRM_BASE 0x48
+#define B_PCH_PMC_PWRM_BASE_BAR 0xFFFF0000 ///< PWRM must be 64KB alignment to align the source decode.
+#define R_PCH_PMC_GEN_PMCON_A 0xA0
+#define B_PCH_PMC_GEN_PMCON_A_DC_PP_DIS BIT30
+#define B_PCH_PMC_GEN_PMCON_A_DSX_PP_DIS BIT29
+#define B_PCH_PMC_GEN_PMCON_A_AG3_PP_EN BIT28
+#define B_PCH_PMC_GEN_PMCON_A_SX_PP_EN BIT27
+#define B_PCH_PMC_GEN_PMCON_A_DISB BIT23
+#define B_PCH_PMC_GEN_PMCON_A_MEM_SR BIT21
+#define B_PCH_PMC_GEN_PMCON_A_MS4V BIT18
+#define B_PCH_PMC_GEN_PMCON_A_GBL_RST_STS BIT16
+#define B_PCH_PMC_GEN_PMCON_A_ALLOW_PLL_SD_INC0 BIT13
+#define B_PCH_PMC_GEN_PMCON_A_ALLOW_SPXB_CG_INC0 BIT12
+#define B_PCH_PMC_GEN_PMCON_A_BIOS_PCI_EXP_EN BIT10
+#define B_PCH_PMC_GEN_PMCON_A_PWRBTN_LVL BIT9
+#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT7
+#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON BIT6
+#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON BIT5
+#define B_PCH_PMC_GEN_PMCON_A_SMI_LOCK BIT4
+#define B_PCH_PMC_GEN_PMCON_A_ESPI_SMI_LOCK BIT3 ///< ESPI SMI lock
+#define B_PCH_PMC_GEN_PMCON_A_PER_SMI_SEL 0x0003
+#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_64S 0x0000
+#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_32S 0x0001
+#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_16S 0x0002
+#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_8S 0x0003
+#define R_PCH_PMC_GEN_PMCON_B 0xA4
+#define B_PCH_PMC_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18 ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width
+#define B_PCH_PMC_GEN_PMCON_B_ACPI_BASE_LOCK BIT17 ///< Lock ACPI BASE at 0x40, only cleared by reset when set
+#define B_PCH_PMC_GEN_PMCON_B_PM_DATA_BAR_DIS BIT16
+#define B_PCH_PMC_GEN_PMCON_B_PME_B0_S5_DIS BIT15
+#define B_PCH_PMC_GEN_PMCON_B_SUS_PWR_FLR BIT14
+#define B_PCH_PMC_GEN_PMCON_B_WOL_EN_OVRD BIT13
+#define B_PCH_PMC_GEN_PMCON_B_DISABLE_SX_STRETCH BIT12
+#define B_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW 0xC00
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_60US 0x000
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_1MS 0x400
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_50MS 0x800
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_2S 0xC00
+#define B_PCH_PMC_GEN_PMCON_B_HOST_RST_STS BIT9
+#define B_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL 0xC0
+#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_64MS 0xC0
+#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_32MS 0x80
+#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_16MS 0x40
+#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_1_5MS 0x00
+#define B_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW 0x30
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_1S 0x30
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_2S 0x20
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_3S 0x10
+#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_4S 0x00
+#define B_PCH_PMC_GEN_PMCON_B_SLP_S4_ASE BIT3
+#define B_PCH_PMC_GEN_PMCON_B_RTC_PWR_STS BIT2
+#define B_PCH_PMC_GEN_PMCON_B_PWR_FLR BIT1
+#define B_PCH_PMC_GEN_PMCON_B_AFTERG3_EN BIT0
+#define R_PCH_PMC_BM_CX_CNF 0xA8
+#define B_PCH_PMC_BM_CX_CNF_STORAGE_BREAK_EN BIT31
+#define B_PCH_PMC_BM_CX_CNF_PCIE_BREAK_EN BIT30
+#define B_PCH_PMC_BM_CX_CNF_AZ_BREAK_EN BIT24
+#define B_PCH_PMC_BM_CX_CNF_DPSN_BREAK_EN BIT19
+#define B_PCH_PMC_BM_CX_CNF_XHCI_BREAK_EN BIT17
+#define B_PCH_PMC_BM_CX_CNF_SATA3_BREAK_EN BIT16
+#define B_PCH_PMC_BM_CX_CNF_SCRATCHPAD BIT15
+#define B_PCH_PMC_BM_CX_CNF_PHOLD_BM_STS_BLOCK BIT14
+#define B_PCH_PMC_BM_CX_CNF_MASK_CF BIT11
+#define B_PCH_PMC_BM_CX_CNF_BM_STS_ZERO_EN BIT10
+#define B_PCH_PMC_BM_CX_CNF_PM_SYNC_MSG_MODE BIT9
+#define R_PCH_PMC_ETR3 0xAC
+#define B_PCH_PMC_ETR3_CF9LOCK BIT31 ///< CF9h Lockdown
+#define B_PCH_PMC_ETR3_USB_CACHE_DIS BIT21
+#define B_PCH_PMC_ETR3_CF9GR BIT20 ///< CF9h Global Reset
+#define B_PCH_PMC_ETR3_SKIP_HOST_RST_HS BIT19
+#define B_PCH_PMC_ETR3_CWORWRE BIT18
+
+//
+// ACPI and legacy I/O register offsets from ACPIBASE
+//
+#define R_PCH_ACPI_PM1_STS 0x00
+#define S_PCH_ACPI_PM1_STS 2
+#define B_PCH_ACPI_PM1_STS_WAK 0x8000
+#define B_PCH_ACPI_PM1_STS_PRBTNOR 0x0800
+#define B_PCH_ACPI_PM1_STS_RTC 0x0400
+#define B_PCH_ACPI_PM1_STS_PWRBTN 0x0100
+#define B_PCH_ACPI_PM1_STS_GBL 0x0020
+#define B_PCH_ACPI_PM1_STS_BM 0x0010
+#define B_PCH_ACPI_PM1_STS_TMROF 0x0001
+#define N_PCH_ACPI_PM1_STS_WAK 15
+#define N_PCH_ACPI_PM1_STS_PRBTNOR 11
+#define N_PCH_ACPI_PM1_STS_RTC 10
+#define N_PCH_ACPI_PM1_STS_PWRBTN 8
+#define N_PCH_ACPI_PM1_STS_GBL 5
+#define N_PCH_ACPI_PM1_STS_BM 4
+#define N_PCH_ACPI_PM1_STS_TMROF 0
+
+#define R_PCH_ACPI_PM1_EN 0x02
+#define S_PCH_ACPI_PM1_EN 2
+#define B_PCH_ACPI_PM1_EN_RTC 0x0400
+#define B_PCH_ACPI_PM1_EN_PWRBTN 0x0100
+#define B_PCH_ACPI_PM1_EN_GBL 0x0020
+#define B_PCH_ACPI_PM1_EN_TMROF 0x0001
+#define N_PCH_ACPI_PM1_EN_RTC 10
+#define N_PCH_ACPI_PM1_EN_PWRBTN 8
+#define N_PCH_ACPI_PM1_EN_GBL 5
+#define N_PCH_ACPI_PM1_EN_TMROF 0
+
+#define R_PCH_ACPI_PM1_CNT 0x04
+#define S_PCH_ACPI_PM1_CNT 4
+#define B_PCH_ACPI_PM1_CNT_SLP_EN 0x00002000
+#define B_PCH_ACPI_PM1_CNT_SLP_TYP 0x00001C00
+#define V_PCH_ACPI_PM1_CNT_S0 0x00000000
+#define V_PCH_ACPI_PM1_CNT_S1 0x00000400
+#define V_PCH_ACPI_PM1_CNT_S3 0x00001400
+#define V_PCH_ACPI_PM1_CNT_S4 0x00001800
+#define V_PCH_ACPI_PM1_CNT_S5 0x00001C00
+#define B_PCH_ACPI_PM1_CNT_GBL_RLS 0x00000004
+#define B_PCH_ACPI_PM1_CNT_BM_RLD 0x00000002
+#define B_PCH_ACPI_PM1_CNT_SCI_EN 0x00000001
+
+#define R_PCH_ACPI_PM1_TMR 0x08
+#define V_PCH_ACPI_TMR_FREQUENCY 3579545
+#define B_PCH_ACPI_PM1_TMR_VAL 0xFFFFFF
+#define V_PCH_ACPI_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow
+
+#define R_PCH_SMI_EN 0x30
+#define S_PCH_SMI_EN 4
+#define B_PCH_SMI_EN_LEGACY_USB3 BIT31
+#define B_PCH_SMI_EN_GPIO_UNLOCK_SMI BIT27
+#define B_PCH_SMI_EN_LEGACY_USB2 BIT17
+#define B_PCH_SMI_EN_PERIODIC BIT14
+#define B_PCH_SMI_EN_TCO BIT13
+#define B_PCH_SMI_EN_MCSMI BIT11
+#define B_PCH_SMI_EN_BIOS_RLS BIT7
+#define B_PCH_SMI_EN_SWSMI_TMR BIT6
+#define B_PCH_SMI_EN_APMC BIT5
+#define B_PCH_SMI_EN_ON_SLP_EN BIT4
+#define B_PCH_SMI_EN_LEGACY_USB BIT3
+#define B_PCH_SMI_EN_BIOS BIT2
+#define B_PCH_SMI_EN_EOS BIT1
+#define B_PCH_SMI_EN_GBL_SMI BIT0
+#define N_PCH_SMI_EN_LEGACY_USB3 31
+#define N_PCH_SMI_EN_ESPI 28
+#define N_PCH_SMI_EN_GPIO_UNLOCK 27
+#define N_PCH_SMI_EN_INTEL_USB2 18
+#define N_PCH_SMI_EN_LEGACY_USB2 17
+#define N_PCH_SMI_EN_PERIODIC 14
+#define N_PCH_SMI_EN_TCO 13
+#define N_PCH_SMI_EN_MCSMI 11
+#define N_PCH_SMI_EN_BIOS_RLS 7
+#define N_PCH_SMI_EN_SWSMI_TMR 6
+#define N_PCH_SMI_EN_APMC 5
+#define N_PCH_SMI_EN_ON_SLP_EN 4
+#define N_PCH_SMI_EN_LEGACY_USB 3
+#define N_PCH_SMI_EN_BIOS 2
+#define N_PCH_SMI_EN_EOS 1
+#define N_PCH_SMI_EN_GBL_SMI 0
+
+#define R_PCH_SMI_STS 0x34
+#define S_PCH_SMI_STS 4
+#define B_PCH_SMI_STS_LEGACY_USB3 BIT31
+#define B_PCH_SMI_STS_GPIO_UNLOCK BIT27
+#define B_PCH_SMI_STS_SPI BIT26
+#define B_PCH_SMI_STS_MONITOR BIT21
+#define B_PCH_SMI_STS_PCI_EXP BIT20
+#define B_PCH_SMI_STS_PATCH BIT19
+#define B_PCH_SMI_STS_INTEL_USB2 BIT18
+#define B_PCH_SMI_STS_LEGACY_USB2 BIT17
+#define B_PCH_SMI_STS_SMBUS BIT16
+#define B_PCH_SMI_STS_SERIRQ BIT15
+#define B_PCH_SMI_STS_PERIODIC BIT14
+#define B_PCH_SMI_STS_TCO BIT13
+#define B_PCH_SMI_STS_DEVMON BIT12
+#define B_PCH_SMI_STS_MCSMI BIT11
+#define B_PCH_SMI_STS_GPIO_SMI BIT10
+#define B_PCH_SMI_STS_GPE0 BIT9
+#define B_PCH_SMI_STS_PM1_STS_REG BIT8
+#define B_PCH_SMI_STS_SWSMI_TMR BIT6
+#define B_PCH_SMI_STS_APM BIT5
+#define B_PCH_SMI_STS_ON_SLP_EN BIT4
+#define B_PCH_SMI_STS_LEGACY_USB BIT3
+#define B_PCH_SMI_STS_BIOS BIT2
+#define N_PCH_SMI_STS_LEGACY_USB3 31
+#define N_PCH_SMI_STS_ESPI 28
+#define N_PCH_SMI_STS_GPIO_UNLOCK 27
+#define N_PCH_SMI_STS_SPI 26
+#define N_PCH_SMI_STS_MONITOR 21
+#define N_PCH_SMI_STS_PCI_EXP 20
+#define N_PCH_SMI_STS_PATCH 19
+#define N_PCH_SMI_STS_INTEL_USB2 18
+#define N_PCH_SMI_STS_LEGACY_USB2 17
+#define N_PCH_SMI_STS_SMBUS 16
+#define N_PCH_SMI_STS_SERIRQ 15
+#define N_PCH_SMI_STS_PERIODIC 14
+#define N_PCH_SMI_STS_TCO 13
+#define N_PCH_SMI_STS_DEVMON 12
+#define N_PCH_SMI_STS_MCSMI 11
+#define N_PCH_SMI_STS_GPIO_SMI 10
+#define N_PCH_SMI_STS_GPE0 9
+#define N_PCH_SMI_STS_PM1_STS_REG 8
+#define N_PCH_SMI_STS_SWSMI_TMR 6
+#define N_PCH_SMI_STS_APM 5
+#define N_PCH_SMI_STS_ON_SLP_EN 4
+#define N_PCH_SMI_STS_LEGACY_USB 3
+#define N_PCH_SMI_STS_BIOS 2
+
+#define R_PCH_ACPI_GPE_CNTL 0x40
+#define B_PCH_ACPI_GPE_CNTL_SWGPE_CTRL BIT17
+
+#define R_PCH_DEVACT_STS 0x44
+#define S_PCH_DEVACT_STS 2
+#define B_PCH_DEVACT_STS_MASK 0x13E1
+#define B_PCH_DEVACT_STS_KBC 0x1000
+#define B_PCH_DEVACT_STS_PIRQDH 0x0200
+#define B_PCH_DEVACT_STS_PIRQCG 0x0100
+#define B_PCH_DEVACT_STS_PIRQBF 0x0080
+#define B_PCH_DEVACT_STS_PIRQAE 0x0040
+#define B_PCH_DEVACT_STS_D0_TRP 0x0001
+#define N_PCH_DEVACT_STS_KBC 12
+#define N_PCH_DEVACT_STS_PIRQDH 9
+#define N_PCH_DEVACT_STS_PIRQCG 8
+#define N_PCH_DEVACT_STS_PIRQBF 7
+#define N_PCH_DEVACT_STS_PIRQAE 6
+
+#define R_PCH_ACPI_PM2_CNT 0x50
+#define B_PCH_ACPI_PM2_CNT_ARB_DIS 0x01
+
+#define R_PCH_OC_WDT_CTL 0x54
+#define B_PCH_OC_WDT_CTL_RLD BIT31
+#define B_PCH_OC_WDT_CTL_ICCSURV_STS BIT25
+#define B_PCH_OC_WDT_CTL_NO_ICCSURV_STS BIT24
+#define B_PCH_OC_WDT_CTL_FORCE_ALL BIT15
+#define B_PCH_OC_WDT_CTL_EN BIT14
+#define B_PCH_OC_WDT_CTL_ICCSURV BIT13
+#define B_PCH_OC_WDT_CTL_LCK BIT12
+#define B_PCH_OC_WDT_CTL_TOV_MASK 0x3FF
+#define B_PCH_OC_WDT_CTL_FAILURE_STS BIT23
+#define B_PCH_OC_WDT_CTL_UNXP_RESET_STS BIT22
+#define B_PCH_OC_WDT_CTL_AFTER_POST 0x3F0000
+#define V_PCH_OC_WDT_CTL_STATUS_FAILURE 1
+#define V_PCH_OC_WDT_CTL_STATUS_OK 0
+
+#define R_PCH_ACPI_GPE0_STS_127_96 0x8C
+#define S_PCH_ACPI_GPE0_STS_127_96 4
+#define B_PCH_ACPI_GPE0_STS_127_96_WADT BIT18
+#define B_PCH_ACPI_GPE0_STS_127_96_LAN_WAKE BIT16
+#define B_PCH_ACPI_GPE0_STS_127_96_PME_B0 BIT13
+#define B_PCH_ACPI_GPE0_STS_127_96_ME_SCI BIT12
+#define B_PCH_ACPI_GPE0_STS_127_96_PME BIT11
+#define B_PCH_ACPI_GPE0_STS_127_96_BATLOW BIT10
+#define B_PCH_ACPI_GPE0_STS_127_96_PCI_EXP BIT9
+#define B_PCH_ACPI_GPE0_STS_127_96_RI BIT8
+#define B_PCH_ACPI_GPE0_STS_127_96_SMB_WAK BIT7
+#define B_PCH_ACPI_GPE0_STS_127_96_TC0SCI BIT6
+#define B_PCH_ACPI_GPE0_STS_127_96_SWGPE BIT2
+#define B_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG BIT1
+#define N_PCH_ACPI_GPE0_STS_127_96_PME_B0 13
+#define N_PCH_ACPI_GPE0_STS_127_96_PME 11
+#define N_PCH_ACPI_GPE0_STS_127_96_BATLOW 10
+#define N_PCH_ACPI_GPE0_STS_127_96_PCI_EXP 9
+#define N_PCH_ACPI_GPE0_STS_127_96_RI 8
+#define N_PCH_ACPI_GPE0_STS_127_96_SMB_WAK 7
+#define N_PCH_ACPI_GPE0_STS_127_96_TC0SCI 6
+#define N_PCH_ACPI_GPE0_STS_127_96_SWGPE 2
+#define N_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG 1
+
+#define R_PCH_ACPI_GPE0_EN_31_0 0x90
+#define R_PCH_ACPI_GPE0_EN_63_31 0x94
+#define R_PCH_ACPI_GPE0_EN_94_64 0x98
+#define R_PCH_ACPI_GPE0_EN_127_96 0x9C
+#define S_PCH_ACPI_GPE0_EN_127_96 4
+#define B_PCH_ACPI_GPE0_EN_127_96_WADT BIT18
+#define B_PCH_ACPI_GPE0_EN_127_96_LAN_WAKE BIT16
+#define B_PCH_ACPI_GPE0_EN_127_96_PME_B0 BIT13
+#define B_PCH_ACPI_GPE0_EN_127_96_ME_SCI BIT12
+#define B_PCH_ACPI_GPE0_EN_127_96_PME BIT11
+#define B_PCH_ACPI_GPE0_EN_127_96_BATLOW BIT10
+#define B_PCH_ACPI_GPE0_EN_127_96_PCI_EXP BIT9
+#define B_PCH_ACPI_GPE0_EN_127_96_RI BIT8
+#define B_PCH_ACPI_GPE0_EN_127_96_TC0SCI BIT6
+#define B_PCH_ACPI_GPE0_EN_127_96_SWGPE BIT2
+#define B_PCH_ACPI_GPE0_EN_127_96_HOT_PLUG BIT1
+#define N_PCH_ACPI_GPE0_EN_127_96_PME_B0 13
+#define N_PCH_ACPI_GPE0_EN_127_96_USB3 12
+#define N_PCH_ACPI_GPE0_EN_127_96_PME 11
+#define N_PCH_ACPI_GPE0_EN_127_96_BATLOW 10
+#define N_PCH_ACPI_GPE0_EN_127_96_PCI_EXP 9
+#define N_PCH_ACPI_GPE0_EN_127_96_RI 8
+#define N_PCH_ACPI_GPE0_EN_127_96_TC0SCI 6
+#define N_PCH_ACPI_GPE0_EN_127_96_SWGPE 2
+#define N_PCH_ACPI_GPE0_EN_127_96_HOT_PLUG 1
+
+
+//
+// TCO register I/O map
+//
+#define R_PCH_TCO_RLD 0x0
+#define R_PCH_TCO_DAT_IN 0x2
+#define R_PCH_TCO_DAT_OUT 0x3
+#define R_PCH_TCO1_STS 0x04
+#define S_PCH_TCO1_STS 2
+#define B_PCH_TCO1_STS_DMISERR BIT12
+#define B_PCH_TCO1_STS_DMISMI BIT10
+#define B_PCH_TCO1_STS_DMISCI BIT9
+#define B_PCH_TCO1_STS_BIOSWR BIT8
+#define B_PCH_TCO1_STS_NEWCENTURY BIT7
+#define B_PCH_TCO1_STS_TIMEOUT BIT3
+#define B_PCH_TCO1_STS_TCO_INT BIT2
+#define B_PCH_TCO1_STS_SW_TCO_SMI BIT1
+#define B_PCH_TCO1_STS_NMI2SMI BIT0
+#define N_PCH_TCO1_STS_DMISMI 10
+#define N_PCH_TCO1_STS_BIOSWR 8
+#define N_PCH_TCO1_STS_NEWCENTURY 7
+#define N_PCH_TCO1_STS_TIMEOUT 3
+#define N_PCH_TCO1_STS_SW_TCO_SMI 1
+#define N_PCH_TCO1_STS_NMI2SMI 0
+
+#define R_PCH_TCO2_STS 0x06
+#define S_PCH_TCO2_STS 2
+#define B_PCH_TCO2_STS_SMLINK_SLV_SMI BIT4
+#define B_PCH_TCO2_STS_BAD_BIOS BIT3
+#define B_PCH_TCO2_STS_BOOT BIT2
+#define B_PCH_TCO2_STS_SECOND_TO BIT1
+#define B_PCH_TCO2_STS_INTRD_DET BIT0
+#define N_PCH_TCO2_STS_INTRD_DET 0
+
+#define R_PCH_TCO1_CNT 0x08
+#define S_PCH_TCO1_CNT 2
+#define B_PCH_TCO_CNT_LOCK BIT12
+#define B_PCH_TCO_CNT_TMR_HLT BIT11
+#define B_PCH_TCO_CNT_NMI2SMI_EN BIT9
+#define B_PCH_TCO_CNT_NMI_NOW BIT8
+#define N_PCH_TCO_CNT_NMI2SMI_EN 9
+
+#define R_PCH_TCO2_CNT 0x0A
+#define S_PCH_TCO2_CNT 2
+#define B_PCH_TCO2_CNT_OS_POLICY 0x0030
+#define B_PCH_TCO2_CNT_GPI11_ALERT_DISABLE 0x0008
+#define B_PCH_TCO2_CNT_INTRD_SEL 0x0006
+#define N_PCH_TCO2_CNT_INTRD_SEL 2
+
+#define R_PCH_TCO_MESSAGE1 0x0C
+#define R_PCH_TCO_MESSAGE2 0x0D
+#define R_PCH_TCO_WDCNT 0x0E
+#define R_PCH_TCO_SW_IRQ_GEN 0x10
+#define B_PCH_TCO_IRQ12_CAUSE BIT1
+#define B_PCH_TCO_IRQ1_CAUSE BIT0
+#define R_PCH_TCO_TMR 0x12
+
+//
+// PWRM Registers
+//
+#define R_PCH_WADT_AC 0x0 ///< Wake Alarm Device Timer: AC
+#define R_PCH_WADT_DC 0x4 ///< Wake Alarm Device Timer: DC
+#define R_PCH_WADT_EXP_AC 0x8 ///< Wake Alarm Device Expired Timer: AC
+#define R_PCH_WADT_EXP_DC 0xC ///< Wake Alarm Device Expired Timer: DC
+#define R_PCH_PWRM_PRSTS 0x10 ///< Power and Reset Status
+#define B_PCH_PWRM_PRSTS_VE_WD_TMR_STS BIT7 ///< VE Watchdog Timer Status
+#define B_PCH_PWRM_PRSTS_WOL_OVR_WK_STS BIT5
+#define B_PCH_PWRM_PRSTS_FIELD_1 BIT4
+#define B_PCH_PWRM_PRSTS_ME_WAKE_STS BIT0
+#define R_PCH_PWRM_14 0x14
+#define R_PCH_PWRM_CFG 0x18 ///< Power Management Configuration
+#define B_PCH_PWRM_CFG_ALLOW_24_OSC_SD BIT29 ///< Allow 24MHz Crystal Oscillator Shutdown
+#define B_PCH_PWRM_CFG_ALLOW_USB2_CORE_PG BIT25 ///< Allow USB2 Core Power Gating
+#define B_PCH_PWRM_CFG_RTC_DS_WAKE_DIS BIT21 ///< RTC Wake from Deep S4/S5 Disable
+#define B_PCH_PWRM_CFG_SSMAW_MASK (BIT19 | BIT18) ///< SLP_SUS# Min Assertion Width
+#define V_PCH_PWRM_CFG_SSMAW_4S (BIT19 | BIT18) ///< 4 seconds
+#define V_PCH_PWRM_CFG_SSMAW_1S BIT19 ///< 1 second
+#define V_PCH_PWRM_CFG_SSMAW_0_5S BIT18 ///< 0.5 second (500ms)
+#define V_PCH_PWRM_CFG_SSMAW_0S 0 ///< 0 second
+#define B_PCH_PWRM_CFG_SAMAW_MASK (BIT17 | BIT16) ///< SLP_A# Min Assertion Width
+#define V_PCH_PWRM_CFG_SAMAW_2S (BIT17 | BIT16) ///< 2 seconds
+#define V_PCH_PWRM_CFG_SAMAW_98ms BIT17 ///< 98ms
+#define V_PCH_PWRM_CFG_SAMAW_4S BIT16 ///< 4 seconds
+#define V_PCH_PWRM_CFG_SAMAW_0S 0 ///< 0 second
+#define B_PCH_PWRM_CFG_RPCD_MASK (BIT9 | BIT8) ///< Reset Power Cycle Duration
+#define V_PCH_PWRM_CFG_RPCD_1S (BIT9 | BIT8) ///< 1-2 seconds
+#define V_PCH_PWRM_CFG_RPCD_2S BIT9 ///< 2-3 seconds
+#define V_PCH_PWRM_CFG_RPCD_3S BIT8 ///< 3-4 seconds
+#define V_PCH_PWRM_CFG_RPCD_4S 0 ///< 4-5 seconds (Default)
+#define R_PCH_PWRM_MTPMC 0x20 ///< Message to PMC
+#define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_0_15 0xE ///< Command to override lanes 0-15 power gating
+#define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_16_31 0xF ///< Command to override lanes 16-31 power gating
+#define B_PCH_PWRM_MTPMC_PG_CMD_DATA 0xFFFF0000 ///< Data part of PowerGate Message to PMC
+#define N_PCH_PWRM_MTPMC_PG_CMD_DATA 16
+#define R_PCH_PWRM_S3_PWRGATE_POL 0x28 ///< S3 Power Gating Policies
+#define B_PCH_PWRM_S3DC_GATE_SUS BIT1 ///< Deep S3 Enable in DC Mode
+#define B_PCH_PWRM_S3AC_GATE_SUS BIT0 ///< Deep S3 Enable in AC Mode
+#define R_PCH_PWRM_S4_PWRGATE_POL 0x2C ///< Deep S4 Power Policies
+#define B_PCH_PWRM_S4DC_GATE_SUS BIT1 ///< Deep S4 Enable in DC Mode
+#define B_PCH_PWRM_S4AC_GATE_SUS BIT0 ///< Deep S4 Enable in AC Mode
+#define R_PCH_PWRM_S5_PWRGATE_POL 0x30 ///< Deep S5 Power Policies
+#define B_PCH_PWRM_S5DC_GATE_SUS BIT15 ///< Deep S5 Enable in DC Mode
+#define B_PCH_PWRM_S5AC_GATE_SUS BIT14 ///< Deep S5 Enable in AC Mode
+#define R_PCH_PWRM_DSX_CFG 0x34 ///< Deep SX Configuration
+#define B_PCH_PWRM_DSX_CFG_WAKE_PIN_DSX_EN BIT2 ///< WAKE# Pin DeepSx Enable
+#define B_PCH_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS BIT1 ///< AC_PRESENT pin pulldown in DeepSx disable
+#define B_PCH_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 ///< LAN_WAKE Pin DeepSx Enable
+#define R_PCH_PWRM_CFG2 0x3C ///< Power Management Configuration Reg 2
+#define B_PCH_PWRM_CFG2_PBOP (BIT31 | BIT30 | BIT29) ///< Power Button Override Period (PBOP)
+#define N_PCH_PWRM_CFG2_PBOP 29 ///< Power Button Override Period (PBOP)
+#define B_PCH_PWRM_CFG2_PB_DIS BIT28 ///< Power Button Native Mode Disable (PB_DIS)
+#define B_PCH_PWRM_CFG2_DRAM_RESET_CTL BIT26 ///< DRAM RESET# control
+#define R_PCH_PWRM_EN_SN_SLOW_RING 0x48 ///< Enable Snoop Request to SLOW_RING
+#define R_PCH_PWRM_EN_SN_SLOW_RING2 0x4C ///< Enable Snoop Request to SLOW_RING 2nd Reg
+#define R_PCH_PWRM_EN_SN_SA 0x50 ///< Enable Snoop Request to SA
+#define R_PCH_PWRM_EN_SN_SA2 0x54 ///< Enable Snoop Request to SA 2nd Reg
+#define R_PCH_PWRM_EN_SN_SLOW_RING_CF 0x58 ///< Enable Snoop Request to SLOW_RING_CF
+#define R_PCH_PWRM_EN_NS_SA 0x68 ///< Enable Non-Snoop Request to SA
+#define R_PCH_PWRM_EN_CW_SLOW_RING 0x80 ///< Enable Clock Wake to SLOW_RING
+#define R_PCH_PWRM_EN_CW_SLOW_RING2 0x84 ///< Enable Clock Wake to SLOW_RING 2nd Reg
+#define R_PCH_PWRM_EN_CW_SA 0x88 ///< Enable Clock Wake to SA
+#define R_PCH_PWRM_EN_CW_SA2 0x8C ///< Enable Clock Wake to SA 2nd Reg
+#define R_PCH_PWRM_EN_CW_SLOW_RING_CF 0x98 ///< Enable Clock Wake to SLOW_RING_CF
+#define R_PCH_PWRM_EN_PA_SLOW_RING 0xA8 ///< Enable Pegged Active to SLOW_RING
+#define R_PCH_PWRM_EN_PA_SLOW_RING2 0xAC ///< Enable Pegged Active to SLOW_RING 2nd Reg
+#define R_PCH_PWRM_EN_PA_SA 0xB0 ///< Enable Pegged Active to SA
+#define R_PCH_PWRM_EN_PA_SA2 0xB4 ///< Enable Pegged Active to SA 2nd Reg
+#define R_PCH_PWRM_EN_MISC_EVENT 0xC0 ///< Enable Misc PM_SYNC Events
+#define R_PCH_PWRM_PMSYNC_TPR_CONFIG 0xC4
+#define B_PCH_PWRM_PMSYNC_TPR_CONFIG_LOCK BIT31
+#define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_EN BIT26
+#define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE (BIT25 | BIT24)
+#define N_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE 24
+#define V_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE_1 1
+#define R_PCH_PWRM_PMSYNC_MISC_CFG 0xC8
+#define B_PCH_PWRM_PMSYNC_PM_SYNC_LOCK BIT15 ///< PM_SYNC Configuration Lock
+#define B_PCH_PWRM_PMSYNC_GPIO_D_SEL BIT11
+#define B_PCH_PWRM_PMSYNC_GPIO_C_SEL BIT10
+#define PM_SYNC_GPIO_B 0
+#define R_PCH_PWRM_PM_SYNC_STATE_HYS 0xD0 ///< PM_SYNC State Hysteresis
+#define R_PCH_PWRM_PM_SYNC_MODE 0xD4 ///< PM_SYNC Pin Mode
+#define R_PCH_PWRM_CFG3 0xE0 ///< Power Management Configuration Reg 3
+#define B_PCH_PWRM_CFG3_DSX_WLAN_PP_EN BIT16 ///< Deep-Sx WLAN Phy Power Enable
+#define B_PCH_PWRM_CFG3_HOST_WLAN_PP_EN BIT17 ///< Host Wireless LAN Phy Power Enable
+#define B_PCH_PWRM_CFG3_PWRG_LOCK BIT2 ///< Lock power gating override messages
+#define R_PCH_PWRM_PM_DOWN_PPB_CFG 0xE4 ///< PM_DOWN PCH_POWER_BUDGET CONFIGURATION
+#define R_PCH_PWRM_CFG4 0xE8 ///< Power Management Configuration Reg 4
+#define B_PCH_PWRM_CFG4_U2_PHY_PG_EN BIT30 ///< USB2 PHY SUS Well Power Gating Enable
+#define B_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR (0x000001FF) ///< CPU I/O VR Ramp Duration, [8:0]
+#define N_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR 0
+#define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_70US 0x007
+#define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_240US 0x018
+#define R_PCH_PWRM_CPU_EPOC 0xEC
+#define R_PCH_PWRM_VR_MISC_CTL 0x100
+#define B_PCH_PWRM_VR_MISC_CTL_VIDSOVEN BIT3
+#define R_PCH_PWRM_GPIO_CFG 0x120
+#define B_PCH_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8)
+#define N_PCH_PWRM_GPIO_CFG_GPE0_DW2 8
+#define B_PCH_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 | BIT5 | BIT4)
+#define N_PCH_PWRM_GPIO_CFG_GPE0_DW1 4
+#define B_PCH_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0)
+#define N_PCH_PWRM_GPIO_CFG_GPE0_DW0 0
+#define R_PCH_PWRM_PM_SYNC_MODE_C0 0xF4 ///< PM_SYNC Pin Mode in C0
+#define R_PCH_PWRM_124 0x124
+#define R_PCH_PWRM_HPR_CAUSE0 0x12C ///< Host partition reset causes
+#define B_PCH_PWRM_HPR_CAUSE0_GBL_TO_HOST BIT15 ///< Global reset converted to host reset
+#define R_PCH_PWRM_MODPHY_PM_CFG1 0x200
+#define R_PCH_PWRM_MODPHY_PM_CFG2 0x204 ///< ModPHY Power Management Configuration Reg 2
+#define B_PCH_PWRM_MODPHY_PM_CFG2_MLSPDDGE BIT30 ///< ModPHY Lane SUS Power Domain Dynamic Gating Enable
+#define B_PCH_PWRM_MODPHY_PM_CFG2_EMFC BIT29 ///< Enable ModPHY FET Control
+#define B_PCH_PWRM_MODPHY_PM_CFG2_EFRT (BIT28 | BIT27 | BIT26 | BIT25 | BIT24) ///< External FET Ramp Time
+#define N_PCH_PWRM_MODPHY_PM_CFG2_EFRT 24
+#define V_PCH_PWRM_MODPHY_PM_CFG2_EFRT_200US 0x0A
+#define B_PCH_PWRM_MODPHY_PM_CFG2_ASLOR_UFS BIT16 ///< UFS ModPHY SPD SPD Override
+#define R_PCH_PWRM_MODPHY_PM_CFG3 0x208 ///< ModPHY Power Management Configuration Reg 3
+#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_UFS BIT16 ///< UFS ModPHY SPD RT Request
+#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XDCI BIT15 ///< xDCI ModPHY SPD RT Request
+#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XHCI BIT14 ///< xHCI ModPHY SPD RT Request
+#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_GBE BIT13 ///< GbE ModPHY SPD RT Request
+#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_SATA BIT12 ///< SATA ModPHY SPD RT Request
+#define R_PCH_PWRM_30C 0x30C
+#define R_PCH_PWRM_OBFF_CFG 0x314 ///< OBFF Configuration
+#define R_PCH_PWRM_31C 0x31C
+#define R_PCH_PWRM_CPPM_MISC_CFG 0x320 ///< CPPM Miscellaneous Configuration
+#define R_PCH_PWRM_CPPM_CG_POL1A 0x324 ///< CPPM Clock Gating Policy Reg 1
+#define R_PCH_PWRM_CPPM_CG_POL2A 0x340 ///< CPPM Clock Gating Policy Reg 3
+#define R_PCH_PWRM_34C 0x34C
+#define R_PCH_PWRM_CPPM_CG_POL3A 0x3A8 ///< CPPM Clock Gating Policy Reg 5
+#define B_PCH_PWRM_CPPM_CG_POLXA_CPPM_GX_QUAL BIT30 ///< CPPM Shutdown Qualifier Enable for Clock Source Group X
+#define B_PCH_PWRM_CPPM_CG_POLXA_LTR_GX_THRESH (0x000001FF) ///< LTR Threshold for Clock Source Group X, [8:0]
+#define R_PCH_PWRM_3D0 0x3D0
+#define R_PCH_PWRM_CPPM_MPG_POL1A 0x3E0 ///< CPPM ModPHY Gating Policy Reg 1A
+#define B_PCH_PWRM_CPPM_MPG_POL1A_CPPM_MODPHY_QUAL BIT30 ///< CPPM Shutdown Qualifier Enable for ModPHY
+#define B_PCH_PWRM_CPPM_MPG_POL1A_LT_MODPHY_SEL BIT29 ///< ASLT/PLT Selection for ModPHY
+#define B_PCH_PWRM_CPPM_MPG_POL1A_LTR_MODPHY_THRESH (0x000001FF) ///< LTR Threshold for ModPHY, [8:0]
+#define R_PCH_PWRM_CS_SD_CTL1 0x3E8 ///< Clock Source Shutdown Control Reg 1
+#define B_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG (BIT22 | BIT21 | BIT20) ///< Clock Source 5 Control Configuration
+#define N_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG 20
+#define B_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG (BIT2 | BIT1 | BIT0) ///< Clock Source 1 Control Configuration
+#define N_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG 0
+#define R_PCH_PWRM_CS_SD_CTL2 0x3EC ///< Clock Source Shutdown Control Reg 2
+#define R_PCH_PWRM_HSWPGCR1 0x5D0
+#define B_PCH_PWRM_SW_PG_CTRL_LOCK BIT31
+#define B_PCH_PWRM_DFX_SW_PG_CTRL BIT0
+#define R_PCH_PWRM_600 0x600
+#define R_PCH_PWRM_604 0x604
+#define R_PCH_PWRM_ST_PG_FDIS_PMC_1 0x620 ///< Static PG Related Function Disable Register 1
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Static Function Disable Lock (ST_FDIS_LK)
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_CAM_FDIS_PMC BIT6 ///< Camera Function Disable (PMC Version) (CAM_FDIS_PMC)
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_ISH_FDIS_PMC BIT5 ///< SH Function Disable (PMC Version) (ISH_FDIS_PMC)
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_GBE_FDIS_PMC BIT0 ///< GBE Function Disable (PMC Version) (GBE_FDIS_PMC)
+#define R_PCH_PWRM_ST_PG_FDIS_PMC_2 0x624 ///< Static Function Disable Control Register 2
+#define V_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_FDIS_PMC 0x7FF ///< Static Function Disable Control Register 2
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI1_FDIS_PMC BIT10 ///< SerialIo Controller GSPI Device 1 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI0_FDIS_PMC BIT9 ///< SerialIo Controller GSPI Device 0 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART2_FDIS_PMC BIT8 ///< SerialIo Controller UART Device 2 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART1_FDIS_PMC BIT7 ///< SerialIo Controller UART Device 1 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART0_FDIS_PMC BIT6 ///< SerialIo Controller UART Device 0 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C5_FDIS_PMC BIT5 ///< SerialIo Controller I2C Device 5 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C4_FDIS_PMC BIT4 ///< SerialIo Controller I2C Device 4 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C3_FDIS_PMC BIT3 ///< SerialIo Controller I2C Device 3 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C2_FDIS_PMC BIT2 ///< SerialIo Controller I2C Device 2 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C1_FDIS_PMC BIT1 ///< SerialIo Controller I2C Device 1 Function Disable
+#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C0_FDIS_PMC BIT0 ///< SerialIo Controller I2C Device 0 Function Disable
+#define R_PCH_PWRM_NST_PG_FDIS_1 0x628
+#define B_PCH_PWRM_NST_PG_FDIS_1_SCC_FDIS_PMC BIT25 ///< SCC Function Disable. This is only avaiable in B0 onward.
+#define B_PCH_PWRM_NST_PG_FDIS_1_XDCI_FDIS_PMC BIT24 ///< XDCI Function Disable. This is only avaiable in B0 onward.
+#define B_PCH_PWRM_NST_PG_FDIS_1_ADSP_FDIS_PMC BIT23 ///< ADSP Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_SATA_FDIS_PMC BIT22 ///< SATA Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C3_FDIS_PMC BIT13 ///< PCIe Controller C Port 3 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C2_FDIS_PMC BIT12 ///< PCIe Controller C Port 2 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C1_FDIS_PMC BIT11 ///< PCIe Controller C Port 1 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C0_FDIS_PMC BIT10 ///< PCIe Controller C Port 0 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B3_FDIS_PMC BIT9 ///< PCIe Controller B Port 3 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B2_FDIS_PMC BIT8 ///< PCIe Controller B Port 2 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B1_FDIS_PMC BIT7 ///< PCIe Controller B Port 1 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B0_FDIS_PMC BIT6 ///< PCIe Controller B Port 0 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A3_FDIS_PMC BIT5 ///< PCIe Controller A Port 3 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A2_FDIS_PMC BIT4 ///< PCIe Controller A Port 2 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A1_FDIS_PMC BIT3 ///< PCIe Controller A Port 1 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A0_FDIS_PMC BIT2 ///< PCIe Controller A Port 0 Function Disable
+#define B_PCH_PWRM_NST_PG_FDIS_1_XHCI_FDIS_PMC BIT0 ///< XHCI Function Disable
+#define R_PCH_PWRM_FUSE_DIS_RD_1 0x640 ///< Fuse Disable Read 1 Register
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E3_FUSE_DIS BIT21 ///< PCIe Controller E Port 3 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E2_FUSE_DIS BIT20 ///< PCIe Controller E Port 2 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E1_FUSE_DIS BIT19 ///< PCIe Controller E Port 1 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E0_FUSE_DIS BIT18 ///< PCIe Controller E Port 0 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D3_FUSE_DIS BIT17 ///< PCIe Controller D Port 3 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D2_FUSE_DIS BIT16 ///< PCIe Controller D Port 2 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D1_FUSE_DIS BIT15 ///< PCIe Controller D Port 1 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D0_FUSE_DIS BIT14 ///< PCIe Controller D Port 0 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C3_FUSE_DIS BIT13 ///< PCIe Controller C Port 3 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C2_FUSE_DIS BIT12 ///< PCIe Controller C Port 2 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C1_FUSE_DIS BIT11 ///< PCIe Controller C Port 1 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C0_FUSE_DIS BIT10 ///< PCIe Controller C Port 0 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B3_FUSE_DIS BIT9 ///< PCIe Controller B Port 3 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B2_FUSE_DIS BIT8 ///< PCIe Controller B Port 2 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B1_FUSE_DIS BIT7 ///< PCIe Controller B Port 1 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B0_FUSE_DIS BIT6 ///< PCIe Controller B Port 0 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A3_FUSE_DIS BIT5 ///< PCIe Controller A Port 3 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A2_FUSE_DIS BIT4 ///< PCIe Controller A Port 2 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A1_FUSE_DIS BIT3 ///< PCIe Controller A Port 1 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A0_FUSE_DIS BIT2 ///< PCIe Controller A Port 0 Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_1_XHCI_FUSE_DIS BIT0 ///< XHCI Fuse Disable
+#define R_PCH_PWRM_FUSE_DIS_RD_2 0x644 ///< Fuse Disable Read 2 Register
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SPC_SS_DIS BIT25 ///< SPC Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SPB_SS_DIS BIT24 ///< SPB Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SPA_SS_DIS BIT23 ///< SPA Fuse Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_PSTH_FUSE_SS_DIS BIT21 ///< PSTH Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_DMI_FUSE_SS_DIS BIT20 ///< DMI Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS BIT19 ///< OTG Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_XHCI_SS_DIS BIT18 ///< XHCI Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_FIA_FUSE_SS_DIS BIT17 ///< FIA Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_DSP_FUSE_SS_DIS BIT16 ///< DSP Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS BIT15 ///< SATA Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_ICC_FUSE_SS_DIS BIT14 ///< ICC Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_LPC_FUSE_SS_DIS BIT13 ///< LPC Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_RTC_FUSE_SS_DIS BIT12 ///< RTC Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_P2S_FUSE_SS_DIS BIT11 ///< P2S Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_TRSB_FUSE_SS_DIS BIT10 ///< TRSB Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SMB_FUSE_SS_DIS BIT9 ///< SMB Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_ITSS_FUSE_SS_DIS BIT8 ///< ITSS Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SERIALIO_FUSE_SS_DIS BIT6 ///< SerialIo Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_SCC_FUSE_SS_DIS BIT4 ///< SCC Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_P2D_FUSE_SS_DIS BIT3 ///< P2D Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_CAM_FUSE_SS_DIS BIT2 ///< Camera Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_ISH_FUSE_SS_DIS BIT1 ///< ISH Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 ///< GBE Fuse or Soft Strap Disable
+#define R_PCH_PWRM_FUSE_DIS_RD_3 0x648 ///< Static PG Fuse and Soft Strap Disable Read Register 3
+#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA3_FUSE_SS_DIS BIT3 ///< PNCRA3 Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA2_FUSE_SS_DIS BIT2 ///< PNCRA2 Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA1_FUSE_SS_DIS BIT1 ///< PNCRA1 Fuse or Soft Strap Disable
+#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA_FUSE_SS_DIS BIT0 ///< PNCRA Fuse or Soft Strap Disable
+
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPsf.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPsf.h
new file mode 100644
index 0000000000..0eb61aa0b7
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPsf.h
@@ -0,0 +1,210 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_PSF_H_
+#define _PCH_REGS_PSF_H_
+
+//
+// Private chipset regsiter (Memory space) offset definition
+// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well.
+//
+
+//
+// PSFx segment registers
+//
+#define R_PCH_PCR_PSF_GLOBAL_CONFIG 0x4000 ///< PSF Segment Global Configuration Register
+#define B_PCH_PCR_PSF_GLOBAL_CONFIG_ENTCG BIT4
+#define B_PCH_PCR_PSF_GLOBAL_CONFIG_ENLCG BIT3
+#define R_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0 0x4014 ///< PSF Segment Rootspace Configuration Register
+#define B_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0_ENADDRP2P BIT1
+#define B_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0_VTDEN BIT0
+#define R_PCH_PCR_PSF_PORT_CONFIG_PG0_PORT0 0x4020 ///< PSF Segment Port Configuration Register
+
+#define S_PCH_PSF_DEV_GNTCNT_RELOAD_DGCR 4
+#define S_PCH_PSF_TARGET_GNTCNT_RELOAD 4
+#define B_PCH_PSF_DEV_GNTCNT_RELOAD_DGCR_GNT_CNT_RELOAD 0x1F
+#define B_PCH_PSF_TARGET_GNTCNT_RELOAD_GNT_CNT_RELOAD 0x1F
+
+//
+// PSFx PCRs definitions
+//
+#define R_PCH_PCR_PSFX_T0_SHDW_BAR0 0 ///< PCI BAR0
+#define R_PCH_PCR_PSFX_T0_SHDW_BAR1 0x04 ///< PCI BAR1
+#define R_PCH_PCR_PSFX_T0_SHDW_BAR2 0x08 ///< PCI BAR2
+#define R_PCH_PCR_PSFX_T0_SHDW_BAR3 0x0C ///< PCI BAR3
+#define R_PCH_PCR_PSFX_T0_SHDW_BAR4 0x10 ///< PCI BAR4
+#define R_PCH_PCR_PSFX_T0_SHDW_PCIEN 0x1C ///< PCI configuration space enable bits
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR0DIS BIT16 ///< Disable BAR0
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR1DIS BIT17 ///< Disable BAR1
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR2DIS BIT18 ///< Disable BAR2
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR3DIS BIT19 ///< Disable BAR3
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR4DIS BIT20 ///< Disable BAR4
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR5DIS BIT21 ///< Disable BAR5
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS BIT8 ///< Function disable
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_MEMEN BIT1 ///< Memory decoding enable
+#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_IOEN BIT0 ///< IO decoding enable
+#define R_PCH_PCR_PSFX_T0_SHDW_PMCSR 0x20 ///< PCI power management configuration
+#define B_PCH_PCR_PSFX_T0_SHDW_PMCSR_PWRST (BIT1 | BIT0) ///< Power status
+#define R_PCH_PCR_PSFX_T0_SHDW_CFG_DIS 0x38 ///< PCI configuration disable
+#define B_PCH_PCR_PSFX_T0_SHDW_CFG_DIS_CFGDIS BIT0 ///< config disable
+
+#define R_PCH_PCR_PSFX_T1_SHDW_PCIEN 0x3C ///< PCI configuration space enable bits
+#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_FUNDIS BIT8 ///< Function disable
+#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_MEMEN BIT1 ///< Memory decoding enable
+#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_IOEN BIT0 ///< IO decoding enable
+
+#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_DEVICE 0x01F0 ///< device number
+#define N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_DEVICE 4
+#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION (BIT3 | BIT2 | BIT1) ///< function number
+#define N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION 1
+
+#define V_PCH_LP_PCR_PSFX_PSF_MC_AGENT_MCAST_TGT_P2SB 0x38A00
+#define V_PCH_H_PCR_PSFX_PSF_MC_AGENT_MCAST_TGT_P2SB 0x38B00
+
+//
+// PSF1 PCRs
+//
+// PSF1 PCH-LP Specific Base Address
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_GBE_REG_BASE 0x0200 ///< D31F6 PSF base address (GBE)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_CAM_REG_BASE 0x0300 ///< D20F3 PSF base address (CAM)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_CSE_WLAN_REG_BASE 0x0500 ///< D22F7 PSF base address (CSME: WLAN)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI3_REG_BASE 0x0700 ///< D22F4 PSF base address (CSME: HECI3)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI2_REG_BASE 0x0800 ///< D22F1 PSF base address (CSME: HECI2)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_CSE_UMA_REG_BASE 0x0900 ///< D18F3 PSF base address (CSME: CSE UMA)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI1_REG_BASE 0x0A00 ///< D22F0 PSF base address (CSME: HECI1)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_KT_REG_BASE 0x0B00 ///< D22F3 PSF base address (CSME: KT)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_IDER_REG_BASE 0x0C00 ///< D22F2 PSF base address (CSME: IDER)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_CLINK_REG_BASE 0x0D00 ///< D18F1 PSF base address (CSME: CLINK)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_PMT_REG_BASE 0x0E00 ///< D18F2 PSF base address (CSME: PMT)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_KVM_REG_BASE 0x0F00 ///< D18F0 PSF base address (CSME: KVM)
+#define R_PCH_LP_PCR_PSF1_T0_SHDW_SATA_REG_BASE 0x1000 ///< PCH-LP D23F0 PSF base address (SATA)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2000 ///< PCH-LP D29F3 PSF base address (PCIE PORT 12)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2100 ///< PCH-LP D29F2 PSF base address (PCIE PORT 11)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2200 ///< PCH-LP D29F1 PSF base address (PCIE PORT 10)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2300 ///< PCH-LP D29F0 PSF base address (PCIE PORT 09)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x2400 ///< PCH-LP D28F7 PSF base address (PCIE PORT 08)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x2500 ///< PCH-LP D28F6 PSF base address (PCIE PORT 07)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x2600 ///< PCH-LP D28F5 PSF base address (PCIE PORT 06)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x2700 ///< PCH-LP D28F4 PSF base address (PCIE PORT 05)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x2800 ///< PCH-LP D28F3 PSF base address (PCIE PORT 04)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x2900 ///< PCH-LP D28F2 PSF base address (PCIE PORT 03)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x2A00 ///< PCH-LP D28F1 PSF base address (PCIE PORT 02)
+#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x2B00 ///< PCH-LP D28F0 PSF base address (PCIE PORT 01)
+
+// PSF1 PCH-H Specific Base Address
+#define R_PCH_H_PCR_PSF1_T0_SHDW_CSE_WLAN_REG_BASE 0x0200 ///< D22F7 PSF base address (CSME: WLAN)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI3_REG_BASE 0x0300 ///< SPT-H D22F4 PSF base address (CSME: HECI3)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI2_REG_BASE 0x0400 ///< SPT-H D22F1 PSF base address (CSME: HECI2)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_CSE_UMA_REG_BASE 0x0500 ///< D18F3 PSF base address (CSME: CSE UMA)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI1_REG_BASE 0x0600 ///< SPT-H D22F0 PSF base address (CSME: HECI1)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE 0x0700 ///< SPT-H D22F3 PSF base address (CSME: KT)
+#define R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE 0x0800 ///< SPT-H D22F2 PSF base address (CSME: IDER)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE20_REG_BASE 0x2000 ///< PCH-H D27F3 PSF base address (PCIE PORT 20)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE19_REG_BASE 0x2100 ///< PCH-H D27F2 PSF base address (PCIE PORT 19)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE18_REG_BASE 0x2200 ///< PCH-H D27F1 PSF base address (PCIE PORT 18)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE17_REG_BASE 0x2300 ///< PCH-H D27F0 PSF base address (PCIE PORT 17)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE16_REG_BASE 0x2400 ///< PCH-H D29F7 PSF base address (PCIE PORT 16)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE15_REG_BASE 0x2500 ///< PCH-H D29F6 PSF base address (PCIE PORT 15)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE14_REG_BASE 0x2600 ///< PCH-H D29F5 PSF base address (PCIE PORT 14)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE13_REG_BASE 0x2700 ///< PCH-H D29F4 PSF base address (PCIE PORT 13)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2800 ///< PCH-H D29F3 PSF base address (PCIE PORT 10)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2900 ///< PCH-H D29F2 PSF base address (PCIE PORT 11)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2A00 ///< PCH-H D29F1 PSF base address (PCIE PORT 10)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2B00 ///< PCH-H D29F0 PSF base address (PCIE PORT 09)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x2C00 ///< PCH-H D28F7 PSF base address (PCIE PORT 08)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x2D00 ///< PCH-H D28F6 PSF base address (PCIE PORT 07)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x2E00 ///< PCH-H D28F5 PSF base address (PCIE PORT 06)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x2F00 ///< PCH-H D28F4 PSF base address (PCIE PORT 05)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x3000 ///< PCH-H D28F3 PSF base address (PCIE PORT 04)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x3100 ///< PCH-H D28F2 PSF base address (PCIE PORT 03)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x3200 ///< PCH-H D28F1 PSF base address (PCIE PORT 02)
+#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x3300 ///< PCH-H D28F0 PSF base address (PCIE PORT 01)
+
+// Other PSF1 PCRs definition
+#define R_PCH_LP_PCR_PSF1_PSF_PORT_CONFIG_PG1_PORT7 0x403C ///< PSF Port Configuration Register
+#define R_PCH_LP_PCR_PSF1_PSF_MC_CONTROL_MCAST0_EOI 0x4050 ///< Multicast Control Register
+#define R_PCH_LP_PCR_PSF1_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4060 ///< Destination ID
+
+
+//PSF 1 Multicast Message Configuration
+
+#define R_PCH_PCR_PSF1_RC_OWNER_RS0 0x4008 ///< Destination ID
+
+#define B_PCH_PCR_PSF1_TARGET_CHANNELID 0xFF
+#define B_PCH_PCR_PSF1_TARGET_PORTID 0x7F00
+#define N_PCH_PCR_PSF1_TARGET_PORTID 8
+#define B_PCH_PCR_PSF1_TARGET_PORTGROUPID BIT15
+#define N_PCH_PCR_PSF1_TARGET_PORTGROUPID 15
+#define B_PCH_PCR_PSF1_TARGET_PSFID 0xFF0000
+#define N_PCH_PCR_PSF1_TARGET_PSFID 16
+#define B_PCH_PCR_PSF1_TARGET_CHANMAP BIT31
+
+#define V_PCH_PCR_PSF1_RC_OWNER_RS0_CHANNELID 0
+#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PORTID 10
+#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PORTGROUPID_DOWNSTREAM 1
+#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PSFID_PMT 0
+#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PSFID_PSF1 1
+
+#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTGROUPID_UPSTREAM 0
+#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTGROUPID_DOWNSTREAM 1
+#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PSFID_PSF1 1
+
+#define R_PCH_LP_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 0x4058 ///< Multicast Control Register
+
+#define B_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_MULTCEN BIT0
+#define B_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_NUMMC 0xFE
+#define N_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_NUMMC 1
+
+#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_CHANNELID_DMI 0
+#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTID_DMI 0
+
+
+
+//
+// controls the PCI configuration header of a PCI function
+//
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F0 0x4198 ///< SPA
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F1 0x419C ///< SPA
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F2 0x41A0 ///< SPA
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F3 0x41A4 ///< SPA
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F4 0x41A8 ///< SPB
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F5 0x41AC ///< SPB
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F6 0x41B0 ///< SPB
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F7 0x41B4 ///< SPB
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F0 0x41B8 ///< SPC
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F1 0x41BC ///< SPC
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F2 0x41C0 ///< SPC
+#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F3 0x41C4 ///< SPC
+
+
+//
+// PSF1 grant count registers
+//
+#define R_PCH_LP_PSF1_DEV_GNTCNT_RELOAD_DGCR0 0x41CC
+#define R_PCH_LP_PSF1_TARGET_GNTCNT_RELOAD_PG1_TGT0 0x45D0
+
+
+//
+// PSF2 PCRs (PID:PSF2)
+//
+#define R_PCH_PCR_PSF2_T0_SHDW_TRH_REG_BASE 0x0100 ///< D20F2 PSF base address (Thermal). // LP&H
+// PSF2 PCH-LP Specific Base Address
+#define R_PCH_LP_PCR_PSF2_T0_SHDW_UFS_REG_BASE 0x0200 ///< D30F7 PSF base address (SCC: UFS)
+#define R_PCH_LP_PCR_PSF2_T0_SHDW_SDCARD_REG_BASE 0x0300 ///< D30F6 PSF base address (SCC: SDCard)
+#define R_PCH_LP_PCR_PSF2_T0_SHDW_SDIO_REG_BASE 0x0400 ///< D30F5 PSF base address (SCC: SDIO)
+#define R_PCH_LP_PCR_PSF2_T0_SHDW_EMMC_REG_BASE 0x0500 ///< D30F4 PSF base address (SCC: eMMC)
+#define R_PCH_LP_PCR_PSF2_T0_SHDW_OTG_REG_BASE 0x0600 ///< D20F1 PSF base address (USB device controller: OTG)
+#define R_PCH_LP_PCR_PSF2_T0_SHDW_XHCI_REG_BASE 0x0700 ///< D20F0 PSF base address (XHCI)
+// PSF2 PCH-H Specific Base Address
+#define R_PCH_H_PCR_PSF2_T0_SHDW_OTG_REG_BASE 0x0200 ///< D20F1 PSF base address (USB device controller: OTG)
+#define R_PCH_H_PCR_PSF2_T0_SHDW_XHCI_REG_BASE 0x0300 ///< D20F0 PSF base address (XHCI)
+
+//
+// PSF3 PCRs (PID:PSF3)
+//
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPsth.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPsth.h
new file mode 100644
index 0000000000..6669cc2bb9
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsPsth.h
@@ -0,0 +1,46 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_PSTH_H_
+#define _PCH_REGS_PSTH_H_
+
+//
+// Private chipset regsiter (Memory space) offset definition
+// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well.
+//
+
+//
+// PSTH and IO Trap PCRs (PID:PSTH)
+//
+#define R_PCH_PCR_PSTH_PSTHCTL 0x1D00 ///< PSTH control register
+#define B_PCH_PCR_PSTH_PSTHIOSFPTCGE BIT2 ///< PSTH IOSF primary trunk clock gating enable
+#define B_PCH_PCR_PSTH_PSTHIOSFSTCGE BIT1 ///< PSTH IOSF sideband trunk clock gating enable
+#define B_PCH_PCR_PSTH_PSTHDCGE BIT0 ///< PSTH dynamic clock gating enable
+#define R_PCH_PCR_PSTH_TRPST 0x1E00 ///< Trap status regsiter
+#define B_PCH_PCR_PSTH_TRPST_CTSS 0x0000000F ///< Cycle Trap SMI# Status mask
+#define R_PCH_PCR_PSTH_TRPC 0x1E10 ///< Trapped cycle
+#define B_PCH_PCR_PSTH_TRPC_RW BIT24 ///< Read/Write#: 1=Read, 0=Write
+#define B_PCH_PCR_PSTH_TRPC_AHBE 0x00000000000F0000 ///< Active high byte enables
+#define B_PCH_PCR_PSTH_TRPC_IOA 0x000000000000FFFC ///< Trap cycle I/O address
+#define R_PCH_PCR_PSTH_TRPD 0x1E18 ///< Trapped write data
+#define B_PCH_PCR_PSTH_TRPD_IOD 0x00000000FFFFFFFF ///< Trap cycle I/O data
+#define R_PCH_PCR_PSTH_TRPREG0 0x1E80 ///< IO Tarp 0 register
+#define R_PCH_PCR_PSTH_TRPREG1 0x1E88 ///< IO Tarp 1 register
+#define R_PCH_PCR_PSTH_TRPREG2 0x1E90 ///< IO Tarp 2 register
+#define R_PCH_PCR_PSTH_TRPREG3 0x1E98 ///< IO Tarp 3 register
+#define B_PCH_PCR_PSTH_TRPREG_RWM BIT17 ///< 49 - 32 for 32 bit access, Read/Write mask
+#define B_PCH_PCR_PSTH_TRPREG_RWIO BIT16 ///< 48 - 32 for 32 bit access, Read/Write#, 1=Read, 0=Write
+#define N_PCH_PCR_PSTH_TRPREG_RWIO 16 ///< 48 - 32 for 32 bit access, 16bit shift for Read/Write field
+#define N_PCH_PCR_PSTH_TRPREG_BEM (36 - 32)
+#define B_PCH_PCR_PSTH_TRPREG_BEM 0x000000F000000000 ///< Byte enable mask
+#define B_PCH_PCR_PSTH_TRPREG_BE 0x0000000F00000000 ///< Byte enable
+#define B_PCH_PCR_PSTH_TRPREG_AM 0x0000000000FC0000 ///< IO Address mask
+#define B_PCH_PCR_PSTH_TRPREG_AD 0x000000000000FFFC ///< IO Address
+#define B_PCH_PCR_PSTH_TRPREG_TSE BIT0 ///< Trap and SMI# Enable
+
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSata.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSata.h
new file mode 100644
index 0000000000..7d91f19dbc
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSata.h
@@ -0,0 +1,634 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_SATA_H_
+#define _PCH_REGS_SATA_H_
+
+//
+// SATA Controller Registers (D23:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_SATA 23
+#define PCI_FUNCTION_NUMBER_PCH_SATA 0
+#define V_PCH_SATA_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+
+#define PCH_SATA_FIRST_CONTROLLER 1
+#define PCH_SATA_SECOND_CONTROLLER 2
+
+//
+// SKL PCH-LP SATA Device ID's
+//
+#define V_PCH_LP_SATA_DEVICE_ID_M_AHCI 0x9D03 ///< SATA Controller (AHCI) - Mobile
+#define V_PCH_LP_SATA_DEVICE_ID_M_RAID 0x9D05 ///< SATA Controller (RAID 0/1/5/10) - NOT premium - Mobile
+#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_ALTDIS 0x282A ///< SATA Controller (RAID 0/1/5/10) - NOT premium - Mobile - Alternate ID
+#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_PREM 0x9D07 ///< SATA Controller (RAID 0/1/5/10) - premium - Mobile
+#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_RRT 0x9D0F ///< SATA Controller (RAID 1/RRT Only) - Mobile
+
+//
+// SKL PCH-H SATA Device ID's
+//
+#define V_PCH_H_SATA_DEVICE_ID_D_AHCI 0xA102 ///< SATA Controller (AHCI)
+#define V_PCH_H_SATA_DEVICE_ID_D_AHCI_A0 0xA103 ///< SATA Controller (AHCI) - SPTH A0
+#define V_PCH_H_SATA_DEVICE_ID_D_RAID 0xA105 ///< SATA Controller (RAID 0/1/5/10) - NOT premium
+#define V_PCH_H_SATA_DEVICE_ID_D_RAID_ALTDIS 0x2822 ///< SATA Controller (RAID 0/1/5/10) - premium - Alternate ID
+#define V_PCH_H_SATA_DEVICE_ID_D_RAID_RSTE 0x2826 ///< SATA Controller (RAID 0/1/5/10) - RSTe of Server SKU
+#define V_PCH_H_SATA_DEVICE_ID_D_RAID_PREM 0xA107 ///< SATA Controller (RAID 0/1/5/10) - premium
+#define V_PCH_H_SATA_DEVICE_ID_D_RAID_RRT 0xA10F ///< SATA Controller (RAID 1/RRT Only)
+
+
+//
+// LBG PRODUCTION INCLUDING QUAL SAMPLES SATA Device ID's
+//
+#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_AHCI 0xA182 ///< Server AHCI Mode (Ports 0-5)
+#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID 0xA184 ///< Server RAID 0/1/5/10 - NOT premium
+#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID_PREMIUM 0xA186 ///< Server RAID 0/1/5/10 - premium
+#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID1 0xA18E ///< Server RAID 1/RRT Only
+
+//
+// LBG SSX (Super SKUs and Pre Production) SATA Device ID's
+//
+#define V_PCH_LBG_SATA_DEVICE_ID_D_AHCI 0xA202 ///< Server AHCI Mode (Ports 0-5)
+#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID 0xA204 ///< Server RAID 0/1/5/10 - NOT premium
+#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM 0xA206 ///< Server RAID 0/1/5/10 - premium
+#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID1 0xA20E ///< Server RAID 1/RRT Only
+
+//
+// LBG Alternate RST Device IDs
+//
+#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0 0x2822 ///< Server RAID 0/1/5/10 - premium - Alternate ID for RST
+#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1 0x2826 ///< Server RAID 0/1/5/10 - premium - Alternate ID for RSTe
+
+//
+// SATA Controller common Registers
+//
+#define V_PCH_SATA_SUB_CLASS_CODE_AHCI 0x06
+#define V_PCH_SATA_SUB_CLASS_CODE_RAID 0x04
+#define R_PCH_SATA_AHCI_BAR 0x24
+#define B_PCH_SATA_AHCI_BAR_BA 0xFFFFF800
+#define V_PCH_SATA_AHCI_BAR_LENGTH 0x800
+#define N_PCH_SATA_AHCI_BAR_ALIGNMENT 11
+#define V_PCH_SATA_AHCI_BAR_LENGTH_512K 0x80000
+#define N_PCH_SATA_AHCI_BAR_ALIGNMENT_512K 19
+#define B_PCH_SATA_AHCI_BAR_PF BIT3
+#define B_PCH_SATA_AHCI_BAR_TP (BIT2 | BIT1)
+#define B_PCH_SATA_AHCI_BAR_RTE BIT0
+#define R_PCH_SATA_PID 0x70
+#define B_PCH_SATA_PID_NEXT 0xFF00
+#define V_PCH_SATA_PID_NEXT_0 0xB000
+#define V_PCH_SATA_PID_NEXT_1 0xA800
+#define B_PCH_SATA_PID_CID 0x00FF
+#define R_PCH_SATA_PC 0x72
+#define S_PCH_SATA_PC 2
+#define B_PCH_SATA_PC_PME (BIT15 | BIT14 | BIT13 | BIT12 | BIT11)
+#define V_PCH_SATA_PC_PME_0 0x0000
+#define V_PCH_SATA_PC_PME_1 0x4000
+#define B_PCH_SATA_PC_D2_SUP BIT10
+#define B_PCH_SATA_PC_D1_SUP BIT9
+#define B_PCH_SATA_PC_AUX_CUR (BIT8 | BIT7 | BIT6)
+#define B_PCH_SATA_PC_DSI BIT5
+#define B_PCH_SATA_PC_PME_CLK BIT3
+#define B_PCH_SATA_PC_VER (BIT2 | BIT1 | BIT0)
+#define R_PCH_SATA_PMCS 0x74
+#define B_PCH_SATA_PMCS_PMES BIT15
+#define B_PCH_SATA_PMCS_PMEE BIT8
+#define B_PCH_SATA_PMCS_NSFRST BIT3
+#define V_PCH_SATA_PMCS_NSFRST_1 0x01
+#define V_PCH_SATA_PMCS_NSFRST_0 0x00
+#define B_PCH_SATA_PMCS_PS (BIT1 | BIT0)
+#define V_PCH_SATA_PMCS_PS_3 0x03
+#define V_PCH_SATA_PMCS_PS_0 0x00
+#define R_PCH_SATA_MID 0x80
+#define B_PCH_SATA_MID_NEXT 0xFF00
+#define B_PCH_SATA_MID_CID 0x00FF
+#define R_PCH_SATA_MC 0x82
+#define B_PCH_SATA_MC_C64 BIT7
+#define B_PCH_SATA_MC_MME (BIT6 | BIT5 | BIT4)
+#define V_PCH_SATA_MC_MME_4 0x04
+#define V_PCH_SATA_MC_MME_2 0x02
+#define V_PCH_SATA_MC_MME_1 0x01
+#define V_PCH_SATA_MC_MME_0 0x00
+#define B_PCH_SATA_MC_MMC (BIT3 | BIT2 | BIT1)
+#define V_PCH_SATA_MC_MMC_4 0x04
+#define V_PCH_SATA_MC_MMC_0 0x00
+#define B_PCH_SATA_MC_MSIE BIT0
+#define V_PCH_SATA_MC_MSIE_1 0x01
+#define V_PCH_SATA_MC_MSIE_0 0x00
+#define R_PCH_SATA_MA 0x84
+#define B_PCH_SATA_MA 0xFFFFFFFC
+#define R_PCH_SATA_MD 0x88
+#define B_PCH_SATA_MD_MSIMD 0xFFFF
+
+//
+// Sata Register for PCH-LP
+//
+#define R_PCH_LP_SATA_MAP 0x90
+#define B_PCH_LP_SATA_MAP_SPD (BIT10 | BIT9 | BIT8)
+#define N_PCH_LP_SATA_MAP_SPD 8
+#define B_PCH_LP_SATA_MAP_SPD2 BIT10
+#define B_PCH_LP_SATA_MAP_SPD1 BIT9
+#define B_PCH_LP_SATA_MAP_SPD0 BIT8
+#define B_PCH_LP_SATA_MAP_SMS_MASK BIT6
+#define N_PCH_LP_SATA_MAP_SMS_MASK 6
+#define V_PCH_LP_SATA_MAP_SMS_AHCI 0x0
+#define V_PCH_LP_SATA_MAP_SMS_RAID 0x1
+#define R_PCH_LP_SATA_PCS 0x92
+#define B_PCH_LP_SATA_PCS_OOB_RETRY BIT15
+#define B_PCH_LP_SATA_PCS_P2P BIT10
+#define B_PCH_LP_SATA_PCS_P1P BIT9
+#define B_PCH_LP_SATA_PCS_P0P BIT8
+#define B_PCH_LP_SATA_PCS_PXE_MASK (BIT2 | BIT1 | BIT0)
+#define B_PCH_LP_SATA_PCS_P2E BIT2
+#define B_PCH_LP_SATA_PCS_P1E BIT1
+#define B_PCH_LP_SATA_PCS_P0E BIT0
+#define R_PCH_LP_SATA_SCLKGC 0x94
+#define B_PCH_LP_SATA_SCLKGC_PCD (BIT26 | BIT25 | BIT24)
+#define B_PCH_LP_SATA_SCLKGC_PORT2_PCD BIT26
+#define B_PCH_LP_SATA_SCLKGC_PORT1_PCD BIT25
+#define B_PCH_LP_SATA_SCLKGC_PORT0_PCD BIT24
+#define R_PCH_LP_SATA_98 0x98
+
+//
+// Sata Register for PCH-H
+//
+#define R_PCH_H_SATA_MAP 0x90
+#define B_PCH_H_SATA_MAP_SPD 0xFF0000
+#define N_PCH_H_SATA_MAP_SPD 16
+#define B_PCH_H_SATA_MAP_SPD7 BIT23
+#define B_PCH_H_SATA_MAP_SPD6 BIT22
+#define B_PCH_H_SATA_MAP_SPD5 BIT21
+#define B_PCH_H_SATA_MAP_SPD4 BIT20
+#define B_PCH_H_SATA_MAP_SPD3 BIT19
+#define B_PCH_H_SATA_MAP_SPD2 BIT18
+#define B_PCH_H_SATA_MAP_SPD1 BIT17
+#define B_PCH_H_SATA_MAP_SPD0 BIT16
+#define B_PCH_H_SATA_MAP_PCD 0xFF
+#define B_PCH_H_SATA_MAP_PORT7_PCD BIT7
+#define B_PCH_H_SATA_MAP_PORT6_PCD BIT6
+#define B_PCH_H_SATA_MAP_PORT5_PCD BIT5
+#define B_PCH_H_SATA_MAP_PORT4_PCD BIT4
+#define B_PCH_H_SATA_MAP_PORT3_PCD BIT3
+#define B_PCH_H_SATA_MAP_PORT2_PCD BIT2
+#define B_PCH_H_SATA_MAP_PORT1_PCD BIT1
+#define B_PCH_H_SATA_MAP_PORT0_PCD BIT0
+#define R_PCH_H_SATA_PCS 0x94
+#define B_PCH_H_SATA_PCS_P7P BIT23
+#define B_PCH_H_SATA_PCS_P6P BIT22
+#define B_PCH_H_SATA_PCS_P5P BIT21
+#define B_PCH_H_SATA_PCS_P4P BIT20
+#define B_PCH_H_SATA_PCS_P3P BIT19
+#define B_PCH_H_SATA_PCS_P2P BIT18
+#define B_PCH_H_SATA_PCS_P1P BIT17
+#define B_PCH_H_SATA_PCS_P0P BIT16
+#define B_PCH_H_SATA_PCS_PXE_MASK 0xFF
+#define B_PCH_H_SATA_PCS_P7E BIT7
+#define B_PCH_H_SATA_PCS_P6E BIT6
+#define B_PCH_H_SATA_PCS_P5E BIT5
+#define B_PCH_H_SATA_PCS_P4E BIT4
+#define B_PCH_H_SATA_PCS_P3E BIT3
+#define B_PCH_H_SATA_PCS_P2E BIT2
+#define B_PCH_H_SATA_PCS_P1E BIT1
+#define B_PCH_H_SATA_PCS_P0E BIT0
+
+#define R_PCH_SATA_SATAGC 0x9C
+#define B_PCH_H_SATA_SATAGC_SMS_MASK BIT16
+#define N_PCH_H_SATA_SATAGC_SMS_MASK 16
+#define V_PCH_H_SATA_SATAGC_SMS_AHCI 0x0
+#define V_PCH_H_SATA_SATAGC_SMS_RAID 0x1
+#define B_PCH_SATA_SATAGC_AIE BIT7
+#define B_PCH_SATA_SATAGC_AIES BIT6
+#define B_PCH_SATA_SATAGC_MSS (BIT4 | BIT3)
+#define V_PCH_SATA_SATAGC_MSS_8K 0x2
+#define N_PCH_SATA_SATAGC_MSS 3
+#define B_PCH_SATA_SATAGC_ASSEL (BIT2 | BIT1 | BIT0)
+
+#define V_PCH_SATA_SATAGC_ASSEL_2K 0x0
+#define V_PCH_SATA_SATAGC_ASSEL_16K 0x1
+#define V_PCH_SATA_SATAGC_ASSEL_32K 0x2
+#define V_PCH_SATA_SATAGC_ASSEL_64K 0x3
+#define V_PCH_SATA_SATAGC_ASSEL_128K 0x4
+#define V_PCH_SATA_SATAGC_ASSEL_256K 0x5
+#define V_PCH_SATA_SATAGC_ASSEL_512K 0x6
+
+#define R_PCH_SATA_SIRI 0xA0
+#define R_PCH_SATA_STRD 0xA4
+#define R_PCH_SATA_SIR_50 0x50
+#define R_PCH_SATA_SIR_54 0x54
+#define R_PCH_SATA_SIR_58 0x58
+#define R_PCH_SATA_SIR_5C 0x5C
+#define R_PCH_SATA_SIR_60 0x60
+#define R_PCH_SATA_SIR_64 0x64
+#define R_PCH_SATA_SIR_68 0x68
+#define R_PCH_SATA_SIR_6C 0x6C
+#define R_PCH_SATA_SIR_70 0x70
+#define R_PCH_SATA_SIR_80 0x80
+#define R_PCH_SATA_SIR_84 0x84
+#define R_PCH_SATA_SIR_8C 0x8C
+#define R_PCH_SATA_SIR_90 0x90
+#define R_PCH_SATA_SIR_98 0x98
+#define R_PCH_SATA_SIR_9C 0x9C
+#define R_PCH_SATA_SIR_A0 0xA0
+#define R_PCH_SATA_SIR_A4 0xA4
+#define R_PCH_SATA_SIR_A8 0xA8
+#define R_PCH_SATA_SIR_C8 0xC8
+#define R_PCH_SATA_SIR_CC 0xCC
+#define R_PCH_SATA_SIR_D0 0xD0
+#define R_PCH_SATA_SIR_D4 0xD4
+#define B_PCH_SATA_STRD_DTA 0xFFFFFFFF
+#define R_PCH_SATA_CR0 0xA8
+#define B_PCH_SATA_CR0_MAJREV 0x00F00000
+#define B_PCH_SATA_CR0_MINREV 0x000F0000
+#define B_PCH_SATA_CR0_NEXT 0x0000FF00
+#define B_PCH_SATA_CR0_CAP 0x000000FF
+#define R_PCH_SATA_CR1 0xAC
+#define B_PCH_SATA_CR1_BAROFST 0xFFF0
+#define B_PCH_SATA_CR1_BARLOC 0x000F
+#define R_PCH_SATA_FLR_CID 0xB0
+#define B_PCH_SATA_FLR_CID_NEXT 0xFF00
+#define B_PCH_SATA_FLR_CID 0x00FF
+#define V_PCH_SATA_FLR_CID_1 0x0009
+#define V_PCH_SATA_FLR_CID_0 0x0013
+#define R_PCH_SATA_FLR_CLV 0xB2
+#define B_PCH_SATA_FLR_CLV_FLRC_FLRCSSEL_0 BIT9
+#define B_PCH_SATA_FLR_CLV_TXPC_FLRCSSEL_0 BIT8
+#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_0 0x00FF
+#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_1 0x00FF
+#define V_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL 0x0006
+#define R_PCH_SATA_FLRC 0xB4
+#define B_PCH_SATA_FLRC_TXP BIT8
+#define B_PCH_SATA_FLRC_INITFLR BIT0
+#define R_PCH_SATA_SP 0xC0
+#define B_PCH_SATA_SP 0xFFFFFFFF
+#define R_PCH_SATA_MXID 0xD0
+#define N_PCH_SATA_MXID_NEXT 8
+
+#define R_PCH_SATA_BFCS 0xE0
+#define B_PCH_SATA_BFCS_P7BFI BIT17
+#define B_PCH_SATA_BFCS_P6BFI BIT16
+#define B_PCH_SATA_BFCS_P5BFI BIT15
+#define B_PCH_SATA_BFCS_P4BFI BIT14
+#define B_PCH_SATA_BFCS_P3BFI BIT13
+#define B_PCH_SATA_BFCS_P2BFI BIT12
+#define B_PCH_SATA_BFCS_P2BFS BIT11
+#define B_PCH_SATA_BFCS_P2BFF BIT10
+#define B_PCH_SATA_BFCS_P1BFI BIT9
+#define B_PCH_SATA_BFCS_P0BFI BIT8
+#define B_PCH_SATA_BFCS_BIST_FIS_T BIT7
+#define B_PCH_SATA_BFCS_BIST_FIS_A BIT6
+#define B_PCH_SATA_BFCS_BIST_FIS_S BIT5
+#define B_PCH_SATA_BFCS_BIST_FIS_L BIT4
+#define B_PCH_SATA_BFCS_BIST_FIS_F BIT3
+#define B_PCH_SATA_BFCS_BIST_FIS_P BIT2
+#define R_PCH_SATA_BFTD1 0xE4
+#define B_PCH_SATA_BFTD1 0xFFFFFFFF
+#define R_PCH_SATA_BFTD2 0xE8
+#define B_PCH_SATA_BFTD2 0xFFFFFFFF
+
+#define R_PCH_SATA_VS_CAP 0xA4
+#define B_PCH_SATA_VS_CAP_NRMBE BIT0 ///< NVM Remap Memory BAR Enable
+#define B_PCH_SATA_VS_CAP_MSL 0x1FFE ///< Memory Space Limit
+#define N_PCH_SATA_VS_CAP_MSL 1
+#define V_PCH_SATA_VS_CAP_MSL 0x1EF ///< Memory Space Limit Field Value
+#define B_PCH_SATA_VS_CAP_NRMO 0xFFF0000 ///< NVM Remapped Memory Offset
+#define N_PCH_SATA_VS_CAP_NRMO 16
+#define V_PCH_SATA_VS_CAP_NRMO 0x10 ///< NVM Remapped Memory Offset Field Value
+
+//
+// RST PCIe Storage Remapping Registers
+//
+#define R_PCH_RST_PCIE_STORAGE_RCR 0x800 ///< Remap Capability Register
+#define B_PCH_RST_PCIE_STORAGE_RCR_NRS (BIT2|BIT1|BIT0) ///< Number of Remapping Supported
+#define B_PCH_RST_PCIE_STORAGE_RCR_NRS_CR1 BIT0 ///< Number of Remapping Supported (RST PCIe Storage Cycle Router #1)
+#define R_PCH_RST_PCIE_STORAGE_SPR 0x80C ///< Scratch Pad Register
+#define R_PCH_RST_PCIE_STORAGE_CR1_DCC 0x880 ///< CR#1 Device Class Code
+#define N_PCH_RST_PCIE_STORAGE_CR1_DCC_SCC 8
+#define N_PCH_RST_PCIE_STORAGE_CR1_DCC_BCC 16
+#define B_PCH_RST_PCIE_STORAGE_CR1_DCC_DT BIT31 ///< Device Type
+#define V_PCH_RST_PCIE_STORAGE_REMAP_CONFIG_CR 0x80 ///< Remapped Configuration for RST PCIe Storage Cycle Router #n
+#define V_PCH_RST_PCIE_STORAGE_REMAP_RP_OFFSET 0x100 ///< Remapped Root Port Offset Value
+#define R_PCH_RST_PCIE_STORAGE_CCFG 0x1D0 ///< Port Configuration Register
+
+//
+// AHCI BAR Area related Registers
+//
+#define R_PCH_SATA_AHCI_CAP 0x0
+#define B_PCH_SATA_AHCI_CAP_S64A BIT31
+#define B_PCH_SATA_AHCI_CAP_SCQA BIT30
+#define B_PCH_SATA_AHCI_CAP_SSNTF BIT29
+#define B_PCH_SATA_AHCI_CAP_SIS BIT28 ///< Supports Interlock Switch
+#define B_PCH_SATA_AHCI_CAP_SSS BIT27 ///< Supports Stagger Spin-up
+#define B_PCH_SATA_AHCI_CAP_SALP BIT26
+#define B_PCH_SATA_AHCI_CAP_SAL BIT25
+#define B_PCH_SATA_AHCI_CAP_SCLO BIT24 ///< Supports Command List Override
+#define B_PCH_SATA_AHCI_CAP_ISS_MASK (BIT23 | BIT22 | BIT21 | BIT20)
+#define N_PCH_SATA_AHCI_CAP_ISS 20 ///< Interface Speed Support
+#define V_PCH_SATA_AHCI_CAP_ISS_1_5_G 0x01
+#define V_PCH_SATA_AHCI_CAP_ISS_3_0_G 0x02
+#define V_PCH_SATA_AHCI_CAP_ISS_6_0_G 0x03
+#define B_PCH_SATA_AHCI_CAP_SNZO BIT19
+#define B_PCH_SATA_AHCI_CAP_SAM BIT18
+#define B_PCH_SATA_AHCI_CAP_PMS BIT17 ///< Supports Port Multiplier
+#define B_PCH_SATA_AHCI_CAP_PMD BIT15 ///< PIO Multiple DRQ Block
+#define B_PCH_SATA_AHCI_CAP_SSC BIT14
+#define B_PCH_SATA_AHCI_CAP_PSC BIT13
+#define B_PCH_SATA_AHCI_CAP_NCS 0x1F00
+#define B_PCH_SATA_AHCI_CAP_CCCS BIT7
+#define B_PCH_SATA_AHCI_CAP_EMS BIT6
+#define B_PCH_SATA_AHCI_CAP_SXS BIT5 ///< External SATA is supported
+#define B_PCH_SATA_AHCI_CAP_NPS 0x001F
+
+#define R_PCH_SATA_AHCI_GHC 0x04
+#define B_PCH_SATA_AHCI_GHC_AE BIT31
+#define B_PCH_SATA_AHCI_GHC_MRSM BIT2
+#define B_PCH_SATA_AHCI_GHC_IE BIT1
+#define B_PCH_SATA_AHCI_GHC_HR BIT0
+
+#define R_PCH_SATA_AHCI_IS 0x08
+#define B_PCH_SATA_AHCI_IS_PORT7 BIT7
+#define B_PCH_SATA_AHCI_IS_PORT6 BIT6
+#define B_PCH_SATA_AHCI_IS_PORT5 BIT5
+#define B_PCH_SATA_AHCI_IS_PORT4 BIT4
+#define B_PCH_SATA_AHCI_IS_PORT3 BIT3
+#define B_PCH_SATA_AHCI_IS_PORT2 BIT2
+#define B_PCH_SATA_AHCI_IS_PORT1 BIT1
+#define B_PCH_SATA_AHCI_IS_PORT0 BIT0
+#define R_PCH_SATA_AHCI_PI 0x0C
+#define B_PCH_H_SATA_PORT_MASK 0xFF
+#define B_PCH_LP_SATA_PORT_MASK 0x03
+#define B_PCH_SATA_PORT7_IMPLEMENTED BIT7
+#define B_PCH_SATA_PORT6_IMPLEMENTED BIT6
+#define B_PCH_SATA_PORT5_IMPLEMENTED BIT5
+#define B_PCH_SATA_PORT4_IMPLEMENTED BIT4
+#define B_PCH_SATA_PORT3_IMPLEMENTED BIT3
+#define B_PCH_SATA_PORT2_IMPLEMENTED BIT2
+#define B_PCH_SATA_PORT1_IMPLEMENTED BIT1
+#define B_PCH_SATA_PORT0_IMPLEMENTED BIT0
+#define R_PCH_SATA_AHCI_VS 0x10
+#define B_PCH_SATA_AHCI_VS_MJR 0xFFFF0000
+#define B_PCH_SATA_AHCI_VS_MNR 0x0000FFFF
+#define R_PCH_SATA_AHCI_EM_LOC 0x1C
+#define B_PCH_SATA_AHCI_EM_LOC_OFST 0xFFFF0000
+#define B_PCH_SATA_AHCI_EM_LOC_SZ 0x0000FFFF
+#define R_PCH_SATA_AHCI_EM_CTRL 0x20
+#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_ALHD BIT26
+#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_XMT BIT25
+#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_SMB BIT24
+#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SGPIO BIT19
+#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SES2 BIT18
+#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SAFTE BIT17
+#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_LED BIT16
+#define B_PCH_SATA_AHCI_EM_CTRL_RST BIT9
+#define B_PCH_SATA_AHCI_EM_CTRL_CTL_TM BIT8
+#define B_PCH_SATA_AHCI_EM_CTRL_STS_MR BIT0
+#define R_PCH_SATA_AHCI_CAP2 0x24
+#define B_PCH_SATA_AHCI_CAP2_DESO BIT5
+#define B_PCH_SATA_AHCI_CAP2_SADM BIT4
+#define B_PCH_SATA_AHCI_CAP2_SDS BIT3
+#define B_PCH_SATA_AHCI_CAP2_APST BIT2 ///< Automatic Partial to Slumber Transitions
+#define R_PCH_SATA_AHCI_VSP 0xA0
+#define B_PCH_SATA_AHCI_VSP_SLPD BIT0
+#define R_PCH_SATA_AHCI_RSTF 0xC8 ///< RST Feature Capabilities
+#define B_PCH_SATA_AHCI_RSTF_OUD (BIT11 | BIT10)
+#define N_PCH_SATA_AHCI_RSTF_OUD 10
+#define B_PCH_SATA_AHCI_RSTF_SEREQ BIT9
+#define B_PCH_SATA_AHCI_RSTF_IROES BIT8
+#define B_PCH_SATA_AHCI_RSTF_LEDL BIT7
+#define B_PCH_SATA_AHCI_RSTF_HDDLK BIT6
+#define B_PCH_SATA_AHCI_RSTF_IRSTOROM BIT5
+#define B_PCH_SATA_AHCI_RSTF_RSTE BIT4
+#define B_PCH_SATA_AHCI_RSTF_R5E BIT3
+#define B_PCH_SATA_AHCI_RSTF_R10E BIT2
+#define B_PCH_SATA_AHCI_RSTF_R1E BIT1
+#define B_PCH_SATA_AHCI_RSTF_R0E BIT0
+#define B_PCH_SATA_AHCI_RSTF_LOWBYTES 0x1FF
+#define R_PCH_SATA_AHCI_P0CLB 0x100
+#define R_PCH_SATA_AHCI_P1CLB 0x180
+#define R_PCH_SATA_AHCI_P2CLB 0x200
+#define R_PCH_SATA_AHCI_P3CLB 0x280
+#define R_PCH_SATA_AHCI_P4CLB 0x300
+#define R_PCH_SATA_AHCI_P5CLB 0x380
+#define R_PCH_SATA_AHCI_P6CLB 0x400
+#define R_PCH_SATA_AHCI_P7CLB 0x480
+#define B_PCH_SATA_AHCI_PXCLB 0xFFFFFC00
+#define R_PCH_SATA_AHCI_P0CLBU 0x104
+#define R_PCH_SATA_AHCI_P1CLBU 0x184
+#define R_PCH_SATA_AHCI_P2CLBU 0x204
+#define R_PCH_SATA_AHCI_P3CLBU 0x284
+#define R_PCH_SATA_AHCI_P4CLBU 0x304
+#define R_PCH_SATA_AHCI_P5CLBU 0x384
+#define R_PCH_SATA_AHCI_P6CLBU 0x404
+#define R_PCH_SATA_AHCI_P7CLBU 0x484
+#define B_PCH_SATA_AHCI_PXCLBU 0xFFFFFFFF
+#define R_PCH_SATA_AHCI_P0FB 0x108
+#define R_PCH_SATA_AHCI_P1FB 0x188
+#define R_PCH_SATA_AHCI_P2FB 0x208
+#define R_PCH_SATA_AHCI_P3FB 0x288
+#define R_PCH_SATA_AHCI_P4FB 0x308
+#define R_PCH_SATA_AHCI_P5FB 0x388
+#define R_PCH_SATA_AHCI_P6FB 0x408
+#define R_PCH_SATA_AHCI_P7FB 0x488
+#define B_PCH_SATA_AHCI_PXFB 0xFFFFFF00
+#define R_PCH_SATA_AHCI_P0FBU 0x10C
+#define R_PCH_SATA_AHCI_P1FBU 0x18C
+#define R_PCH_SATA_AHCI_P2FBU 0x20C
+#define R_PCH_SATA_AHCI_P3FBU 0x28C
+#define R_PCH_SATA_AHCI_P4FBU 0x30C
+#define R_PCH_SATA_AHCI_P5FBU 0x38C
+#define R_PCH_SATA_AHCI_P6FBU 0x40C
+#define R_PCH_SATA_AHCI_P7FBU 0x48C
+#define B_PCH_SATA_AHCI_PXFBU 0xFFFFFFFF
+#define R_PCH_SATA_AHCI_P0IS 0x110
+#define R_PCH_SATA_AHCI_P1IS 0x190
+#define R_PCH_SATA_AHCI_P2IS 0x210
+#define R_PCH_SATA_AHCI_P3IS 0x290
+#define R_PCH_SATA_AHCI_P4IS 0x310
+#define R_PCH_SATA_AHCI_P5IS 0x390
+#define R_PCH_SATA_AHCI_P6IS 0x410
+#define R_PCH_SATA_AHCI_P7IS 0x490
+#define B_PCH_SATA_AHCI_PXIS_CPDS BIT31
+#define B_PCH_SATA_AHCI_PXIS_TFES BIT30
+#define B_PCH_SATA_AHCI_PXIS_HBFS BIT29
+#define B_PCH_SATA_AHCI_PXIS_HBDS BIT28
+#define B_PCH_SATA_AHCI_PXIS_IFS BIT27
+#define B_PCH_SATA_AHCI_PXIS_INFS BIT26
+#define B_PCH_SATA_AHCI_PXIS_OFS BIT24
+#define B_PCH_SATA_AHCI_PXIS_IPMS BIT23
+#define B_PCH_SATA_AHCI_PXIS_PRCS BIT22
+#define B_PCH_SATA_AHCI_PXIS_DIS BIT7
+#define B_PCH_SATA_AHCI_PXIS_PCS BIT6
+#define B_PCH_SATA_AHCI_PXIS_DPS BIT5
+#define B_PCH_SATA_AHCI_PXIS_UFS BIT4
+#define B_PCH_SATA_AHCI_PXIS_SDBS BIT3
+#define B_PCH_SATA_AHCI_PXIS_DSS BIT2
+#define B_PCH_SATA_AHCI_PXIS_PSS BIT1
+#define B_PCH_SATA_AHCI_PXIS_DHRS BIT0
+#define R_PCH_SATA_AHCI_P0IE 0x114
+#define R_PCH_SATA_AHCI_P1IE 0x194
+#define R_PCH_SATA_AHCI_P2IE 0x214
+#define R_PCH_SATA_AHCI_P3IE 0x294
+#define R_PCH_SATA_AHCI_P4IE 0x314
+#define R_PCH_SATA_AHCI_P5IE 0x394
+#define R_PCH_SATA_AHCI_P6IE 0x414
+#define R_PCH_SATA_AHCI_P7IE 0x494
+#define B_PCH_SATA_AHCI_PXIE_CPDE BIT31
+#define B_PCH_SATA_AHCI_PXIE_TFEE BIT30
+#define B_PCH_SATA_AHCI_PXIE_HBFE BIT29
+#define B_PCH_SATA_AHCI_PXIE_HBDE BIT28
+#define B_PCH_SATA_AHCI_PXIE_IFE BIT27
+#define B_PCH_SATA_AHCI_PXIE_INFE BIT26
+#define B_PCH_SATA_AHCI_PXIE_OFE BIT24
+#define B_PCH_SATA_AHCI_PXIE_IPME BIT23
+#define B_PCH_SATA_AHCI_PXIE_PRCE BIT22
+#define B_PCH_SATA_AHCI_PXIE_DIE BIT7
+#define B_PCH_SATA_AHCI_PXIE_PCE BIT6
+#define B_PCH_SATA_AHCI_PXIE_DPE BIT5
+#define B_PCH_SATA_AHCI_PXIE_UFIE BIT4
+#define B_PCH_SATA_AHCI_PXIE_SDBE BIT3
+#define B_PCH_SATA_AHCI_PXIE_DSE BIT2
+#define B_PCH_SATA_AHCI_PXIE_PSE BIT1
+#define B_PCH_SATA_AHCI_PXIE_DHRE BIT0
+#define R_PCH_SATA_AHCI_P0CMD 0x118
+#define R_PCH_SATA_AHCI_P1CMD 0x198
+#define R_PCH_SATA_AHCI_P2CMD 0x218
+#define R_PCH_SATA_AHCI_P3CMD 0x298
+#define R_PCH_SATA_AHCI_P4CMD 0x318
+#define R_PCH_SATA_AHCI_P5CMD 0x398
+#define R_PCH_SATA_AHCI_P6CMD 0x418
+#define R_PCH_SATA_AHCI_P7CMD 0x498
+#define B_PCH_SATA_AHCI_PxCMD_ICC (BIT31 | BIT30 | BIT29 | BIT28)
+#define B_PCH_SATA_AHCI_PxCMD_MASK (BIT27 | BIT26 | BIT22 | BIT21 | BIT19 | BIT18)
+#define B_PCH_SATA_AHCI_PxCMD_ASP BIT27
+#define B_PCH_SATA_AHCI_PxCMD_ALPE BIT26
+#define B_PCH_SATA_AHCI_PxCMD_DLAE BIT25
+#define B_PCH_SATA_AHCI_PxCMD_ATAPI BIT24
+#define B_PCH_SATA_AHCI_PxCMD_APSTE BIT23
+#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1
+#define R_PCH_SATA_AHCI_P0DEVSLP 0x144
+#define R_PCH_SATA_AHCI_P1DEVSLP 0x1C4
+#define R_PCH_SATA_AHCI_P2DEVSLP 0x244
+#define R_PCH_SATA_AHCI_P3DEVSLP 0x2C4
+#define R_PCH_SATA_AHCI_P4DEVSLP 0x344
+#define R_PCH_SATA_AHCI_P5DEVSLP 0x3C4
+#define R_PCH_SATA_AHCI_P6DEVSLP 0x444
+#define R_PCH_SATA_AHCI_P7DEVSLP 0x4C4
+#define B_PCH_SATA_AHCI_PxDEVSLP_DSP BIT1
+#define B_PCH_SATA_AHCI_PxDEVSLP_ADSE BIT0
+#define B_PCH_SATA_AHCI_PxDEVSLP_DITO_MASK 0x01FF8000
+#define V_PCH_SATA_AHCI_PxDEVSLP_DITO_625 0x01388000
+#define B_PCH_SATA_AHCI_PxDEVSLP_DM_MASK 0x1E000000
+#define V_PCH_SATA_AHCI_PxDEVSLP_DM_16 0x1E000000
+#define B_PCH_SATA_AHCI_PxCMD_ESP BIT21 ///< Used with an external SATA device
+#define B_PCH_SATA_AHCI_PxCMD_MPSP BIT19 ///< Mechanical Switch Attached to Port
+#define B_PCH_SATA_AHCI_PxCMD_HPCP BIT18 ///< Hotplug capable
+#define B_PCH_SATA_AHCI_PxCMD_CR BIT15
+#define B_PCH_SATA_AHCI_PxCMD_FR BIT14
+#define B_PCH_SATA_AHCI_PxCMD_ISS BIT13
+#define B_PCH_SATA_AHCI_PxCMD_CCS 0x00001F00
+#define B_PCH_SATA_AHCI_PxCMD_FRE BIT4
+#define B_PCH_SATA_AHCI_PxCMD_CLO BIT3
+#define B_PCH_SATA_AHCI_PxCMD_POD BIT2
+#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1
+#define B_PCH_SATA_AHCI_PxCMD_ST BIT0
+#define R_PCH_SATA_AHCI_P0TFD 0x120
+#define R_PCH_SATA_AHCI_P1TFD 0x1A0
+#define R_PCH_SATA_AHCI_P2TFD 0x220
+#define R_PCH_SATA_AHCI_P3TFD 0x2A0
+#define R_PCH_SATA_AHCI_P4TFD 0x320
+#define R_PCH_SATA_AHCI_P5TFD 0x3A0
+#define R_PCH_SATA_AHCI_P6TFD 0x420
+#define B_PCH_SATA_AHCI_PXTFD_ERR 0x0000FF00
+#define B_PCH_SATA_AHCI_PXTFD_STS 0x000000FF
+#define R_PCH_SATA_AHCI_P0SIG 0x124
+#define R_PCH_SATA_AHCI_P1SIG 0x1A4
+#define R_PCH_SATA_AHCI_P2SIG 0x224
+#define R_PCH_SATA_AHCI_P3SIG 0x2A4
+#define R_PCH_SATA_AHCI_P4SIG 0x324
+#define R_PCH_SATA_AHCI_P5SIG 0x3A4
+#define R_PCH_SATA_AHCI_P6SIG 0x424
+#define B_PCH_SATA_AHCI_PXSIG_LBA_HR 0xFF000000
+#define B_PCH_SATA_AHCI_PXSIG_LBA_MR 0x00FF0000
+#define B_PCH_SATA_AHCI_PXSIG_LBA_LR 0x0000FF00
+#define B_PCH_SATA_AHCI_PXSIG_SCR 0x000000FF
+#define R_PCH_SATA_AHCI_P0SSTS 0x128
+#define R_PCH_SATA_AHCI_P1SSTS 0x1A8
+#define R_PCH_SATA_AHCI_P2SSTS 0x228
+#define R_PCH_SATA_AHCI_P3SSTS 0x2A8
+#define R_PCH_SATA_AHCI_P4SSTS 0x328
+#define R_PCH_SATA_AHCI_P5SSTS 0x3A8
+#define R_PCH_SATA_AHCI_P6SSTS 0x428
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_0 0x00000000
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_1 0x00000100
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_2 0x00000200
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_6 0x00000600
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_0 0x00000000
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_1 0x00000010
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_2 0x00000020
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_3 0x00000030
+#define B_PCH_SATA_AHCI_PXSSTS_DET_0 0x00000000
+#define B_PCH_SATA_AHCI_PXSSTS_DET_1 0x00000001
+#define B_PCH_SATA_AHCI_PXSSTS_DET_3 0x00000003
+#define B_PCH_SATA_AHCI_PXSSTS_DET_4 0x00000004
+#define R_PCH_SATA_AHCI_P0SCTL 0x12C
+#define R_PCH_SATA_AHCI_P1SCTL 0x1AC
+#define R_PCH_SATA_AHCI_P2SCTL 0x22C
+#define R_PCH_SATA_AHCI_P3SCTL 0x2AC
+#define R_PCH_SATA_AHCI_P4SCTL 0x32C
+#define R_PCH_SATA_AHCI_P5SCTL 0x3AC
+#define R_PCH_SATA_AHCI_P6SCTL 0x42C
+#define B_PCH_SATA_AHCI_PXSCTL_IPM 0x00000F00
+#define V_PCH_SATA_AHCI_PXSCTL_IPM_0 0x00000000
+#define V_PCH_SATA_AHCI_PXSCTL_IPM_1 0x00000100
+#define V_PCH_SATA_AHCI_PXSCTL_IPM_2 0x00000200
+#define V_PCH_SATA_AHCI_PXSCTL_IPM_3 0x00000300
+#define B_PCH_SATA_AHCI_PXSCTL_SPD 0x000000F0
+#define V_PCH_SATA_AHCI_PXSCTL_SPD_0 0x00000000
+#define V_PCH_SATA_AHCI_PXSCTL_SPD_1 0x00000010
+#define V_PCH_SATA_AHCI_PXSCTL_SPD_2 0x00000020
+#define V_PCH_SATA_AHCI_PXSCTL_SPD_3 0x00000030
+#define B_PCH_SATA_AHCI_PXSCTL_DET 0x0000000F
+#define V_PCH_SATA_AHCI_PXSCTL_DET_0 0x00000000
+#define V_PCH_SATA_AHCI_PXSCTL_DET_1 0x00000001
+#define V_PCH_SATA_AHCI_PXSCTL_DET_4 0x00000004
+#define R_PCH_SATA_AHCI_P0SERR 0x130
+#define R_PCH_SATA_AHCI_P1SERR 0x1B0
+#define R_PCH_SATA_AHCI_P2SERR 0x230
+#define R_PCH_SATA_AHCI_P3SERR 0x2B0
+#define R_PCH_SATA_AHCI_P4SERR 0x330
+#define R_PCH_SATA_AHCI_P5SERR 0x3B0
+#define R_PCH_SATA_AHCI_P6SERR 0x430
+#define B_PCH_SATA_AHCI_PXSERR_EXCHG BIT26
+#define B_PCH_SATA_AHCI_PXSERR_UN_FIS_TYPE BIT25
+#define B_PCH_SATA_AHCI_PXSERR_TRSTE_24 BIT24
+#define B_PCH_SATA_AHCI_PXSERR_TRSTE_23 BIT23
+#define B_PCH_SATA_AHCI_PXSERR_HANDSHAKE BIT22
+#define B_PCH_SATA_AHCI_PXSERR_CRC_ERROR BIT21
+#define B_PCH_SATA_AHCI_PXSERR_10B8B_DECERR BIT19
+#define B_PCH_SATA_AHCI_PXSERR_COMM_WAKE BIT18
+#define B_PCH_SATA_AHCI_PXSERR_PHY_ERROR BIT17
+#define B_PCH_SATA_AHCI_PXSERR_PHY_RDY_CHG BIT16
+#define B_PCH_SATA_AHCI_PXSERR_INTRNAL_ERR BIT11
+#define B_PCH_SATA_AHCI_PXSERR_PROTOCOL_ERR BIT10
+#define B_PCH_SATA_AHCI_PXSERR_PCDIE BIT9
+#define B_PCH_SATA_AHCI_PXSERR_TDIE BIT8
+#define B_PCH_SATA_AHCI_PXSERR_RCE BIT1
+#define B_PCH_SATA_AHCI_PXSERR_RDIE BIT0
+#define R_PCH_SATA_AHCI_P0SACT 0x134
+#define R_PCH_SATA_AHCI_P1SACT 0x1B4
+#define R_PCH_SATA_AHCI_P2SACT 0x234
+#define R_PCH_SATA_AHCI_P3SACT 0x2B4
+#define R_PCH_SATA_AHCI_P4SACT 0x334
+#define R_PCH_SATA_AHCI_P5SACT 0x3B4
+#define R_PCH_SATA_AHCI_P6SACT 0x434
+#define B_PCH_SATA_AHCI_PXSACT_DS 0xFFFFFFFF
+#define R_PCH_SATA_AHCI_P0CI 0x138
+#define R_PCH_SATA_AHCI_P1CI 0x1B8
+#define R_PCH_SATA_AHCI_P2CI 0x238
+#define R_PCH_SATA_AHCI_P3CI 0x2B8
+#define R_PCH_SATA_AHCI_P4CI 0x338
+#define R_PCH_SATA_AHCI_P5CI 0x3B8
+#define R_PCH_SATA_AHCI_P6CI 0x438
+#define B_PCH_SATA_AHCI_PXCI 0xFFFFFFFF
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsScs.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsScs.h
new file mode 100644
index 0000000000..9684a6d259
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsScs.h
@@ -0,0 +1,152 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_SCS_H_
+#define _PCH_REGS_SCS_H_
+
+//
+// SCS Devices PCI Config Space Registers
+//
+#define R_PCH_SCS_DEV_PCS 0x84 ///< PME Control Status
+#define B_PCH_SCS_DEV_PCS_PMESTS BIT15 ///< PME Status
+#define B_PCH_SCS_DEV_PCS_PMEEN BIT8 ///< PME Enable
+#define B_PCH_SCS_DEV_PCS_NSS BIT3 ///< No Soft Reset
+#define B_PCH_SCS_DEV_PCS_PS (BIT1 | BIT0) ///< Power State
+#define B_PCH_SCS_DEV_PCS_PS_D3HOT (BIT1 | BIT0) ///< Power State: D3Hot State
+#define R_PCH_SCS_DEV_PG_CONFIG 0xA2 ///< PG Config
+#define B_PCH_SCS_DEV_PG_CONFIG_SE BIT3 ///< Sleep Enable
+#define B_PCH_SCS_DEV_PG_CONFIG_PGE BIT2 ///< PG Enable
+#define B_PCH_SCS_DEV_PG_CONFIG_I3E BIT1 ///< I3 Enable
+#define B_PCH_SCS_DEV_PG_CONFIG_PMCRE BIT0 ///< PMC Request Enable
+#define V_PCH_SCS_DEV_BAR0_SIZE 0x1000 ///< BAR0 size
+//
+// SCS Devices MMIO Space Register
+//
+#define R_PCH_SCS_DEV_MEM_DMAADR 0x00
+#define R_PCH_SCS_DEV_MEM_BLKSZ 0x04
+#define R_PCH_SCS_DEV_MEM_BLKCNT 0x06
+#define R_PCH_SCS_DEV_MEM_CMDARG 0x08
+#define R_PCH_SCS_DEV_MEM_XFRMODE 0x0C
+#define B_PCH_SCS_DEV_MEM_XFRMODE_DMA_EN BIT0
+#define B_PCH_SCS_DEV_MEM_XFRMODE_BLKCNT_EN BIT1
+#define B_PCH_SCS_DEV_MEM_XFRMODE_AUTOCMD_EN_MASK (BIT2 | BIT3)
+#define V_PCH_SCS_DEV_MEM_XFRMODE_AUTOCMD12_EN 1
+#define B_PCH_SCS_DEV_MEM_XFRMODE_DATA_TRANS_DIR BIT4 ///< 1: Read (Card to Host), 0: Write (Host to Card)
+#define B_PCH_SCS_DEV_MEM_XFRMODE_MULTI_SINGLE_BLK BIT5 ///< 1: Multiple Block, 0: Single Block
+#define R_PCH_SCS_DEV_MEM_SDCMD 0x0E
+#define B_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_MASK (BIT0 | BIT1)
+#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_NO_RESP 0
+#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP136 1
+#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP48 2
+#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP48_CHK 3
+#define B_PCH_SCS_DEV_MEM_SDCMD_CMD_CRC_CHECK_EN BIT3
+#define B_PCH_SCS_DEV_MEM_SDCMD_CMD_INDEX_CHECK_EN BIT4
+#define B_PCH_SCS_DEV_MEM_SDCMD_DATA_PRESENT_SEL BIT5
+#define R_PCH_SCS_DEV_MEM_RESP 0x10
+#define R_PCH_SCS_DEV_MEM_BUFDATAPORT 0x20
+#define R_PCH_SCS_DEV_MEM_PSTATE 0x24
+#define B_PCH_SCS_DEV_MEM_PSTATE_DAT0 BIT20
+#define R_PCH_SCS_DEV_MEM_PWRCTL 0x29
+#define R_PCH_SCS_DEV_MEM_CLKCTL 0x2C
+#define R_PCH_SCS_DEV_MEM_TIMEOUT_CTL 0x2E ///< Timeout Control
+#define B_PCH_SCS_DEV_MEM_TIMEOUT_CTL_DTCV 0x0F ///< Data Timeout Counter Value
+#define R_PCH_SCS_DEV_MEM_SWRST 0x2F
+#define B_PCH_SCS_DEV_MEM_SWRST_CMDLINE BIT1
+#define B_PCH_SCS_DEV_MEM_SWRST_DATALINE BIT2
+#define R_PCH_SCS_DEV_MEM_NINTSTS 0x30
+#define B_PCH_SCS_DEV_MEM_NINTSTS_MASK 0xFFFF
+#define B_PCH_SCS_DEV_MEM_NINTSTS_CLEAR_MASK 0x60FF
+#define B_PCH_SCS_DEV_MEM_NINTSTS_CMD_COMPLETE BIT0
+#define B_PCH_SCS_DEV_MEM_NINTSTS_TRANSFER_COMPLETE BIT1
+#define B_PCH_SCS_DEV_MEM_NINTSTS_DMA_INTERRUPT BIT3
+#define B_PCH_SCS_DEV_MEM_NINTSTS_BUF_READ_READY_INTR BIT5
+#define R_PCH_SCS_DEV_MEM_ERINTSTS 0x32
+#define B_PCH_SCS_DEV_MEM_ERINTSTS_MASK 0x13FF
+#define B_PCH_SCS_DEV_MEM_ERINTSTS_CLEAR_MASK 0x13FF
+#define R_PCH_SCS_DEV_MEM_NINTEN 0x34
+#define B_PCH_SCS_DEV_MEM_NINTEN_MASK 0x7FFF
+#define R_PCH_SCS_DEV_MEM_ERINTEN 0x36
+#define B_PCH_SCS_DEV_MEM_ERINTEN_MASK 0x13FF
+#define R_PCH_SCS_DEV_MEM_NINTSIGNEN 0x38
+#define B_PCH_SCS_DEV_MEM_NINTSIGNEN_MASK 0x7FFF
+#define R_PCH_SCS_DEV_MEM_ERINTSIGNEN 0x3A
+#define B_PCH_SCS_DEV_MEM_ERINTSIGNEN_MASK 0x13FF
+#define R_PCH_SCS_DEV_MEM_HOST_CTL2 0x3E
+#define B_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_MASK (BIT0 | BIT1 | BIT2)
+#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_HS400 5
+#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_DDR50 4
+#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_SDR104 3
+#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_SDR25 1
+#define R_PCH_SCS_DEV_MEM_CAP1 0x40
+#define R_PCH_SCS_DEV_MEM_CAP2 0x44
+#define B_PCH_SCS_DEV_MEM_CAP2_HS400_SUPPORT BIT31
+#define B_PCH_SCS_DEV_MEM_CAP2_SDR104_SUPPORT BIT1
+#define R_PCH_SCS_DEV_MEM_CESHC2 0x3C ///< Auto CMD12 Error Status Register & Host Control 2
+#define B_PCH_SCS_DEV_MEM_CESHC2_ASYNC_INT BIT30 ///< Asynchronous Interrupt Enable
+#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_CONTROL 0x810
+#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_CONTROL_EN 0x5A
+#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1 0x814
+#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_EMMC_DEFAULTS 0x3C80EB1E
+#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SDIO_DEFAULTS 0x1C80EF1E
+#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SDCARD_DEFAULTS 0x1C80E75C
+#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_HS400 BIT29
+#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ (BIT27 | BIT26 | BIT25 | BIT24 | BIT23 | BIT22)
+#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ 22
+#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ 0x1
+#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT (BIT20 | BIT19 | BIT18 | BIT17)
+#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT 17
+#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT 0x8
+#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE (BIT12 | BIT11)
+#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE 11
+#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE_EMBEDDED 0x1
+#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2 0x818
+#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_EMMC_DEFAULTS 0x040040C8
+#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_SDIO_DEFAULTS 0x040000C8
+#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_SDCARD_DEFAULTS 0x040000C8
+#define R_PCH_SCS_DEV_MEM_TX_CMD_DLL_CNTL1 0x820
+#define R_PCH_SCS_DEV_MEM_TX_CMD_DLL_CNTL2 0x80C
+#define R_PCH_SCS_DEV_MEM_TX_DATA_DLL_CNTL1 0x824
+#define R_PCH_SCS_DEV_MEM_TX_DATA_DLL_CNTL2 0x828
+#define R_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL1 0x82C
+#define R_PCH_SCS_DEV_MEM_RX_STROBE_DLL_CNTL 0x830
+#define R_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2 0x834
+#define N_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX 16
+#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_AUTO 0x2
+#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_BEFORE 0x1
+#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_AFTER 0x0
+
+//
+// SCS Private Configuration Space Registers
+//
+#define R_PCH_PCR_SCS_IOSFCTL 0x00 ///< IOSF Control
+#define B_PCH_PCR_SCS_IOSFCTL_NSNPDIS BIT7 ///< Non-Snoop Disable
+#define B_PCH_PCR_SCS_IOSFCTL_MAX_RD_PEND (BIT3 | BIT2 | BIT1 | BIT0) ///< Max upstream pending reads
+#define R_PCH_PCR_SCS_OCPCTL 0x10 ///< OCP Control
+#define B_PCH_PCR_SCS_OCPCTL_NPEN BIT0 ///< Downstream non-posted memory write capability
+#define R_PCH_PCR_SCS_PMCTL 0x1D0 ///< Power Management Control
+#define R_PCH_PCR_SCS_PCICFGCTR1 0x200 ///< PCI Configuration Control 1 - eMMC
+#define R_PCH_PCR_SCS_PCICFGCTR2 0x204 ///< PCI Configuration Control 2 - SDIO
+#define R_PCH_PCR_SCS_PCICFGCTR3 0x208 ///< PCI Configuration Control 3 - SD Card
+#define B_PCH_PCR_SCS_PCICFGCTR_PCI_IRQ 0x0FF00000 ///< PCI IRQ number
+#define N_PCH_PCR_SCS_PCICFGCTR_PCI_IRQ 20
+#define B_PCH_PCR_SCS_PCICFGCTR_ACPI_IRQ 0x000FF000 ///< ACPI IRQ number
+#define N_PCH_PCR_SCS_PCICFGCTR_ACPI_IRQ 12
+#define B_PCH_PCR_SCS_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | BIT8) ///< Interrupt Pin
+#define N_PCH_PCR_SCS_PCICFGCTR_IPIN1 8
+#define B_PCH_PCR_SCS_PCICFGCTR_BAR1DIS BIT7 ///< BAR 1 Disable
+#define B_PCH_PCR_SCS_PCICFGCTR_PS 0x7C ///< PME Support
+#define B_PCH_PCR_SCS_PCICFGCTR_ACPI_INT_EN BIT1 ///< ACPI Interrupt Enable
+#define B_PCH_PCR_SCS_PCICFGCTR_PCI_CFG_DIS BIT0 ///< PCI Configuration Space Disable
+
+#define R_PCH_PCR_SCS_GPPRVRW1 0x600 ///< Clock Gating Control
+#define R_PCH_PCR_SCS_GPPRVRW2 0x604 ///< Host Controller Disable
+#define B_PCH_PCR_SCS_GPPRVRW2_EMMC_DIS BIT1 ///< eMMC Host Controller Disable
+#define B_PCH_PCR_SCS_GPPRVRW2_SDIO_SDCARD_DIS BIT2 ///< 1: SDIO Host Controller Disable, 0: SDCARD Host Controller Disable
+#define R_PCH_PCR_SCS_GPPRVRW6 0x614 ///< 1.8V Signal Select Delay Control
+#define V_PCH_PCR_SCS_GPPRVRW6_1P8_SEL_DELAY 0x7F ///< Rcomp SDCARD 10ms delay during switch
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h
new file mode 100644
index 0000000000..3142e702f2
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h
@@ -0,0 +1,282 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_SERIAL_IO_
+#define _PCH_REGS_SERIAL_IO_
+
+
+//
+// Serial IO I2C0 Controller Registers (D21:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0 21
+#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0 0
+#define V_PCH_LP_SERIAL_IO_I2C0_SKL_DEVICE_ID 0x9D60
+#define V_PCH_H_SERIAL_IO_I2C0_SKL_DEVICE_ID 0xA160
+
+//
+// Serial IO I2C1 Controller Registers (D21:F1)
+//
+#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1 21
+#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1 1
+#define V_PCH_LP_SERIAL_IO_I2C1_SKL_DEVICE_ID 0x9D61
+#define V_PCH_H_SERIAL_IO_I2C1_SKL_DEVICE_ID 0xA161
+
+//
+// Serial IO I2C2 Controller Registers (D21:F2)
+//
+#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2 21
+#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2 2
+#define V_PCH_LP_SERIAL_IO_I2C2_SKL_DEVICE_ID 0x9D62
+#define V_PCH_H_SERIAL_IO_I2C2_SKL_DEVICE_ID 0xA162
+
+//
+// Serial IO I2C3 Controller Registers (D21:F3)
+//
+#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3 21
+#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3 3
+#define V_PCH_LP_SERIAL_IO_I2C3_SKL_DEVICE_ID 0x9D63
+#define V_PCH_H_SERIAL_IO_I2C3_SKL_DEVICE_ID 0xA163
+
+//
+// Serial IO I2C4 Controller Registers (D25:F2)
+//
+#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4 25
+#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4 2
+#define V_PCH_LP_SERIAL_IO_I2C4_SKL_DEVICE_ID 0x9D64
+
+//
+// Serial IO I2C5 Controller Registers (D25:F1)
+//
+#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5 25
+#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5 1
+#define V_PCH_LP_SERIAL_IO_I2C5_SKL_DEVICE_ID 0x9D65
+
+//
+// Serial IO SPI0 Controller Registers (D30:F2)
+//
+#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0 30
+#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0 2
+#define V_PCH_LP_SERIAL_IO_SPI0_SKL_DEVICE_ID 0x9D29
+#define V_PCH_H_SERIAL_IO_SPI0_SKL_DEVICE_ID 0xA129
+
+//
+// Serial IO SPI1 Controller Registers (D30:F3)
+//
+#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1 30
+#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1 3
+#define V_PCH_LP_SERIAL_IO_SPI1_SKL_DEVICE_ID 0x9D2A
+#define V_PCH_H_SERIAL_IO_SPI1_SKL_DEVICE_ID 0xA129
+
+//
+// Serial IO UART0 Controller Registers (D30:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0 30
+#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0 0
+#define V_PCH_LP_SERIAL_IO_UART0_SKL_DEVICE_ID 0x9D28
+#define V_PCH_H_SERIAL_IO_UART0_SKL_DEVICE_ID 0xA128
+
+//
+// Serial IO UART1 Controller Registers (D30:F1)
+//
+#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1 30
+#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1 1
+#define V_PCH_LP_SERIAL_IO_UART1_SKL_DEVICE_ID 0x9D66
+#define V_PCH_H_SERIAL_IO_UART1_SKL_DEVICE_ID 0xA166
+
+#define V_PCH_SERIAL_IO_DEV_MIN_FUN 0
+#define V_PCH_SERIAL_IO_DEV_MAX_FUN 5
+
+//
+// Serial IO Controllers General PCI Configuration Registers
+// registers accessed using PciD21FxRegBase + offset
+//
+#define R_PCH_SERIAL_IO_BAR0_LOW 0x10
+#define B_PCH_SERIAL_IO_BAR0_LOW_BAR 0xFFFFF000
+#define R_PCH_SERIAL_IO_BAR0_HIGH 0x14
+#define R_PCH_SERIAL_IO_BAR1_LOW 0x18
+#define B_PCH_SERIAL_IO_BAR1_LOW_BAR 0xFFFFF000
+#define R_PCH_SERIAL_IO_BAR1_HIGH 0x1C
+#define V_PCH_SERIAL_IO_BAR_SIZE (4 * 1024)
+#define N_PCH_SERIAL_IO_BAR_ALIGNMENT 12
+
+#define R_PCH_SERIAL_IO_PME_CTRL_STS 0x84
+#define B_PCH_SERIAL_IO_PME_CTRL_STS_PWR_ST (BIT1| BIT0)
+
+#define R_PCH_SERIAL_IO_D0I3MAXDEVPG 0xA0
+#define B_PCH_SERIAL_IO_D0I3MAXDEVPG_PMCRE BIT16
+#define B_PCH_SERIAL_IO_D0I3MAXDEVPG_I3E BIT17
+#define B_PCH_SERIAL_IO_D0I3MAXDEVPG_PGE BIT18
+
+#define R_PCH_SERIAL_IO_INTERRUPTREG 0x3C
+#define B_PCH_SERIAL_IO_INTERRUPTREG_INTLINE 0x000000FF
+
+//
+// Serial IO Controllers Private Registers
+// registers accessed : BAR0 + offset
+//
+#define R_PCH_SERIAL_IO_SSCR1 0x4
+#define B_PCH_SERIAL_IO_SSCR1_IFS BIT16
+
+#define R_PCH_SERIAL_IO_PPR_CLK 0x200
+#define B_PCH_SERIAL_IO_PPR_CLK_EN BIT0
+#define B_PCH_SERIAL_IO_PPR_CLK_UPDATE BIT31
+#define V_PCH_SERIAL_IO_PPR_CLK_M_DIV 0x30
+#define V_PCH_SERIAL_IO_PPR_CLK_N_DIV 0xC35
+
+#define R_PCH_SERIAL_IO_PPR_RESETS 0x204
+#define B_PCH_SERIAL_IO_PPR_RESETS_FUNC BIT0
+#define B_PCH_SERIAL_IO_PPR_RESETS_APB BIT1
+#define B_PCH_SERIAL_IO_PPR_RESETS_IDMA BIT2
+
+#define R_PCH_SERIAL_IO_ACTIVE_LTR 0x210
+#define R_PCH_SERIAL_IO_IDLE_LTR 0x214
+#define B_PCH_SERIAL_IO_LTR_SNOOP_VALUE 0x000003FF
+#define B_PCH_SERIAL_IO_LTR_SNOOP_SCALE 0x00001C00
+#define B_PCH_SERIAL_IO_LTR_SNOOP_REQUIREMENT BIT15
+
+#define R_PCH_SERIAL_IO_SPI_CS_CONTROL 0x224
+#define B_PCH_SERIAL_IO_SPI_CS_CONTROL_STATE BIT1
+#define B_PCH_SERIAL_IO_SPI_CS_CONTROL_MODE BIT0
+
+#define R_PCH_SERIAL_IO_REMAP_ADR_LOW 0x240
+#define R_PCH_SERIAL_IO_REMAP_ADR_HIGH 0x244
+
+#define R_PCH_SERIAL_IO_I2C_SDA_HOLD 0x7C
+#define V_PCH_SERIAL_IO_I2C_SDA_HOLD_VALUE 0x002C002C
+
+//
+// I2C Controller
+// Registers accessed through BAR0 + offset
+//
+#define R_IC_CON 0x00 // I2c Control
+#define B_IC_MASTER_MODE BIT0
+#define B_IC_RESTART_EN BIT5
+#define B_IC_SLAVE_DISABLE BIT6
+#define V_IC_SPEED_STANDARD 0x02
+#define V_IC_SPEED_FAST 0x04
+#define V_IC_SPEED_HIGH 0x06
+
+#define R_IC_TAR 0x04 // I2c Target Address
+#define B_IC_TAR_10BITADDR_MASTER BIT12
+
+#define R_IC_DATA_CMD 0x10 // I2c Rx/Tx Data Buffer and Command
+#define B_IC_CMD_READ BIT8 // 1 = read, 0 = write
+#define B_IC_CMD_STOP BIT9 // 1 = STOP
+#define B_IC_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
+#define V_IC_WRITE_CMD_MASK 0xFF
+
+#define R_IC_SS_SCL_HCNT 0x14 // Standard Speed I2c Clock SCL High Count
+#define R_IC_SS_SCL_LCNT 0x18 // Standard Speed I2c Clock SCL Low Count
+#define R_IC_FS_SCL_HCNT 0x1C // Full Speed I2c Clock SCL High Count
+#define R_IC_FS_SCL_LCNT 0x20 // Full Speed I2c Clock SCL Low Count
+#define R_IC_HS_SCL_HCNT 0x24 // High Speed I2c Clock SCL High Count
+#define R_IC_HS_SCL_LCNT 0x28 // High Speed I2c Clock SCL Low Count
+#define R_IC_INTR_STAT 0x2C // I2c Inetrrupt Status
+#define R_IC_INTR_MASK 0x30 // I2c Interrupt Mask
+#define B_IC_INTR_GEN_CALL BIT11 // General call received
+#define B_IC_INTR_START_DET BIT10
+#define B_IC_INTR_STOP_DET BIT9
+#define B_IC_INTR_ACTIVITY BIT8
+#define B_IC_INTR_TX_ABRT BIT6 // Set on NACK
+#define B_IC_INTR_TX_EMPTY BIT4
+#define B_IC_INTR_TX_OVER BIT3
+#define B_IC_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
+#define B_IC_INTR_RX_OVER BIT1
+#define B_IC_INTR_RX_UNDER BIT0
+#define R_IC_RAW_INTR_STAT ( 0x34) // I2c Raw Interrupt Status
+#define R_IC_RX_TL ( 0x38) // I2c Receive FIFO Threshold
+#define R_IC_TX_TL ( 0x3C) // I2c Transmit FIFO Threshold
+#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts
+#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt
+#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt
+#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt
+#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt
+#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt
+#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt
+#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt
+#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt
+#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt
+#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt
+#define R_IC_ENABLE ( 0x6C) // I2c Enable
+
+#define R_IC_STATUS 0x70 // I2c Status
+#define B_IC_STATUS_RFF BIT4 // RX FIFO is completely full
+#define B_IC_STATUS_RFNE BIT3 // RX FIFO is not empty
+#define B_IC_STATUS_TFE BIT2 // TX FIFO is completely empty
+#define B_IC_STATUS_TFNF BIT1 // TX FIFO is not full
+#define B_IC_STATUS_ACTIVITY BIT0 // Controller Activity Status.
+
+#define R_IC_TXFL R ( 0x74) // Transmit FIFO Level Register
+#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register
+#define R_IC_SDA_HOLD ( 0x7C)
+#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2c Transmit Abort Status Register
+#define B_IC_TX_ABRT_7B_ADDR_NACK BIT0 // NACK on 7-bit address
+
+#define R_IC_SDA_SETUP ( 0x94) // I2c SDA Setup Register
+#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2c ACK General Call Register
+#define R_IC_ENABLE_STATUS ( 0x9C) // I2c Enable Status Register
+#define B_IC_EN BIT0 // I2c enable status
+
+#define R_IC_CLK_GATE (0xC0)
+#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register
+#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID
+#define R_IC_COMP_TYPE ( 0xFC) // Component Type
+
+
+
+//
+// Bridge Private Configuration Registers
+// accessed only through SB messaging. SB access = SerialIo IOSF2OCP Bridge Port ID + offset
+//
+#define R_PCH_PCR_SERIAL_IO_PMCTL 0x1D0
+#define V_PCH_PCR_SERIAL_IO_PMCTL_PWR_GATING 0x3F
+
+#define R_PCH_PCR_SERIAL_IO_PCICFGCTRLx 0x200
+#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_N_OFFS 0x04
+#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL1 0x200 //I2C0
+#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL2 0x204 //I2C1
+#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL3 0x208 //I2C2
+#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL4 0x20C //I2C3
+#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL5 0x210 //I2C4
+#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL6 0x214 //I2C5
+#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL9 0x218 //UA00
+#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL10 0x21C //UA01
+#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL11 0x220 //UA02
+#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL13 0x224 //SPI0
+#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL14 0x228 //SPI1
+
+#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_PCI_CFG_DIS BIT0
+#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_ACPI_INTR_EN BIT1
+#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_BAR1_DIS BIT7
+#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_INT_PIN (BIT11 | BIT10 | BIT9 | BIT8)
+#define N_PCH_PCR_SERIAL_IO_PCICFGCTRL_INT_PIN 8
+#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTA 0x01
+#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTB 0x02
+#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTC 0x03
+#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTD 0x04
+#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_ACPI_IRQ 0x000FF000
+#define N_PCH_PCR_SERIAL_IO_PCICFGCTRL_ACPI_IRQ 12
+#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_PCI_IRQ 0x0FF00000
+#define N_PCH_PCR_SERIAL_IO_PCICFGCTRL_PCI_IRQ 20
+
+#define R_PCH_PCR_SERIAL_IO_GPPRVRW2 0x604
+#define V_PCH_PCR_SERIAL_IO_GPPRVRW2_CLK_GATING (BIT11 | BIT1)
+
+#define R_PCH_PCR_SERIAL_IO_GPPRVRW7 0x618
+#define B_PCH_PCR_SERIAL_IO_GPPRVRW7_UART0_BYTE_ADDR_EN BIT0
+#define B_PCH_PCR_SERIAL_IO_GPPRVRW7_UART1_BYTE_ADDR_EN BIT1
+#define B_PCH_PCR_SERIAL_IO_GPPRVRW7_UART2_BYTE_ADDR_EN BIT2
+
+//
+// Number of pins used by SerialIo controllers
+//
+#define PCH_SERIAL_IO_PINS_PER_I2C_CONTROLLER 2
+#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4
+#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2
+#define PCH_SERIAL_IO_PINS_PER_SPI_CONTROLLER 4
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSmbus.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSmbus.h
new file mode 100644
index 0000000000..1f0912bec8
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSmbus.h
@@ -0,0 +1,134 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_SMBUS_H_
+#define _PCH_REGS_SMBUS_H_
+
+//
+// SMBus Controller Registers (D31:F4)
+//
+#define PCI_DEVICE_NUMBER_PCH_SMBUS 31
+#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4
+#define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_SMBUS_DEVICE_ID 0xA123
+//
+// LBG Production SMBus Controller Device ID
+//
+#define V_PCH_LBG_PROD_SMBUS_DEVICE_ID 0xA1A3
+//
+// LBG SSX (Super SKU) SMBus Controller Device ID
+//
+#define V_PCH_LBG_SMBUS_DEVICE_ID 0xA223
+#define V_PCH_LP_SMBUS_DEVICE_ID 0x9D23
+#define R_PCH_SMBUS_BASE 0x20
+#define V_PCH_SMBUS_BASE_SIZE (1 << 5)
+#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0
+#define R_PCH_SMBUS_HOSTC 0x40
+#define B_PCH_SMBUS_HOSTC_SPDWD BIT4
+#define B_PCH_SMBUS_HOSTC_SSRESET BIT3
+#define B_PCH_SMBUS_HOSTC_I2C_EN BIT2
+#define B_PCH_SMBUS_HOSTC_SMI_EN BIT1
+#define B_PCH_SMBUS_HOSTC_HST_EN BIT0
+#define R_PCH_SMBUS_TCOBASE 0x50
+#define B_PCH_SMBUS_TCOBASE_BAR 0x0000FFE0
+#define R_PCH_SMBUS_TCOCTL 0x54
+#define B_PCH_SMBUS_TCOCTL_TCO_BASE_EN BIT8
+#define B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK BIT0
+#define R_PCH_SMBUS_64 0x64
+#define R_PCH_SMBUS_80 0x80
+
+//
+// SMBus I/O Registers
+//
+#define R_PCH_SMBUS_HSTS 0x00 ///< Host Status Register R/W
+#define B_PCH_SMBUS_HBSY 0x01
+#define B_PCH_SMBUS_INTR 0x02
+#define B_PCH_SMBUS_DERR 0x04
+#define B_PCH_SMBUS_BERR 0x08
+#define B_PCH_SMBUS_FAIL 0x10
+#define B_PCH_SMBUS_SMBALERT_STS 0x20
+#define B_PCH_SMBUS_IUS 0x40
+#define B_PCH_SMBUS_BYTE_DONE_STS 0x80
+#define B_PCH_SMBUS_ERROR (B_PCH_SMBUS_DERR | B_PCH_SMBUS_BERR | B_PCH_SMBUS_FAIL)
+#define B_PCH_SMBUS_HSTS_ALL 0xFF
+#define R_PCH_SMBUS_HCTL 0x02 ///< Host Control Register R/W
+#define B_PCH_SMBUS_INTREN 0x01
+#define B_PCH_SMBUS_KILL 0x02
+#define B_PCH_SMBUS_SMB_CMD 0x1C
+#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00
+#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04
+#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08
+#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C
+#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10
+#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14
+#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18
+#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C
+#define B_PCH_SMBUS_LAST_BYTE 0x20
+#define B_PCH_SMBUS_START 0x40
+#define B_PCH_SMBUS_PEC_EN 0x80
+#define R_PCH_SMBUS_HCMD 0x03 ///< Host Command Register R/W
+#define R_PCH_SMBUS_TSA 0x04 ///< Transmit Slave Address Register R/W
+#define B_PCH_SMBUS_RW_SEL 0x01
+#define B_PCH_SMBUS_READ 0x01 // RW
+#define B_PCH_SMBUS_WRITE 0x00 // RW
+#define B_PCH_SMBUS_ADDRESS 0xFE
+#define R_PCH_SMBUS_HD0 0x05 ///< Data 0 Register R/W
+#define R_PCH_SMBUS_HD1 0x06 ///< Data 1 Register R/W
+#define R_PCH_SMBUS_HBD 0x07 ///< Host Block Data Register R/W
+#define R_PCH_SMBUS_PEC 0x08 ///< Packet Error Check Data Register R/W
+#define R_PCH_SMBUS_RSA 0x09 ///< Receive Slave Address Register R/W
+#define B_PCH_SMBUS_SLAVE_ADDR 0x7F
+#define R_PCH_SMBUS_SD 0x0A ///< Receive Slave Data Register R/W
+#define R_PCH_SMBUS_AUXS 0x0C ///< Auxiliary Status Register R/WC
+#define B_PCH_SMBUS_CRCE 0x01
+#define B_PCH_SMBUS_STCO 0x02 ///< SMBus TCO Mode
+#define R_PCH_SMBUS_AUXC 0x0D ///< Auxiliary Control Register R/W
+#define B_PCH_SMBUS_AAC 0x01
+#define B_PCH_SMBUS_E32B 0x02
+#define R_PCH_SMBUS_SMLC 0x0E ///< SMLINK Pin Control Register R/W
+#define B_PCH_SMBUS_SMLINK0_CUR_STS 0x01
+#define B_PCH_SMBUS_SMLINK1_CUR_STS 0x02
+#define B_PCH_SMBUS_SMLINK_CLK_CTL 0x04
+#define R_PCH_SMBUS_SMBC 0x0F ///< SMBus Pin Control Register R/W
+#define B_PCH_SMBUS_SMBCLK_CUR_STS 0x01
+#define B_PCH_SMBUS_SMBDATA_CUR_STS 0x02
+#define B_PCH_SMBUS_SMBCLK_CTL 0x04
+#define R_PCH_SMBUS_SSTS 0x10 ///< Slave Status Register R/WC
+#define B_PCH_SMBUS_HOST_NOTIFY_STS 0x01
+#define R_PCH_SMBUS_SCMD 0x11 ///< Slave Command Register R/W
+#define B_PCH_SMBUS_HOST_NOTIFY_INTREN 0x01
+#define B_PCH_SMBUS_HOST_NOTIFY_WKEN 0x02
+#define B_PCH_SMBUS_SMBALERT_DIS 0x04
+#define R_PCH_SMBUS_NDA 0x14 ///< Notify Device Address Register RO
+#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE
+#define R_PCH_SMBUS_NDLB 0x16 ///< Notify Data Low Byte Register RO
+#define R_PCH_SMBUS_NDHB 0x17 ///< Notify Data High Byte Register RO
+
+//
+// SMBus Private Config Registers
+// (PID:SMB)
+//
+#define R_PCH_PCR_SMBUS_TCOCFG 0x00 ///< TCO Configuration register
+#define B_PCH_PCR_SMBUS_TCOCFG_IE BIT7 ///< TCO IRQ Enable
+#define B_PCH_PCR_SMBUS_TCOCFG_IS (BIT2 | BIT1 | BIT0) ///< TCO IRQ Select
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_9 0x00
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_10 0x01
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_11 0x02
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_20 0x04 ///< only if APIC enabled
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_21 0x05 ///< only if APIC enabled
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_22 0x06 ///< only if APIC enabled
+#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_23 0x07 ///< only if APIC enabled
+#define R_PCH_PCR_SMBUS_SMBTM 0x04 ///< SMBus Test Mode
+#define B_PCH_PCR_SMBUS_SMBTM_SMBCT BIT1 ///< SMBus Counter
+#define B_PCH_PCR_SMBUS_SMBTM_SMBDG BIT0 ///< SMBus Deglitch
+#define R_PCH_PCR_SMBUS_SCTM 0x08 ///< Short Counter Test Mode
+#define B_PCH_PCR_SMBUS_SCTM_SSU BIT31 ///< Simulation Speed-Up
+#define R_PCH_PCR_SMBUS_GC 0x0C ///< General Control
+#define B_PCH_PCR_SMBUS_GC_FD BIT0 ///< Function Disable
+#define B_PCH_PCR_SMBUS_GC_NR BIT1 ///< No Reboot
+#define B_PCH_PCR_SMBUS_GC_SMBSCGE BIT2 ///< SMB Static Clock Gating Enable
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSpi.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSpi.h
new file mode 100644
index 0000000000..ef5dd8ea18
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsSpi.h
@@ -0,0 +1,291 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_SPI_H_
+#define _PCH_REGS_SPI_H_
+
+//
+// SPI Registers (D31:F5)
+//
+
+#define PCI_DEVICE_NUMBER_PCH_SPI 31
+#define PCI_FUNCTION_NUMBER_PCH_SPI 5
+#define V_PCH_SPI_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_SPI_DEVICE_ID 0xA124
+//
+// LBG PRODUCTION SPI Device ID
+//
+#define V_PCH_LBG_PROD_SPI_DEVICE_ID 0xA1A4
+//
+// LBG SSX (Super SKU) SPI Device ID
+//
+#define V_PCH_LBG_SPI_DEVICE_ID 0xA224
+#define V_PCH_LP_SPI_DEVICE_ID 0x9D24
+#define R_PCH_SPI_BAR0 0x10
+#define B_PCH_SPI_BAR0_MASK 0x0FFF
+
+#define R_PCH_SPI_BDE 0xD8
+#define B_PCH_SPI_BDE_F8 0x8000
+#define B_PCH_SPI_BDE_F0 0x4000
+#define B_PCH_SPI_BDE_E8 0x2000
+#define B_PCH_SPI_BDE_E0 0x1000
+#define B_PCH_SPI_BDE_D8 0x0800
+#define B_PCH_SPI_BDE_D0 0x0400
+#define B_PCH_SPI_BDE_C8 0x0200
+#define B_PCH_SPI_BDE_C0 0x0100
+#define B_PCH_SPI_BDE_LEG_F 0x0080
+#define B_PCH_SPI_BDE_LEG_E 0x0040
+#define B_PCH_SPI_BDE_70 0x0008
+#define B_PCH_SPI_BDE_60 0x0004
+#define B_PCH_SPI_BDE_50 0x0002
+#define B_PCH_SPI_BDE_40 0x0001
+
+#define R_PCH_SPI_BC 0xDC
+#define S_PCH_SPI_BC 4
+#define N_PCH_SPI_BC_ASE_BWP 11
+#define B_PCH_SPI_BC_ASE_BWP BIT11
+#define N_PCH_SPI_BC_ASYNC_SS 10
+#define B_PCH_SPI_BC_ASYNC_SS BIT10
+#define B_PCH_SPI_BC_OSFH BIT9 ///< OS Function Hide
+#define N_PCH_SPI_BC_SYNC_SS 8
+#define B_PCH_SPI_BC_SYNC_SS BIT8
+#define B_PCH_SPI_BC_BILD BIT7
+#define B_PCH_SPI_BC_BBS BIT6 ///< Boot BIOS strap
+#define N_PCH_SPI_BC_BBS 6
+#define V_PCH_SPI_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI
+#define V_PCH_SPI_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC
+#define B_PCH_SPI_BC_EISS BIT5 ///< Enable InSMM.STS
+#define B_PCH_SPI_BC_TSS BIT4
+#define B_PCH_SPI_BC_SRC (BIT3 | BIT2)
+#define N_PCH_SPI_BC_SRC 2
+#define V_PCH_SPI_BC_SRC_PREF_EN_CACHE_EN 0x02 ///< Prefetching and Caching enabled
+#define V_PCH_SPI_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefetching and no caching
+#define V_PCH_SPI_BC_SRC_PREF_DIS_CACHE_EN 0x00 ///< No prefetching, but caching enabled
+#define B_PCH_SPI_BC_LE BIT1 ///< Lock Enable
+#define N_PCH_SPI_BC_BLE 1
+#define B_PCH_SPI_BC_WPD BIT0 ///< Write Protect Disable
+
+//
+// BIOS Flash Program Registers (based on SPI_BAR0)
+//
+#define R_PCH_SPI_BFPR 0x00 ///< BIOS Flash Primary Region Register(32bits), which is RO and contains the same value from FREG1
+#define B_PCH_SPI_BFPR_PRL 0x7FFF0000 ///< BIOS Flash Primary Region Limit mask
+#define N_PCH_SPI_BFPR_PRL 16 ///< BIOS Flash Primary Region Limit bit position
+#define B_PCH_SPI_BFPR_PRB 0x00007FFF ///< BIOS Flash Primary Region Base mask
+#define N_PCH_SPI_BFPR_PRB 0 ///< BIOS Flash Primary Region Base bit position
+#define R_PCH_SPI_HSFSC 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits)
+#define B_PCH_SPI_HSFSC_FSMIE BIT31 ///< Flash SPI SMI# Enable
+#define B_PCH_SPI_HSFSC_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
+#define N_PCH_SPI_HSFSC_FDBC 24
+#define B_PCH_SPI_HSFSC_CYCLE_MASK 0x001E0000 ///< Flash Cycle.
+#define N_PCH_SPI_HSFSC_CYCLE 17
+#define V_PCH_SPI_HSFSC_CYCLE_READ 0 ///< Flash Cycle Read
+#define V_PCH_SPI_HSFSC_CYCLE_WRITE 2 ///< Flash Cycle Write
+#define V_PCH_SPI_HSFSC_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase
+#define V_PCH_SPI_HSFSC_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase
+#define V_PCH_SPI_HSFSC_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP
+#define V_PCH_SPI_HSFSC_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID
+#define V_PCH_SPI_HSFSC_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status
+#define V_PCH_SPI_HSFSC_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status
+#define B_PCH_SPI_HSFSC_CYCLE_FGO BIT16 ///< Flash Cycle Go.
+#define B_PCH_SPI_HSFSC_FLOCKDN BIT15 ///< Flash Configuration Lock-Down
+#define B_PCH_SPI_HSFSC_FDV BIT14 ///< Flash Descriptor Valid, once valid software can use hareware sequencing regs
+#define B_PCH_SPI_HSFSC_FDOPSS BIT13 ///< Flash Descriptor Override Pin-Strap Status
+#define B_PCH_SPI_HSFSC_PRR34_LOCKDN BIT12 ///< PRR3 PRR4 Lock-Down
+#define B_PCH_SPI_HSFSC_SAF_CE BIT8 ///< SAF ctype error
+#define B_PCH_SPI_HSFSC_SAF_MODE_ACTIVE BIT7 ///< Indicates flash is attached either directly to the PCH via the SPI bus or EC/BMC
+#define B_PCH_SPI_HSFSC_SAF_LE BIT6 ///< SAF link error
+#define B_PCH_SPI_HSFSC_SCIP BIT5 ///< SPI cycle in progress
+#define B_PCH_SPI_HSFSC_SAF_DLE BIT4 ///< SAF Data length error
+#define B_PCH_SPI_HSFSC_SAF_ERROR BIT3 ///< SAF Error
+#define B_PCH_SPI_HSFSC_AEL BIT2 ///< Access Error Log
+#define B_PCH_SPI_HSFSC_FCERR BIT1 ///< Flash Cycle Error
+#define B_PCH_SPI_HSFSC_FDONE BIT0 ///< Flash Cycle Done
+#define R_PCH_SPI_FADDR 0x08 ///< SPI Flash Address
+#define B_PCH_SPI_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit)
+#define R_PCH_SPI_DLOCK 0x0C ///< Discrete Lock Bits
+#define B_PCH_SPI_DLOCK_PR0LOCKDN BIT8 ///< PR0LOCKDN
+#define R_PCH_SPI_FDATA00 0x10 ///< SPI Data 00 (32 bits)
+#define R_PCH_SPI_FDATA01 0x14 ///< SPI Data 01
+#define R_PCH_SPI_FDATA02 0x18 ///< SPI Data 02
+#define R_PCH_SPI_FDATA03 0x1C ///< SPI Data 03
+#define R_PCH_SPI_FDATA04 0x20 ///< SPI Data 04
+#define R_PCH_SPI_FDATA05 0x24 ///< SPI Data 05
+#define R_PCH_SPI_FDATA06 0x28 ///< SPI Data 06
+#define R_PCH_SPI_FDATA07 0x2C ///< SPI Data 07
+#define R_PCH_SPI_FDATA08 0x30 ///< SPI Data 08
+#define R_PCH_SPI_FDATA09 0x34 ///< SPI Data 09
+#define R_PCH_SPI_FDATA10 0x38 ///< SPI Data 10
+#define R_PCH_SPI_FDATA11 0x3C ///< SPI Data 11
+#define R_PCH_SPI_FDATA12 0x40 ///< SPI Data 12
+#define R_PCH_SPI_FDATA13 0x44 ///< SPI Data 13
+#define R_PCH_SPI_FDATA14 0x48 ///< SPI Data 14
+#define R_PCH_SPI_FDATA15 0x4C ///< SPI Data 15
+#define R_PCH_SPI_FRAP 0x50 ///< Flash Region Access Permisions Register
+#define B_PCH_SPI_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
+#define N_PCH_SPI_FRAP_BRWA 8 ///< BIOS Region Write Access bit position
+#define B_PCH_SPI_FRAP_BRRA_MASK 0x000000FF ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
+#define B_PCH_SPI_FRAP_BMRAG_MASK 0x00FF0000 ///< BIOS Master Read Access Grant
+#define B_PCH_SPI_FRAP_BMWAG_MASK 0xFF000000 ///< BIOS Master Write Access Grant
+#define R_PCH_SPI_FREG0_FLASHD 0x54 ///< Flash Region 0(Flash Descriptor)(32bits)
+#define R_PCH_SPI_FREG1_BIOS 0x58 ///< Flash Region 1(BIOS)(32bits)
+#define R_PCH_SPI_FREG2_ME 0x5C ///< Flash Region 2(ME)(32bits)
+#define R_PCH_SPI_FREG3_GBE 0x60 ///< Flash Region 3(GbE)(32bits)
+#define R_PCH_SPI_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4(Platform Data)(32bits)
+#define R_PCH_SPI_FREG5_DER 0x68 ///< Flash Region 5(Device Expansion Region)(32bits)
+#define S_PCH_SPI_FREGX 4 ///< Size of Flash Region register
+#define B_PCH_SPI_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh
+#define N_PCH_SPI_FREGX_LIMIT 16 ///< Region limit bit position
+#define N_PCH_SPI_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position
+#define B_PCH_SPI_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12]
+#define N_PCH_SPI_FREGX_BASE 0 ///< Region base bit position
+#define N_PCH_SPI_FREGX_BASE_REPR 12 ///< Region base bit represents position
+#define R_PCH_SPI_PR0 0x84 ///< Protected Region 0 Register
+#define R_PCH_SPI_PR1 0x88 ///< Protected Region 1 Register
+#define R_PCH_SPI_PR2 0x8C ///< Protected Region 2 Register
+#define R_PCH_SPI_PR3 0x90 ///< Protected Region 3 Register
+#define R_PCH_SPI_PR4 0x94 ///< Protected Region 4 Register
+#define S_PCH_SPI_PRX 4 ///< Protected Region X Register size
+#define B_PCH_SPI_PRX_WPE BIT31 ///< Write Protection Enable
+#define B_PCH_SPI_PRX_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask, [30:16] here represents upper limit of address [26:12]
+#define N_PCH_SPI_PRX_PRL 16 ///< Protected Range Limit bit position
+#define B_PCH_SPI_PRX_RPE BIT15 ///< Read Protection Enable
+#define B_PCH_SPI_PRX_PRB_MASK 0x00007FFF ///< Protected Range Base Mask, [14:0] here represents base limit of address [26:12]
+#define N_PCH_SPI_PRX_PRB 0 ///< Protected Range Base bit position
+#define R_PCH_SPI_SFRAP 0xB0 ///< Secondary Flash Regions Access Permisions Register
+#define R_PCH_SPI_FDOC 0xB4 ///< Flash Descriptor Observability Control Register(32 bits)
+#define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descritor Section Select
+#define V_PCH_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map
+#define V_PCH_SPI_FDOC_FDSS_COMP 0x1000 ///< Component
+#define V_PCH_SPI_FDOC_FDSS_REGN 0x2000 ///< Region
+#define V_PCH_SPI_FDOC_FDSS_MSTR 0x3000 ///< Master
+#define V_PCH_SPI_FDOC_FDSS_PCHS 0x4000 ///< PCH soft straps
+#define V_PCH_SPI_FDOC_FDSS_SFDP 0x5000 ///< SFDP Parameter Table
+#define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index
+#define R_PCH_SPI_FDOD 0xB8 ///< Flash Descriptor Observability Data Register(32 bits)
+#define R_PCH_SPI_SFDP0_VSCC0 0xC4 ///< Vendor Specific Component Capabilities Register(32 bits)
+#define B_PCH_SPI_SFDPX_VSCCX_CPPTV BIT31 ///< Component Property Parameter Table Valid
+#define B_PCH_SPI_SFDP0_VSCC0_VCL BIT30 ///< Vendor Component Lock
+#define B_PCH_SPI_SFDPX_VSCCX_EO_64K BIT29 ///< 64k Erase valid (EO_64k_valid)
+#define B_PCH_SPI_SFDPX_VSCCX_EO_4K BIT28 ///< 4k Erase valid (EO_4k_valid)
+#define B_PCH_SPI_SFDPX_VSCCX_RPMC BIT27 ///< RPMC Supported
+#define B_PCH_SPI_SFDPX_VSCCX_DPD BIT26 ///< Deep Powerdown Supported
+#define B_PCH_SPI_SFDPX_VSCCX_SUSRES BIT25 ///< Suspend/Resume Supported
+#define B_PCH_SPI_SFDPX_VSCCX_SOFTRES BIT24 ///< Soft Reset Supported
+#define B_PCH_SPI_SFDPX_VSCCX_64k_EO_MASK 0x00FF0000 ///< 64k Erase Opcode (EO_64k)
+#define B_PCH_SPI_SFDPX_VSCCX_4k_EO_MASK 0x0000FF00 ///< 4k Erase Opcode (EO_4k)
+#define B_PCH_SPI_SFDPX_VSCCX_QER (BIT7 | BIT6 | BIT5) ///< Quad Enable Requirements
+#define B_PCH_SPI_SFDPX_VSCCX_WEWS BIT4 ///< Write Enable on Write Status
+#define B_PCH_SPI_SFDPX_VSCCX_WSR BIT3 ///< Write Status Required
+#define B_PCH_SPI_SFDPX_VSCCX_WG_64B BIT2 ///< Write Granularity, 0: 1 Byte; 1: 64 Bytes
+#define R_PCH_SPI_SFDP1_VSCC1 0xC8 ///< Vendor Specific Component Capabilities Register(32 bits)
+#define R_PCH_SPI_PINTX 0xCC ///< Parameter Table Index
+#define N_PCH_SPI_PINTX_SPT 14
+#define V_PCH_SPI_PINTX_SPT_CPT0 0x0 ///< Component 0 Property Parameter Table
+#define V_PCH_SPI_PINTX_SPT_CPT1 0x1 ///< Component 1 Property Parameter Table
+#define N_PCH_SPI_PINTX_HORD 12
+#define V_PCH_SPI_PINTX_HORD_SFDP 0x0 ///< SFDP Header
+#define V_PCH_SPI_PINTX_HORD_PT 0x1 ///< Parameter Table Header
+#define V_PCH_SPI_PINTX_HORD_DATA 0x2 ///< Data
+#define R_PCH_SPI_PTDATA 0xD0 ///< Parameter Table Data
+#define R_PCH_SPI_SBRS 0xD4 ///< SPI Bus Requester Status
+#define R_PCH_SPI_SSML 0xF0 ///< Set Strap Msg Lock
+#define B_PCH_SPI_SSML_SSL BIT0 ///< Set_Strap Lock
+#define R_PCH_SPI_SSMC 0xF4 ///< Set Strap Msg Control
+#define B_PCH_SPI_SSMC_SSMS BIT0 ///< Set_Strap Mux Select
+#define R_PCH_SPI_SSMD 0xF8 ///< Set Strap Msg Data
+//
+// @todo Follow up with EDS owner if it should be 3FFF or FFFF.
+//
+#define B_PCH_SPI_SRD_SSD 0x0000FFFF ///< Set_Strap Data
+//
+// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
+//
+#define R_PCH_SPI_FDBAR_FLVALSIG 0x00 ///< Flash Valid Signature
+#define V_PCH_SPI_FDBAR_FLVALSIG 0x0FF0A55A
+#define R_PCH_SPI_FDBAR_FLASH_MAP0 0x04
+#define B_PCH_SPI_FDBAR_FCBA 0x000000FF ///< Flash Component Base Address
+#define B_PCH_SPI_FDBAR_NC 0x00000300 ///< Number Of Components
+#define N_PCH_SPI_FDBAR_NC 8 ///< Number Of Components
+#define V_PCH_SPI_FDBAR_NC_1 0x00000000
+#define V_PCH_SPI_FDBAR_NC_2 0x00000100
+#define B_PCH_SPI_FDBAR_FRBA 0x00FF0000 ///< Flash Region Base Address
+#define B_PCH_SPI_FDBAR_NR 0x07000000 ///< Number Of Regions
+#define R_PCH_SPI_FDBAR_FLASH_MAP1 0x08
+#define B_PCH_SPI_FDBAR_FMBA 0x000000FF ///< Flash Master Base Address
+#define B_PCH_SPI_FDBAR_NM 0x00000700 ///< Number Of Masters
+#define B_PCH_SPI_FDBAR_FPSBA 0x00FF0000 ///< PCH Strap Base Address, [23:16] represents [11:4]
+#define N_PCH_SPI_FDBAR_FPSBA 16 ///< PCH Strap base Address bit position
+#define N_PCH_SPI_FDBAR_FPSBA_REPR 4 ///< PCH Strap base Address bit represents position
+#define B_PCH_SPI_FDBAR_PCHSL 0xFF000000 ///< PCH Strap Length, [31:24] represents number of Dwords
+#define N_PCH_SPI_FDBAR_PCHSL 24 ///< PCH Strap Length bit position
+#define R_PCH_SPI_FDBAR_FLASH_MAP2 0x0C
+#define B_PCH_SPI_FDBAR_FCPUSBA 0x000000FF ///< CPU Strap Base Address, [7:0] represents [11:4]
+#define N_PCH_SPI_FDBAR_FCPUSBA 0 ///< CPU Strap Base Address bit position
+#define N_PCH_SPI_FDBAR_FCPUSBA_REPR 4 ///< CPU Strap Base Address bit represents position
+#define B_PCH_SPI_FDBAR_CPUSL 0x0000FF00 ///< CPU Strap Length, [15:8] represents number of Dwords
+#define N_PCH_SPI_FDBAR_CPUSL 8 ///< CPU Strap Length bit position
+//
+// Flash Component Base Address (FCBA) from Flash Region 0
+//
+#define R_PCH_SPI_FCBA_FLCOMP 0x00 ///< Flash Components Register
+#define B_PCH_SPI_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27) ///< Read ID and Read Status Clock Frequency
+#define B_PCH_SPI_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24) ///< Write and Erase Clock Frequency
+#define B_PCH_SPI_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21) ///< Fast Read Clock Frequency
+#define B_PCH_SPI_FLCOMP_FR_SUP BIT20 ///< Fast Read Support.
+#define B_PCH_SPI_FLCOMP_RC_FREQ (BIT19 | BIT18 | BIT17) ///< Read Clock Frequency.
+#define V_PCH_SPI_FLCOMP_FREQ_48MHZ 0x02
+#define V_PCH_SPI_FLCOMP_FREQ_30MHZ 0x04
+#define V_PCH_SPI_FLCOMP_FREQ_17MHZ 0x06
+#define B_PCH_SPI_FLCOMP_COMP1_MASK 0xF0 ///< Flash Component 1 Size MASK
+#define N_PCH_SPI_FLCOMP_COMP1 4 ///< Flash Component 1 Size bit position
+#define B_PCH_SPI_FLCOMP_COMP0_MASK 0x0F ///< Flash Component 0 Size MASK
+#define V_PCH_SPI_FLCOMP_COMP_512KB 0x80000
+//
+// Descriptor Upper Map Section from Flash Region 0
+//
+#define R_PCH_SPI_FLASH_UMAP1 0xEFC ///< Flash Upper Map 1
+#define B_PCH_SPI_FLASH_UMAP1_VTBA 0x000000FF ///< VSCC Table Base Address
+#define B_PCH_SPI_FLASH_UMAP1_VTL 0x0000FF00 ///< VSCC Table Length
+
+#define R_PCH_SPI_VTBA_JID0 0x00 ///< JEDEC-ID 0 Register
+#define S_PCH_SPI_VTBA_JID0 0x04
+#define B_PCH_SPI_VTBA_JID0_VID 0x000000FF
+#define B_PCH_SPI_VTBA_JID0_DID0 0x0000FF00
+#define B_PCH_SPI_VTBA_JID0_DID1 0x00FF0000
+#define N_PCH_SPI_VTBA_JID0_DID0 0x08
+#define N_PCH_SPI_VTBA_JID0_DID1 0x10
+#define R_PCH_SPI_VTBA_VSCC0 0x04
+#define S_PCH_SPI_VTBA_VSCC0 0x04
+
+
+//
+// SPI Private Configuration Space Registers
+//
+#define R_PCH_PCR_SPI_CLK_CTL 0xC004
+#define R_PCH_PCR_SPI_PWR_CTL 0xC008
+
+//
+// MMP0
+//
+#define R_PCH_SPI_STRP_MMP0 0xC4 ///< MMP0 Soft strap offset
+#define B_PCH_SPI_STRP_MMP0 0x10 ///< MMP0 Soft strap bit
+
+
+#define R_PCH_SPI_STRP_SFDP 0xF0 ///< PCH Soft Strap SFDP
+#define B_PCH_SPI_STRP_SFDP_QIORE BIT3 ///< Quad IO Read Enable
+#define B_PCH_SPI_STRP_SFDP_QORE BIT2 ///< Quad Output Read Enable
+#define B_PCH_SPI_STRP_SFDP_DIORE BIT1 ///< Dual IO Read Enable
+#define B_PCH_SPI_STRP_SFDP_DORE BIT0 ///< Dual Output Read Enable
+
+//
+// Descriptor Record 0
+//
+#define R_PCH_SPI_STRP_DSCR_0 0x00 ///< PCH Soft Strap 0
+#define B_PCH_SPI_STRP_DSCR_0_PTT_SUPP BIT22 ///< PTT Supported
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsThermal.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsThermal.h
new file mode 100644
index 0000000000..dfd6d4e37c
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsThermal.h
@@ -0,0 +1,93 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_THERMAL_H_
+#define _PCH_REGS_THERMAL_H_
+
+//
+// Thermal Device Registers (D20:2)
+//
+#define PCI_DEVICE_NUMBER_PCH_THERMAL 20
+#define PCI_FUNCTION_NUMBER_PCH_THERMAL 2
+#define V_PCH_THERMAL_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_THERMAL_DEVICE_ID 0x8C24
+
+//
+// LBG Production Thermal Device Device ID
+//
+#define V_PCH_LBG_PROD_THERMAL_DEVICE_ID 0xA1B1
+//
+// LBG SSX (Super SKU) Thermal Device Device ID
+//
+#define V_PCH_LBG_THERMAL_DEVICE_ID 0xA231
+
+#define V_PCH_LP_THERMAL_DEVICE_ID 0x9C24
+#define R_PCH_THERMAL_TBAR 0x10
+#define V_PCH_THERMAL_TBAR_SIZE (4 * 1024)
+#define N_PCH_THREMAL_TBAR_ALIGNMENT 12
+#define B_PCH_THERMAL_TBAR_MASK 0xFFFFF000
+#define R_PCH_THERMAL_TBARH 0x14
+#define R_PCH_THERMAL_TBARB 0x40
+#define V_PCH_THERMAL_TBARB_SIZE (4 * 1024)
+#define N_PCH_THREMAL_TBARB_ALIGNMENT 12
+#define B_PCH_THERMAL_SPTYPEN BIT0
+#define R_PCH_THERMAL_TBARBH 0x44
+#define B_PCH_THERMAL_TBARB_MASK 0xFFFFF000
+
+//
+// Thermal TBAR MMIO registers
+//
+#define R_PCH_TBAR_TSC 0x04
+#define B_PCH_TBAR_TSC_PLD BIT7
+#define B_PCH_TBAR_TSC_CPDE BIT0
+#define R_PCH_TBAR_TSS 0x06
+#define R_PCH_TBAR_TSEL 0x08
+#define B_PCH_TBAR_TSEL_PLD BIT7
+#define B_PCH_TBAR_TSEL_ETS BIT0
+#define R_PCH_TBAR_TSREL 0x0A
+#define R_PCH_TBAR_TSMIC 0x0C
+#define B_PCH_TBAR_TSMIC_PLD BIT7
+#define B_PCH_TBAR_TSMIC_SMIE BIT0
+#define R_PCH_TBAR_CTT 0x10
+#define R_PCH_TBAR_TAHV 0x14
+#define R_PCH_TBAR_TALV 0x18
+#define R_PCH_TBAR_TSPM 0x1C
+#define B_PCH_TBAR_TSPM_LTT (BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
+#define V_PCH_TBAR_TSPM_LTT 0x0C8
+#define B_PCH_TBAR_TSPM_MAXTSST (BIT11 | BIT10 | BIT9)
+#define V_PCH_TBAR_TSPM_MAXTSST (0x4 << 9)
+#define B_PCH_TBAR_TSPM_MINTSST BIT12
+#define B_PCH_TBAR_TSPM_DTSSIC0 BIT13
+#define B_PCH_TBAR_TSPM_DTSSS0EN BIT14
+#define B_PCH_TBAR_TSPM_TSPMLOCK BIT15
+#define R_PCH_TBAR_TL 0x40
+#define B_PCH_TBAR_TL_LOCK BIT31
+#define B_PCH_TBAR_TL_TTEN BIT29
+#define R_PCH_TBAR_TL2 0x50
+#define R_PCH_TBAR_TL2_LOCK BIT15
+#define R_PCH_TBAR_TL2_PMCTEN BIT14
+#define R_PCH_TBAR_PHL 0x60
+#define B_PCH_TBAR_PHLE BIT15
+#define R_PCH_TBAR_PHLC 0x62
+#define B_PCH_TBAR_PHLC_LOCK BIT0
+#define R_PCH_TBAR_TAS 0x80
+#define R_PCH_TBAR_TSPIEN 0x82
+#define R_PCH_TBAR_TSGPEN 0x84
+#define B_PCH_TBAR_TL2_PMCTEN BIT14
+#define R_PCH_TBAR_A4 0xA4
+#define R_PCH_TBAR_C0 0xC0
+#define R_PCH_TBAR_C4 0xC4
+#define R_PCH_TBAR_C8 0xC8
+#define R_PCH_TBAR_CC 0xCC
+#define R_PCH_TBAR_D0 0xD0
+#define R_PCH_TBAR_E0 0xE0
+#define R_PCH_TBAR_E4 0xE4
+#define R_PCH_TBAR_E8 0xE8
+#define R_PCH_TBAR_TCFD 0xF0 ///< Thermal controller function disable
+#define B_PCH_TBAR_TCFD_TCD BIT0 ///< Thermal controller disable
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsTraceHub.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsTraceHub.h
new file mode 100644
index 0000000000..43c2b7c699
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsTraceHub.h
@@ -0,0 +1,125 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_TRACE_HUB_H_
+#define _PCH_REGS_TRACE_HUB_H_
+
+//
+// TraceHub Registers (D31:F7)
+//
+#define PCI_DEVICE_NUMBER_PCH_TRACE_HUB 31
+#define PCI_FUNCTION_NUMBER_PCH_TRACE_HUB 7
+
+#define V_PCH_TRACE_HUB_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_TRACE_HUB_DEVICE_ID 0x0963
+
+//
+// LBG Production (PRQ) TraceHub Device ID
+//
+#define V_PCH_LBG_PROD_TRACE_HUB_DEVICE_ID 0xA1A6
+//
+// LBG SuperSKU (SSX) TraceHub Device ID
+//
+#define V_PCH_LBG_TRACE_HUB_DEVICE_ID 0xA226
+
+#define R_PCH_TRACE_HUB_CSR_MTB_LBAR 0x10
+#define B_PCH_TRACE_HUB_CSR_MTB_RBAL 0xFFF00000
+#define R_PCH_TRACE_HUB_CSR_MTB_UBAR 0x14
+#define B_PCH_TRACE_HUB_CSR_MTB_RBAU 0xFFFFFFFF
+#define R_PCH_TRACE_HUB_SW_LBAR 0x18
+#define B_PCH_TRACE_HUB_SW_RBAL 0xFFE00000
+#define R_PCH_TRACE_HUB_SW_UBAR 0x1C
+#define B_PCH_TRACE_HUB_SW_RBAU 0xFFFFFFFF
+#define R_PCH_TRACE_HUB_RTIT_LBAR 0x20
+#define B_PCH_TRACE_HUB_RTIT_RBAL 0xFFFFFF00
+#define R_PCH_TRACE_HUB_RTIT_UBAR 0x24
+#define B_PCH_TRACE_HUB_RTIT_RBAU 0xFFFFFFFF
+#define R_PCH_TRACE_HUB_MSICID 0x40
+#define R_PCH_TRACE_HUB_MSINCP 0x41
+#define R_PCH_TRACE_HUB_MSIMC 0x42
+#define R_PCH_TRACE_HUB_MSILMA 0x44
+#define R_PCH_TRACE_HUB_MSIUMA 0x48
+#define R_PCH_TRACE_HUB_MSIMD 0x4C
+#define B_PCH_TRACE_HUB_FW_RBAL 0xFFFC0000
+#define B_PCH_TRACE_HUB_FW_RBAU 0xFFFFFFFF
+#define R_PCH_TRACE_HUB_DSC 0x80
+#define B_PCH_TRACE_HUB_BYP BIT0 //< TraceHub Bypass
+#define R_PCH_TRACE_HUB_DSS 0x81
+#define R_PCH_TRACE_HUB_ISTOT 0x84
+#define R_PCH_TRACE_HUB_ICTOT 0x88
+#define R_PCH_TRACE_HUB_IPAD 0x8C
+#define R_PCH_TRACE_HUB_DSD 0x90
+
+//
+// Offsets from CSR_MTB_BAR
+//
+#define R_PCH_TRACE_HUB_MTB_GTHOPT0 0x00
+#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P0FLUSH BIT7
+#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P1FLUSH BIT15
+#define V_PCH_TRACE_HUB_MTB_SWDEST_PTI 0x0A
+#define V_PCH_TRACE_HUB_MTB_SWDEST_MEMEXI 0x08
+#define V_PCH_TRACE_HUB_MTB_SWDEST_DISABLE 0x00
+#define R_PCH_TRACE_HUB_MTB_SWDEST_1 0x0C
+#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_1 0x0000000F
+#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_2 0x000000F0
+#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_3 0x00000F00
+#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_1 0x0000F000
+#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_2 0x000F0000
+#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_3 0x00F00000
+#define B_PCH_TRACE_HUB_MTB_SWDEST_AUDIO 0x0F000000
+#define B_PCH_TRACE_HUB_MTB_SWDEST_PMC 0xF0000000
+#define R_PCH_TRACE_HUB_MTB_SWDEST_2 0x10
+#define B_PCH_TRACE_HUB_MTB_SWDEST_FTH 0x0000000F
+#define R_PCH_TRACE_HUB_MTB_SWDEST_3 0x14
+#define B_PCH_TRACE_HUB_MTB_SWDEST_MAESTRO 0x00000F00
+#define B_PCH_TRACE_HUB_MTB_SWDEST_SKYCAM 0x0F000000
+#define B_PCH_TRACE_HUB_MTB_SWDEST_AET 0xF0000000
+#define R_PCH_TRACE_HUB_MTB_SWDEST_4 0x18
+#define R_PCH_TRACE_HUB_MTB_MSC0CTL 0xA0100
+#define R_PCH_TRACE_HUB_MTB_MSC1CTL 0xA0200
+#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DCI 0x2
+#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DEBUG 0x3
+#define B_PCH_TRACE_HUB_MTB_MSCNLEN (BIT10 | BIT9 | BIT8)
+#define B_PCH_TRACE_HUB_MTB_MSCNMODE (BIT5 | BIT4)
+#define N_PCH_TRACE_HUB_MTB_MSCNMODE 0x4
+#define B_PCH_TRACE_HUB_MTB_MSCN_RD_HDR_OVRD BIT2
+#define B_PCH_TRACE_HUB_MTB_WRAPENN BIT1
+#define B_PCH_TRACE_HUB_MTB_MSCNEN BIT0
+#define R_PCH_TRACE_HUB_MTB_GTHSTAT 0xD4
+#define R_PCH_TRACE_HUB_MTB_SCR2 0xD8
+#define B_PCH_TRACE_HUB_MTB_SCR2_FCD BIT0
+#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF2 BIT2
+#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF3 BIT3
+#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF4 BIT4
+#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF5 BIT5
+#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF6 BIT6
+#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF7 BIT7
+#define R_PCH_TRACE_HUB_MTB_MSC0BAR 0xA0108
+#define R_PCH_TRACE_HUB_MTB_MSC0SIZE 0xA010C
+#define R_PCH_TRACE_HUB_MTB_MSC1BAR 0xA0208
+#define R_PCH_TRACE_HUB_MTB_MSC1SIZE 0xA020C
+#define R_PCH_TRACE_HUB_MTB_STREAMCFG1 0xA1000
+#define B_PCH_TRACE_HUB_MTB_STREAMCFG1_ENABLE BIT28
+#define R_PCH_TRACE_HUB_MTB_PTI_CTL 0x1C00
+#define B_PCH_TRACE_HUB_MTB_PTIMODESEL 0xF0
+#define B_PCH_TRACE_HUB_MTB_PTICLKDIV (BIT17 | BIT16)
+#define B_PCH_TRACE_HUB_MTB_PATGENMOD (BIT22 | BIT21 | BIT20)
+#define B_PCH_TRACE_HUB_MTB_PTI_EN BIT0
+#define R_PCH_TRACE_HUB_MTB_SCR 0xC8
+#define R_PCH_TRACE_HUB_MTB_GTH_FREQ 0xCC
+#define V_PCH_TRACE_HUB_MTB_SCR 0x00130000
+#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD0 0xE0
+#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD1 0xE4
+#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD10 0xE40
+#define R_PCH_TRACE_HUB_MTB_CTPGCS 0x1C14
+#define B_PCH_TRACE_HUB_MTB_CTPEN BIT0
+#define V_PCH_TRACE_HUB_MTB_CHLCNT 0x80
+#define V_PCH_TRACE_HUB_MTB_STHMSTR 0x20
+#define R_PCH_TRACE_HUB_CSR_MTB_TSUCTRL 0x2000
+#define B_PCH_TRACE_HUB_CSR_MTB_TSUCTRL_CTCRESYNC BIT0
+
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsUsb.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsUsb.h
new file mode 100644
index 0000000000..a25e9981b3
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Include/Register/PchRegsUsb.h
@@ -0,0 +1,463 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_REGS_USB_H_
+#define _PCH_REGS_USB_H_
+
+//
+// USB3 (XHCI) related definitions
+//
+#define PCI_BUS_NUMBER_PCH_XHCI 0
+#define PCI_DEVICE_NUMBER_PCH_XHCI 20
+#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
+
+//
+// XHCI PCI Config Space registers
+//
+#define V_PCH_USB_VENDOR_ID V_PCH_INTEL_VENDOR_ID
+#define V_PCH_H_USB_DEVICE_ID_XHCI_1 0x8C31 ///< SKL PCH H XHCI#1
+//
+// LBG Production (PRQ) XHCI Controller Device ID
+//
+#define V_PCH_LBG_PROD_USB_DEVICE_ID_XHCI_1 0xA1AF ///< LBG Production DID XHCI#1
+//
+// LBG Super SKU (SSX) XHCI Controller Device ID
+//
+#define V_PCH_LBG_USB_DEVICE_ID_XHCI_1 0xA22F ///< LBG Super SKU DID XHCI#1
+#define V_PCH_LP_USB_DEVICE_ID_XHCI_1 0x9C31 ///< SKL PCH LP XHCI#1
+
+#define R_PCH_XHCI_MEM_BASE 0x10
+#define V_PCH_XHCI_MEM_LENGTH 0x10000
+#define N_PCH_XHCI_MEM_ALIGN 16
+#define B_PCH_XHCI_MEM_ALIGN_MASK 0xFFFF
+
+#define R_PCH_XHCI_XHCC1 0x40
+#define B_PCH_XHCI_XHCC1_ACCTRL BIT31
+#define B_PCH_XHCI_XHCC1_RMTASERR BIT24
+#define B_PCH_XHCI_XHCC1_URD BIT23
+#define B_PCH_XHCI_XHCC1_URRE BIT22
+#define B_PCH_XHCI_XHCC1_IIL1E (BIT21 | BIT20 | BIT19)
+#define V_PCH_XHCI_XHCC1_IIL1E_DIS 0
+#define V_PCH_XHCI_XHCC1_IIL1E_32 (BIT19)
+#define V_PCH_XHCI_XHCC1_IIL1E_64 (BIT20)
+#define V_PCH_XHCI_XHCC1_IIL1E_128 (BIT20 | BIT19)
+#define V_PCH_XHCI_XHCC1_IIL1E_256 (BIT21)
+#define V_PCH_XHCI_XHCC1_IIL1E_512 (BIT21 | BIT19)
+#define V_PCH_XHCI_XHCC1_IIL1E_1024 (BIT21 | BIT20)
+#define V_PCH_XHCI_XHCC1_IIL1E_131072 (BIT21 | BIT20 | BIT19)
+#define B_PCH_XHCI_XHCC1_XHCIL1E BIT18
+#define B_PCH_XHCI_XHCC1_D3IL1E BIT17
+#define B_PCH_XHCI_XHCC1_UNPPA (BIT16 | BIT15 | BIT14 | BIT13 | BIT12)
+#define B_PCH_XHCI_XHCC1_SWAXHCI BIT11
+#define B_PCH_XHCI_XHCC1_L23HRAWC (BIT10 | BIT9 | BIT8)
+#define B_PCH_XHCI_XHCC1_UTAGCP (BIT7 | BIT6)
+#define B_PCH_XHCI_XHCC1_UDAGCNP (BIT5 | BIT4)
+#define B_PCH_XHCI_XHCC1_UDAGCCP (BIT3 | BIT2)
+#define B_PCH_XHCI_XHCC1_UDAGC (BIT1 | BIT0)
+
+#define R_PCH_XHCI_XHCC2 0x44
+#define B_PCH_XHCI_XHCC2_OCCFDONE BIT31
+#define B_PCH_XHCI_XHCC2_XHCUPRDROE BIT11
+#define B_PCH_XHCI_XHCC2_IOSFSRAD BIT10
+#define B_PCH_XHCI_XHCC2_SWACXIHB (BIT9 | BIT8)
+#define B_PCH_XHCI_XHCC2_SWADMIL1IHB (BIT7 | BIT6)
+#define B_PCH_XHCI_XHCC2_L1FP2CGWC (BIT5 | BIT4 | BIT3)
+#define B_PCH_XHCI_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0)
+
+#define R_PCH_XHCI_XHCLKGTEN 0x50
+#define B_PCH_XHCI_XHCLKGTEN_SSLSE BIT26
+#define B_PCH_XHCI_XHCLKGTEN_USB2PLLSE BIT25
+#define B_PCH_XHCI_XHCLKGTEN_IOSFSTCGE BIT24
+#define B_PCH_XHCI_XHCLKGTEN_HSTCGE (BIT23 | BIT22 | BIT21 | BIT20)
+#define B_PCH_XHCI_XHCLKGTEN_SSTCGE (BIT19 | BIT18 | BIT17 | BIT16)
+#define B_PCH_XHCI_XHCLKGTEN_XHCIGEU3S BIT15
+#define B_PCH_XHCI_XHCLKGTEN_XHCFTCLKSE BIT14
+#define B_PCH_XHCI_XHCLKGTEN_XHCBBTCGIPISO BIT13
+#define B_PCH_XHCI_XHCLKGTEN_XHCHSTCGU2NRWE BIT12
+#define B_PCH_XHCI_XHCLKGTEN_XHCUSB2PLLSDLE (BIT11 | BIT10)
+#define B_PCH_XHCI_XHCLKGTEN_HSPLLSUE (BIT9 | BIT8)
+#define B_PCH_XHCI_XHCLKGTEN_SSPLLSUE (BIT7 | BIT6 | BIT5)
+#define B_PCH_XHCI_XHCLKGTEN_XHCBLCGE BIT4
+#define B_PCH_XHCI_XHCLKGTEN_HSLTCGE BIT3
+#define B_PCH_XHCI_XHCLKGTEN_SSLTCGE BIT2
+#define B_PCH_XHCI_XHCLKGTEN_IOSFBTCGE BIT1
+#define B_PCH_XHCI_XHCLKGTEN_IOSFGBLCGE BIT0
+
+#define R_PCH_XHCI_USB_RELNUM 0x60
+#define B_PCH_XHCI_USB_RELNUM 0xFF
+#define R_PCH_XHCI_FL_ADJ 0x61
+#define B_PCH_XHCI_FL_ADJ 0x3F
+#define R_PCH_XHCI_PWR_CAPID 0x70
+#define B_PCH_XHCI_PWR_CAPID 0xFF
+#define R_PCH_XHCI_NXT_PTR1 0x71
+#define B_PCH_XHCI_NXT_PTR1 0xFF
+#define R_PCH_XHCI_PWR_CAP 0x72
+#define B_PCH_XHCI_PWR_CAP_PME_SUP 0xF800
+#define B_PCH_XHCI_PWR_CAP_D2_SUP BIT10
+#define B_PCH_XHCI_PWR_CAP_D1_SUP BIT9
+#define B_PCH_XHCI_PWR_CAP_AUX_CUR (BIT8 | BIT7 | BIT6)
+#define B_PCH_XHCI_PWR_CAP_DSI BIT5
+#define B_PCH_XHCI_PWR_CAP_PME_CLK BIT3
+#define B_PCH_XHCI_PWR_CAP_VER (BIT2 | BIT1 | BIT0)
+#define R_PCH_XHCI_PWR_CNTL_STS 0x74
+#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15
+#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13)
+#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9)
+#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8
+#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)
+#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)
+#define R_PCH_XHCI_MSI_MCTL 0x82
+#define R_PCH_XHCI_U2OCM 0xB0
+#define R_PCH_XHCI_U3OCM 0xD0
+#define V_PCH_XHCI_NUMBER_OF_OC_PINS 8
+
+#define R_PCH_XHCI_FUS 0xE0
+#define B_PCH_XHCI_FUS_USBR (BIT5)
+#define V_PCH_XHCI_FUS_USBR_EN 0
+#define V_PCH_XHCI_FUS_USBR_DIS (BIT5)
+
+#define R_PCH_XHCI_FC 0xFC
+
+#define B_PCH_XHCI_FUS_SSPRTCNT (BIT4 | BIT3)
+#define V_PCH_XHCI_FUS_SSPRTCNT_00B 0
+#define V_PCH_XHCI_FUS_SSPRTCNT_01B (BIT3)
+#define V_PCH_XHCI_FUS_SSPRTCNT_10B (BIT4)
+#define V_PCH_XHCI_FUS_SSPRTCNT_11B (BIT4 | BIT3)
+
+#define B_PCH_XHCI_FUS_HSPRTCNT (BIT2 | BIT1)
+#define V_PCH_XHCI_FUS_HSPRTCNT_00B 0
+#define V_PCH_XHCI_FUS_HSPRTCNT_01B (BIT1)
+#define V_PCH_XHCI_FUS_HSPRTCNT_10B (BIT2)
+#define V_PCH_XHCI_FUS_HSPRTCNT_11B (BIT2 | BIT1)
+
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_CNT 6
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_CNT 4
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_CNT 2
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_CNT 0
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_MASK 0x3F
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_MASK 0x0F
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_MASK 0x03
+#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_MASK 0x00
+
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_CNT 14
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_CNT 12
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_CNT 10
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_CNT 8
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_MASK 0x3FFF
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_MASK 0x3F3F
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_MASK 0x03FF
+#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_MASK 0x00FF
+
+#define V_PCH_LP_XHCI_FIXED_SSPRTCNT 4
+#define V_PCH_LP_XHCI_FIXED_SSPRTCNT_MASK 0x0F
+
+#define V_PCH_LP_XHCI_FIXED_HSPRTCNT 8
+#define V_PCH_LP_XHCI_FIXED_HSPRTCNT_MASK 0x00FF
+
+//
+// xHCI MMIO registers
+//
+
+//
+// 0x00 - 0x1F - Capability Registers
+//
+#define R_PCH_XHCI_CAPLENGTH 0x00
+#define R_PCH_XHCI_HCIVERSION 0x02
+#define R_PCH_XHCI_HCSPARAMS1 0x04
+#define R_PCH_XHCI_HCSPARAMS2 0x08
+#define R_PCH_XHCI_HCSPARAMS3 0x0C
+#define B_PCH_XHCI_HCSPARAMS3_U2DEL 0xFFFF0000
+#define B_PCH_XHCI_HCSPARAMS3_U1DEL 0x0000FFFF
+#define R_PCH_XHCI_HCCPARAMS 0x10
+#define B_PCH_XHCI_HCCPARAMS_LHRC BIT5
+#define B_PCH_XHCI_HCCPARAMS_MAXPSASIZE 0xF000
+#define R_PCH_XHCI_DBOFF 0x14
+#define R_PCH_XHCI_RTSOFF 0x18
+
+//
+// 0x80 - 0xBF - Operational Registers
+//
+#define R_PCH_XHCI_USBCMD 0x80
+#define B_PCH_XHCI_USBCMD_RS BIT0 ///< Run/Stop
+#define B_PCH_XHCI_USBCMD_RST BIT1 ///< HCRST
+#define R_PCH_XHCI_USBSTS 0x84
+#define B_PCH_XHCI_USBSTS_HCH BIT0
+#define B_PCH_XHCI_USBSTS_CNR BIT11
+
+//
+// 0x480 - 0x5CF - Port Status and Control Registers
+//
+#define R_PCH_LP_XHCI_PORTSC01USB2 0x480
+#define R_PCH_LP_XHCI_PORTSC02USB2 0x490
+#define R_PCH_LP_XHCI_PORTSC03USB2 0x4A0
+#define R_PCH_LP_XHCI_PORTSC04USB2 0x4B0
+#define R_PCH_LP_XHCI_PORTSC05USB2 0x4C0
+#define R_PCH_LP_XHCI_PORTSC06USB2 0x4D0
+#define R_PCH_LP_XHCI_PORTSC07USB2 0x4E0
+#define R_PCH_LP_XHCI_PORTSC08USB2 0x4F0
+#define R_PCH_LP_XHCI_PORTSC09USB2 0x500
+#define R_PCH_LP_XHCI_PORTSC10USB2 0x510
+
+
+#define R_PCH_LP_XHCI_PORTSC01USB3 0x540
+#define R_PCH_LP_XHCI_PORTSC02USB3 0x550
+#define R_PCH_LP_XHCI_PORTSC03USB3 0x560
+#define R_PCH_LP_XHCI_PORTSC04USB3 0x570
+#define R_PCH_LP_XHCI_PORTSC05USB3 0x580
+#define R_PCH_LP_XHCI_PORTSC06USB3 0x590
+
+//
+// 0x480 - 0x5CF - Port Status and Control Registers
+//
+#define R_PCH_H_XHCI_PORTSC01USB2 0x480
+#define R_PCH_H_XHCI_PORTSC02USB2 0x490
+#define R_PCH_H_XHCI_PORTSC03USB2 0x4A0
+#define R_PCH_H_XHCI_PORTSC04USB2 0x4B0
+#define R_PCH_H_XHCI_PORTSC05USB2 0x4C0
+#define R_PCH_H_XHCI_PORTSC06USB2 0x4D0
+#define R_PCH_H_XHCI_PORTSC07USB2 0x4E0
+#define R_PCH_H_XHCI_PORTSC08USB2 0x4F0
+#define R_PCH_H_XHCI_PORTSC09USB2 0x500
+#define R_PCH_H_XHCI_PORTSC10USB2 0x510
+#define R_PCH_H_XHCI_PORTSC11USB2 0x520
+#define R_PCH_H_XHCI_PORTSC12USB2 0x530
+#define R_PCH_H_XHCI_PORTSC13USB2 0x540
+#define R_PCH_H_XHCI_PORTSC14USB2 0x550
+
+#define R_PCH_H_XHCI_PORTSC15USBR 0x560
+#define R_PCH_H_XHCI_PORTSC16USBR 0x570
+
+#define R_PCH_H_XHCI_PORTSC01USB3 0x580
+#define R_PCH_H_XHCI_PORTSC02USB3 0x590
+#define R_PCH_H_XHCI_PORTSC03USB3 0x5A0
+#define R_PCH_H_XHCI_PORTSC04USB3 0x5B0
+#define R_PCH_H_XHCI_PORTSC05USB3 0x5C0
+#define R_PCH_H_XHCI_PORTSC06USB3 0x5D0
+#define R_PCH_H_XHCI_PORTSC07USB3 0x5E0
+#define R_PCH_H_XHCI_PORTSC08USB3 0x5F0
+#define R_PCH_H_XHCI_PORTSC09USB3 0x600
+#define R_PCH_H_XHCI_PORTSC10USB3 0x610
+
+#define B_PCH_XHCI_PORTSCXUSB2_WPR BIT31 ///< Warm Port Reset
+#define B_PCH_XHCI_PORTSCXUSB2_CEC BIT23 ///< Port Config Error Change
+#define B_PCH_XHCI_PORTSCXUSB2_PLC BIT22 ///< Port Link State Change
+#define B_PCH_XHCI_PORTSCXUSB2_PRC BIT21 ///< Port Reset Change
+#define B_PCH_XHCI_PORTSCXUSB2_OCC BIT20 ///< Over-current Change
+#define B_PCH_XHCI_PORTSCXUSB2_WRC BIT19 ///< Warm Port Reset Change
+#define B_PCH_XHCI_PORTSCXUSB2_PEC BIT18 ///< Port Enabled Disabled Change
+#define B_PCH_XHCI_PORTSCXUSB2_CSC BIT17 ///< Connect Status Change
+#define B_PCH_XHCI_PORTSCXUSB2_LWS BIT16 ///< Port Link State Write Strobe
+#define B_PCH_XHCI_USB2_U3_EXIT (BIT5 | BIT6 | BIT7 | BIT8)
+#define B_PCH_XHCI_USB2_U0_MASK (BIT5 | BIT6 | BIT7 | BIT8)
+#define B_PCH_XHCI_PORTSCXUSB2_PP BIT9
+#define B_PCH_XHCI_PORTSCXUSB2_PLS (BIT5 | BIT6 | BIT7 | BIT8) ///< Port Link State
+#define B_PCH_XHCI_PORTSCXUSB2_PR BIT4 ///< Port Reset
+#define B_PCH_XHCI_PORTSCXUSB2_PED BIT1 ///< Port Enable/Disabled
+#define B_PCH_XHCI_PORTSCXUSB2_CCS BIT0 ///< Current Connect Status
+#define B_PCH_XHCI_PORT_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB2_CEC | B_PCH_XHCI_PORTSCXUSB2_PLC | B_PCH_XHCI_PORTSCXUSB2_PRC | B_PCH_XHCI_PORTSCXUSB2_OCC | B_PCH_XHCI_PORTSCXUSB2_WRC | B_PCH_XHCI_PORTSCXUSB2_PEC | B_PCH_XHCI_PORTSCXUSB2_CSC | B_PCH_XHCI_PORTSCXUSB2_PED)
+#define B_PCH_XHCI_PORTPMSCXUSB2_PTC (BIT28 | BIT29 | BIT30 | BIT31) ///< Port Test Control
+
+#define B_PCH_XHCI_PORTSCXUSB3_WPR BIT31 ///< Warm Port Reset
+#define B_PCH_XHCI_PORTSCXUSB3_CEC BIT23 ///< Port Config Error Change
+#define B_PCH_XHCI_PORTSCXUSB3_PLC BIT22 ///< Port Link State Change
+#define B_PCH_XHCI_PORTSCXUSB3_PRC BIT21 ///< Port Reset Change
+#define B_PCH_XHCI_PORTSCXUSB3_OCC BIT20 ///< Over-current Change
+#define B_PCH_XHCI_PORTSCXUSB3_WRC BIT19 ///< Warm Port Reset Change
+#define B_PCH_XHCI_PORTSCXUSB3_PEC BIT18 ///< Port Enabled Disabled Change
+#define B_PCH_XHCI_PORTSCXUSB3_CSC BIT17 ///< Connect Status Change
+#define B_PCH_XHCI_PORTSCXUSB3_PP BIT9 ///< Port Power
+#define B_PCH_XHCI_PORTSCXUSB3_PLS (BIT8 | BIT7 | BIT6 | BIT5) ///< Port Link State
+#define V_PCH_XHCI_PORTSCXUSB3_PLS_POLLING 0x000000E0 ///< Link is in the Polling State
+#define V_PCH_XHCI_PORTSCXUSB3_PLS_RXDETECT 0x000000A0 ///< Link is in the RxDetect State
+#define B_PCH_XHCI_PORTSCXUSB3_PR BIT4 ///< Port Reset
+#define B_PCH_XHCI_PORTSCXUSB3_PED BIT1 ///< Port Enable/Disabled
+#define B_PCH_XHCI_PORTSCXUSB3_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB3_CEC | B_PCH_XHCI_PORTSCXUSB3_PLC | B_PCH_XHCI_PORTSCXUSB3_PRC | B_PCH_XHCI_PORTSCXUSB3_OCC | B_PCH_XHCI_PORTSCXUSB3_WRC | B_PCH_XHCI_PORTSCXUSB3_PEC | B_PCH_XHCI_PORTSCXUSB3_CSC | B_PCH_XHCI_PORTSCXUSB3_PED)
+//
+// 0x2000 - 0x21FF - Runtime Registers
+// 0x3000 - 0x307F - Doorbell Registers
+//
+#define R_PCH_XHCI_XECP_SUPP_USB2_2 0x8008
+#define R_PCH_XHCI_XECP_SUPP_USB3_2 0x8028
+#define R_PCH_XHCI_HOST_CTRL_SCH_REG 0x8094
+#define R_PCH_XHCI_HOST_CTRL_IDMA_REG 0x809C
+#define R_PCH_XHCI_PMCTRL 0x80A4
+#define R_PCH_XHCI_PGCBCTRL 0x80A8 ///< PGCB Control
+#define R_PCH_XHCI_HOST_CTRL_MISC_REG 0x80B0 ///< Host Controller Misc Reg
+#define R_PCH_XHCI_HOST_CTRL_MISC_REG_2 0x80B4 ///< Host Controller Misc Reg 2
+#define R_PCH_XHCI_SSPE 0x80B8 ///< Super Speed Port Enables
+#define B_PCH_XHCI_LP_SSPE_MASK 0x3F ///< LP: Mask for 6 USB3 ports
+#define B_PCH_XHCI_H_SSPE_MASK 0x3FF ///< H: Mask for 10 USB3 ports
+#define R_PCH_XHCI_DUAL_ROLE_CFG0 0x80D8
+#define R_PCH_XHCI_DUAL_ROLE_CFG1 0x80DC
+#define R_PCH_XHCI_AUX_CTRL_REG1 0x80E0
+#define R_PCH_XHCI_HOST_CTRL_PORT_LINK_REG 0x80EC ///< SuperSpeed Port Link Control
+#define R_PCH_XHCI_XECP_CMDM_CTRL_REG1 0x818C ///< Command Manager Control 1
+#define R_PCH_XHCI_XECP_CMDM_CTRL_REG2 0x8190 ///< Command Manager Control 2
+#define R_PCH_XHCI_XECP_CMDM_CTRL_REG3 0x8194 ///< Command Manager Control 3
+#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW1 0x80F0 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
+#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW2 0x80F4 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
+#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW3 0x80F8 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
+#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW4 0x80FC ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
+#define R_PCH_XHCI_HOST_CTRL_TRM_REG2 0x8110 ///< HOST_CTRL_TRM_REG2 - Host Controller Transfer Manager Control 2
+#define R_PCH_XHCI_AUX_CTRL_REG2 0x8154 ///< AUX_CTRL_REG2 - Aux PM Control Register 2
+#define R_PCH_XHCI_AUXCLKCTL 0x816C ///< xHCI Aux Clock Control Register
+#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG0 0x8140 ///< HOST_IF_PWR_CTRL_REG0 - Power Scheduler Control 0
+#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG1 0x8144 ///< HOST_IF_PWR_CTRL_REG1 - Power Scheduler Control 1
+#define R_PCH_XHCI_XHCLTVCTL2 0x8174 ///< xHC Latency Tolerance Parameters - LTV Control
+#define R_PCH_XHCI_LTVHIT 0x817C ///< xHC Latency Tolerance Parameters - High Idle Time Control
+#define R_PCH_XHCI_LTVMIT 0x8180 ///< xHC Latency Tolerance Parameters - Medium Idle Time Control
+#define R_PCH_XHCI_LTVLIT 0x8184 ///< xHC Latency Tolerance Parameters - Low Idle Time Control
+#define R_PCH_XHCI_USB2PHYPM 0x8164 ///< USB2 PHY Power Management Control
+#define R_PCH_XHCI_PDDIS 0x8198 ///< xHC Pulldown Disable Control
+#define R_PCH_XHCI_THROTT 0x819C ///< XHCI Throttle Control
+#define R_PCH_XHCI_LFPSPM 0x81A0 ///< LFPS PM Control
+#define R_PCH_XHCI_THROTT2 0x81B4 ///< XHCI Throttle
+#define R_PCH_XHCI_LFPSONCOUNT 0x81B8 ///< LFPS On Count
+#define R_PCH_XHCI_D0I2CTRL 0x81BC ///< D0I2 Control Register
+#define R_PCH_XHCI_USB2PMCTRL 0x81C4 ///< USB2 Power Management Control
+
+//
+// SKL PCH LP FUSE
+//
+#define R_PCH_XHCI_LP_FUSE1 0x8410
+#define B_PCH_XHCI_LP_FUS_HSPRTCNT (BIT1)
+#define B_PCH_XHCI_LP_FUS_USBR (BIT5)
+#define R_PCH_XHCI_STRAP2 0x8420 ///< USB3 Mode Strap
+#define R_PCH_XHCI_USBLEGCTLSTS 0x8470 ///< USB Legacy Support Control Status
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIBAR BIT31 ///< SMI on BAR Status
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCIC BIT30 ///< SMI on PCI Command Status
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSC BIT29 ///< SMI on OS Ownership Change Status
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIBARE BIT15 ///< SMI on BAR Enable
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCICE BIT14 ///< SMI on PCI Command Enable
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSOE BIT13 ///< SMI on OS Ownership Enable
+#define B_PCH_XHCI_USBLEGCTLSTS_SMIHSEE BIT4 ///< SMI on Host System Error Enable
+#define B_PCH_XHCI_USBLEGCTLSTS_USBSMIE BIT0 ///< USB SMI Enable
+
+//
+// Extended Capability Registers
+//
+#define R_PCH_XHCI_USB2PDO 0x84F8
+#define B_PCH_XHCI_LP_USB2PDO_MASK 0x3FF ///< LP: Mask for 10 USB2 ports
+#define B_PCH_XHCI_H_USB2PDO_MASK 0x7FFF ///< H: Mask for 14 USB2 ports
+#define B_PCH_XHCI_USB2PDO_DIS_PORT0 BIT0
+
+#define R_PCH_XHCI_USB3PDO 0x84FC
+#define B_PCH_XHCI_LP_USB3PDO_MASK 0x3F ///< LP: Mask for 6 USB3 ports
+#define B_PCH_XHCI_H_USB3PDO_MASK 0x3FF ///< H: Mask for 10 USB3 ports
+#define B_PCH_XHCI_USB3PDO_DIS_PORT0 BIT0
+
+//
+// Debug Capability Descriptor Parameters
+//
+#define R_PCH_XHCI_DBC_DBCCTL 0x8760 ///< DBCCTL - DbC Control
+
+//
+// xDCI (OTG) USB Device Controller
+//
+#define PCI_DEVICE_NUMBER_PCH_XDCI 20
+#define PCI_FUNCTION_NUMBER_PCH_XDCI 1
+
+//
+// xDCI (OTG) PCI Config Space Registers
+//
+#define R_PCH_XDCI_MEM_BASE 0x10
+#define V_PCH_XDCI_MEM_LENGTH 0x200000
+#define R_PCH_XDCI_PMCSR 0x84 ///< Power Management Control and Status Register
+#define R_PCH_XDCI_GENERAL_PURPOSER_REG1 0xA0 ///< General Purpose PCI RW Register1
+#define R_PCH_XDCI_CPGE 0xA2 ///< Chassis Power Gate Enable
+#define R_PCH_XDCI_GENERAL_PURPOSER_REG4 0xAC ///< General Purpose PCI RW Register4
+#define R_PCH_OTG_GENERAL_INPUT_REG 0xC0 ///< General Input Register
+
+//
+// xDCI (OTG) MMIO registers
+//
+#define R_PCH_XDCI_GCTL 0xC110 ///< Xdci Global Ctrl
+#define B_PCH_XDCI_GCTL_GHIBEREN BIT1 ///< Hibernation enable
+#define R_PCH_XDCI_GUSB2PHYCFG 0xC200 ///< Global USB2 PHY Configuration Register
+#define B_PCH_XDCI_GUSB2PHYCFG_SUSPHY BIT6 ///< Suspend USB2.0 HS/FS/LS PHY
+#define R_PCH_XDCI_GUSB3PIPECTL0 0xC2C0 ///< Global USB3 PIPE Control Register 0
+#define B_PCH_XDCI_GUSB3PIPECTL0_UX_IN_PX BIT27 ///< Ux Exit in Px
+#define R_PCH_XDCI_APBFC_U3PMU_CFG2 0x10F810
+#define R_PCH_XDCI_APBFC_U3PMU_CFG4 0x10F818
+
+//
+// xDCI (OTG) Private Configuration Registers
+// (PID:OTG)
+//
+#define R_PCH_PCR_OTG_IOSF_A2 0xA2
+#define R_PCH_PCR_OTG_IOSF_PMCTL 0x1D0
+#define R_PCH_PCR_OTG_PCICFGCTRL1 0x200
+#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 0x0FF00000
+#define N_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 20
+#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 0x000FF000
+#define N_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 12
+#define B_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 0x00000F00
+#define N_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 8
+#define B_PCH_PCR_OTG_PCICFGCTRL_BAR1_DIS 0x00000080
+#define B_PCH_PCR_OTG_PCICFGCTRL_PME_SUP 0x0000007C
+#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_INT_EN 0x00000002
+#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_CFG_DIS 0x00000001
+
+//
+// USB2 Private Configuration Registers
+// USB2 HIP design featured
+// (PID:USB2)
+//
+#define R_PCH_PCR_USB2_GLOBAL_PORT 0x4001 ///< USB2 GLOBAL PORT
+#define R_PCH_PCR_USB2_400C 0x400C
+#define R_PCH_PCR_USB2_PP_LANE_BASE_ADDR 0x4000 ///< PP LANE base address
+#define V_PCH_PCR_USB2_PER_PORT 0x00 ///< USB2 PER PORT Addr[7:2] = 0x00
+#define V_PCH_PCR_USB2_UTMI_MISC_PER_PORT 0x08 ///< UTMI MISC REG PER PORT Addr[7:2] = 0x08
+#define V_PCH_PCR_USB2_PER_PORT_2 0x26 ///< USB2 PER PORT 2 Addr[7:2] = 0x26
+#define R_PCH_PCR_USB2_402A 0x402A
+#define R_PCH_PCR_USB2_GLB_ADP_VBUS_REG 0x402B ///< GLB ADP VBUS REG
+#define R_PCH_PCR_USB2_GLOBAL_PORT_2 0x402C ///< USB2 GLOBAL PORT 2
+#define R_PCH_PCR_USB2_7034 0x7034
+#define R_PCH_PCR_USB2_7038 0x7038
+#define R_PCH_PCR_USB2_703C 0x703C
+#define R_PCH_PCR_USB2_7040 0x7040
+#define R_PCH_PCR_USB2_7044 0x7044
+#define R_PCH_PCR_USB2_7048 0x7048
+#define R_PCH_PCR_USB2_704C 0x704C
+#define R_PCH_PCR_USB2_CFG_COMPBG 0x7F04 ///< USB2 COMPBG
+
+//
+// xHCI SSIC registers
+//
+#define R_PCH_XHCI_SSIC_GLOBAL_CONF_CTRL 0x8804 ///< SSIC Global Configuration Control
+#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_1 0x8808 ///< SSIC Configuration Register 1 Port 1
+#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_1 0x880C ///< SSIC Configuration Register 2 Port 1
+#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_1 0x8810 ///< SSIC Configuration Register 3 Port 1
+#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_2 0x8838 ///< SSIC Configuration Register 1 Port 2
+#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_2 0x883C ///< SSIC Configuration Register 2 Port 2
+#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_2 0x8840 ///< SSIC Configuration Register 3 Port 2
+#define B_PCH_XHCI_SSIC_CONF_REG2_PORT_UNUSED BIT31
+#define B_PCH_XHCI_SSIC_CONF_REG2_PROG_DONE BIT30
+
+#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_1 0x8900 ///< Profile Attributes: Port 1 ... N
+#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_1 0x8904 ///< SSIC Port N Register Access Control: Port 1
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_0C 0x890C
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_10 0x8910
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_14 0x8914
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_18 0x8918
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_1C 0x891C
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_20 0x8920
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_24 0x8924
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_28 0x8928
+
+#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_2 0x8A10 ///< Profile Attributes: Port 2 ... N
+#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_2 0x8A14 ///< SSIC Port N Register Access Control: Port 2
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_0C 0x8A1C
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_10 0x8A20
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_14 0x8A24
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_18 0x8A28
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_1C 0x8A2C
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_20 0x8A30
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_24 0x8A34
+#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_28 0x8A38
+
+#endif
--
2.27.0.windows.1
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