[edk2-devel] [edk2-platforms] [PATCH V1 04/18] PurleyRefreshSiliconPkg/Pch: Add Private Header Files
Nate DeSimone
nathaniel.l.desimone at intel.com
Tue May 11 09:48:12 UTC 2021
Cc: Chasel Chiu <chasel.chiu at intel.com>
Cc: Mike Kinney <michael.d.kinney at intel.com>
Cc: Isaac Oram <isaac.w.oram at intel.com>
Cc: Mohamed Abbas <mohamed.abbas at intel.com>
Cc: Michael Kubacki <michael.kubacki at microsoft.com>
Cc: Zachary Bobroff <zacharyb at ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad at ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone at intel.com>
---
.../Library/PchResetCommonLib.h | 59 +++++++
.../Pch/IncludePrivate/PchHHsioAx.h | 16 ++
.../Pch/IncludePrivate/PchHHsioBx.h | 16 ++
.../Pch/IncludePrivate/PchHHsioDx.h | 16 ++
.../Pch/IncludePrivate/PchHsio.h | 147 ++++++++++++++++++
.../Pch/IncludePrivate/PchLbgHsioAx.h | 16 ++
.../Pch/IncludePrivate/PchLbgHsioBx.h | 17 ++
.../Pch/IncludePrivate/PchLbgHsioBxD.h | 19 +++
.../Pch/IncludePrivate/PchLbgHsioBxD_Ext.h | 19 +++
.../Pch/IncludePrivate/PchLbgHsioBx_Ext.h | 17 ++
.../Pch/IncludePrivate/PchLbgHsioSx.h | 17 ++
.../Pch/IncludePrivate/PchLbgHsioSx_Ext.h | 17 ++
.../Pch/IncludePrivate/PchLpHsioBx.h | 16 ++
.../Pch/IncludePrivate/PchLpHsioCx.h | 16 ++
.../Pch/IncludePrivate/PchPolicyHob.h | 18 +++
15 files changed, 426 insertions(+)
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/Library/PchResetCommonLib.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioAx.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioBx.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioDx.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHsio.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioAx.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBxD.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBxD_Ext.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx_Ext.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx_Ext.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioBx.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioCx.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchPolicyHob.h
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/Library/PchResetCommonLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/Library/PchResetCommonLib.h
new file mode 100644
index 0000000000..a1d076c06c
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/Library/PchResetCommonLib.h
@@ -0,0 +1,59 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_RESET_COMMON_LIB_H_
+#define _PCH_RESET_COMMON_LIB_H_
+#include <Uefi/UefiSpec.h>
+#include <Protocol/PchReset.h>
+///
+/// Private data structure definitions for the driver
+///
+#define PCH_RESET_SIGNATURE SIGNATURE_32 ('I', 'E', 'R', 'S')
+
+typedef struct {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ union {
+ PCH_RESET_PPI PchResetPpi;
+ PCH_RESET_PROTOCOL PchResetProtocol;
+ }PchResetInterface;
+ UINT32 PchPwrmBase;
+ UINT16 PchAcpiBase;
+ UINTN PchPmcBase;
+} PCH_RESET_INSTANCE;
+
+//
+// Function prototypes used by the Pch Reset ppi/protocol.
+//
+/**
+ Initialize an Pch Reset ppi/protocol instance.
+
+ @param[in] PchResetInstance Pointer to PchResetInstance to initialize
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @exception EFI_UNSUPPORTED The PCH is not supported by this module
+**/
+EFI_STATUS
+PchResetConstructor (
+ PCH_RESET_INSTANCE *PchResetInstance
+ );
+
+/**
+ Execute Pch Reset from the host controller.
+ @param[in] PchResetInstance Pointer to PchResetInstance to initialize
+ @param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset,
+ PowerCycleReset, GlobalReset, GlobalResetWithEc
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER If ResetType is invalid.
+**/
+EFI_STATUS
+PchReset (
+ IN PCH_RESET_INSTANCE *PchResetInstance,
+ IN PCH_RESET_TYPE PchResetType
+ );
+#endif
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioAx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioAx.h
new file mode 100644
index 0000000000..37adb642c6
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioAx.h
@@ -0,0 +1,16 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_H_HSIO_AX_H_
+#define _PCH_H_HSIO_AX_H_
+
+#define PCH_H_HSIO_VER_AX 0x11
+
+extern UINT8 PchHChipsetInitTable_Ax[1300];
+extern PCH_SBI_HSIO_TABLE_STRUCT PchHHsio_Ax[136];
+
+#endif //_PCH_H_HSIO_AX_H_
\ No newline at end of file
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioBx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioBx.h
new file mode 100644
index 0000000000..abbe638ff7
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioBx.h
@@ -0,0 +1,16 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_H_HSIO_BX_H_
+#define _PCH_H_HSIO_BX_H_
+
+#define PCH_H_HSIO_VER_BX 0x3e
+
+extern UINT8 PchHChipsetInitTable_Bx[2060];
+extern PCH_SBI_HSIO_TABLE_STRUCT PchHHsio_Bx[136];
+
+#endif //_PCH_H_HSIO_BX_H_
\ No newline at end of file
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioDx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioDx.h
new file mode 100644
index 0000000000..ea778f3855
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioDx.h
@@ -0,0 +1,16 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_H_HSIO_DX_H_
+#define _PCH_H_HSIO_DX_H_
+
+#define PCH_H_HSIO_VER_DX 0x34
+
+extern UINT8 PchHChipsetInitTable_Dx[2180];
+extern PCH_SBI_HSIO_TABLE_STRUCT PchHHsio_Dx[157];
+
+#endif //_PCH_H_HSIO_DX_H_
\ No newline at end of file
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHsio.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHsio.h
new file mode 100644
index 0000000000..584838fb83
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHsio.h
@@ -0,0 +1,147 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_HSIO_H_
+#define _PCH_HSIO_H_
+
+#define PCH_HSIO_SKU_SKL 0x01
+
+#define PCH_LANE_OWN_COMMON 0x10
+#define PCH_LANE_BDCAST 0x11
+
+#define PCH_HSIO_LANE_GROUP_NO 0x09
+#define PCH_HSIO_LANE_GROUP_COMMON_LANE 0x00
+#define PCH_HSIO_LANE_GROUP_PCIE 0x01
+#define PCH_HSIO_LANE_GROUP_DMI 0x02
+#define PCH_HSIO_LANE_GROUP_GBE 0x03
+#define PCH_HSIO_LANE_GROUP_USB3 0x04
+#define PCH_HSIO_LANE_GROUP_SATA 0x05
+#define PCH_HSIO_LANE_GROUP_SSIC 0x06
+
+#define PCH_MODPHY0_LP_LOS1_LANE_START 0x00
+#define PCH_MODPHY0_LP_LOS1_LANE_END 0x05
+#define PCH_MODPHY1_LP_LOS1_LANE_START 0x06
+#define PCH_MODPHY1_LP_LOS1_LANE_END 0x07
+#define PCH_MODPHY1_LP_LOS2_LANE_START 0x00
+#define PCH_MODPHY1_LP_LOS2_LANE_END 0x01
+#define PCH_MODPHY2_LP_LOS2_LANE_START 0x02
+#define PCH_MODPHY2_LP_LOS2_LANE_END 0x07
+
+#define PCH_MODPHY1_LOS1_LANE_START 0x00
+#define PCH_MODPHY1_LOS1_LANE_END 0x07
+#define PCH_MODPHY1_LOS2_LANE_START 0x00
+#define PCH_MODPHY1_LOS2_LANE_END 0x01
+#define PCH_MODPHY2_LOS2_LANE_START 0x02
+#define PCH_MODPHY2_LOS2_LANE_END 0x07
+#define PCH_MODPHY2_LOS3_LANE_START 0x00
+#define PCH_MODPHY2_LOS3_LANE_END 0x07
+#define PCH_MODPHY2_LOS4_LANE_START 0x00
+#define PCH_MODPHY2_LOS4_LANE_END 0x01
+
+/**
+ PCH SBI HSIO table data structure
+**/
+typedef struct {
+ UINT32 PortId;
+ UINT32 Value;
+ UINT16 Offset;
+ UINT8 LanePhyMode;
+} PCH_SBI_HSIO_TABLE_STRUCT;
+
+
+#define PMC_DATA_SBI_CMD_SIZE ((12/sizeof(UINT16))-1)
+#define PMC_DATA_DELAY_CMD_SIZE ((4/sizeof(UINT16))-1)
+
+// Commands specified command table and processed by the PMC & it's HW accelerator
+typedef enum {
+ SendSBIPosted = 0x0, // Perform a SBI Write & wait for result
+ SendSBINonPosted, // Perform a SBI Write & ignore return result (Not Supported in HW)
+ DoDelay, // PMC Inserts Delay when command detected
+ EndStruct = 0x7 // No-op Command indicating end of list
+} PHY_COMMANDS;
+
+/**
+PCH HSIO PMC XRAM Header
+**/
+typedef struct {
+ UINT16 Word0;
+ UINT16 Word1;
+ UINT16 Word2;
+ UINT16 Word3;
+ UINT16 Word4;
+ UINT16 Word5;
+ UINT16 Word6;
+ UINT16 Word7;
+ UINT16 Word8;
+ UINT16 Word9;
+ UINT16 Word10;
+ UINT16 Word11;
+ UINT16 Word12;
+ UINT16 Word13;
+ UINT16 Word14;
+ UINT16 Word15;
+} PCH_SBI_HSIO_HDR_TBL;
+
+/**
+PCH HSIO PMC XRAM Data
+**/
+typedef struct {
+ UINT8 Command : 3;
+ UINT8 Size : 5;
+ UINT8 Pid;
+ UINT8 OpCode; //PrivateControlWrite
+ UINT8 Bar; //0
+ UINT8 Fbe; //First Byte Enable : 0x0F
+ UINT8 Fid; //0
+ UINT16 Offset;
+ UINT32 Value;
+} PCH_SBI_HSIO_CMD_TBL;
+
+/**
+PCH HSIO Delay XRAM Data
+**/
+typedef struct {
+ UINT8 Command : 3;
+ UINT8 Size : 5;
+ UINT8 DelayPeriod; //(00h = 1us, 01h = 10us, 02h = 100us, ..., 07h = 10s; others reserved)
+ UINT8 DelayCount; //(0 - 255); total delay = Delay period * Delay count
+ UINT8 Padding;
+} PCH_DELAY_HSIO_CMD_TBL;
+
+typedef enum {
+ Delay1us = 0x0,
+ Delay10us,
+ Delay100us,
+ Delay1ms,
+ Delay10ms,
+ Delay100ms,
+ Delay1s,
+ Delay10s
+} DELAY;
+
+/**
+PCH PCIE PLL SSC Data
+**/
+#define MAX_PCIE_PLL_SSC_PERCENT 20
+
+#include <IncludePrivate/PchHHsioBx.h>
+#include <IncludePrivate/PchHHsioDx.h>
+#include <IncludePrivate/PchLpHsioBx.h>
+#include <IncludePrivate/PchLpHsioCx.h>
+
+#include <IncludePrivate/PchLbgHsioAx.h>
+#include <IncludePrivate/PchLbgHsioBx.h>
+#include <IncludePrivate/PchLbgHsioBx_Ext.h>
+#include <IncludePrivate/PchLbgHsioSx.h>
+#include <IncludePrivate/PchLbgHsioSx_Ext.h>
+#ifdef SKXD_EN
+#include <IncludePrivate/PchLbgHsioBxD.h>
+#include <IncludePrivate/PchLbgHsioBxD_Ext.h>
+#endif // SKXD_EN
+
+#endif //_PCH_HSIO_H_
+
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioAx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioAx.h
new file mode 100644
index 0000000000..5bd69194f8
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioAx.h
@@ -0,0 +1,16 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_LBG_HSIO_AX_H_
+#define _PCH_LBG_HSIO_AX_H_
+
+#define PCH_LBG_HSIO_VER_AX 0x19
+
+extern UINT8 PchLbgChipsetInitTable_Ax[2988];
+extern PCH_SBI_HSIO_TABLE_STRUCT PchLbgHsio_Ax[81];
+
+#endif //_PCH_LBG_HSIO_AX_H_
\ No newline at end of file
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx.h
new file mode 100644
index 0000000000..4cc1ff977d
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx.h
@@ -0,0 +1,17 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_LBG_HSIO_BX_H_
+#define _PCH_LBG_HSIO_BX_H_
+
+#define PCH_LBG_HSIO_VER_BX 0x2f
+
+extern UINT8 PchLbgChipsetInitTable_Bx[2844];
+extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_Bx_Ptr;
+extern UINT16 PchLbgHsio_Bx_Size;
+
+#endif //_PCH_LBG_HSIO_BX_H_
\ No newline at end of file
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBxD.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBxD.h
new file mode 100644
index 0000000000..8ee7a664ec
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBxD.h
@@ -0,0 +1,19 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifdef SKXD_EN
+#ifndef _PCH_LBG_HSIO_BX_D_H_
+#define _PCH_LBG_HSIO_BX_D_H_
+
+#define PCH_LBG_HSIO_VER_BX_D 0x2
+
+extern UINT8 PchLbgChipsetInitTable_BxD[2844];
+extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_BxD_Ptr;
+extern UINT16 PchLbgHsio_BxD_Size;
+
+#endif //_PCH_LBG_HSIO_BX_D_H_
+#endif // SKXD_EN
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBxD_Ext.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBxD_Ext.h
new file mode 100644
index 0000000000..4d13c2a1db
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBxD_Ext.h
@@ -0,0 +1,19 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifdef SKXD_EN
+#ifndef _PCH_LBG_HSIO_BX_D_EXT_H_
+#define _PCH_LBG_HSIO_BX_D_EXT_H_
+
+#define PCH_LBG_HSIO_VER_BX_D_EXT 0x2
+
+extern UINT8 PchLbgChipsetInitTable_BxD_Ext[2844];
+extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_BxD_Ext_Ptr;
+extern UINT16 PchLbgHsio_BxD_Ext_Size;
+
+#endif //_PCH_LBG_HSIO_BX_D_EXT_H_
+#endif // SKXD_EN
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx_Ext.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx_Ext.h
new file mode 100644
index 0000000000..4b228c6044
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx_Ext.h
@@ -0,0 +1,17 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_LBG_HSIO_BX_EXT_H_
+#define _PCH_LBG_HSIO_BX_EXT_H_
+
+#define PCH_LBG_HSIO_VER_BX_EXT 0x2f
+
+extern UINT8 PchLbgChipsetInitTable_Bx_Ext[2844];
+extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_Bx_Ext_Ptr;
+extern UINT16 PchLbgHsio_Bx_Ext_Size;
+
+#endif //_PCH_LBG_HSIO_BX_EXT_H_
\ No newline at end of file
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx.h
new file mode 100644
index 0000000000..3e3d10bd3e
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx.h
@@ -0,0 +1,17 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_LBG_HSIO_SX_H_
+#define _PCH_LBG_HSIO_SX_H_
+
+#define PCH_LBG_HSIO_VER_SX 0x8
+
+extern UINT8 PchLbgChipsetInitTable_Sx[2844];
+extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_Sx_Ptr;
+extern UINT16 PchLbgHsio_Sx_Size;
+
+#endif //_PCH_LBG_HSIO_SX_H_
\ No newline at end of file
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx_Ext.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx_Ext.h
new file mode 100644
index 0000000000..616212f4b1
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx_Ext.h
@@ -0,0 +1,17 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_LBG_HSIO_SX_EXT_H_
+#define _PCH_LBG_HSIO_SX_EXT_H_
+
+#define PCH_LBG_HSIO_VER_SX_EXT 0x8
+
+extern UINT8 PchLbgChipsetInitTable_Sx_Ext[2844];
+extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_Sx_Ext_Ptr;
+extern UINT16 PchLbgHsio_Sx_Ext_Size;
+
+#endif //_PCH_LBG_HSIO_SX_EXT_H_
\ No newline at end of file
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioBx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioBx.h
new file mode 100644
index 0000000000..774a0a09f5
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioBx.h
@@ -0,0 +1,16 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_LP_HSIO_BX_H_
+#define _PCH_LP_HSIO_BX_H_
+
+#define PCH_LP_HSIO_VER_BX 0x3e
+
+extern UINT8 PchLpChipsetInitTable_Bx[1492];
+extern PCH_SBI_HSIO_TABLE_STRUCT PchLpHsio_Bx[109];
+
+#endif //_PCH_LP_HSIO_BX_H_
\ No newline at end of file
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioCx.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioCx.h
new file mode 100644
index 0000000000..9740763098
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioCx.h
@@ -0,0 +1,16 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_LP_HSIO_CX_H_
+#define _PCH_LP_HSIO_CX_H_
+
+#define PCH_LP_HSIO_VER_CX 0x34
+
+extern UINT8 PchLpChipsetInitTable_Cx[1548];
+extern PCH_SBI_HSIO_TABLE_STRUCT PchLpHsio_Cx[120];
+
+#endif //_PCH_LP_HSIO_CX_H_
\ No newline at end of file
diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchPolicyHob.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchPolicyHob.h
new file mode 100644
index 0000000000..1fafaae47e
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchPolicyHob.h
@@ -0,0 +1,18 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_POLICY_HOB_H_
+#define _PCH_POLICY_HOB_H_
+
+#include <PchPolicyCommon.h>
+
+typedef struct _PCH_POLICY PCH_POLICY_HOB;
+
+extern EFI_GUID gPchPolicyHobGuid;
+
+#endif // _PCH_POLICY_HOB_H_
+
--
2.27.0.windows.1
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