[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #9 from Chitlesh GOORAH <cgoorah at yahoo.com.au>  2008-12-06 05:36:20 EDT ---
#001: Summary:        Verilator is a fast simulator for synthesizable Verilog

Summary should not include the %{name}
Instead it should be "A fast synthesizable Verilog simulator"

#002: For rpmfusion, I'm packaging systemc, however the "libsystemc-devel" is
simply systemc.

#003: Verilator 3.681 has been released .

Lane are you still interested with verilator ?

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