[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #10 from Lane <dirjud at gmail.com>  2008-12-06 05:48:30 EDT ---
I am swamped right now with a tape out.  I will try to get some time over the
next two weeks to incorporate your comments.

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