[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #11 from Lane <dirjud at gmail.com>  2009-01-01 10:34:07 EDT ---
> #004: Are these useful ?
> /usr/share/verilator/bin
> /usr/share/verilator/bin/verilator_includer

Yes. As far as I know, verilator uses these.

> #005: move BUIDROOT/usr/share/verilator/examples to examples/
> then %doc examples/

I don't understand this comment.

> #006: Are these important:
> chitlesh(SPECS)[1]$rpm -ql verilator | grep -v examples | grep .cpp
> /usr/share/verilator/include/verilated.cpp
> /usr/share/verilator/perl-systemc/src/SpTraceVcdC.cpp

Yes.  These are included in all verilator simulation builds.

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