[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #12 from Lane <dirjud at gmail.com>  2009-01-01 11:14:59 EDT ---
Created an attachment (id=328036)
 --> (https://bugzilla.redhat.com/attachment.cgi?id=328036)
simple verilator test case

Attached is a simple verilator test case per Chitlesh's request.  Here is how
to run this:

1. untar the file and cd into the verilator_test_case directory.
2. Compile the simulation by running 'make'.  This generates an executable
   called obj_dir/Vcounter.
3. Run the simulation: 'obj_dir/Vcounter'

This will output the following to stdout:

Hello World from counter!
Time  0: count = 0x0
Time  2: count = 0x0
Time  4: count = 0x0
Time  6: count = 0x1
Time  8: count = 0x2
Time 10: count = 0x3
Time 12: count = 0x4
Time 14: count = 0x5
Time 16: count = 0x6
Time 18: count = 0x7
Time 20: count = 0x8
Time 22: count = 0x9
Time 24: count = 0xa


SUMMARY OF TEST CASE:
This test case implements a counter in the verilog file counter.v.  The C++
file tb.cpp implements the testbench that provides the input, including the
clock.  This example does not turn on any tracing.  See the verilator
documentation on how to enable tracing to generate a VCD file for viewing with
gtkwaves.

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