[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #33 from wsnyder at wsnyder.org  2009-06-12 09:53:47 EDT ---
Grr, every GCC version has slightly different things it complains about...

This will patch it, let me know if you want a new release instead.  If there's
another bug, please try "make -k" so they'll all show up rather than one at a
time.  Thanks

diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp
index 84856dc..4f76ba8 100644
--- a/src/V3PreProc.cpp
+++ b/src/V3PreProc.cpp
@@ -990,7 +990,7 @@ int V3PreProcImp::getToken() {
 string V3PreProcImp::getline() {
     // Get a single line from the parse stream.  Buffer unreturned text until
the newline.
     if (isEof()) return "";
-    char* rtnp;
+    const char* rtnp;
     bool gotEof = false;
     while (NULL==(rtnp=strchr(m_lineChars.c_str(),'\n')) && !gotEof) {
  int tok = getToken();

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