[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #34 from Chitlesh GOORAH <chitlesh at gmail.com>  2009-06-13 15:43:47 EDT ---
Lane, the package is ready. please update the package with respect to the
following minor details. Then I'll approve.

#1 add the Artistic file as %doc

#2 compiler fix from Wilson:
sed -i "s|char\* rtnp;|const char\* rtnp;|" src/V3PreProc.cpp

#3: rpmlint warning spurious-executable-perm
chmod 0644 %{buildroot}%{_mandir}/man1/%{name}.1.gz

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